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ATFundament of High Perf Comp

by: Mireya Heidenreich

ATFundament of High Perf Comp CS 6463

Mireya Heidenreich
GPA 3.55

Richard Whaley

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About this Document

Richard Whaley
Class Notes
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This 4 page Class Notes was uploaded by Mireya Heidenreich on Thursday October 29, 2015. The Class Notes belongs to CS 6463 at University of Texas at San Antonio taught by Richard Whaley in Fall. Since its upload, it has received 7 views. For similar materials see /class/231413/cs-6463-university-of-texas-at-san-antonio in ComputerScienence at University of Texas at San Antonio.

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Date Created: 10/29/15
l 1 Required Knowledge to Write in Assembly Application Binary Interface a ABI FunctionOS interop eration a Argument passing b Stack handling 2 3 A These are the c Register conventions Instruction Set Architecture a ISA ISA actually hegtlt inst formats but most assem blers use suggested mneu monics instructions that you must build programs out of Registersflags 4 Assembler used EMASM a Assembler directives fixed by b Operand order src dest c Const identifier d Register identifiers X e gtlt86gas suffixes commands with precision qualifier pre i b 1 byte int ii w 2 byte int iii 1 4 byte int iv q 8 byte int v 1 8 byte float vi 5 4 byte float 2 Further Resources 0 80gtlt8O Assembly Language and Computer Architecture by Richard C Detmer Doesn39t cover SSEl 3 but good basic ref 0 ATLAS assembly page from links on class homepage httpmathatlassourceforgenetdevelassembly o ATLAS architecture page from links on class homepage httpmathat1assourceforgenetdevelarch 3 x86 Calling Sequence and Stack Frame Stack grows downward in mem ory Caller puts callees39 args in its frame Frame 4 byte 32 bit aligned If callee needs no scratch space can leave SP unmodified Otherwise subtract frame size from SP keeping 4 byte aligned Caller39s frame Stack frame passed to callee 4 x86 Integer Registers general purpose 31 O EAX AX EBX BX ECX CX EDX DX All but eax edx ecx callee saved 8 regs of every size esp is stack pointer ebp can be frame ptr eax is integer return val reg int64edxlthi32eax4lo32 E51 EDI Also have 0 EIPIP instruction ptr o EFLAGSFLAGS control 84 status bits 5 x86 Assembly Overview 0 Two operand assembler gas ltmnemgt ltsrcgt ltdestgt masm ltmnemgt ltdestgt ltsrcgt Dest is inputoutput add src dst gt dst dst src 0 Most ODS take memregimmed rdest gt call this mris rd constants begin with regs with mem is address Ops with memory operands need size suffix bwqls Usually only one operand can be from memory CISC format diff inst of different sizesefficiencies Generally arithmetic affects status word movement does not 6 x86 Addressing Modes CONSTbreg nreg mul examples 0 2 va1breg va1nregmu1 o 120esp CUNST a Load item 1208 above SP CUNST is signed integer constant c eaxedi4 7128127 8 bit offset a xi assuming edii eaxx else 32 bit offset single 0 breg reg holding base address 0 16eaxecx8 nreg indegtlt reg a A211da assuming mul amount to muI index value ecxda eaxA double by Can be 12 4 8 7 x86 Integer MovementInit Operations 8 Common Integer Arithmetic Operations mrs mem mem LEA Load Effective Address can add without needing scratch regs 0 takes any valid indegtlting mode puts target Q in rdest o ecx 8 4eax eh i lea 8ebxeax4 ecx be used for multiply shift andor 9 Common Bit Level Operations 10 x86 Integer Condition Codes Conditions signaled in fIag register ZF bit 6 result of op is zero CF bit 0 unsigned only set to 1 if un signed addition overflows or unsigned sub traction borrows from beyond integer SF bit 7 set to most sig bit of result 1 means neg number OF bit 11 most sig bit of dest different than both src sig bits 0 PF bit 2 set to 1 if there39s an even number of ls in least sig byte of dest oth erwise O 11 Common x86 Comparison Instructions imm bit in rd set imm bit in rd to 0 set imm bit in rd to l 0 Can do comparison early branch later A Must be no intervening iops that set the same CC bits 12 Common x86 Comparison 84 Branching Instruction 13 x87 Floating Point Registers STO aka ST stack top For most fp ops one operand must be STO other operand memory As new values are loaded values pushed down in stack Two regs swapped via FXCII Values added by push ops im plicitexplicit Values removed by pop ops im plicitexplicit register or 14 Common x87 Stack Manipulation Instructions Mnemonic Operands Action finit none init FPU 84 clear stack fld mem mem pushed onto stack fld stx STgtlt pushed onto stack f1d1 none 10 pushed onto stack fldz none 00 pushed onto stack fst stx STgtlt 2 ST fstp stx STgtlt 2 ST ST popped fst mem mem 2 ST fstp mem mem 2 ST ST popped fxch none swap ST and STl fxch stx swap ST and STgtlt 15 Common x87 Floating Point Computation Instructions 16 x87 Comparison Instructions Result 14 10 8 of fcom C3 0 use fstsw store fp status word to agtlt then use test or bt to trigger branches C2 C0 STgt O O O STlt O O l ST 1 O O fcomii ZF PF fp status bits set Mnemonic Operands Action faddfmu1 none replace ST 84 STl with their sum product faddfmu1 mem replace ST with its sum product with mem Mnem Ops Cmp ST again faddfmu1 ststx replace STgtlt with sum product fcom one STl faddfmu1 stxst replace ST with sum product fcom 5tltgtltgt STgtlt faddpfmu1p ststx replace STgtlt with sum product pop ST fcom mem mem fsub none replace ST 84 STl with STl ST 515 one 00 fsub mem replace ST with ST mem fc mP one STlv pop ST fsub ststx STgtlt ST fc0m W STWv POP ST fsub stxst ST STgtlt fcomp mem memi pop ST fsubp ststx STgtlt ST pop ST fc mPP one STlv pop STO 8 STl fsubr none replace ST 84 STl with ST ST1 fstsquot ax ax W Status word fsubr mem replace ST with mem ST fsubr ststx STgtlt 2 ST STgtlt c From PPRO on have fcomi for all all fsubr 510051 ST STgtlt ST register fcom variants that directly sets fsubpr ststx STgtlt 2 ST STgtlt pop ST int ags as shown in table fabs none ST 2 lSTl fchs none ST 2 ST


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