Des Microproc Syst
Des Microproc Syst EECS 373
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This 2 page Class Notes was uploaded by Ophelia Ritchie on Thursday October 29, 2015. The Class Notes belongs to EECS 373 at University of Michigan taught by Brehob in Fall. Since its upload, it has received 16 views. For similar materials see /class/231515/eecs-373-university-of-michigan in Engineering Computer Science at University of Michigan.
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Date Created: 10/29/15
Programmable Counters and Timers A programmable countertimer is a peripheral that counts edges voltage transitions that occur on an input signal counts events measures time Basic operation Application MPC823 specific information Generic CounterTimer Structure CLK controlstatus reister GATE count register limit register OUT n n INT Basic Operation User program initializes register values Typically count register is initialized to 0 On each eg falling edge of CLK value in count register is incremented When count register limit register things happen as determined by settings of controlstatus register Flexible operation since much of device behavior can be programmed via the controlstatus registers Downcounters Operation complementary to upcounters Programmable Options Depending on controlstatus register When count limit one or more of the following Will happen Always set bit in status register May generate interrupt to CPU May reset count to 0 May continue counting or stop May change signal on OUT pin set clear pulse toggle GATE signal can be programmed to Enabledisable counting of CLK edges Reset count to 0 on edge CounterTimer Applications MPC823 Timers See Sec 164 of User s Manual part of Communication Processor Interval timer Module I Clock divider Four 16 bit counters on chip two of them 1 and 2 work Each has external input TIN1 TIN2 TIN3 TIN4 which is also Watchdog timer used for capture mode Other inputs system clock system clock divided by 16 Only 1 and 2 have output pins TOUT1 and TOUT2 Active low pulse Toggle Frequency counter Only one gate input TGATE1 can be used with 1 or 2 Enable count on falling edge disable count on rising edge Can also reset counter on falling edge when in restart mode Timer Block Diagram MPC823 Timer Control Registers CPM local bus TGCR Timer Global Configuration Register 16 bit memory Systerln Clock 325ng register that contains configuration parameters used Capture Reg Can pair two to act as a 32 bit timer 1 amp 2 andor 3 amp 4 Power control Gate mode TGATE 1 ENX I For each timer x TOUT Mode controlstatus register TMRx Reference limit register TRRx Counter register TCNx Capture reg39ster TCRX Latch value of counter at event Event register TERx Bits to indicate referencecapture event Capture Detection