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Digit Integrat Circ

by: Ophelia Ritchie

Digit Integrat Circ EECS 312

Ophelia Ritchie
GPA 3.8


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Class Notes
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This 56 page Class Notes was uploaded by Ophelia Ritchie on Thursday October 29, 2015. The Class Notes belongs to EECS 312 at University of Michigan taught by Staff in Fall. Since its upload, it has received 26 views. For similar materials see /class/231540/eecs-312-university-of-michigan in Engineering Computer Science at University of Michigan.

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Date Created: 10/29/15
Digital Integrated Circuits A Design Perspective Jan M Rabaey Anantha Chandrakasan Borivoje Nikolic Slides revised by R Dick The Devices July 30 2002 Goal of this chapter El Present intuitive understanding of device operation El Introduction of basic device equations El Introduction of models for manual analySIs El Introduction of models for SPICE simulation El Analysis of secondary and deepsub micron effects El Future trends The Diode Onedimensional representatlon dlode symbol Mostly occurring as parasitic element in Digital 03 Depletion Region hole dif JSlOIl a Current ow b Charge density c Electric eld d Electrostatic potential Diode Current w 1 5 m5 E E u 5 mm 2 a p Vdecade current w VB 5 U 5 1 U n n n 2 n A n 5 VD V VD V a On a hnear scam b On a uga mmm scam furward was I I zVD T7 1 D S Diode Current I Jquot4771 ID diode current ls saturation current VD diode voltage CDT thermal voltage kTq k Boltzmann constant T temperature q elementary charge Forward Bias 39WI 0 W2 X p reglon n reglon dz tsion Typically avoided in Digital 03 Reverse Bias W1 0 W2 X p reglon nregjon di usion The Dominant Operation Mode Models for Manual Analysis lllkj D 139 VD T 1 llll ri D quotl quotquotquotquotquot quotlquot a quot lm VD link VDon 3 Ideal diode model b Firstorder diode model Junction Capacitance abrupt junction linearjunclion 0 m 05 abrupt junction C 7 m 033 linearjunclion Diffusion Capacitance Excess Minority Carrier Charge W10 W2 pregwn nIeglon CJO AD asiqZ NANDNA ND 1 012 AD area of diode as permitivity of Si NX carrier density Do ltDT nNANDni2 DT kTq ni intrinsic carrier concentration Diffusion Capacitance CJO AD ssi CV2 NANDNA ND 1 O12 AD area of diode est permitivity of Si NX carrier density DO CDT nNANDni2 CDT kTq ni intrinsic carrier concentration Secondary Effects 01 g Q 0 01 39 39 250 150 50 0 50 VD V Avalanche Breakdown Diode Model SPICE Parameters Parameter Name Symb 01 Units SPICE ame Default Value What is a Transistor A Switch lt gt An MOS Transistor It It The MOS Transistor Gate Fieid 1da X Field MOS Transistors Types and Symbols n s 6w 64E 64 S s PMOS Enhancement NMOS With Bulk Contact nchannel Threshold Voltage psub strate R Depletion egion Concept The Threshold Voltage E V 2 T pm 45quotquot Cox Cox Cox More dopants 9 higher VT V I 11mm Thicker oxide 9 higher VT gvgi fml gum Surface Charge DepletiunLayerCharge o VTO VT WlthOUt blaS BndyE 39ectCue 39icient 0 39Y effect coeffiCient Fermi otential VT VTO Jr 2 F VSB HI 2 IDF p with VSB sourcebulk voltage PTO m32 FQss cpmSLgate work function G C C 03C 03C 031 and 5 a N T 2 OS A 03C The Body Effect CurrentVoltage Relations Resistive RV Saturation IN 4 6 X 10 Wis 25 V Resistive Saturation 4 VGs 20 V is Quadratic VDs VGS 39 VT Relationship 2 VGS 15 V 1 VGs 10 V j o o 05 1 15 2 25 Transistor in Linear EF 39 psubstrate MOS transistor and its bias conditions moiu m 519 mm gt gt Hgtum gtA mQgt 203253 E 333 Current Voltage Relations LongChannel Device JOX OXIde C Linear Region VDS gVGs VT 1 carrier mobility 1V VD ID k39n LUV VTWDS 752 39 N Width with V 7 7 5150 Process Transconductance LI Ien th kn 7 Junch 2 Parameter g 0 SS permitivity Saturation Mode V95 2 VGs VT channel Length Modula on tox OXIde thickness 1639 quotVV 2 ID 2 LWGS VT IMVDS A proportional to inverse of channel length A model for manual analysis Gn n D 539 VDS gt VGS VT k n I VV D 2 2 V637 VT 1 HLVDS VDSlt VGS VT V VV D32 ID k39n LQVGS TWDS 2 j with VT V70 y 72 F VSB i HM CurrentVoltage Relations The DeepSubmicron Era 4 X 10 25 I a VGs 25 V Early Saturation 2 5 quot VGs 20 V 15 5 Linear 1 VGS 15 V Relationship 05 5 VGS 10 V 39 I 0 o o 5 1 15 2 2 5 Velocity Saturation A 0 ms Usat105 Constant velocity Constant mobility slope p 39 hr ac 15 altwumgt Perspective ID A Longchannel device Shortchannel device ID versus VGS 4 4 UX 10 2X 10 5 2 4 quadratlc 1 5 3 3 3 1 2 1 05 quadratic c c o 05 1 15 2 25 o 05 1 15 2 25 VG3V VGSV Long Channel Short Channel ID versus VDS x 104 104 D 395 I 1 ins 25 VG V R 139 39V quot r i n 4 es stl Satu at o VGSZ 20y VGS 20 V 15 2 g 13339 ixquot 39 D VDS Vcs 39 VT 1 VG5 15V 239 VGS 15 V 1 q 0539 VGS VGS 10 V I U 0o 05 1 15 2 25 0 05 1 15 25 VDSV VDsV Long Channel Short Channel A unified model for manual analysis ID 0 for 2 V ID k VZVVGTVmin 1 1XVDSfor VGTZO with me minVGT VDS VDSAT VGT VGS VT7 and VT VTO Y 2 F VSB A 2 F Simple Model versus SPICE VDSVDSAT 2 W o 0 Veloc1ty 139539 o 9 g D Llne o 1 To v v v v 39 39 6 VDSATVGT 6 05 o Lil 6 o 6 6 GT Saturated o A 0 05 1 15 2 25 VDS V A PMOS Transistor X10 VGS 10V VGs 15V Assume all variables negative Transistor Model for Manual Analysis Table 32 Parameters for manual model of generic 025 pm CMOS process minimum length device Vin V v w Vow V k39 AN A V1 NMOS 043 04 063 115 x10 006 PMOS 704 04 1 30 x 10396 01 The Transistor as a Switch a VDS VDD2 VDD 39 V V 2 V qu lL DD ljwm 2 IDSAT1 XVDD IDSAT1 gtVDD 4IDSAT 6 The Transistor as a Switch DD The Transistor as a Switch a le 33 Equivalent resistance Rea WL 1 of NMOS and PMOS transistors in 025 pm CMOS process with L me For larger devices divide Rea by Vol V 1 15 2 25 NMOS kg 35 19 15 13 PMOS kg 115 55 3s 31 MOS Capacitances Dynamic Behavior Dynamic Behavior of MOS Transistor 39 39 l I I l39 munai r I q F I d h ii it In lllll ll i A I ll Inuit The Gate Capacitance Polysilicon gate Top view Cross section Gate Capacitance iiiiuimii uimmimuw 7 iiiiiiiiiiiiiiimuiiiiiiii iiiiiulm lmmlmuw iquulumMumml e 0 CDXWLE 2 i Saturation i 0 i 23CMWLE i Most important regions in digital design saturation and cutoff Gate Capacitance Vt VGS VDSA VGS39VT 1 Capacitance as a function of VGS Capacitance as a function of the with VDS 0 degree of saturation Measuring the Gate Cap 310216 Gate Capacitance F 2215212050 05 1 15 2 VGsV Diffusion Capacitance Channelstop implant NAl Bottom Channel LS Substrate NA Cum CAM NC CgtltAREA CMgtltPER1METER CiLSW C 2LS W m Junction Capacitance abrupt junction linearjunclion 40 20 00 VD V Co mo5 m03 C abrupl junclion J 1 7 VDNO 3 linearjunclion CDO junction potential Linearizing the Junction Capacitance Replace non linear capacitance by large signal equivalent linear capacitance which displaces equal charge over voltage swing of interest g QJltVmghgtigjltVWgt C K C 29 AVD Vmgh Vtaw eq JO 7 m Keg WWJO Vmgh1 m o Vzaw1quot l Capacitances in 025 um CMOS process LA 79 Q m m PM quotW m IF1m IFurn IF1m V IFurn V NMOS 5 031 2 05 09 028 044 09 PMOS 5 027 19 048 09 022 032 09 The SubMicron MOS Transistor CI Threshold Variations CI Subthreshold Conduction El Parasitic Resistances Threshold Variations VT VT Longchannel threshold LOW VDs threShOId L L r VDS Threshold as a function of Draininduced barrier lowering the length for low VDS for low L SubThreshold Conduction The Slope Factor Linear chs C 1039 IDIOe kT n1 D 1 56 Quadratic 50 8 1s AVGS for DZ1D1 10 10398 Ex onential S 1n10 161039 39 q I 012 I I I I Typical values for S o 05 1 15 2 25 60 100 mV decade qVGS quDS nkT kT I D I 0e 1 e IDIOenkT1 e kT 11VDS Summary of MOSFE T Operating Regions El Strong Inversion VGS gt VT Linear Resistive VDS lt VDSAT Saturated Constant Current VDS 2 VDSAT DWeak Inversion SubThreshold VGS s VT Exponential in VGSwith linear VDS dependence Parasitic Resistances Polysilicon gate I Dram RJEEII Allii i G 335555EEEEEEEEEEEEEEEEEEEEEI LD IIIEII18EEEEEEEEEEEEEEEEEEEEI ImmEIEEEEEEEWEEEEEEEIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII JHmElll lmml lmlml 1r IIIIIIIIIIIIIIIIIIIIIIIIIIIIIr IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I IIIIIIIIIIIIIIIIIIIIIIIIIIIII IlEEEEHEEEEEEEEEEEEEEEEEEEEEEI I IIIIIIIIIIIIIIIIIIIIIIIIIIIIII I I I r WIIEEEEEEEEEEEEEEEEEEEEEEEI WIIEEEEEEEEEEEEEEEEEEEEEEEI WIIEEEEEEEEEEEEEEEEEEEEEEEI WIIEEEEEEEEEEEEEEEEEEEEEEEI IIEEEEEEEEEEEEEEEEEEEEEEEE quotquot1HImIIEEEEEEEEEEEEEEEEEEEEI39quot ImEEEEEEEEEEEEEEEEEEEEEEI WIIEEEEEEEEEEEEEEEEEEEEEEEI WIIEEEEEEEEEEEEEEEEEEEEEEEI WIIEEEEEEEEEEEEEEEEEEEEEEEI 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