Des Microproc Syst
Des Microproc Syst EECS 373
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This 6 page Class Notes was uploaded by Ophelia Ritchie on Thursday October 29, 2015. The Class Notes belongs to EECS 373 at University of Michigan taught by Staff in Fall. Since its upload, it has received 17 views. For similar materials see /class/231554/eecs-373-university-of-michigan in Engineering Computer Science at University of Michigan.
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Date Created: 10/29/15
IO Data Transfer There are two key questions that determine how data is transferred to and from a nontrivial IO device Each question has two possible answers 1 How does the CPU know when data is available a Polling b Interrupts 2 How is data transferred into and out of the device a Programmed 10 b Direct Memory Access DMA So far we have implicitly assumed the simple answers to these questions polling and programmed 10 We will look at interrupts next and DMA later in the term EECS 373 F99 Notes Interrupts An interrupt also known as an exception or trap is an event that causes the CPU to stop executing the current program and start executing a special piece of code called an interrupt handler or interrupt service routine ISR The ISR typically does some work then resumes the interrupted program Similar to a procedure call except that an interrupt l 4 V39 can occur between any two instructions of the program is transparent to the running program usually is typically not explicitly requested by the program calls a routine at an address determined by the type of interrupt not by the program atomically changes some processor mode bits in the machine status register MSR 1998 1999 Steven K Reinhardt Interrupt Types Microprocessors use the interrupt mechanism for lots of largely unrelated things These things can be grouped into two categories 1 Synchronous instructionrelated illegal instruction privileged instruction bus error machine check divide by 0 on most processors oatingpoint errors virtual memory page fault system call into operating system 2 Asynchronous not instructionrelated external hardware device timer expiration reset power failure onchip debugging on 823 See Section 638 ofthe MPC823 data book EECS 373 F99 Notes PowerPC Interrupt Structure As for procedure calls the PowerPC architecture provides bare bones support for interrupts Two specialpurpose registers saverestore registers 0 and l SRRO and SRRl One instruction return from interrupt r Basic interrupt process 1 stop executing current program 2 save PC of next instruction in SRRO 3 save the processor mode bits from MSR in SRRl 4 change some ofthe processor mode bits in MSR 5 branch to address determined by type of interrupt ISR see Table 71 on p 78 of MPC823 data book The last instruction in the ISR will be an r which will 1 restore the processor mode bits from SRRl to MSR 2 branch to the address in SRRO 1998 1999 Steven K Reinhardt A Simple Example Nesting Interrupts An interrupt can happen while executing an ISR This is called a nested interrupt multiple interrupting devices with longrunning ISRs debugging ISR code supporting Virtual memory in ISRs What must a PowerPC ISR do to support nested interrupts EECS 373 F99 Notes 53 1998 1999 Steven K Reinhardt Disabling Interrupts Sometimes you can t afford to take an interrupt timecritical instruction sequences before you ve initialized data needed by an ISR changing data structures shared with an ISR Synchronous interrupts can be avoided by not executing instructions that might cause them illegal instructions loads or stores to nonexistent addresses etc Asynchronous interrupts from external devices can be disabled masked using the external interrupt enable EE mode bit bit 16 of the machine status register MSR if 0 external interrupt signal is ignored if 1 external interrupt signal causes interrupt when asserted EE is atomically set to 0 on any interrupt Note that some interrupts e g reset are not maskable EECS 373 F99 Notes Managing Multiple Device Interrupts A system with multiple devices that can interrupt the CPU must be able to determine which device to service on an interrupt There are two related issues 1 Identi cation which devices caused the current interrupt 2 Prioritization if more than one device is simultaneously interrupting which one gets handled rst Depending on the system highpriority interrupts may or may not be able to interrupt lowpriority service routines Three standard approaches 1 Nonvectored 2 Vectored 3 Autovectored 1998 1999 Steven K Reinhardt N 0n Vect0red Interrupts Simplest hardware least exible Used in 6802 PowerPC MIPS single CPU interrupt inputvector ISR checks polls each device to see which may have caused interrupt prioritization nesting EECS 373 F99 Notes Vectored Interrupts Used in 8080 80x86 Z80 again single CPU interrupt input CPU has special interrupt acknowledge bus cycle to get vector number directly from device like read but dilTerent control signals 0 8086 INTA prioritization typically via daisy chain typically requires that devices be designed to work with speci c CPU nesting 1998 1999 Steven K Reinhardt Autovectored Interrupts Used in 68000 SPARC Can be built on top ofvectored 80x86 w8259A PC or nonvectored interrupts MPC823 multiple CPU interrupt inputs one for each priority level eg IRQO IRQl IRQ2 etc CPU autovectors based on highestpriority asserted interrupt CPU interrupt priority level controls which interrupts get recognized eg if IPL 3 then disable IRQ3 IRQ4 IRQS on interrupt CPU atomically raises IPL to match level request being serviced generalization of enable bit EECS 373 F99 Notes Autovectored Interrupts cont d directly provides prioritization nesting more devices than priority levels Intel 8259A interrupt controller chip builds autovectoring on top of 80x86 vectoring IBM PC MPC823 provides onchip interrupt controller for pseudo autovectored interrupts 1998 1999 Steven K Reinhardt
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