Des Microproc Syst
Des Microproc Syst EECS 373
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This 4 page Class Notes was uploaded by Ophelia Ritchie on Thursday October 29, 2015. The Class Notes belongs to EECS 373 at University of Michigan taught by Staff in Fall. Since its upload, it has received 21 views. For similar materials see /class/231554/eecs-373-university-of-michigan in Engineering Computer Science at University of Michigan.
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Date Created: 10/29/15
Review software viewpoint Interrupt occurs Processor saves limited state I SRRO Next instruction to be executed when return from A walk through interrupts on interrupt SRRI Copy of MSR MSR is modified Most important is EE bit0 Processorjumps to the Interrupt Service Routine ISR executes Needs to save state so that it can put it all back before return from interrupt May enable nested interrupts 39 Does its thing 6 This is a big step Restores state disables nested interrupts if needed Return from interrupt rfi instruction Vlewpomt Table 71 Offset of First Instruction by Interrupt Type OFFSET HEX INTERRU PT TYPE How does the ISR know where to branch to 00000 WWI Table 71 indicates the low 5hex digits of the Wer Wm Rye address 39 quot The IP bit of the MSR a e 621 determines the 00m WWWquot p 9 00300 Data Storage high order bits 00400 instruction Storage But even then we need to do 00500 Ema TOI Table710IisetolFlrsl Instruction by lnlerrupl39lype mam Alimmm interrUpt OFFSEIIIIEX INIERFIUFTTIPE SIVEC Writ liztwe C h tutu Data Slang UNI lrs39rudoiShter 300 Evletral So how do we run the right code SIVEC holds an 8 bit code which indicates which interrupt was the highest level external interrupt Page 126 This can be used to figure out which line is the highest priority interrupt While a switch statement would work it is fairly ugly Ratherwe use an indirect branch Sample code is on page 1211 Save slate R3 lt 4 sIvEc R4 lt ase of branch table lhz RX Rain mad ashyle add RXRRXXA mtspr or R bctr BASE b Routinel BASE EASE u b Rautinez BASE m BASE a RoutineJ BASE v 300 BASE 4 c b Routine BASE CW BASE 10 39 BASE 1000 BASE n 39 BASE n ll Figure 123 Interrupt Table Handling Example Ok so we ve got the software mostly down Some issues Changing the MSR could be important We need to be sure we save everything we change Don39t forget the condition register Not sure what to do to stopthe interrupt We need to clear something somewhere 80 onto hardware MP0 823 hardware So how about from the hardware side We39ve already seen one specialpurpose register SIVEC It turns out there are a few more SIPEND is a vector of pending interrupts SIMASK is a vector that allows one to mask out certain interrupts SIELtogglesthe lFlQinterrupts from edge to level We also have to understand what the different souces of interrupts might do Let39s start there External Interrupts There are two basic types of external interrupts Those generated offchip and those generated onchip Hardware devices you generate on the FPGA will all be offchip These use the IRQ interrupts Timers and other onchip devices use the LVL interrupts Each has somewhat different functionality Clearing interrupts Every interrupt doesshould have a single point of reset Think of it this way Somewhere out there is something that is saying this interrupt is occurring the device is asking for service The ISR needs some way to clear this and indicate that the device is being dealt with Doing so remove the interrupt from SIPEND Clearing LVL interrupts Always levelsensitive Probably why named the way they are Interrupt source is either CIPR 16497 or an event bit associated with the interrupt You do NOT clear them by writing to SIPEND Clearing IRQ interrupts If the IRQ is edgetriggered the SIPEND register stores the fact that an interrupt has occurred The interrupt is cleared at SIPEND in this case If the IRQ is levelsensitive the interrupt is cleared by direct communication to the IO device When designing lO devices that generate interrupts keep these things in mind Interrupt related registers We ve seen SIVEC but there are more SIEL System Interrupt EdgeLevel Determines if IRQ interrupts are level or edge sensitive Also controls if IRQ can wake the processor from lowpower mode 3 d 5 6 7 B a In 11 12 I3 1 l5 FIELD ED2 5 mm E56 Ville EDT RESET It v u it it it RIW w w R W Rial RyJ mixRivfrwr W ADDR union amp DXFFF SIPEND Keeps track of the external interrupts that are PENDing Used to clear edgetriggered IRQ interrupts Can be used rather than SIVEC to figure out what interrupt to service if you really really want to SIMASK Allows certain interrupts to be ignored or masked out Is ANDed with SIPEND to determine which interrupts are allowed to interrupt the core and set their value in SIVEC SIMASK an o 1 2 z 4 5 a 1 a n in 11 12 13 14 l 15 FIELD L JM l I UJM7 RESET i w r w n a U o l n t 0 RM R Pu M R R Ry l w 1396 Rm ADDR illlllR s DxFFFFOUCOi 393C39 l4