CAD Verif Dig Syst
CAD Verif Dig Syst EECS 578
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This 2 page Class Notes was uploaded by Ophelia Ritchie on Thursday October 29, 2015. The Class Notes belongs to EECS 578 at University of Michigan taught by Staff in Fall. Since its upload, it has received 12 views. For similar materials see /class/231558/eecs-578-university-of-michigan in Engineering Computer Science at University of Michigan.
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Date Created: 10/29/15
Soft Error Verification for Sequential Circuits ChienChih Yu Cheng Zhuo EECS Department University of Michigan Ann Arbor ccyu czhuoumichedu 1 Introduction Soft error or transient error is a nonreproducible error caused by cosmic rays or high energy particles The Soft Error Rate SER of a device is de ned as the error rate due to Signal Event Upsets SEUs Memory elements and some special purpose circuits like aviation or military computers implement extra blocks ECC checkers or TMR to protect them from SEU attacks With the increase in density of transistors and operation speed as well as the decrease in supply voltage of circuits soft errors are becoming more prominent nowadays Thus it is of crucial importance to develop ef cient techniques for soft error analysis and veri cation 2 Motivation One of the major reliability veri cation methods is to use probability transfer matrices PTM 1 With the PTM method each gate in a combinational circuit is represented by a matrix and each element of a PTM represents one possible input and output combination Since a PTM contains the probabilities of all possible combinations the computation result of a PTM covers all possible scenarios implicitly and no input pattern is needed during the evaluation process In this project we want to design a framework to verify the soft error reliability of sequential circuits by combining time frame expansion and the PTM method 3 Background Most existing papers that discuss SEUs and SERs consider only a single error In General techniques to verify the SER can be categorized into three classes 1 SPICE modelbased algorithms 4 5 2 signal propagationbased algorithms 6 and 3 probability networksbased algorithms 1 2 3 SPICE modelbased methods focus on the transistor level and their SEU parameters are more complicated than the methods in the other two classes A SPICE modelbased SEU contains error signal amplitude pulse width and bias condition input vector The fault models used in the rest of two classes is simpler than the SPICEbased one Those fault models usually contain no error duration and voltage but they allow di erent combinations of gate 1 types and input vectors to be mapped to diiTerent probabilities l 2 3 The main advantage of signal propagationbased methods is that they are much faster than probability probabilitybased algorithms however they suiTer from the same drawbacks 1 their algorithms may overestimate the error probability because not all conditional probabilities are accounted for and 2 the accuracy of the SER will decrease when the number of SEUs increases In other words they have the best performance when only single SEU is considered Clearly probabilitybased algorithms are good at handling complex conditional probabilities relationship because they can perform multiple errors computation implicitly without losing information 4 Soft Error Veri cation for Sequential Circuits 41 Project Details Until now few papers discussed the methodology of verifying the reliability of a sequential circuit One reason is that handling all states transitions cycle by cycle may be difficult Some techniques such as tracing the transitions of internal states Markov chain and time frame expansion are developed to evaluate the reliability of sequential circuits The PTM framework is proven to be suitable for evaluating the reliability of a combinational circuit However it may suffer from intensive memory usage We want to efficiently extend the PTM application to sequential circuits and evaluate the reliabilities of circuits under di erent applications How to prevent the number of traced states from growing too fast to engulf all computation resource and storage space is always the key issue when handling the sequential circuits The concept of the time frame expansion is to capture the computation boundary of sequential circuits at each cycle In each time interval the sequential circuits will be treated as a combinational one Since the system only records the values of combinational parts and previous values stored in each register at each time frame the total number of stored states or values will not grow with the increasing of cycle time Thus we decide to combine the time frame expansion and the PTM techniques to estimate the soft error reliability of sequential circuits 42 Contributions The goal of this project is to design a framework that can 1 parse the sequential circuits 2 extract the circuit boundary for time frame expansion 3 implement an efficient PTM generation program using circuit partition technique and 4 2
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