Des Microproc Syst
Des Microproc Syst EECS 373
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AnalogDigital Conversion The real world is analog Interfacing a microprocessorbased system to realworld devices often requires conversion between the microprocessor s digital representation of values to an analog representation We will focus on conversions to and from analog voltages converting from electrical signals to other signals is the domain of sensors e g thermistors and transducers eg speakers Analog input signals are converted to digital values using analogtodigital converters ADCs Analog output signals based on digital values are generated using digitaltoanalog converters DACs ADCs and DACs are commonly available as singlechip devices that can be easily interfaced to microprocessor busses EECS 373 F99 Notes Outline Common conversion concepts Digitaltoanalog conversion circuits Analogtodigital conversion circuits 1998 1999 Steven K Reinhardt Basics The primary characteristic of a converter is its resolution expressed as the number of signi cant data bits on the digital side of the converter An nbit converter divides an analog voltage range into 2quot sections providing a resolution of 239quot times the voltage range Error is the difference between the analog voltage you believe a digital value represents and what that analog voltage acutally is As we will see shortly even an ideal converter introduces some error Accuracy refers to how close an actual converter is to an ideal converter Inaccuracies are another source of error The graph below shows the transfer function for an ideal 2bit ADC The input voltage range 0 Vref is divided into 22 4 sections so the ADC s resolution is 2392 14 of Vref Output Code ref Vref Vref o elt 3Vref 4 Input Voltage EECS 373 F99 Notes Quantization Error and LSBs Each code digital value represents a range of analog inputs e g the ADC will read 01 for any voltage in the range Vref4 Vref 2 The best we can do is assume that 01 means 3Vref8 Since the actual voltage could be as low as Vref4 or as high as Vref 2 there is a potential error of inef 8 This error is called quantization error Quantization error is inherent in the process of converting a continuous analog voltage to a finite number of discrete digital values Even an ideal converter introduces quantization error The absolute value of the quantization error in volts along with most other types of conversion errors depends on the voltage range ie the value of Vref and the resolution of the converter To normalize these parameters away errors are typically expressed in terms of the ideal analog voltage difference represented by a unit change in the digital value Since this unit change represents a change in the least significant bit of the digital value this voltage difference is referred to as an LSB Quantization error is always ilZ LSB 1998 1999 Steven K Reinhardt Accuracy Non linearity or absolute accuracy is the absolute deviation from the ideal transfer curve The total error bound is the sum of the magnitudes of the absolute accuracy and the quantization error Differential non linearity is the deviation of the difference between two consecutive codes from the ideal I LSB difference An absolute nonlinearity of i14 LSB could result in a differential nonlinearity of ilZ LSB The manufacturer may or may not specify a tighter bound on differential nonlinearity A converter is monotonic if an increasedecrease in the digital code always corresponds to an increasedecrease in the analog voltage A nonmonotonic converter by definition has gt ilZ LSB nonlinearity F ull scale error also called just scale error is the deviation from the ideal at full scale ie code is all 1 s Note that the ideal full scale is 2quot12quot Vref not Vref Typically fullscale error and its counterpart zero error can be adjusted to 0 using external potentiometers if necessary EECS 373 F99 Notes Conversion Time Conversion time is simply the time required to convert an input to an output Depending on the type of converter ie the internal design conversion time can range from a few nanoseconds to a few milliseconds As we will see shortly designing converters is athreeway tradeoff between cost conversion time and accuracy Some converters are internally pipelined to provide conversion rate gt 1conversion time ADCs Most ADCs provide an end of conversion signal that can be used as an interrupt input A sample anal holal ADC samples the analog input at the start of its conversion process and produces a code representing that specific voltage An averaging ADC produces a code representing the average input voltage over the conversion time Other ADCs may rely on you to not change the voltage e g with an external sampleandhold DACs DAC conversion time is typically specified as the settling time required for the output to reach the specified accuracy Most DACs can be driven faster than the specified conversion rate at a corresponding loss of accuracy 1998 1999 Steven K Reinhardt DAC Types Voltage divider Dull Vref 2to 4 decoder R f R J l l R l l R Fast Expensive requires 2quot resistors switches accuracy depends on matching all resistor values but not exact resistor values Guaranteed monotonic EECS 373 F99 Notes R2R Ladder V ref R wage MSB L Iout D3 E2 E1 Cheaper 2n resistors 71 switches Again accuracy depends on matching all resistor values but not exact resistor values Harder to enforce monotonicity consider 01 11 gt 1000 Provides current output opamp required to convert to voltage increases conversion time 1998 1999 Steven K Reinhardt ADC Types Flash Vref Vin R 3 R 39 2 priority encoder Doutp R l R VCC 0 ADC equivalent of voltagedivider DAC Same issues fast but expensive 2quot resistors 2quotl comparators EECS 373 F99 Notes S roximation SA V uccessive A ref out n Vin successive control approximation register binary search to match voltage Algorithm 1 Set successive approximation register to 0 2 Starting at MSB ip one bit to l 3 If DAC output lt Vin leave else reset to 0 4 go to next bit example 4bit ADC Vref 48V Vin 32V need fairly stable input through conversion process much cheaper than ash only one comparator 2quot or 211 resistors depending on DAC type conversion time gt n times DAC settling time 1998 1999 Steven K Reinhardt General Description The DACO830 is an advanced CMOSSiCr 8bit multiplying DAC designed to interface directly with the 8080 8048 8085 Z80 and other popular microprocessors A deposit ed siliconchromium R2R resistor ladder network divides the reference current and provides the circuit with excellent temperature tracking characteristics 005 of Full Scale Range maximum linearity error over temperature The cir cuit uses CMOS current switches and control logic to achieve low power consumption and low output leakage current errors Special circuitry provides TTL logic input volt age level compatibility Double buffering allows these DACs to output a voltage cor responding to one digital word while holding the next digital word This permits the simultaneous updating of any num ber of DACs The DACO830 series are the 8bit members of a family of microprocessorcompatible DACs MlCRODACTM For ap plications demanding higher resolution the DAC1000 series 10bits and the DAC1208 and DAC1230 12 bits are avail able alternatives Bl FEl39TM and MICRO DAC39I39M are trademarks of National Sem conductor Corporation ZSO is a registered trademark of Zilog Corporation yNational Semiconductor DAC0830DAC0831DAC0832 8Bit pP Compatible DoubleBuffered D to A Converters February 1995 Features I Doublebuffered singlebuffered or flowthrough digital data inputs l Easy interchange and pincompatible with DAC1230 series Direct interface to all popular microprocessors Linearity specified with zero and full scale adjust only NOT BEST STRAIGHT LINE FIT Works with i1OV referencefull 4quadrant multiplication Can be used in the voltage switching mode Logic inputs which meet TTL voltage level specs 14V logic threshold Operates STAND ALONE without uP if desired Available in 20pin smalloutline or molded chip carrier package 12bit Key Specifications I Current settling time 1 us I Resolution 8 bits I Linearity 8 9 or 10 bits guaranteed over temp I Gain Tempco I Low power dissipation I Single power supply 00002 FS C 20 mW 5 to 15 VDC Typical Application CONTROL BUS E39s WH ILE39 T71 vcc 15ch Allows easy upgrade to 12bit DAC1230 See application hints 057 17 1 18 I gum BU 5 DB LSB cacao 3 Vnzr 8080 BUS Connection Diagrams Top Views DuallnLine and SmallOutline Packages 12 loutz GND 1a 11 lmm TLH5608 21 DACDBSO 3831 IUBGZ ES 1 20 Vac fThls IS necessary for the 18 17 16 15 14 m 2 9 LE mm 12bit DAC1230 series to ILEEYTE1BYTE2 r 13 DI7MSE GND 3 1a sz permit interchanging from Vcc 20 12 lourz ma 39 4 1 5quot an 8 bit to a 12bit DAC 35 11loun m i quot 2 5 16 4 With No PC board changes WR1 10 GND on B 15 395 GND 9 Rb mu L53 7 M m6 and no software changes 4 5 6 7 8 VRE a 3 m M53 See applications section 9 TLH5608 1 Molded Chip Carrier Package WR2XFER DI4 DI5 m6 03 02 Di1 Dlo vREF TLH5608 22 1995 National Semiconductor Corporation TLH5608 RRD BSOM115Printed in U S A Sievewoo v 01 a peJeunaelqnoa elqnedwoo d Ilia8 zesoovaLssoovaoesoova Absolute Maximum Ratings Notes1 32 If MilitaryAerospace s ec ied devices are required lease contact the National Semiconductor sales OfficeDistributors for availability and specifications Supply Voltage V33 17 V93 Voltage at Any Digital lnput V33 to GND Voltage at VREF lnput 25V Storage Temperature Range 765 Cto 150 C Package Dissipation at TA 25 c Note 3 500 mW DC Voltage Applied to loun or lam2 Note 4 7100 mV to Vac ESD Susceptability Note 14 800V Lead Temperature solderingj 10 sec DuallnLine Package plastic DuallnLine Package ceramic Surlace Mount Package Vapor Phase 60 sec lnlrared 15 sec Operating Conditions Temperature Range Part numbers with LCN sullix Part numbers with LCWM sullix Part numbers with LCV sullix Part numbers with LCJ sullix Part numbers with LJ sullix Voltage at Any Digital input 260 300 219C 220 TMINSTA TMAX 0 Cto 70 C 0 Cto 70 C 0 Cto 70 C 40 C to 85 C 759010 1290 vac to GND Electrical Characteristics vREF 10000 vDC unless otherwise noted Boldface limits apply over tempera 25 C ture TMINSTA TMAx For all other limits TA vcc 475 vac V0 VD W v 1575v 0 12V W See 0 39 c to 15 ch 5 Limit Parameter Conditions 7 Note Unlts Tested Limquot Deslgn lelt Note 12 Note 5 Resolution 8 8 8 bits Linearity Error Max Zero and lull scale adjusted 4 8 710V3VREF 10v DACOBBOLJ amp LCJ 005 005 o FSR DACOBBZLJ amp LCJ 02 02 FSR DACOBBOLCN LCWM amp LCV 005 005 FSR DA00831LCN 01 0 1 FSR DACOBBZLCN LCWM amp LCV 02 0 2 FSR Dillerential Nonlinearity Zero and lull scale adjusted 4 8 Max 10VSVREFS1 10V DACOBBOLJ amp LCJ 01 0 1 FSR DACOBBZLJ amp LCJ 04 0 4 FSR DACOBBOLCN LCWM amp LCV 01 0 1 FSR DA00831LCN 02 0 2 FSR DACOBBZLCN LCWM amp LCV 04 0 4 FSR Monotonicity 710VSVREF LJ amp L0 8 8 bits V LCN LCWM amp LCV 8 8 bits Gain Error Max Using internal Rm 7 o 710V3VREF310V 0392 1 1 A FS Gain Error Tempco Max Using internal Rm 00002 00006 F87 Power Supply Rejection All digital inputs latched high as 5Vt 15 v 00002 00025 115V to 125V 00006 FSRV 0013 0015 Relerence lnput Max 1 5 20 20 kn Min 1 5 1 0 1 0 kn Output Feedthrough Error 20 Vppjl 100 kHz All data inputs latched low 3 mVpp Electrical Characteristics v 10000 A u REF u P ture TMm TASTMAx For all other limits TA 25 C Continued a vcc 475 vac v 5 v 5 A vcc 12 vac 15 See v 3975 V to 15 v 5 Parameter Conditions Dc Mme Tested Typ Limquot Design Limit N l 12 N l 6 e Notes 3 nniinii rl Output Leakage logn All data inputs LJ amp LCJ 10 100 100 A Current Max latched low LCN1LCWM amp LCV 50 1 00 1011 All data inputs LJ amp LCJ 100 100 A latched high LCN LCWM amp LCV 50 1 00 Output logn All data inputs 45 F Capacitance logr2 latched low 115 p logn All data inputs 130 F 1011 latched high 30 p DIGITAL Digital lnput Max Logic Low LJ 47 V 06 Voltages LJ 1575V 08 L0 475v 01 vDC LQJ 1575V 08 LCN LCWM LCV 095 08 Min Logic High LJ amp LCJ 20 20 V LCN LCWM ch 19 20 DC Digital lnput Max Digital inputs lt08V Currents LJ amp LCJ 7 50 7 200 7 200 LA LCN LCWM LCV 7160 7 200 LA Digital inputsgt20V LJampLCJ 01 10 10 LA LCN LCWM LCV 8 10 Supply Current Max LJ amp LCJ 12 35 35 mA Drain LCN LCWM LCV 17 20 Electrical Characteristics VREF 10000 VDG unless otherwise noted Boldface limlts apply over tempera ture TMINSTA TMAx For all other limits TA 25 C Continued vcc 12 Vpc5 vcc 5 vac vcc 1575 vac 015 VDC ak vcc 475 vac 57 I imquot symbOI Paramemr cond39l39ons Note Tested Design Tested Design Units WP WP Note 12 lel Iml Note 12 Umquot leI Note 5 Note 6 Note 5 Note 6 1S Current Setting VIL 0V VIH 5V 10 10 Ms TIme 1W Write and XFER VIL 0v VIH 5v 11 100 250 375 600 Pulse Width Min 9 320 320 900 900 1135 Data Setup Time VIL 0V VIH 5V 9 100 250 375 600 Min 320 320 900 900 15 Data Hold Time VIL 0v VIH 5v 9 30 50 S in 30 50 lcs Control Setup Time VIL 0V VIH 5V 9 110 250 600 900 Min 320 320 1100 1 100 13H Control Hold Time VIL 0V VIH 5V 0 0 Min 9 0 o 10 0 0 Note V we devme beyond 1ts specmed operatmg oond1t1ons Note 2 0 Ta mn ax1mum Note a T a TA Tne m aiiowabie power d1ss1pat1on a1 any temperature 15 Pp TJMAX mum or we number gwen m we Absoiute Max1mum Rat1ngswh1ohever1s Men For 0115 m ng dev1oeTJMAx 1250 piastm 01150an 1 m1 1 me N package 0115 number moveases 1g 1000w and 101 me v package 0115 number 15 12001111 Note 4 For current sw1toh1ng app11ca11gns both low and 10m must go 10 ground or me Vmuai Groundquot 01 an gpeva11gna1 ampi1i1evThei1neav1ty enm 1s degraded by appmx1ma1e1y v05 VREF For examp1e wag 10v1nen a1 mV oilsei v05 on low or low W111 mtvoduoe an add1t1onai 001 11nean1y enm Mm 5 1 m 1 11 m1 h111n11v a a Note 7 Guaranteed a1 veg 10 V93 and veg 1 v90 Note aTne0n11 an standsiov FuH Soaie mange uneam trim anu W pamouiav veg vaiue and 1a 1nd1oate 1ne 1me penmmance 01 me pan Tne Lmeamy Errorquot spemncangn 01 we 13100330 15 005 01 Pm MAX Tn1s guarantees 1na1 anev pengnmng a zem and 101 seats adjustment see Semmns 25 and 26 we pivot 01 Me 256 anaiog voitage outputs W111 each be w11n1n 005XVRE 01 a straight 11ne whmh passes through zem and 1011 soaie Note 9 Boidiaoe 1es1ed i1m1ts appiy 10 me LJ and LCJ 5qu pans oniy Note 10 A 100nA teakage current w1th Rm 20k and veg 10v corresponds 1a a zem error 01 100x 10 9X20x103gtlt10010 wh1oh1s 002 01 F3 Note 11 Tne enme wn1e puise must occur w11n1n1ne vahd data 1n1ema1 101 we specmed 1W 195 19H and 15 1g appiy Note 12 Typmais are a1 25 and represent most hkeiy pavamemo norm Note 13 Human body modei 100 pF d1soharged through a 15 kn ves1stov Switching Waveform VIH n5 E 50 ViL VIH DATA BITS Inun lourz Definition of Package Pinouts Control Signals All control signals level actuated CS ILE WR1 WR2 XFER Chip Select active low The in combina tion with ILE will enable W1 Input Latch Enable active high The ILE in combination with enables Write 1 The active low WR1 is used to load the digital input data bits DI into the input latch The data in the input latch is latched when W is high To update the input latch and W R1 must be low while ILE is high Write 2 active low This signal in combination with XFER causes the 8bit data which is avail able in the input latch to transfer to the DAC register Transfer control signal active low The XFER will enable W Rg Other Pin Functions DloDl7 39our lourz be Digital Inputs Big is the least significant bit LSB and Dl7 is the most significant bit MSB DAC Current Output 1 IOUT1 is a maximum for a digital code of all 1 s in the DAC register and is zero for all 0 s in DAC register DAC Current Output 2 IOUT2 is a constant minus IOUT1 or IOUT1IOUT2 constant full scale for a fixed reference voltage Feedback Resistor The feedback resistor is provided on the IC chip for use as the shunt Ics gt lt Icu 50 l 50 VREF Vcc GND SETTLED T0 i lz LSB TL H 5608 2 feedback resistor for the external op amp which is used to provide an output voltage for the DAC This onchip resistor should always be used not an external resistor since it matches the resistors which are used in the onchip R2R ladder and tracks these resistors over temperature Reference Voltage Input This input connects an external precision voltage source to the internal R 2R ladder VREF can be selected over the range of 10 to 10V This is also the analog voltage in put for a 4quadrant multiplying DAC application Digital Supply Voltage This is the power supply pin for the part VCC can be from 5 to 15VDC Operation is optimum for 15VDC The pin 10 voltage must be at the same ground potential as IOUT1 and IOUT2 for current switching applications Any difference of potential V05 pin 10 will result in a linearity change of VOS pin 10 3VREF For example if VREF 10V and pin 10 is 9mV offset from IOUT1 and IOUT2 the linearity change will be 003 Pin 3 can be offset i100mV with no linearity change but the logic input threshold will shift Linearity Error ACTUAL V2 LSB ERROR ANALOG OUTPUT ANALOG OUTPUT DIGITAL INPUT a End point test after zero and fs adj Definition of Terms Resolution Resolution is directly related to the number of switches or bits within the DAC For example the DA00830 has 28 or 256 steps and therefore has 8bit resolution Linearity Error Linearity Error is the maximum deviation from a straight line passing through the endpoints of the DAC transfer characteristic It is measured after adjusting for zero and fullscale Linearity error is a parameter intrinsic to the device and cannot be externally adjusted National s linearity end point test a and the best straight line test bc used by other suppliers are illustrated above The end point test greatly simplifies the adjust ment procedure by eliminating the need for multiple itera tions of checking the linearity and then adjusting full scale until the linearity is met The end point test guarantees that linearity is met after a single full scale adjust One ad justment vs multiple iterations of the adjustment The end point test uses a standard zero and FS adjustment proce dure and is a much more stringent test for DAC linearity Power Supply Sensitivity Power supply sensitivity is a measure of the effect of power supply changes on the DAC fullscale output Imsa ms nu snn INPUT 0 REGISTER I1 Dlz O1 LSD Dln 8 lSI x 11 39NOTE WHEN WHEN FIGURE 1 DACO b Best straight line t lz LSB ERROR BAND ACTUAL 1 L38 ERROR ANALOG OUTPUT IDEAL RESPONSE DIGITAL INPUT DIGITAL INPUT TLH5608 3 c Shifting fs adj to pass best straight line test Settling Time Settling time is the time required from a code transition until the DAC output reaches within i12LSB of the final output value Fullscale settling time requires a zero to fullscale or fullscale to zero output change FullScale Error Full scale error is a measure of the output error between an ideal DAC and the actual device output Ideally for the DA00830 series fullscale is VREF 1LSB For VREF 10V and unipolar operation VFULLSCALE 100000V 39mV 9961V Fullscale error is adjustable to zero Differential Nonlinearity The difference between any two consecutive codes in the transfer curve from the theoretical 1 L88 is differential nonlinearity Monotonic If the output of a DAC increases for increasing digital input code then the DAC is monotonic An 8bit DAC which is monotonic to 8 bits simply means that increasing digital input codes will produce an increasing analog output I 10 OUTPUTS FOLLOW D INPUTS O OND ATA AT D IS LATCHED J EI1n 0 LE n TLH5608 4 830 Functional Diagram 6 Typical Performance Characteristics Digital Input Threshold vs Temperature 24 20 20 2 16 a 15 g 3 g 12 g 12 r i g 03 g 03 lt3 2 E a 0 55 3515 5 25 45 65 85105125 TA AMBIENT TEMPERATURE C Gain and Linearity Error Variation vs Supply Voltage 25 0000 0025 005 0075 0100 CHANGE IN ERROR n TYPICAL WIDTH 0F WRI us 0125 o 5 1a 15 V55 SUPPLY VOLTAGE vac DAC0830 Series Application Hints These DAC s are the industry s first microprocessor com patible doublebuffered 8bit multiplying D to A converters Doublebuffering allows the utmost application flexibility from a digital control point of view This 20pin device is also pin for pin compatible with one exception with the DAC1230 a 12bit MICRODAG In the event that a sys tem s analog output resolution and accuracy must be up graded substituting the DAC1230 can be easily accom plished By tying address bit A0 to the ILE pin a twobyte uP write instruction double precision which automatically in crements the address for the second byte write starting with A0 1 can be used This allows either an 8bit or the 12bit part to be used with no hardware or software chang es For the simplest 8bit application this pin should be tied to VCC also see other uses in section 11 Analog signal control versatility is provided by a precision R 2R ladder network which allows full 4quadrant multiplica tion of a wide range bipolar reference voltage by an applied digital word 10 DIGITAL CONSIDERATIONS A most unique characteristic of these DAC s is that the 8bit digital input byte is doublebuffered This means that the data must transfer through two independently controlled 8 bit latching registers before being applied to the RZR lad der network to change the analog output The addition of a second register allows two useful control features First any DAC in a system can simultaneously hold the current DAC data in one register DAC register and the next data word in the second register input register to allow fast updating of the DAC output on demand Second and probably more important doublebuffering allows any number of DAC s in a Digital Input Threshold VS VCC 24 Write Pulse Width 55 35 15 5 25 45 65 85105125 TA AMBIENT TEMPERATURE C Gain and Linearity Error Variation vs Temperature 01 0075 005 0025 0 0025 CHANGE IN ERROR 1 005 D075 01 55 35 15 5 25 45 65 85 105125 TA AMBIENT TEMPERATURE 1 C 10 15 V55 SUPPLY VOLTAGE V Data Hold Time N 0 0 N c a VCC 150 VIH3V vclc 100 VIH3V Vcc5V 12V15V a a toquot TYPICAL DATA HOLD TIME ns 55 35 15 5 25 45 65 35105125 TA AMBIENT TEMPERATURE 1 C TLH5608 5 system to be updated to their new analog output levels simultaneously via a common strobe signal The timing requirements and logic level convention of the register control signals have been designed to minimize or eliminate external interfacing logic when applied to most popular microprocessors and development systems It is easy to think of these converters as 8bit writeonly mem ory locations that provide an analog output quantity All in puts to these DAC s meet TTL voltage level specs and can also be driven directly with high voltage CMOS logic in non microprocessor based systems To prevent damage to the chip from static discharge all unused digital inputs should be tied to VCC or ground If any of the digital inputs are inadvertantly left floating the DAC interprets the pin as a logic 11 DoubleBuffered Operation Updating the analog output of these DAC s in a doublebuff ered manner is basically a two step or double write opera tion In a microprocessor system two unique system ad dresses must be decoded one for the input latch controlled by the pin and a second for the DAC latch which is controlled by the XFER line If more than one DAC is being driven Figure 2 the E line of each DAC would typically be decoded individually but all of the converters could share a common XFER address to allow simultaneous updating of any number of DAC s The timing for this operation is shown Figure 3 It is important to note that the analog outputs that will change after a simultaneous transfer are those from the DAC s whose input register had been modified prior to the m command DAC0830 Series Application Hints Continued ADDRESS BUS sverMquot n Ac DISABLE SVSTEM srnan ANALOG OUTPUT 1 ANALOG OUTPUT 2 ANALOG OUTPUT n TIE TO LOGIC 1 IF NOT NEEDED SEE SEC 11 FIGURE 2 Controlling Mutiple DACs DATA BUS 7 Q g i 82 W amp R2 INPUT LATCH ANALOG OUTPUT UPDATED UPDATED llAC REGISTER LATCHED W 33 ILELOGIC 1quot TLH5608 6 FIGURE 3 The ILE pin is an active high chip select which can be de coded from the address bus as a qualifier for the normal E signal generated during a write operation This can be used to provide a higher degree of decoding unique control sig nals for a particular DAC and thereby create a more effi cient addressing scheme Another useful application of the ILE pin of each DAC in a multiple DAC system is to tie these inputs together and use this as a control line that can effectively freeze the out puts of all the DAC s at their present value Pulling this line low latches the input register and prevents new data from being written to the DAC This can be particularly useful in multiprocessing systems to allow a processor other than the one controlling the DAC s to take over control of the data bus and control lines If this second system were to use the same addresses as those decoded for DAC control but for a different purpose the ILE function would prevent the DAC s from being erroneously altered In a StandAlone system the control signals are generat ed by discrete logic In this case doublebuffering can be controlled by simply taking E and XFER to a logic ILE to a logic 1 and pulling W R1 low to load data to the input latch Pulling WR2 low will then update the analog output A logic 1 on either of these lines will prevent the changing of the analog output DAC0830 Series Application Hints Continued A 06 OUTPUT UPDATED ILE LOGIC 1 WR2 and XFER GROUNDED DATA LATCHED TLH5608 7 FIGURE 4 12 SingleBuffered Operation In a microprocessor controlled system where maximum data throughput to the DAC is of primary concern or when only one DAC of several needs to be updated at a time a singlebuffered configuration can be used One of the two internal registers allows the data to flow through and the other register will serve as the data latch Digital signal feedthrough see Section 15 is minimized if the input register is used as the data latch Timing for this mode is shown in Figure 4 Singlebuffering in a standalone system isachieved by strobing WR1 low to update the DAC with CS WR2 and XFER grounded and ILE tied high 13 FlowThrough Operation Though primarily designed to provide microprocessor inter face compatibility the MlCRODAC s can easily be config ured to allow the analog output to continuously reflect the state of an applied digital input This is most useful in appli cations where the DAC is used in a continuous feedback control loop and is driven by a binary updown counter or in function generation circuits where a ROM is continuously providing DAC data Simply grounding E and XFER and tying ILE high allows both internal registers to follow the applied digi tal inputs flowthrough and directly affect the DAC analog output 14 Control Signal Timing When interfacing these MICRODAG to any microprocessor there are two important time relationships that must be con sidered to insure proper operation The first is the minimum W strobe pulse width which is specified as 900 ns for all valid operating conditions of supply voltage and ambient temperature but typically a pulse width of only 180ns is adequate if VCC 15VDC A second consideration is that the guaranteed minimum data hold time of 50ns should be met or erroneous data can be latched This hold time is defined as the length of time data must be held valid on the digital inputs after a qualified via E W strobe makes a low to high transition to latch the applied data If the controlling device or system does not inherently meet these timing specs the DAC can be treated as a slow mem ory or peripheral and utilize a technique to extend the write strobe A simple extension of the write time by adding a wait state can simultaneously hold the write strobe active and data valid on the bus to satisfy the minimum W pulse width If this does not provide a sufficient data hold time at the end of the write cycle a negative edge triggered one shot can be included between the system write strobe and the W pin of the DAC This is illustrated in Figure 5 for an exemplary system which provides a 250ns W strobe time with a data hold time of less than 10ns The proper data setup time prior to the latching edge L0 to HI transition of the W strobe is insured if the W pulse width is within spec and the data is valid on the bus for the duration of the DAC W strobe 15 Digital Signal Feedthrough When data is latched in the internal registers but the digital inputs are changing state a narrow spike of current may flow out of the current output terminals This spike is caused by the rapid switching of internal logic gates that are re sponding to the input changes There are several recommendations to minimize this effect When latching data in the DAC always use the input regis ter as the latch Second reducing the V00 supply for the DAC from 15V to 5V offers a factor of 5 improvement in the magnitude of the feedthrough but at the expense of internal logic switching speed Finally increasing CC Figure 8 to a value consistent with the actual circuit bandwidth requirements can provide a substantial damping effect on any output spikes DAC0830 Series Application Hints Continued DATA BUS SYSTEM WRITE STROBE DACOB30 o ANALOG OUTPUT 9 x DATA VALID SYSTEM WRITE STHOBE 250 nsi m OUTPUT 0F ONESHOT DAc WI PULSE WIDTH 350 ns gti gti lt SYSTEM DATA HOLD TIME lt10ns I NORMAL ONE WAIT I WRITE moss 4 STATE 250 ns M me gt DATA HDLD TIME lt 5 TLH5608 8 FIGURE 5 Accommodating a High Speed System 20 ANALOG CONSIDERATIONS The fundamental purpose of any D to A converter is to pro vide an accurate analog output quantity which is representa tive of the applied digital word In the case of the DA00830 the output IOUT1 is a current directly proportional to the product of the applied reference voltage and the digital input word For application versatility a second output IOUTg is provided as a current directly proportional to the comple ment of the digital input Basically VREF X Digital Input I OUT 15 kn 256 I VREF X255 Digital Input OUT2 15 kn 256 where the digital input is the decimal base 10 equivalent of the applied 8bit binary word 0 to 255 VREF is the voltage at pin 8 and 15 km is the nominal value of the internal resist ance R of the R2R ladder network discussed in Section 21 Several factors external to the DAC itself must be consid ered to maintain analog accuracy and are covered in subse quent sections 21 The Current Switching R2R Ladder The analog circuitry Figure 6 consists of a siliconchromi um SiCr or Sichrome thin film R2R ladder which is depos ited on the surface oxide of the monolithic chip As a result there are no parasitic diode problems with the ladder as there may be with diffused resistors so the reference volt age VREF can range 10V to 1OV even if VCC for the device is 5VDC The digital input code to the DAC simply controls the posi tion of the SPDT current switches and steers the available ladder current to either IOUT1 or IOUT2 as determined by the logic input level 1 or quot0 respectively as shown in Figure 6 The MOS switches operate in the current mode with a small voltage drop across them and can therefore switch currents of either polarity This is the basis for the 4 quadrant multiplying feature of this DAC 22 Basic Unipolar Output Voltage To maintain linearity of output current with changes in the applied digital code it is important that the voltages at both of the current output pins be as near ground potential OVDC as possible With VREF 1OV every millivolt ap pearing at either IOUT1 or IOUT2 will cause a 001 linearity error In most applications this output current is converted to a voltage by using an op amp as shown in Figure 7 The inverting input of the op amp is a virtual ground creat ed by the feedback from its output through the internal 15 km resistor be All of the output current determined by the digital input and the reference voltage will flow through Rib to the output of the amplifier Twoquadrant operation can be obtained by reversing the polarity of VREF thus causing IOUT1 to flow into the DAC and be sourced from the output of the amplifier The output voltage in either case is always equal to OUT1 gtlt be and is the opposite polarity of the refer ence voltage The reference can be either a stable DC voltage source or an AC signal anywhere in the range from 10V to 1OV The DAC can be thought of as a digitally controlled attenua tor the output voltage is always less than or equal to the applied reference voltage The VREF terminal of the device presents a nominal impedance of 15 km to ground to exter nal circuitry Always use the internal be resistor to create an output volt age since this resistor matches and tracks with tempera ture the value of the resistors used to generate the output current IOUT1 DAC0830 Series Application Hints Continued VREF in in v O loun 0 Iouu FIGURE 6 DIGITAL INPUT Rib INTERNAL VnEF FIGURE 7 V 23 Op Amp Considerations The op amp used in Figure 7 should have offset voltage nulling capability See Section 25 The selected op amp should have as low a value of input bias current as possible The product of the bias current times the feedback resistance creates an output voltage er ror which can be significant in low reference voltage appli cations BlFET op amps are highly recommended for use with these DACs because of their very low input current Transient response and settling time of the op amp are im portant in fast data throughput applications The largest sta bility problem is the feedback pole created by the feedback resistance be and the output capacitance of the DAC This appears from the op amp output to the input and includes the stray capacitance at this node Addition of a lead capacitance CC in Figure 8 greatly reduces overshoot and ringing at the output for a step change in DAC output current Finally the output voltage swing of the amplifier must be greater than VREF to allow reaching the full scale output voltage Depending on the loading on the output of the am plifier and the available op amp supply voltages only i 12 volts in many development systems a reference voltage less than 10 volts may be necessary to obtain the full ana log output voltage range 24 Bipolar Output Voltage with a Fixed Reference The addition of a second op amp to the previous circuitry can be used to generate a bipolar output voltage from a fixed reference voltage This in effect gives sign signifi cance to the M88 of the digital input word and allows two quadrant multiplication of the reference voltage The polarity of the reference can also be reversed to realize full 4quad rant multiplication iVREFX iDigitaI Code iVOUT This circuit is shown in Figure 9 VUUT ou11 gtlt Hm VREF DIGITAL INPUThQ 256 TLH5608 9 This configuration features several improvements over ex isting circuits for bipolar outputs with other multiplying DACs Only the offset voltage of amplifier 1 has to be nulled to preserve linearity of the DAC The offset voltage error of the second op amp although a constant output voltage er ror has no effect on linearity It should be nulled only if absolute output accuracy is required Finally the values of the resistors around the second amplifier do not have to match the internal DAC resistors they need only to match and temperature track each other A thin film 4resistor net work available from Beckman Instruments Inc part no 6943R10KD is ideally suited for this application These resistors are matched to 01 and exhibit only 5 ppm C resistance tracking temperature coefficient Two of the four available 10 km resistors can be paralleled to form R in Figure 9 and the other two can be used independently as the resistances labeled 2R 25 Zero Adjustment For accurate conversions the input offset voltage of the output amplifier must always be nulled Amplifier offset er rors create an overall degradation of DAC linearity The fundamental purpose of zeroing is to make the voltage appearing at the DAC outputs as near OVDC as possible This is accomplished for the typical DAC op amp connec tion Figure 7 by shorting out be the amplifier feedback resistor and adjusting the V05 nulling potentiometer of the op amp until the output reads zero volts This is done of course with an applied digital code of all zeros if IOUT1 is driving the op amp all one s for IouTg The short around be is then removed and the converter is zero adjusted DAC0830 Series Application Hints Continued cc VREF O 39L 00 Csmv t S OP Amp cc 0 to Full Scale LF356 22 pF 4 5 LF351 22 pF 5 5 LF357 10 pF 2 5 24 k RESISTOR ADDED FROM INPUT TO GROUND TO INSURE STABILITY 1 FIGURE 8 DIGITAL CODE 128 I VOUT VREF VREF DACOB30 128 Rib V TLH5608 10 1LSB E 128 Input Code IDEAL VOUT MSB LSB VREF VREF THESE RESISTORSAREAVAILABLEFROM 1 1 1 1 1 1 1 1 VREF1LSB VREF1LSB BECKMAN INSTRUMENTS INCASTHEIR 1 1 O O O O O O V 2 IV I2 PART NO 6943R10KD REF REF 1 O O O O O O O O 0 01111111 1LSB 1LSB V V 0 011111 1LSB IRZ EFI1LSB o o o o o o o o vREF VREF FIGURES 26 FullScale Adjustment In the case where the matching of be to the R value of the R2R ladder typically i02 is insufficient for fullscale accuracy in a particular application the VREF voltage can be adjusted or an external resistor and potentiometer can be added as shown in Figure 10 to provide a fullscale adjust ment The temperature coefficients of the resistors used for this adjustment are an important concern To prevent degrada tion of the gain error temperature coefficient by the external resistors their temperature coefficients ideally would have to match that of the internal DAC resistors which is a highly impractical constraint For the values shown in Figure 10 if the resistor and the potentiometer each had a temperature coefficient of i 100 ppm C maximum the overall gain error temperature coefficent would be degraded a maximum of 00025 C for an adjustment pot setting of less than 3 of R 27 Using the DA0083O in a Voltage Switching Configuration The R2R ladder can also be operated as a voltage switch ing network In this mode the ladder is used in an inverted manner from the standard current switching configuration The reference voltage is connected to one of the current output terminals IOUT1 for true binary digital control IOUT2 is for complementary binary and the output voltage is taken from the normal VREF pin The converter output is now a voltage in the range from 0V to 255256 VREF as a function of the applied digital code as shown in Figure 11 FULL SCALE ADJUSTMENT DIGITAL INPUT VREF DAcoaao O Vout ZERO ADJUSTMENT 0 AMP Vus ADJ OVcc TLH5608 11 FIGURE 10 Adding FullScale Adjustment DAC0830 Series Application Hints Continued V 8m n R E quotV lt VDUT lt 256 Vac M53 quot7 a 211 2a 2a quot L83 0 DIo lounl 11 A 25 Vnc REFERENCE loun 12 TLH5608 12 FIGURE 11 Voltage Mode Switching This configuration offers several useful application advan tages Since the output is a voltage an external op amp is not necessarily required but the output impedance of the DAC is fairly high equal to the specified reference input resistance of 10 kn to 20 kn so an op amp may be used for buffering purposes Some of the advantages of this mode are illustrated in Figures 12 13 14 and 15 There are two important things to keep in mind when using this DAC in the voltage switching mode The applied refer ence voltage must be positive since there are internal para sitic diodes from ground to the IOUT1 and IOUT2 terminals which would turn on if the applied reference went negative There is also a dependence of conversion linearity and a a l 1 n u 2 All 2 vme vow 25vnc1 X2559 39V 10k 2k R2 AAA V V 30k 39 0 Voltage switching mode eliminates output signal inversion and therefore a need for a negative power supply 0 Zero code output voltage is limited by the low level output saturation volt age of the op amp The 2 k5 pulldown resistor helps to reduce this volt age VOS of the op amp has no effect on DAC linearity FIGURE 12 Single Supply DAC gain error on the voltage difference between VCC and the voltage applied to the normal current output terminals This is a result of the voltage drive requirements of the ladder switches To ensure that all 8 switches turn on sufficiently so as not to add significant resistance to any leg of the ladder and thereby introduce additional linearity and gain errors it is recommended that the applied reference voltage be kept less than 5VDC and VCC be at least 9V more positive than VREF These restrictions ensure less than 01 linearity and gain error change Figures 16 17 and 18 characterize the effects of bringing VREF and VCC closer together as well as typical temperature performance of this voltage switching configuration 25v nsrsnancs a mono v quot5F 1 mass 11 10k 39 A A V V V 10k 39 I 2 15 7 LF356 6 25 vac lt vow lt 25vnc TLH5608 13 D 0 V 25V 1 OUT 128 gt Slewing and settling time for a full scale output change is z 18 us FIGURE 13 Obtaining a Bipolar Output from a Fixed Reference with a Single Op Amp DAC0830 Series Application Hints Continued CHANGE IN ERROR 4 gt I 15VDc Av 4 DACOB3O VnEF 255 256 0 lt Vmc lt 25V 15V DAC0830 la com in 255 0 TLH5608 14 0 Only a single 15V supply required 0 Noninteractive fullscale and zero code output adjustments VMAX and VMIN must be i 5VDC and 20V 1 olncrementalOutputStep EWMAX VMIN D 255 VOUT VMAX VMIN VMIN 256 256 FIGURE 15 Single Supply DAC with Level Shift and Span Adiustable Output Gain and Linearity Error Variation vs Temperature 100 Gain and Linearity Error Variation vs Reference Voltage 04 Gain and Linearity Error 0 4 Variation vs Supply Voltage 0075 E 02 g 02 a 0050 vcc15v a Vcc 2 g 0025 E z 0 E 0 g o quotquot w 2 g 0025 4392 5 AGAIN ERROR 5 4050 15v39 VREF5V Vcc 12V VREF25V 0015 nnm 04 04 0100 0 2 4 s a 10 12 14 15 o 2 4 s s 10 55 35 15 5 25 45 55 as 105 125 TA AMBIENT TEMPERATURE C TLH5608 15 V00 SUPPLY VOLTAGE Vnc VREF REFERENCE VOLTAGE Vpc FIGURE 17 FIGURE 18 Note For these curves VREF is the voltage ap plied tO pin 11 IOUT1 with pin 12 IOUTZ grounded FIGURE 16 DAC0830 Series Application Hints Continued 28 Miscellaneous Application Hints These converters are CMOS products and reasonable care should be exercised in handling them to prevent catastroph ic failures due to static discharge Conversion accuracy is only as good as the applied refer ence voltage so providing a stable source over time and temperature changes is an important factor to consider A good ground is most desirable A single point ground distribution technique for analog signals and supply returns keeps other devices in a system from affecting the output of the DACs During powerup supply voltage sequencing the 15V or 12V supply of the op amp may appear first This will cause the output of the op amp to bias near the negative supply potential No harm is done to the DAC however as the onchip 15 kn feedback resistor sufficiently limits the current flow from IOUT1 when this lead is internally clamped to one diode drop below ground Careful circuit construction with minimization of lead lengths around the analog circuitry is a primary concern Good high frequency supply decoupling will aid in preventing inadver tant noise from appearing on the analog output Applications DAC Controlled Amplifier Volume Control DIGITAL INPUTS 20 O 15V DACOBBO VIN 256 D VOUT 0 When D 0 the amplifier will go open loop and the output will saturate 0 Feedback impedance from the input to the output varies from 15 k to 00 as the input code changes from fullscale to zero Overall noise reduction and reference stability is of particu lar concern when using the higher accuracy versions the DAC0830 and DAC0831 or their advantages are wasted 30 GENERAL APPLICATION IDEAS The connections for the control pins of the digital input reg isters are purposely omitted Any of the control formats dis cussed in Section 1 of the accompanying text will work with any of the circuits shown The method used depends on the overall system provisions and requirements The digital input code is referred to as D and represents the decimal equivalent value of the 8bit binary input for exam ple Binary Input Pin 13 Pin 7 D MSB LSB Decimal Equivalent 1 1 1 1 1 1 1 1 255 1 O O O O O O O 128 O O O 1 O O O O 16 O O O O O O 1 O 2 O O O O O O O O O Capacitance Multiplier 32 0 15V L Ceuuw I 1 TLH5608 16 256 CEQUIV C1 1 0 Maximum voltage across the equivalent capacitance is W 256 D 0 Cg is used to improve settling time of op amp limited to Applications Continued Variable f0 Variable Go Constant BW Bandpass Filter R5 A AA H6 VVV ALL 7777 1 RIquot 15k 15k Rn R A A VVV 7 15k TLH5608 17 KB 256 KB 2H Fl Fl K 1 0 f0 QO Q 113deW 27rR1C 256 FlQK 1 27TR1C2RQ R1 Fl where C1 Cg C K R 6 and R1 Fl of DAC 15k 5 HO 1 for RIN R4 R1 O Range of f0 and Q is Z 16 to 1 for circuit shown The range can be extended to 255 to 1 by replacing R1 with a second DA00830 driven by the same digital input word 0 Maximum f0 gtlt Q product should be 200 kHz DAC Controlled Function Generator 15v AMPLITUDE mam 15v 10quot C 100 1 25 gIUNTEP WAVE ur svmmmv T mm 15v WAVESHAPE TRIM 1 v Fioour 5 5 TillWAVE 4 c quot 0 N OUTPUT 4 2k 5 aouk 15V 20 7 5 2 LM392 on SQUARE WAVE OUTPUT LH5608 18 o DAC controls the frequency of sine square and triangle outputs fOI39V V Of sq are a eo t tand 3 u w v u u Fl Fl 25620k0 OMAX OMIN P 1 2 0 255 to 1 linear frequency range oscillator stops with D 0 0 Trim symmetry and waveshape for minimum sine wave distortion 16 Applications Continued Two Terminal Floating 4 to 20 mA Current Loop Controller N4001 5009 IL nAcoasu 92mm LM329I GND LM329D a 109 4 mA s lom lt 20 mA TLH5608 19 I V 1 D H1R2 OUT REF R1 256 M R3 c DACOBSO linearly controls the current flow from the input terminal to the output terminal to be 4 mA for D 0 to 1994 mA for D 255 c Circuit operates with a terminal voltage differential of 16V to 55V 39 P2 adjusts the magnitude of the output current and P1 adjusts the zero to full scale range of output current c Digital inputs can be supplied from a processor using opto isolators on each input or the DAC latches can flowthrough connect control lines to pins 3 and 10 of the DAC and the input data can be set by SPST toggle switches to ground pins 3 and 10 DAC Controlled Exponential Time Response 15 9 20 Vcc loun a income I VFINAL VnEF lourz 12 0 VIN VINITIAL 10 3 C 4 15 rlt thr 3 4 347 f VFINAL VINITIAL 1 D 255 Taronmnc 15 V iV0UT VNi VlN TLH5608 20 c Output responds exponentially to input changes and automatically stops when VOUT VIN c Output time constant is directly proportional to the DAC input code and capacitor C c Input voltage must be positive See section 27 17 Ordering Information Temperature Range 0 C to 70 40 C to 85 C 55 C to 125 C Non 005 FSR DACO830LCN DACO830LCM DACO830LCV DACO830LCJ DACO830LJ Linearity 01 FSR DACO831LCN 02 FSR DACO832LCN DACO832LCM DACO832LCV DACO832LCJ DACO832LJ Package Outline N20A Molded DIP M208 Small Outline V20A Chip Carrier J20A Ceramic DIP PhYSical Dimensions inches millimeters 0985 0 025 4 25019 gt M X W L mmmWWWWWH 0220 0310 5588 1874 wmmmmmmmm 0005 0020 0127 0500 A TV 003710005 004010127 0005 0055i0005 gt lt 02904320 gt 0127 13970127 0020 0050 MAX fuses 0120 GLASS SEALANT MIN 0 508 152 4 ll 1 I I I 0200 5000 V m V MAX x 7 quot 95 i5 86 94 A 0000 0012 3810 W32quot 0 203 0 305 mm 3175 5000 0310 0410 gt 0000 00100003 7074 1041 1524 0457i0 76 MAX 0010 ENDS w 2540i0254 J20A1FlEV M Ceramic DualInLine Package J Order Number DAC0830LCJ DAC0830LJ DAC0832LJ or DAC0832LCJ NS Package Number J20A Physical Dimensions inches millimeters Continued 0496 0512 12598 13005 0394 0419 10000 10643 LEADNO1 000000000 1 2 3 4 5 5 7 0 9 0010 MAX 0254 0291 0299 7391 7595 0010 0029 0093 0104 0254 0737 quot 23621642 quot j 0004 0012 0 MAX TYP j in ALL LEADS 0102 0305 L N E L SEATING f T i PLANE 0004 0014 0009 0013 7 0050 0014 0020 0102 0016 0050 TVP 0229 0330 ALL LEAD TIPS m 1356 A 6 1270 gt 035670500 TYP ALL LEADS TYP ALL LEADS TYP Mm 0203 M2OBREV F Molded Small Outline Package M Order Number DAC0830LCM or DACOS32LCM NS Package Number MZOB I 1013 1040 quot092 X 3quot 2573 2042 2337 x 0752 0032 10005 MAX OP 00130127 m m RAD PIN N01IDET G 25 0005 PIN No DEM I i0127 0200 O OPTION 1 I 7112 I MIN 0090 OPTION 2 0300 0320 2286 1020 0128 we NON 0040 OPTION 2 gt lt 9 lt 0355 1524 1010 4 4quot m 165 TYP TYP I l N 0145 0200 l 3003 5000 1 3 95 5 00094315 90 O004 1 I 0020 170220 0301 TYP 010000010 1 I 0125 0140 0500 00600005 204010254 31310003 3075 0550 MIN 0340 39 152410127 045710070 quot325 0015 1016 8255 41381 N20A REV G Molded DuallnLine Package N Order Number DAC0830LCM DAC0831LCN or DAC0832LCN NS Package Number N20A 19 DMF 5000 SERIES USERS MANUAL OCTOBER 1996 OPTREX CORPORATION DMF 5000 TABLE OF CONTENTS 1 OUTLlNE OF LCD MODITI F 4 11 FEATURF 4 2 SPFCTFTCATION 21 MAXIMUM RATING 22 ELECTRICAL CHARACTFRIQTTF 6 23 LCD DRIVING VOLTAGE AND CONNECTION 24 EL BACK LIGHT O 25 CCT BACK LIGHT 10 3 IN39I39FRFAW n 31 INTERFACE CONNECTION II 32 BLOCK DIAGRAM 15 33 SIGNAL TTMTNG 17 34 MEMORY ADDRESS AND DISPLAY POSITION IR 34 MemoryAddress andDisplayanitinn 3 342Memory Address andDisplayanitinn 7n 3 4 3 RAM Map 7 7 4 SOLDERING JUMPER SETTINI 7 z 41 INITIAL SETTING 73 42 EXPLANATION OF EACH SOT DER INC JUMPER 74 5 COMIVIUNICATION BETWEEN CPU AND MOUTH F 26 51 DATA TRANSMISSION METHOD 75 51 Status nr 7 52 COMMAND 7g 52 39nmmanrlT ivt 78 522 Description of nmmnml Q7 5221 Pointer Set nmmnml 27 5222 Control Word Set Comm1an 22 5223 Mode Set nmmnml Q4 5224DisplayMode Set nmmnnrl 25 5225 Cursor Pattern Select nmmnml 95 5226Data Auto WriteData Auto R or 215 522 7Data WriteDarn R m QR 5228 Screen Pnrkin 2 5229 Screen Cop 40 522IOBitSetBitR v t 41 531N1T1ALIZE 42 54 CHARACTER GENERATOR 44 541 Character Generator ROM 44 542 User Character Generator RAM 46 55 ATTRIBUTF 48 551 Attribute Fun tinn 48 552 Procedure ofsem39ng attrihm 49 6 APPLICATION CIRCUqu 1 61 MODULE LOCATED IN THE MEMORY AREA OF CPU 50 62MODULE LOCATED IN THE IO AREA OF CPII 51 63 INTERFACE CIRCUIT WITH PPII QT lt7 7 INSTALLATTnN z 8 CAUTION S AND HANDLlNG PRECAUTTan 2 81 HANm ma 3 82 STORAGE 3 83 OPFRATTON 3 84 OTHFR lt3 9 PROFR AM FYAWI F 4 1 Outline of LCD Module The DMF 5000 series dot matrix graphic LCD modules include an LCD controller a display RAM a character generator ROM an drive circuim These modules are suitable for copiers facsimiles PBXs marine instruments and messaging displays for various instruments 11 Features 1 Excellent readability and high contrast ratio 2 bit parallel bus interface 3 Builtin LCD controller T6963C and display RAM 8K byte 4 Large graphic display 5 Various attribute functions 6 Builtin 128 word character generator ROM and 256 word character generator RAM 7 Wide operating temperature range 8 Compact and easily mountable on any equipment 2 Specification 2 1 Maximum Ratings VccVss Supply Voltage LCD Drive Operating CCT T emperature Backlight Storag e Make sure not to exceed above maximum rating values under the worst probable conditions 22 Electrical Characteristics Standard Value Item Symbol Condition Min Typ Max Unit Supply Voltage VccVss Ta 25 C 475 5 525 V Logic Supply VccVee Ta 25 C 10 28 V Voltage LCD DING VccVadj Ta 25 C 8 26 v 100 Ta 25 C 10 20 mA Supply Current lee Ta 25 C 4 8 mA lnp Voltage H ViH Ta 25 C Vac22 Vcc V Level Input Voltage V1L Ta 25 C 0 08 V L Level 23 LCD Driving Voltage and Connection The LCD Panel is driven by the voltage VccVee or VccVadj Adjustable Vee or Vadj is required for contrast control and temperature compensation Table 21 is a recommended power supply voltage for the LCD drive VccVee or Vc cVadJ Table 21 Temp 0 C 10 C 25 C 40 C 50 C Note Model DMFSOOlN Series 232V 203V 183V 1128 Duty VccVadj DMF5002N Series 224V 197V 176V 11 1 2 Duty VccVadj DMFSOOSN Series 196V 184V 174V 1128 Duty VccVadj CCT Backlight DMFSOOSN Series 148V 136V 123V 164 Duty VccVee DMFSOl 0N Series 144V 136V 128V 164 Duty VccVee CCT Backlight Consult your local Optrex representative to obtain detailed specifications for each module part number Example of power Supply Connection 5V C Vcc DMFSOOSN GND DMFSOI ON C VS 5 Series lt R Vee VR Tr lt 1 2V 0 4 5V C Vcc GND DMFSOOIN C Vss DMFSOOZN R DMFSOOSN lt Serles VR Vadj 21 V C Vee Note R SKQ IOKQ VR IOKQ ZOKQ Tr 28A 1162Y etc 24 EL Back Light Recommended Inverter and Connection 5VDC rN OUT DMFSOOIN 0 DMFSOOZN NEL D3249 DMFSOOSN GND GND NEC GND 0 SERIES NELD3249 Specification O1N GNDO OUTO Bottom View Maximum Rating 5 Acceptable Operating Range I Input Voltage I 355VDC I I Load Lamp Surface Area I 5083 cm2 I 25 CCT Back Light Recommended Inverter and Connection 24VDC VJN OUT 1 CXA1301 TDK OUT 2 GND GND I 39 OUT GND I CXA1301 Specification 0 VJN OUT 1 0 OUT 2 O 0 GND OUT GND 0 Bottom View Maximum Ratings Acceptable Operating Range 24t12VDC DMFSOOSN DMFSOI 0N SERIES 3 Interface 31 Interface Connection WR L CD H ComandWrite CD L DataWrite HL Font Size Select H 6x 8 DOT EL Back Light Terminal for DMF 5001N 5002N 5005N Series I Pin No I Symbol I Level I Function I 21 I EL I I EL Power Supply I 22 I EL I I EL Power Supply CCT Back Light Terminal for DMF 5003N Series CCT Back Light Terminal for DMF 5010N Series Pin No Layout DMFSOOIN 5002N Series 1 2 o 0 Top View 19 20 El 21 El 22 EL DMF 5005N Series Top View 22 O o 21 EL DMF 5003N Series 1 CCT 1 Top View 4 J ST VHR4N B 4PVH 0139 B 4P S VH DMF 5010N Series BP4VH BP4SVH 32 GND Block Diagram D0 1 D COM DRV p LCDP S S T6961B D7 lt gt p CONTROL RT gt LSI 5E gt T6963C SEGDRV CA3 p T7778A HAL1 gt RESET gt NOTE FS p For DMFSOOlN 5002N 5003N series only 2 For DMFSOOSN 5010N series only 8KBYTE 3 DMFSOOBN 5010N SRAM are already included 4 Availa e or DMFSOOlN 5002N 5005N gt To LSl gt BIAS 5 CIRCUIT gt 4 OCT EL EL BACKLIGHT BACKLIGHT UNIT EL FOJL 33 Signal Timings CE RD WR Pulse LCP LRP LWP Conditions VCC 5 r 025V GND 0V Ta 25 C Bus Timing CA3 l ths CDH 7 4 CE t 7 tCP tRP tWP 7 tDS D0 to D7 WRITE tDH D0 to D7 READ tAcc tOH 34 Memory Address and Display Position 6 X 8 Font The relationship between display memory address and display position on the LCD module is defined in section 341 note this is for 6x8 character font Graphic home address GH number of graphic area GA text home address TH and number of text area TA are defined by Control Word Set command The position of GH TH is described in 343 RAM map 341 Memory Address and Display Position Text Display Ex 240 x 64 DOT TA 28H GA 28H TH amp GH Within 0000H lFFFH TH TH 27H TH TA 27H TH7TA TH7TA27H 1AllllAllllAlllAAIAlllllllllllllllll 40 Character Graphic Display EX 240 X 64 DOT TA 28H GA 28H TH amp GH Within 0000H lFFFH a GH 27H I GHGA GHGA27H I l l I 64 Dot l l l GH63GA GH63GA27H I 1lllAAlAlAAlAIAllIAlllllllllAAlAlAIA 40 x 6 240 Dot Note In case of graphic display 8 bit data is as follows MSB LSB I D7 I D6 I D5 I D4 I D3 I D2 I D1 I DO I Gmphic Data 1442443 144444444424444444443 lnv alid Data Valid Data 8 X 8 Font The relationship between display memory address and display position on the LCD module is defined in section 342 note this is for 8x8 character font Graphics home address GH number of graphic area GA text home address TH and number of text area TA are defined by Control Word Set command The position of GH TH is described in 343 RAM map 342 Memory Address and Display Position Text Display Ex 240 x 64 DOT TA lEH GA lEH TH amp GH Within 0000H FPF H TH TH1DH THTAlDH TH7TA TH 7TA lDH 1AllllAllllAlllAAIAlllllllllllllllll 30 Character Graphic Display EX 240 X 64 DOT TA1EH GA lEH TH amp GH Within 0000H 1F FFH GH TH1DH l THTA1DH l l l l l t 64 Dot l l l l GH63GA TH7TA1DH l 1AllllAllllAlllAAIAlllllllllllllllll 30 x 8 240 Dot Note In case ofgraphic display 8 bit data is as follows MSB LSB l D7 l D6 l D5 l D4 l D3 l D2 l D1 I DO I lt GTaphic Data 14444444444444244444444444443 Valid Data 343 RAM Map The Display RAM is built into the module and display data is Written to this display RAM The builtin controller LSlT6963C automatically reads the display RAM and sends the appropriate data to LCD drivers The Control Word Set command text home set text area set etc defines the RAM area which is read by the controller 151 making the RAM map programmable by the user If more than 1 screen can be stored in the RAM Vertical scrolling and paging is easily performed by resetting text home andor graphic home address DMFSOOO series have 8K byte builtin RAM located at address 0000H lFFFH and the following is an example of RAM mapping 240 x 64 DOT 0000H OFOOH l OOOH 1 COOH lFFFH Graphic RAM Area OOOOH OEFFH Attribute RAM Area OFOOH OFFFH Text RAM Area 1 OOOH lBFFH CG RAM Area 1CO0H IFFFH GH OOOOH 6 x 8 Font 15 screen 8 x 8 Font 20 screen Text For 256 characters TH lOOOH 6 x 8 Font 96 screen 8 x 8 Font 128 screen CGRAM For 128 words Offset register et data 03H 4 Soldering Jumper Setting 41 Initial Setting Initial setting for Font and Column are described in Table 41 Table 41 Dot Duty Bias Font Column DMFSOOlN Series 160x 128 1128 112 8x8 32 valid 20 DMF5002N Series 128x 112 1112 112 8x8 32 valid 16 DMF5003N Series 160x 128 1128 112 8 x 8 32 valid 20 DMFSOOSN Series 240 x 64 164 19 6 x 8 64 F SH valid 40 DMFSOl 0N Series 240 x 64 164 19 6x 8 64 F SH valid 40 42 Explanation of Each Soldering Jumper Column designate by soldering jumper 16 17 for DMF5001N 5002N 5003N Series 12 13 for DMF 5005N 5010N Series CharacterFont designate by soldering jumper 18 19 for DMF5001N 5002N 5003N Series F4 FS for DMF5005N 5010N Series DMF5001N 5002N 5003N Series DMF5005N 5010N Series 32 40 H L H H set 1617H 12H13L Character Font Character Font 5x8 6X8 7X8 8x8 5X8 6X8 7X8 8X8 18 H L H L 14 H L H L 19 H H L L FS H H L L Initial set 18 19 L Initial set 14 L FS Pull up H Note H 5V Vcc L 0V Vss FS lO terminal pin no 19 for designate the Font from outside ofthe module 1umper Position DMFSOOIN L H G D 16 G D 17 G D 18 0 D I9 DMFSOOIN DMFSOOSN H L GED I9 GED I8 CHJD 17 GJD 16 DMF5003 DMFSOI 0N Note DMFSOOZN 19 18 17 16 L 00 Hggaa DMFSOOZN DMFSOOSN 12 13 14 DMFSOOSN 12 13 14 HOD L66 DMFSOI 0 All drawings are PWB S bottom View 5 Communication between CPU and Module 51 Data Transmission Method The builtin LCD controller T6963C is operating asynchronously to the CPU clock The following procedure is required for data transmission between the module and the CPU 1 Command with 2 byte data 2 Command with 1 byte data Status Read Status Read YES Data Write Dl lower 8 bit Status Read YES Data Write D2 upper 8 bit Command Write Status Read 3 Command with no data Status Read Command Write Command Write 4 Data Auto WriteData Auto Read STA2 STA3 should be checked between all data and command Refer 5226 Data Auto WriteData Auto Read 5 Screen Peeking Screen Copy STA6 should be checked just after Screen Peeking Screen Copy Refer 52289 Screen Peeking Screen Copy 511 Status Read Status of the controller LSl should be checked between all command and data in order to complete a communication cycle CAD H and RD L with the CPU The status can be read from 8 bit data lines D0 to D7 by setting STAO Check capability of instruction STAO0 Disable Busyl execution 39 Enable STAl Check capability of data read or STAl 0 Disable Busy2 data write Enab e STA2 Check capability of data read STA20 Disable DAV only effective in auto mode 1 Enable STA3 Check capability of data write STA30 Disable RDY only effective in auto mode Enable STA4 7 7 STA5 Check possibility of controller STA50 Disable CLR operation Ena e STA6 Address pointer is out of graphic STA6l Out of Error area on screen peeking and graphic area screen copy command STA7 Check the condition of blink STA70 Display off Blink Normal display On Status Register STA7 STA6 STA4 STA3 STA2 STAl STAO MSB LSB 52 Command 521 Command List Command Code Execution Command Description Time D7 D6 D5 D4 D3 D2 D1 D0 Note 1 Pointer Set 0 0 l 0 0 N2 N1 N0 N2 N1 N0 Status Check 0 0 1 Cursor pointer set 0 1 0 Offset register set 1 0 0 Address pointer set Control 0 1 0 0 0 0 N1 N0 N1 N0 Status Check Word Set 0 0 Text home address set 0 1 Text area set 1 0 Graphic home address set 1 1 Graphic area set CG CG ROM Mode Mode Set 1 0 0 0 CG N2 N1 N0 CG l CG RAM Mode 32xlfOSC N2 N1 N0 Graphic and Text 0 0 0 OR 0 0 l EXOR 0 l 1 AND 1 0 0 Text only attribute capability Display 1 0 0 1 N3 N2 N1 N0 N30 Graphic display off 32x1IDSC Mode 1 Graphic display on N20 Text display off 1 Text display on N10 Cursor display off 1 Cursor display on N00 Cursor blink off 1 Cursor blink on Cursor 0 0 0 N2 N1 N0 N2 N1 N0 specify the number of cursor 32x1fOSC Pattern lines Select EX N2 N1 N0 0 0 0 1 line cursor bottom line 1 1 1 8 line cursor 8x8 dot cursor Command Code Execution Command Description time D7 D6 D5 D4 D3 D2 D1 D0 MAX Note 1 Data Auto 1 0 1 1 0 0 N1 N0 N1 N0 32X1IDSC ReadWrite 0 0 Data auto WIite set 0 1 Data auto read set 1 Auto reset A er this command continuous data can be WIitten or read Address pointer automatically increment Data 1 1 0 0 0 N2 N1 N0 Data readWIite command for 1 byte 32x1IDSC ReadWm39e N20 Address pointer updown 1 Address pointer unchanged N10 Address pointer up 1 Address pointer down N00 Data WIite 1 Data read Screen 1 1 1 0 0 0 0 0 Transfer display data to data stack for read Status Check Parking from CPU Screen Copy 1 1 1 0 1 0 0 0 1 line displayed data which address is indicated Status Check by address pointer is copied to graphic RAM area Bit 1 1 1 1 N3 N2 N1 N0 Setreset command for abit in the address Status Check SetquotReset pointed by address pointer N30 Bit reset 1 Bit set N2 N1 N0 indicate the bit in the pointed address 000 is LSB and 111 is MSB Note 1 Status check between all commands and data is recommended though execution time for several commands are specified in above command list For the commands with status check in execution time execution time is not specified because it is variable depending on the internal operations of the controller LSI 2 In case of 2 screen mode Screen copy command cannot be used 522 Description of Command 5221 Pointer Set Command Command is selectedby setting 1 at selected bit N2 N1 N0 Command D1 D2 0 0 l Cursor pointer set Column position Row Position 0 l 0 Offset regis ter set Address 00H 1 0 0 Address pointer set Address Lower Address Upper a Cursor Pointer Set The cursor is displayed at the position specified by the D1 D2 The cursor position is shifted only by this command and does not shift by other commands Dl D2 are specified as follows Dl Horizontal cursor position counted by character 5 8 dot widthcharacter specified by hard setting refer 4 Soldering Iumper Setting MSB ofDl is neglected and 127 is the maximum D2 Vertical cursor position counted by character 8 dot high character 1 st row of lower half screen is llH Upper 3 bit are neglected and 32 is the maximum Note Please note that the cursor position should be within actual display area b Offset Register Set The offset register set command is used to determine the character generator RAM area The upper 5 his in start address of CG area is set as the lower 5 bits ofDl and the upper 3 bits ofDl are neglected D2 should be 00H Refer to section 54 Character Generator for details of the CG RAM c Address Pointer Set The address pointer set command is used to indicate the start address for writingreading data tofrom the builtin RAM The address should be located in the actual RAM area specified by individual specifications Refer to 343 RAMMAP 5222 Control Word Set Command Home address of display RAM Text Graphic and areas are defined by this command a Text Home Address Set TH This command defines the starting address of display RAM for text display The data in the text home address TH is displayed at the home position of display left end character on lst row b Text Area Set TA This command defines the number of columns by Dl Text area can be defined independently from the number of characters fixed by hardware setting of controller LSI The text area is usually defined as the actual number of characters on LCD display so addressing can be continuous in the text area c Graphic Home Address Set GH This command defines the starting address of display RAM for the graphic display The data in the Graphic home address GH is displayed at the home position of display left end 8 bits in lst line When using the attribute function the graphic home address indicates the starting address of distribute RAM area d Graphic Address Set GA This command defines the number of columns by D1 The graphic area can be defined independently from the number of characters fixed by hardware setting of controller LSI If the graphic area is defined as the actual number of columns on the LCD display the address in graphic area can be continuous and the RAM area can be used without ineffective areas Note that the Graphic area will be different for depending on character font settings even if horizontal dot number is the same 5223 Mode Set Command No data 1 o o 0 CG N2 N1 N0 Mode set command selects character generator CG ROM ModeCG RAM Mode and combination of textgraphic display CG Command 0 CG ROM Mode Builtin 128 character CG ROM code 00H 7FH and builtin CG RAM for 128 characters can be used 1 CG RAM Mode Builtin CG RAM for 256 characters code 00H FEH can be used When CG ROM Mode is selected character code 00H 7FH is selected from builtin CG ROM and 80H FFH is automatically selected from CG RAM Logically OR EXOR and AND of graphic and text display can be displayed by this command Only text display is attributed because Attribute RAM is located in Graphic RAM area Refer 55 Attribute 5224 Display Mode Set Command No data 1 o o 1 N3 N2 N1 N0 Display mode is selected from combination of following 4 bits by setting 1 at the selected bit After hard reset all displays are inhibited N 0NlN2N30 5225 Cursor Pattern Select Command No data 1 o 1 o 0 N2 N1 N0 When cursor display is ON this command selects the cursor pattern from 1 line width cursor to 8 line width cursor block 1 line width cursor 8 line width cursor 5226 Data Auto WriteData Auto Read No data 1 0 l This command is convenient to send full screen data or receive full screen data from builtin RAM After setting auto mode data write or read command is not necessary between each data Data auto write or read command should follow the address pointer set and address pointer is automatically increment by 1 after each data After sending or receiving all data auto mode reset is necessary to return normal operation because all data is regarded display data and no command can be accepted in the auto mode Don t care Note Status check for auto mode STA2 STA3 should be checked between each data Auto reset should be performed after checking STA3l Data Auto Write only Refer to the following chart START i no no Status check STAOl STAll yes Dl address data no i Status check STAOl STAll D2 address data m l Status check STAOl STAl 1 Address pointer set 21H i no no Status check STAOl STAll Data Auto write BOH Status check STA2l STA3l l D ata L Status check STA2l STA3l D ata L Status check STA2l STA3l Status check STA2l STA3l Auto reset B 2H 5227 Data WriteData Read Dl Note D1 is necessary only for data Write This command is used for data write from CPU to builtin RAM and data read from builtin RAM to CPU Data writedata read should be executed after setting address by address pointer set command Address pointer can be automatically increment or decrement by setting this comman Don t care This command is necessary for each 1 byte data 5228 Screen Parking No data 1 1 1 o o o o o This command is used to transfer displayed 1 byte data to data stack and this 1 byte data can be read from CPU by data read command So logical combination data of text and graphic display on LCD screen can be read by this command Status STAG should be checked just after screen peeking command If the address determined by address pointer set command is not in graphic RAM area this command is ignored and status flag STAG is set The procedure to read displayed data using this command is as follows START L no Status check STAOl STAl 1 yes Dl address data L no no Status check STAOl STAll yes D2 address data i no no Status check STAOl STAl 1 yes Address pointer set i no Status check STAOl STAl 1 yes Screen peeking command EOH Status check STA60 yes Status check STAOl STAll yes Data read command E6 Screen peeking command can be used for getting hard copy of LCD display Another application of this command is that modified CG is set in the CG RAM area by reading combination data of text and graphic data and writing to CG RAM area For example CG for reverse character is made by this method 5229 Screen Copy No data 1 1 1 o 1 o o o 1 low data displayed in LCD screen can be copied to the graphic RAM area specified by address pointer set comman Start point of 1 low data in the screen is determined by the address pointer set command If attribute for text display is set by Mode Set command screen copy command can not be used Status STA6 should be checked just after this command If the address determined by address pointer set command is not located in graphic RAM area this command is ignored and status flag STA6 is set The procedure to copy the displayed data using this command is as follows START L no Status check STAOl STAll i yes i no Dl address data Status check STA60 i no yes Status check STAOl STAl 1 yes I no D2 address data Status check STAOl STAll L no L yes Status check STAOl STAl 1 End yes Address pointer set 24H I Note In case of 2 screen mode Screen copy command cannot be used 52210 Bit Set Bit Reset N 0 data 1 N3 N2 N1 N0 One bit in the 1 byte data specified by address pointer set command can be set or reset Plural bits in the 1 byte data cannot be setreset at a time Description N3 N3 1 bit set N3 0 bit reset N2 N1 N0 N2 N1 N0 specify the bit for N2 N1 N0 setreset 0 0 0 bit 0 LSB 0 0 1 bit 1 0 1 0 bit 2 1 1 1 bit7 MSB 53 Initialize Initialize of controller LST T6963C is required for Mode set Control word set after power on Following is the one example of initialize procedure of 240 X 64 dot display Command CD D7 D6 D5 D4 D3 D2 D1 I DO Note Power on Power on Hard reset Use reset terminal RESET L lmSec minimum a er Vcc 2 475V Mode set 1 1 0 0 0 0 0 0 0 OR mode Control word set Graphic home position set 0 0 0 0 0 0 0 0 0 Graphic home Graphic home position 0000H 0 0 0 0 0 0 0 0 0 address command 1 0 l 0 0 0 0 l 0 Number of graphic area set 0 0 0 0 1 0 1 1 1 Graphic 30 X 8 dots 0 0 0 0 0 0 0 0 0 Number of area 1 0 l 0 0 0 0 l 1 Command Text home position set 0 0 0 0 0 0 0 0 0 Text home Text home position 1000H 0 0 0 0 1 0 0 0 0 address 1 0 l 0 0 0 0 0 0 Command Number of text area set 0 0 0 0 1 0 1 1 1 Number of area Text 30 column 0 0 0 0 0 0 0 0 0 Command 1 0 l 0 0 0 0 0 l Initialize end Data w1ite Address pointer set 0 0 0 0 0 0 0 0 0 Graphic home Address pointer 0000H 0 0 0 0 0 0 0 0 0 address 1 0 0 l 0 0 l 0 0 Command Data write Graphic 0 0 1 0 1 0 1 0 1 Data Command 1 l l l 0 0 0 0 0 0 l 0 l 0 l 0 l 0 Data Command 1 l l l 0 0 0 0 0 Address pointer set 0 0 0 0 0 0 0 0 0 Text home Address pointer 1000H 0 0 0 0 1 0 0 0 0 address 1 0 0 l 0 0 l 0 0 Command Data w1ite Text 0 0 0 0 1 0 1 1 1 1 Data Command 1 l l 0 0 0 0 0 0 p 0 0 0 1 1 0 0 0 0 Data Command 1 l l 0 0 0 0 0 0 l l 0 0 l l l 0 0 Display Mode Set TextGraphic on Note 1 Status check 7 should be inserted between all command and data Display mode set register is cleared no display mode by the hard reset and no display is appeared on LCD panel And just after Display Mode set 9CH written data is displayed on the LCD 54 Character Generator 541 Character Generator ROM Character generator ROM for 128 characters is builtin this module Character code map ROM Code 0101 LSO ASO 542 User Character Generator RAM The character generator RAM is the builtin RAM which can be used as character generator after writing character pattern by program The part of builtin RAM can be used as User CG RAM for 256 characters by selecting CG RAM Mode or for 128 characters by selecting CG ROM Mode 1 Position of User CG RAM The upper 5 bits in start address of User CG RAM NNNNN is defined by Pointer Set command Offset register set and following 2048 byte are defined as User CG RAM area when CG RAM Mode is selected 1024 byte address NNNNN10000000000 NNNNNI l l l l l l l l l l is defined as User CG RAM area when CG ROM Mode is selected 2 Writing to User CG RAM Character pattern of specified CG code can be written in the pointed address by Pointer Set command Address pointer set 8 byte data should be sent to following 8 byte address for 1 character MSB LSB NNNNNM 144442444443 1444444442444444443 1442443 Upper 5 bit defined by CG code 8 bit Automatically pointer Set command Ml for CG ROM Mode scan for display Offset register set M0 for CG RAM Mode 3 Display Pattern in User CG RAM Character pattern can be displayed by sending CG code with Data Write command But Display Mode Set for text display should be selected before using CG In case that CG ROM Mode is selected character pattern is selected from builtin CG ROM when MSBl 00H 7FH and from User CG RAM when MSB0 80H F In case that CG RM Mode is selected all character patterns are selected from User CG RAM OOHFFH 4 Relation between User CG RAM Address and CG code and Character Pattern When character pattern is written to User CG RAM relation between CG code and User CG RAM address is shown in the following chart Character Code RAMAddress forUser CG CharacterPattern 76543210 FEDCBA9876543210 76543210 M0000000 NNNNNM0000000000 00000000 001 00001000 010 00000100 011 01111110 100 00000100 101 00001000 110 00000000 111 00000000 M0000001 NNNNNM0000001000 01000010 001 01100110 010 01011010 011 01011010 100 01000010 101 01000010 110 01000010 111 00000000 M0000010 NNNNNM0000010000 01000010 001 01100010 010 01010010 111 00000000 11111111 NNNNN11111111000 01110000 01000000 01111010 00011010 01111010 00001110 00001010 00001010 Note 1 Character code in User CG RAM is located from 80H to FFH in case of CG ROM Mode and from 00H to FFH in case of CG RAM Mode So M in above chart is as follows M1 CG ROM Mode M0 CG RAM Mode Note 2 NNNNN is the upper 5 bits in start address of User CG RAM defined by Pointer Set command Offset Register Set Note 3 It must be careful so that User CG RAM area should not be rewritten by display data etc 55 Attribute 551 Attribute Function This module has attribute function for Reverse display Blink in text display mode Attribute data is written in the Graphic area defined by Control word set command Graphic home address set and Graphic area set So Text display only Mode should be selected by Mode Set command and graphic display cannot be displayed The attribute data of the lst character in Text area is written at the lst byte in graphic area and attribute data of nth character is written at the nth 1 byte in Graphic area Attribute function is defined as follows Attribute RAM lbytel N3N2N1No Don t care 552 Procedure of setting attribute The example of the procedure of setting attribute is as follows Command 7 C D7 D6 D5 D4 D3 D2 D1 D0 Note Graphic display off 1 1 0 0 0 0 Graphic home 0 0 0 0 0 0 0 0 0 home address address set 0 0 0 0 1 1 0 0 0 1400H 1 0 1 0 0 0 0 1 0 command Attribute data write 0 0 0 0 0 0 0 0 0 address 1400H 0 0 0 0 1 1 0 0 0 address pointer 1 0 0 1 0 0 1 0 0 attribute data write 0 0 0 0 0 0 0 0 0 command attribute 1 1 1 0 0 0 0 0 0 data write command 0 0 0 0 0 1 1 0 0 1 1 1 0 0 0 0 0 0 Mode s et 1 1 0 0 0 0 1 0 0 Graphic display on 1 1 0 0 0 1 Don t care 6 Application Circuits Following diagrams are the examples of interface circuit with CPU TMPZ84CO0P Z80 CMOS 4MHZ For the interface to 16 bit CPU please refer the diagram using PPI LSI TMP82C55 61 Module Located in the Memory Area of CPU The module can be directly connected to CPU data bus as following diagram Control signals of the module are made from MREQ WR RD signals of CPU and chip select signal from address decoder LSB of address bus A0 can be used as CD commanddata selection signal TC74l lC244 x 3 TC74HC32 Address Decoder LCD Module TMPZ84CO0P 4MHZ CMOS TC7 4HC32X4 62 Module Located in the 0 Area of CPU The module can be controlled as the device located in the 10 area Control signals are made from IORQ WR RD of CPU and the chop select signal from address decoder LSB of address bus A0 can be used as CD commanddata selection signal TC74l lC244 x 3 LCD Module Address Decoder TMPZ84CO0P 4MHZ CMOS TC7 4HC32X4 63 Interface Circuit with PPI L8 The module can be interfaced with PM LSI as shown in the following diagram 8 bit data bus of the module is connected to A port of PPI and control signals CD CE WR RD are sent from upper 4 bit of C port In following diagram PM is located in the 10 address area but interface between CPU and PM can be left for user s des1gn TC74l 1 C244 x 3 Address Decoder A3 to A0 TMPZ84CO0P 4MHZ CMOS TMP82C55 LCD Module TC74HC32X2 7 Installation For installation of the module please use four mounting holes located at the corners of PCB or Bezel The Bezel is not intended to be used as a cosmetic purpose A proper protective cover lens over the LCD surface and a proper enclosure are recommended to be used in order to preventLCD surface polarizer from scratching or staining 8 Cautions and Handling Precautions 81 Handling a V Refrain from strong mechanical shock or applying force to the display plane It may cause malfunction or damage of LCD b In the case of leakage of liquid crystal material avoid ingestion contact of skin If liquid crystal material sticks to skin wash with alcohol and rinse thoroughly with water Note that LCD surface polarizer is very soft as is easily damaged Do not press the polarizer surface with hard object d The polarizer and adhesive used for lamination may be attacked by some organic solvent WhenLCD surface becomes dirty wipe softly with absorbent cotton soaked in benzene Protect the LCD module from the electro static discharge It will damage CMOS LSI in the module 0 V I2 V 82 Storage a Do not leave the LCD module in high temperature especially in high humidity for a long time It is recommended to store it in the place where the temperature is between 03C and 35 C and where the humidity is lower than 70 store the module without exposure to the direct sunlight Caquot V 83 Operation a Do not connect or remove LCD module to main system with power applied b Power supplies should always be turned on before the independent input signal sources are turned on and input signals should be turned off before power supplies are turned off 84 Others a Avoid condensation of water it may cause mis operation or corrosion of electrode Ultraviolet ray cut filter is necessary for outdoor operation c Do not exceed the maximum ratings under the worst probable conditions with respect to supply voltage variation input voltage variation environmental temperature etc Caquot V 9 Program Example DMF 5001 DEMO 87921 0000 0000 0001 0002 0003 001 0 8800 2000 4000 6000 A000 0000 F3 0001 31 8800 0004 3E 82 0006 D3 03 0008 3E 80 000A CD 016C 000D 000D CD 00DA 0010 21 2000 001 3 01 01 40 001 6 0016 CD 01 56 0019 7E 001A D6 20 MACRO80 34 01Dec80 Page 1 TITLE DMF5001 DEMO 87921 DEAF5001 DEMO MACHJNE VER 10 1987926 PROGRAM NAME D5001 MAC 280 ASEG ORG 0 PA EQU 0 PB EQU 1 PC EQU 2 cw EQU 3 LCD EQU 10H DATA4 EQU 0A000H D1 LD SP STACK 8255 MODE SET LD A82H OUT CW A LD A80H CWR BC1 620 MAINI 0 CALL SAREAD LD MEL SUB 20H 001CCD0178 001F 23 0020 OB 0021 78 0022 B1 0023 C2 001 6 0026 21 4000 0029 01 0140 DMF 5001 DEMO 87921 MACRO80 34 002C 002C CD 0156 002F 7E 0030 D6 20 0032 CD 0178 0035 23 0036 OB 0037 78 0038 B1 0039 C2 002C 003C 21 6000 003F 01 0140 0042 0042 CD 0156 0045 7E 0046 D6 20 0048 CD 0178 004B 23 004C 0B 004D 78 004E B1 004F C2 0042 0052 3E B2 0054 CD 016C 0057 CD 010D 005A 21 A000 005D 01 0A00 0060 0060 CD 0156 0063 7E 0064 CD 01 A4 0067 CD 0178 006A 23 CALL DWRT 1NC HL DEC BC LD AB OR C JP NZMAIN1 0 LD HLDATA2 LD BC1 620 MA1N11 01 Dec80 Page 11 CALL SAREAD 1D AXHL SUB 20H CALL DWRT NC El DEC BC LD AB OR C JP NZMAIN1 1 LD HLDATA3 LD BC1 620 MATN1 2 CALL SAREAD LD AXHL SUB 20H CALL DWRT TNC HL DEC BC LD AB OR C JP NZMAIN12 LD A0B2H CALL CWRT AUTO WRITE RESET CALL GMSET LD HLDATA4 LD BC1 6 20 8 MATN1 3 CALL SAREAD 1D AXHL CALL BCG DATA CHANGE CALL DWRT NC El DEC BC 0063 78 LD A B 006DB1 OR C 006E C2 0060 JP NZMAIN13 0071 3E B2 LD A0B2H 0073 CD 016C CALL CWRT AUTO WRITE RESET 0076 16 00 LD D0 COUNTER RESET 0078 MAIN50 0078 7A LD AD 0079 PE 00 CP 0 007B C2 0084 JP NZMAIN51 007E 21 0000 LD HL0000H DATA1 START 0081 C3 00A4 JP MAIN60 0084 MAIN51 0084 PE 01 CP 1 0086 C2 008F JP NZMAIN52 0089 21 0140 LD HL0140H DATA2 START 008C C3 00A4 JP MA1N60 DMF 5001 DEMO 87921 MACRO80 34 01 Dec80 Page 12 008F MAIN52 008F PE 02 CP 2 0091 C2 009A JP NZMAIN53 0094 21 0280 LD HL0280H DATA3 START 0097 C3 00A4 JP 60 009A MAIN53 009A 3E 98 LD A98H 009C CD 016C CALL CWRT 009F 16 00 LD D0 00A1 C3 00BA MAIN20 00A4 MAIN60 00A4 7D LD AL 00A5 CD 0178 CALL DWRT 00A8 7C LD AH 00A9 CD 0178 CALL DWRT 00AC 3E 40 LD A40H TEXT HOME ADDRESS 00AE CD 016C CALL T 00B1 3E 94 LD A94H TEXT ON 00B3 CD 016C CALL CWRT 00B6 14 INC D 00B7 C3 00BA JP MA1N20 SWITCH CHECK LOOP 00BA MAIN20 00BA CD 0199 CALL SWOFF 00BD MAIN30 00BD 0E 01 LD CPB 00BF CD 01 E2 CALL INPUT 00C2 CB 47 BIT 0 A 00C4 C2 00D1 JP NZMAIN40 00C7 CD 018A CALL SWON SW ON CHECK 00CA B7 OR 00CB CA 00 78 JP ZMAIN50 NEXT MODE 00CE C3 00BD JP MAN30 00D1 MAN40 00D1 01 9C40 LD BC40000 00D4 CD 01 F4 CALL DELAY 00D7 C3 0078 JP MAN50 TMSET TEXT MODE SET 00DA TMSET 00DA 3E 00 LD A0 D1 00DC CD 0178 CALL DWRT 00DF 3E 00 LD A0 D2 00E1 CD 0178 CALL DWRT 00E4 3E 40 LD A40H TEXT HOME ADRS 00E6 CD 016C CALL CWRT 00E9 3E 14 LD A14H D1 20 DMF 5001 DEMO 87921 MACRO80 34 01Dec80 Page 13 00EB CD 0178 CALL DWRT 00EB 3E 00 LD A0 D2 00F0 CD 0178 CALL DWRT 00F3 3E 41 LD A41H AREA SET 00F5 CD 016C CALL CWRT 00F8 3E 00 LD A0 D1 00FA CD 0178 CALL DWRT 00FD 3E 00 LD A0 D2 00FF CD 0178 CALL DWRT 0102 3E 00 LD A0 D2 01 04 CD 016C CALL CWRT 0107 3E B0 LD A0BOH AUTO WRITE SET 01 09 CD 016C CALL CWRT 010C C9 RET GMSET GRAPHIC MODE SET 010D GMSET 010D 3E00 LD A0 D1 010F CD 0178 CALL DWRT 0112 3E 05 LD A05H D2 01 14 CD 0178 CALL DWRT 01 17 3E 42 LD A42H GRAPHIC HOME ADRS 01 19 CD 016C CALL CWRT 011C3E14 LD A14H D120 011E CD 0178 CALL DWRT 0121 3E 00 LD A0 D2 01 23 CD 0178 CALL DWRT 0126 3E 43 LD A43H AREA SET 01 28 CD 016C CALL CWRT 012B 3E 00 LD A0 D1 012D CD 0178 CALL DWRT 0130 3E 05 LD A05H D2 01 32 CD 01 78 CALL DWRT 0135 3E 24 LD A24H ADDRESS POINT SET 01 37 CD 016C CALL CWRT 013A 3E B0 LD A0BOH AUTO WRITE SET 013C CD 016C CALL CWRT 013F C9 RET DMF 5001 DEMO 87921 MACRO80 34 01 Dec80 Page 14 SREAD STATAS READ 0140 SREAD 01 40 F5 PUSH AF 01 41 C5 PUSH BC 01 42 D5 PUSH DE 0144 3E 01 ID A1 0146 D3 00 OUT PAA 0148 SRDOO 0148 DB 10 1N ALCD 014A E6 03 AND 3 014CEE 03 CP 3 014E C2 0148 JP NzSRD00 0151 E1 POP HL 0152 D1 POP DE 0153 C1 POP BC 0154 F1 POP AF 0155 C9 RET 0156 SREAD 0156 E5 PUSH AF 0157 C5 PUSH BC 0158 D5 PUSH DE 0159 E5 PUSH HL 015A 3E 01 A1 015C D3 00 OUT PAA 015E SARDO 015E DB 10 TN ALCD 0160 08 AND 8 0162 EE08 CP 8 0164 C2 015E 1P NzSARD0 0167 E1 POP HL 0168 D1 POP DE 0169 C1 POP BC 016A F1 POP AF 016B C9 RET 01 6C CWRT 016C CD 0140 CALL SREAD PUSH AF 0170 3E 01 ID A1 0172 D3 00 OUT PAA 0174 F1 POP AF 0175 D3 10 OUT LCDA 0177 C9 RET DMF 5001 DEMO 87921 MACRO80 34 01Dec80 Page 1 5 0178 DWRT 0178 CD 0140 CALL SREAD 017B DWRTO 017B F5 PUSH AF 017C 3E 00 LD A0 017E D3 00 OUT PAA 018 F1 P0P AF 0181 D3 10 OUT LCDA 0183 C9 RET 0184 DWRT2 0184 CD 0156 CALL SAREAD 0187 C3 017B 1P DWRTO SWON MANUAL SW ON CHECK 018A SWON 018A 0E 01 LD CPB 018C CD 01E2 CALL INPUT 018F CB 4F BIT 1A 0191 CA 0197 JP zSWON0 0194 3EFF LD A0FFH 0196 C9 RET 0197 SWONO 0197 AF XORA 0198 C9 PET SWOFF MANUAL SW OFF CHECK 0199 SWOFF 0199 OF 01 LD CPB 019B CD 01E2 CALL INP 019E CD 4F BIT 1A 01A0 CA 0199 JP zSWOFF 01A3 C9 RET BIT CHANGE 01A4 BCG 01A4 C5 PUSH BC 01A5 06 00 LD B0 01A7 CB 47 BO BIT 0A 01A9 CA 01 AE 1P zB1 01AC CBF8 SET 7B 01 AE CB 4F B1 BIT 1A 01B0 CA 01B5 JP zB2 01 B3 CB F0 SET 6B 01B5 CB 57 B2 BIT 2A 01 B7 CA 01 BC JP zB3 01BA CB E8 SET 5B 01BC CB 5F BIT 3A 01BE CA 01C3 B3 JP ZB4 01 C1 CB E0 SET 4B 01 C3 CB 67 B4 BIT 4A 01 C5 CA 01CA JP zB5 DME 5001 DEMO 87921 MACRO80 34 01Dec80 Page 16 01 C8 CB D8 SET 3B 01 CA CB 6F B5 BIT 5A 01 CC CA 01DI JP zB6 01CF CB D0 SET 2B 01D1 CB 77 B6 BIT 6A 01D3 CA 01D8 JP zB7 01D6CB C8 SET IB 01D8 CB 7E B7 BIT 7A OlDA CA OlDF JP zB8 OlDD Co SET oB OlDF B8 OlDF 78 ID AB 01Eo C8 POP BC 01 E1 C9 RET INPUT C PORT ADDRESS 01E2 NPUT 01E2 C5 PUSH BC 01 E3 D5 PUSH DE 01E4 1NPUT1 01E4 06 01 ID BIo 01E6 ED 78 IN AC 013 57 LD DA 01E9 NPUT2 01 E9 ED 78 IN AC 01EBBA CP D 01EC C2 01E4 JP NZ11PUT1 OIEF 10 F8 mm 2 01F1 D1 POP DE 01F2 C1 POP BC 01F3 C9 RET DELAY BC LOOP CNT 171BC442510 6 SEC 01F4 DELAY 01F4 C5 PUSH BC 01F5 D5 PUSH DE display Application Note AN029 0 products group Interfacing and setup of Toshiba T6963C Introduction The Toshiba T6963C is a very popular LCD controller for use in small graphics modules It is capable of controlling displays With a resolution up to 240x128 Because of its low power and small outline it is most suitable for mobile applications such as PDAs MP3 players or mobile measurement equipment A number of Hitachi Liquid Crystal Display modules have this controller builtin these include the SP12N002 amp SP14N001 Although this controller is small it has the capability of displaying and merging text and graphics and it manages all the interfacing signals to the displays Row and Column drivers Other related documents Interfacing and setup of the Sanyo LC7981 controller Application Note AN030 Driving Displays With T6963C and Touch Panel from a PIC Application Note AN037 Datasheet ofT6963C rtn39 WWW emimn tn hiha m39 1 m Di nlav Driver leen 20030618 T6963C d atasheetpdf Application Note ANVOZQ August 2004 Page i of 23 display IrII slpll qg elli Interfacing and setup of Toshiba T6963C products group Contents 1 rnMTFMTlt 7 INDEX OF FICUPE 4 INDEX OF TARI E 4 1 BASIC nu H AND m mm H 5 5 1 ANn TERMS IN 5 13 DOCUMENT n Iw 6 2 CONNECTION TO A DISPLAY 7 21 SINGLEDUAL SCAN 7 22 TIMINK SIPNAI 7 2215mm ltrm 7 222 DUAL QPAN 8 3 CONNECTION TO A MPU AND DISPLAY MEMORY 31 DISPLAY MEMORY VRAM q 9 312 r39IN IUK 1D 32 MPU PnNNn TInN 10 321 GENERAL 10 322 PINS FDR MPU 1o Apphcauon Note ANVOZQ August 2004 Page 2 of23 H H I display Inspire the Nexi Interfacing and setup ofToshiba T6963C products group 4 SETTING UP THE TIMEquot 11 41 GFNFRAI THE anmr 11 411 GENERAL PIN 11 412APPLYING POWERTO Tu TM 12 42 HARDWARE CONSIDERATIONS FDR SE39I39I39ING UP THE T6963 FOR A DISPLAY 421 PIN 422 FONT SIZE NUMBER OF COLUMNS AND PIXELS PER COLUMN 43 I INPA DI PIA 14 431 GENERAL Annl n rnmnmn ANn nan 14 432 COMMANDS TO SET THE DISPLAY l E 15 433 MEMORY AND FONT ltI 16 434 MODE SEI IU 8FH 16 435 THE MODE SEI 90H TO 9F 17 43 18 437 Hum 7n 438 ADDITIONAL PnMMANn 7n 5 EXAMPLE OF EXTERNAL PM EPATInM 21 6 SUMMARY 22 Apphcauon Note ANVOZQ August 2004 Page 3 of23 HITACHI lnspire the Nexf Interfacing and setup ofToshiba T6963C display products group Index of Fiures Figure 1 Block diagram ofa typical display 39 6 Figure 2 Example for Reset irmiit 12 Figure 3 Example ofMemory allocation 1 5 Figure 4 Combinations for Mode Set Functions from 90h to 9Fh 17 Figure 5 Euro Symbol as quotDot Character 71 Index of Tables Table 1 39 39 and terms Table 2 Pins for memory 10 1 0 Table 3 Pins for MPU Table 4 Pins With general functions Table 5 Overview of Command quotSet Control Word Table 6 The Mode Set Commands from 80h to SF Table 7 Possible external character generator area 18 Table 8 Dependence of CG RAM area and character code 19 Application Note ANVOZQ August 2004 Page 4 of 23 H H I display lnspi re the Nexi Interfacing and setup ofToshiba T6963C products group 1 Basic Operations and Information 11 Main Features Resolution up to 240x128 pixels or 320x64 pixels Capable of displaying text and graphics Buildin character generator ROM CGROM With 128 predefined characters 8 bit parallel bus and signal lines for interfacing to a micro controller Data and commands from and to the micro controller are multiplexed on this bus Capable of controlling up to 64 kByte of external display memory Hitachi s SPl4 amp SP12 have 8 kBytes of VRAM Duty Ratio for display multiplex driving in the range of l16 up to l128 Current consumption 34 mA maximum Buildin crystal oscillator Operating temperature 720 to 70 degrees Celsius 12 Abbreviations and terms in this document and needs to be T6963C It contains prede ned characters Which can easily be table of them can be found in the T6963C datasheet a Hexadecimal Format T6963C and thus all are via this RAM a resolution and the second number the vertical resolution Table 1 Abbrevia om and terms Application Note ANVOZQ August 2004 Page 5 of23 H I Q display mphe the Next Interfacing and setup of Toshiba T6963C products group 13 Document Overview Although the T6963C is a controller for small LCDs it has a lot of functions and options This section gives a short overview of the structure of this Application Note The document is split into the three sections which can be identified in the block diagram below The first part of the Application Note is about connecting a display to the T6963C The second part is about connecting and communicating with a micro controller and external display memory The third part is about the T6963C imelf It describes the options this LCD controller has available and how to set them up T T6963C Dlsplay w o S U a 2 i External RAM up to 64k Figure I 39 Block diagram of a typical display neighborhood Of course the connection to a display and micro controller needs some software code A brief description of the necessary code can be found in the T6963C section of this document Software means commands from a MPU The T6963C can not operate without a controlling element usually a MIPU The T6963C is controlled by commands and data from the MIPU It is not possible to load instructions or a program into the T6963C imelf Every operation and setup parameter must be sent by the MPU Every software consideration or command mentioned in this Application Note means a set of commands or data sent by the MIPU Application Note AN029 August 2004 Page 6 of 23 H H I display lnspi re the Nexi Interfacing and setup ofToshiba T6963C products group 2 Connection to a Display 21 SingleDual Scan The T6963C is used to control the row and column drivers of monochrome STN graphic displays with a resolution up to 240x128 pixels The display row and column drivers are connected to the T6963C via a number of timing signals and one or two serial data lines These signals vary dependent on whether it is a Single Scan display or a Dual Scan display Single Scan displays with a resolution of for example 240x128 pixels have three column drivers and two row drivers eg column drivers can drive 80 lines and the row drivers 64 lines Dual Scan displays are separated in an upper and a lower half A 240x128 display would still have 2 row drivers but 6 column drivers Three drivers are used for the upper half and three for the lower half of the display The Dual Scan method is used to increase the contrast on STN displays The smaller the LCD area lower duty the lower driving voltage needs to be to achieve the same contrast as a single scan device Both the SPl2N002 amp SPl4N001 are single scan devices Please nd more information about activepassive display technologies in Application Note AN 002 22 Timing Signals 221 Single Scan DUAL Pin 54 This signal must be driven high when using a Single Scan display SDSEL Pin 62 This signal is used to choose the data transmission method to the display row and column drivers It must be driven high when the data is sent by evenodd separation method and low when simple serial method is used The display s datasheet should give information if this is necessary Usually it is not HOD 51 ED Pin 52 Serial data signal lines for the column drivers lfSDSEL is low data sending method is simpleserial all data comes from the ED line If SDSEL is driven high evenodd separation is used ED provides the data for the even columns and HOD for the odd columns On many displays these signals are just called D0 and D1 or serial data HSCP Pin 53 Shi Clock for serial data The edge typically the falling of this signal causes e current column driver to take one or two depends on SDSEL bits from the data lines in its input latch Other names CL2 CP Clock XCK Shi Clock LP Pin 55 Latch Pulse for column drivers Shi clock pulse for row drivers The edge typically the falling of this signal causes all column drivers to output the latched signals to the display lines This edge also causes the current row driver to switch to the next row The time delay between the output of the column drivers and the switching to the next row is called Horizontal nondisplay period Other names of LP Horizontal Sync Load CLl CDATA Pin 56 Synchronous signal for the row drivers The edge typically the falling of this signal indicates a new frame The frequency of this signal is called Frame Rate Other names First Line Marker Frame Vertical Sync YD Line Clock FR Pin 57 This signal must be provided to both the row and column drivers They use this signal to change the polarity of the LCD driving voltage to prevent a DC component applied to the Liquid Crystal material This signal is called MSignal on most displays For details please see section 412 Applying Power to the system Application Note ANVOZQ August 2004 Page 7 of23 H H I display lnspi re the Nexi Interfacing and setup ofToshiba T6963C products group 222 Dual Scan DUAL Pin 54 For a Dual Scan display this pin must be driven low SDSEL Pin 62 Same as for Single Scan Drive this signal low when the display data transmission method shall be simple serial High will cause transmission by evenodd separation LOD Pin 49 shared with ce0 HOD Pin 51 ED Pin 52 Serial display data signals When SDSEL is low Data transmission by simple serial method all data to the columns is provided via the ED line If SDSEL is high data transmission by evenodd separation the EDline provides the data for the even columns in the upper and lower part of the display HOD provides data for the odd columns in the upper area of the display and LOD provides data for the odd columns in the lower half of the display On displays data signals usually are just called Data or Serial Data HSCP Pin 53 LSCP Pin 50 shared with cel Shi clocks for serial data HSCP is for the upper half of the display an LSCP is for the lower area of the display Function is the same as for Single Scan The edge usually the falling of these signals causes the current column driver to take data bits in its input latch Other names CL2 CP Clock XCK Shift Clock LP Pin 55 Latch Pulse for column driver Shi clock pulse for row driver The edge usually the falling of this signal causes all column drivers to output the latched signals to the lines This edge also causes the row drivers to switch to the next row Other names Horizontal Sync Load CLl CDATA Pin 56 Synchronous Signal for the row drivers The edge typically the falling of this signal indicates a new frame This signal is also called First Line Marker and the frequency is called Frame Rate Other names Frame Vertical Sync YD Line Clock FR Pin 57 This signal must be provided to both the row and column drivers They use this signal to change the polarity of the LCD driving voltage to prevent a DC component applied to the Liquid Crystal material On most displays this signal is called MSignal For details please see section 412 Applying Power to the system Note LOD and LSCP are only available when Dual Scan is used For Single Scan operation these Pins have the name ce0 and cel and can be used as chip enable signals for VRAM Application Note ANVOZQ August 2004 Page 8 of23 H H I display lnspi re the Nexi Interfacing and setup ofToshiba T6963C products group 3 Connection to a MPU and Display Memory Typically the T6963C is connected to a micro controller unit and external display memory o en called VRAM or display RAM 31 Display Memory VRAM 311 Basic Considerations The T6963C can control up to 64 kByte display memory which must be of SRAM type memory The T6963C can not refresh DRAM The T6963C has 16 address lines 8 data lines and several controlling lines to access the display memory An option would be the direct mapping of the display memory in the micro controller internal RAM The advantage would be easy manipulation of the RAM by the micro controller Without external address decoder logic The T6963C differs from most other LCD controllers in its use of the display RAM A xed area of memory is normally allocated for text graphics and the external character generator but with the T6963C the size for each area can be set by software commands This means that the area for text graphics and external character generator can be freely allocated within the external memory up to 64 kByte With Dual Scan displays LCDl top half is allocated in the rst half of the VRAM amp LCD2 bottom half is allocated in the second half of the VRAM but both areas must be allocated identically with respect to text graphics and the external character generator area The address line adl 5 is used to switch between the memory for the rst screen and the second screen te In this document the words VRAM display memory and external RAM mean the same Application Note ANVOZQ August 2004 Page 9 of23 H H I display lnspi re the Nexi Interfacing and setup ofToshiba T6963C products group 312 Pins for VRAM f dONd7 Pins 2226 and 2830 Data IO pins for VRAM adONad15 Pins 3348 Address lines for VRAM RWPin 31 ReadWrite signal for VRAM ce Pin 32 Chip Enable pin for VRAM of any address ce0 Pin 49 Chip Enable pin for VRAM in the address range 0000h to 07FFh ce1 Pin 50 Chip Enable pin for VRAM in the address range 0800h to OFFFh Table 2 Pim for memory communications Notes ce0 and ce1 are only available for Single Scan display mode In Dual Scan display mode these pins become timing signals for the lower half of the display to The display memory address line ad15 selects the display memory for the lower and upper half of a Dual Scan display Drive this pin low to access the upper half and drive it high for the lower half 32 MPU Connection 321 General Considerations The communication between the T6963C and a MPU is not complex and there are only few hardware considerations The T6963C has an 8 bit data bus and several signals for communication with a MPU See a list of pins inTab1e 3 Pins for MPU communication For the interface timing please see the T6963C datasheet Note if the MPU instruction execution time is less than 200 ns wait states NOPs or delay loops may be required to allow time for the T6963C to recognise the instruction 322 Pins for MPU f DOND7 Pins 1017 Data IO pins for communications between MPU and T6963C WR Pin 18 Data Write It must be driven low to write data to VRAM via the T6963C RD Pin 19 Data Read It must be driven low to read data from VRAM via the 3C CE Pin 20 Chip Enable It must be driven low while MPU communicates with T6963C CD Pin 21 CommandWrite selection To write or read data it must be driven low To write a Command or read status it must be driven high Table 3 Pim for MPU commurrica om Application Note ANVOZQ August 2004 Page 10 of 23 H H I display lnspi re the Nexi Interfacing and setup ofToshiba T6963C products group 4 Settin up the T6963C With the above information it will be possible to connect the T6963C pins to the correct display pins If using the SP12N002 or SP14N001 these connections are already made If using another display please check the displays datasheet for considerations such as SingleDual Scan simple serial or evenodd separation and of course duty cycle and resolution The T6963C must be setup so that it operates correctly with the given display characteristics There are both hardware and software issues to consider Hardware issues include selecting the correct pins which determine the size of the display ie the resolution or set the Font Size for example Software issues include commands from the micro controller for example to set the software size of the display please see next sections for details 41 General Hardware Considerations of the T6963C 411 General Pins VDD Pins 2761 Power connection 5 V and Ground Depending on the power VSS pin 63 supply it may be necessary to add some capacitors as close as possible to lter noise and ripple HALT Pin 1 Driving it low stops the clock oscillation and a reset is issued Check datasheet for register states a er reset RESET Pin 2 Driving it low causes a reset and the T6963C is initialised Check datasheet for register states after reset This pin has an internal pullup DSPON Pin 50 Control output pin for external DCDC DSPON is low when HALT or RESET are driven low This is useful to switch the display off while T6963C is not in normal operation XI Pin 66 External clock source input XO Pin 67 External clock source output CHl Pin 58 CH2 Pin 59 Check signal outputs T 1 Pin 65 T 2 Pin 64 Test inputs Leave them open Table 4 Pim with general mctiom Application Note ANVOZQ August 2004 Page ii of 23 H H I display lnspi re the Nexf Interfacing and setup ofToshiba T6963C products group 412 Applying Power to the system A er powering on the whole system a reset of the T6963C should be issued to ensure correct operation This is achieved by holding the RESET pin low for at least 56 clock cycles VDD must be stable at 5 V for the reset This can be achieved with an output pin of the MCU or just with a simple capacitorresistor network See Figure 2 for an example 5V 10 k0 100 LF TGND Figure 2 Example for Reset circuit It is important to keep the correct power on sequence for the whole system because the T6963C generates the MSignal In the T6963C datasheet it is called FRSignal for the LCD row and c l 39vers The MSignal is used to change the polarity of the driving voltage so that in sum no DC is applied to the Liquid Crystal material To ensure the stability of the MSignal the T6963C must be fully initialised before applying the Voltage VEE to the Liquid Crystal material The displays DISPOFF pin can be useful for this purpose If T6963C is reset during normal operation it must be ensured that the VEE voltage and the display are turned off until the T6963C is fully reinitialised This applies also when using the HALT pin to stop the T6963C operation HALT includes a reset The DSPON pin pin 60 of the T6963C can be useful for controlling the power supply to the display This pin is an output and indicates ifthe T6963C HALT or RESET Pin is low DSPON is then low too Application Note ANVOZQ August 2004 Page 12 of 23 H H I display lnspi re the Nexi Interfacing and setup ofToshiba T6963C products group The correct power up sequence would be 1 Apply power to MPU and T6963C The display and the display s power VEE should be off Reset T6963C and wait until it is fully initialised 56 clock cycles Apply power to the display VEE on for example with the T6963C DSPON pin Apply signals to the display and switch it on for example with the DISPOFF pin of the display hm v Normal operating parameters are reached Notes The states of the T6963C registers a er a reset or halt are in the T6963C datasheet For powering off the reverse applies ie rst switch off the display remove si nals remove VEE display power and then switch off the MPU and T6963C with proper delays to too 42 Hardware considerations for setting up the T6963C for a display 421 Pins The states of the following pins are used to set the T6963C for a particular display DUAL Pin 54 For Dual Scan displays this pin must be driven low However the most displays are Single Scan and this pin can be set high SDSEL Pin 62 This pin must be driven high when the data is sent by evenodd separation method However most of the displays use the simple serial method and therefore this pin can be driven low MDS MDO MDl Pins 3 4 5 Pins for selection ofLCD vertical size Please see the T6963C datasheet for valid values For example the combination MDSMDlMDO HLL would set 128 vertical dots for a Single Scan display MD2 MD3 Pins 6 7 Pins used to select the number of columns Columns in this instance refers to the number of displayable characters per row There can be 4 combinations 32 columns 40 columns 64 columns and 80 columns Please nd more information about this setting in the following section FSO FSl Pins 8 9 Pins for selection of Font Size There are four Font Sizes available 5x8 6x8 7x8 and 8x8 dots per font horizontal dots by vertical dots The horizontal Font Size does not affect the driving signals ie it does not change the horizontal resolution of the display when changing the Font Size Please nd more information about Font Size in the following section Application Note ANVOZQ August 2004 Page is of 23 H H I display lnspi re the Nexi Interfacing and setup ofToshiba T6963C products group 422 Font Size Number of Columns and Pixels Der Column The T6963C datasheet is unclear regarding to horizontal resolution Font Size the number of columns and the pixel width of one column The T6963C data sheet says that the number of columns can be chosen by driving the pins MD2 and MD3 but it is not speci c about how many horizontal pixels are in one column and additionally the selectable options with the MD2 and MD3 pins are poor Only four display sizes The datasheet does not specify the maximum horizontal resolution this controller can drive In combination with the Font Size one might have expected that the formula Font Size multiplied with the MD2 and MD3 column setting must result in the actual horizontal display resolution But in practice changing the Font Size does not affect any driving signals and therefore the Font Size does not set anything regarding the horizontal display resolution The most important task for the Font Size is the character spacing and that the mapping of display pixels to VRAM bits becomes clear and logical For further details please see section 433 Memory and Font Size The actual physical display resolution is determined by software commands The state on the MD2 and MD3 pins should be selected that the number of horizontal pixels is a multiple of the number of columns For 240 horizontal pixels a number of columns of 40 is recommended 43 Software for controlling a display Various functions and options can be selected using software commands The commands are sent from the micro controller and affect the display the external memory and the T6963C functions 431 General f 39 39 about anmands and Data When sending commands andor data to the T6963C a certain sequence must be obeyed First of all before sending any commands andor data to the T6963C a status check must be performed The status check is necessary to nd out if the T6963C is ready to accept any commands andor data The status check is done by driving RD low and of course WD high CE low and CD high Now a status byte can be read from the data lines D7ND0 Each bit except bit 5 represents a certain state of the T6963C Please check the datasheet for details Important for the status check in normal mode are bits 0 and l of the status byte STAO and STAl D0 is LSB The T6963C is still busy when one of them is low To accept commands andor data STAO and STAl must be high A er a successful status check the T6963C is ready to accept commands andor data A command is always one byte long However some commands for example the command Set Cursor Pointer requires some data this example would need two data bytes the Xcoordinate and the Ycoordinate There are commands which need two data bytes one data byte or none The data must be sent before the Command ie if a command needs two data bytes the rst data byte must be sent then the next and nally the actual command status checks must be performed before sending each byte Application Note ANVOZQ August 2004 Page M of 23 H H I display lnspi re the Nexi Interfacing and setup ofToshiba T6963C products group 432 Commands to set the Display Size As mentioned in previous sections the actual display size is set using software commands These commands come under the heading of Set Control Word Two commands Set Text Area and Set Graphic Area are important to set the software display size Both commands need one data byte Their values in HEX indicate how many bytes are used for one complete row ie how far it is from one byte to the same byte of the next row It makes sense to assign the same value to both Text Area and Graphics Area See the section 433 Memory and Font Size for more details about how many bytes of memory are used for one row The two other commands of Set Control Word are Set Text Home Address and Set Graphic Home Address They are used to set the beginning of the text area and graphic area in the VRAM The text and graphic area can be freely allocated but of course care should be taken that they do not overlap Please nd an example of memory allocation below and a summary of the command in Table 5 Value HEX Function Data Byte 1 Data Byte 2 0100 0011 43h Set Graphic Area Number of Columns Nothing 0100 0001 41h Set Text Area Number of Columns Nothing 0100 0010 42h Set Graphic Home Address Low Byte High Byte 0100 0000 40h Set Text Home Address Low Byte High Byte Table 5 Overview of Command quotSet Control Word This Figure is an example for the memory OOOOh allocation in the VRAM The graphics area and text area are big enough to store data to ll several pages of a display For a 240x128 display 3840 bytes are Graphlc Area necessary to ll one screen with graphics This can be useful to implement for example a scrolling function Scrolling can be done for example by altering the Text Home Address The small space between the areas is for safety 9FFFh but usually not required It should just show Unused 1 kByte that the areas can really be free allocated A400h The external character generator area IS always Text Area 2 can only be set to certain addresses For details please see section 436 Character Generator F3FFh Unused 1 kByte F 800h CG Area 2 kByte F FF F h Figure 3 Example of Wmory allocation Application Note ANVOZQ August 2004 Page 15 of 23 H H I display lnspi re the Nexi Interfacing and setup ofToshiba T6963C products group 433 Memom and Font Size Although the Font Size is selected by hardware pins it is necessary to talk about it here in the software section The Font Size affects the number of bits used of a byte for displaying text and graphics If the font is 8 horizontal pixels wide every bit of a byte in the VRAM controls a pixel on the display If the Font Size is 6 horizontal pixels wide only 6 bits of each byte control pixels The rst two bits are then don t care That means regardless of its size a character is controlled by one byte in memory always Keep this in mind for setting the Text and Graphic Areas see previous section Example With a Font Size of 6x8 and 40 columns one row needs 40 bytes of memory and a total of 10 bytes are don t care With a font of 8x8 and 30 columns 30 bytes of memory are necessary for one row Here with no don t cares Again it does not matter if text or graphics are used the Font Size affects both This should be kept in mind when choosing the number of columns and calculating the required memory space for applications 434 Mode Set Commands from son to 8Fh The information given in the T6963C datasheet is not clear about this set of commands With these commands the user can set two functions The rst is how graphics and text are merged on the display The second enablesdisables functions such as Cursor onoff Text onoff etc These commands require no data byte The graphicstext merge function is set by the Command values 80h to 8Fh Binary Code Hex Code in Hex Code ex Function ternal CG ternal CG 1000 X000 80h 88h OR Mode 1000 X001 81h 89h EXOR Mode 1000 X011 83h 8Bh AND Mode 1000 X100 84h 8Ch Text Attribute Mode Table 6 The Mode Set Commandr om 8011 to 8Fh Note Bit 3 X is used to set the character generator Bit 3 0 means Internal CG ROM Mode and Bit 3 1 means External CG RAM Mode OR Mode In the OR Mode text and graphics can be displayed and the data is logically ORed This is the most common way of combining text and graphics for example labels on buttons EXORMode In this mode the text and graphics data is combined via the logical exclusive OR This can be useful to display text in negative mode ie white text on black background ANDMode The text and graphic data shown on the display are combined via the logical AND function Apphcahon Note ANVOZQ August 2004 Page 16 of 23 H H I display lnspi re the Nexf Interfacing and setup ofToshiba T6963C products group TEXT ATTRlBUTE This option is only available when displaying just text The Text Attribute values are stored in the graphic area of the display memory which was de ned by the Set Graphic Home Address command Because the graphic memory is also used both text and graphic display bits must be enabled with the Mode Set commands values 90h to 9Fh see next section The TEXT ATTRIBUTE options are Reverse display show the character in negative mode ie white character on black background Character Blink and Inhibit do not display this character Notes 1 When choosing a certain mode it applies for the whole display It is for example not possible to apply attributes to text in one part of the display and graphics in another part of the display to There are no other bit combinations for the Mode Set commands in the range of 80h to 8Fh than the four shown above in Table 6 435 The Mode Set Commands from Son to 9Fh The second set of commands are selected with bit combinations 90h to 9Fh 9h means binary 1001 The second nibble bit combinations set the cursor and text andor graphics display ll 0 0 1D3D2D1D0 Cursor Blink 1 on 0 off Cursor display 1 Z on 0 off Text display 1 on 0 of1 Graphic Display 1 on 0 off Figure 4 Combimztiom for llfade Set Functions om 90k to 9Fh The four least signi cant bits can be con gured for Display Off all 0 to Text On Graphic On Nearly any combinations are possible See the T6963C datasheet for details Apphcahon Note ANVOZQ August 2004 Page 17 of 23 H H I display lnspi re the Nexi Interfacing and setup ofToshiba T6963C products group 436 Character Generator The T6963C has the capability to generate characters in two ways The rst way is with the builtin character generator ROM It contains 128 prede ned characters The second way is using the external character generator To ensure high exibility the T6963C can operate in two modes One mode is using the internal character generator ROM for the 128 prede ned characters and the external character generator area for 128 userde ned characters The other mode is using only the external character generator RAM for up to 256 userde ned characters The two modes are called lntemal CG ROM Mode and External CG RAM Mode The con guration is selected by the Mode Set commands See previous section The location of external CG Area in VRAM is set by the command Set Offset Register The external CG Area is always 2 kByte in size 2048 Bytes and can store up to 256 userde ned characters Each character needs 8 bytes 256 x 8 bytes 2048 bytes The command Set Offset Register is 22h 0010 0010 and needs 2 bytes of data The second data byte of the Command Set Offset Register must always be 00h The ve least signi cant bits of the rst data byte sets the 2k external CG Area within VRAM With ve bits 32 different memory segments can be selected 25 32 There are 32 possible locations for a block of 2 kBytes within 64 kBytes of memory therefore 5 bits are enough to set the external CG RAM area The 5 bit combination corresponds to a memory block address in the table below Least signi cant data bits of first data byte CGArea start and end 2 kByte 00000 0000h 7 07FFh 00001 0800h 7 OFFFh 00010 1000h717FFh 11101 E800h7EFFFh 11110 F000h 7 F7FFh 11111 F800h7FFFFh Table 7 Possible external character generator areas In lntemal CGROM Mode the rst 1024 bytes 1024 400h of the external character generator memory block are not used therefore the address of the rst external character must have an offset of 400h to the start address With a start address of 1000h for example the rst character would be located at 1400h 1n internal CGROM mode the character codes 00h to 7Fh are used for selecting a character from the internal character generator ROM The codes 80h to FFh are used for the external character generator RAM 1n the mode External CGRAM Mode the internal character generator is disabled and all character codes 00h to FFh represent characters in the external M Application Note AN7029 August 2004 Page 18 of 23 H H I display lnspi re the Nexi Interfacing and setup ofToshiba T6963C products group Each character in the external RAM is 8 bytes wide A character can have a Font Size of up to 8 by 8 dots and therefore the character with code 80h is located from l400h to l407h And therefore the data for this character must be written to these addresses See the example in section 5 To show this character on the display Text Mode must be enabled By the Mode Set Commands see previous section the selected character is taken from the memory location in character RAM and stored in the TEXT area of VRAM prior to display on the screen The address pointer must be set to the appropriate address in the Text Area of VRAM and then the comm Write Data must be executed with the data byte 80h The T6963C knows automatically this is a character from the external CGRAM and writes all 8 bytes from the CG RAM locations l400h to l407h to the appropriate text memory location Note A table of the internal character generator ROM content is on page 26 in the T6963C datasheet A character code of 7Fh represents the letter f for the common CGROM type 0101 This character generator table is similar to a small area of the ASCII Table The characters of the T6963C CGROM from 00h to 5Fh are the same as for ASCII 20h to 7Fh The ASCII characters have an offset of 20h compared to the T6963C characters If you want an ASCII character displayed you need its hex code and subtract 20h If you send this value as character code to the T6963C you have it To see an ASCII table visit wwwasciitablecom Below is a table describing how the T6963C combines the Off Set Register value and character code to locate the physical memory location of the chosen character RAM Address HEX VRAM Address 0 0 0 l 0 l 0 0 0 0 0 0 0 0 0 0 BinaIY Actual 5 Bits Offset Register Data 8 Bits Character Code 3 Bits Line Meaning 0 0010 02h 1000 0000 80h Scan Table 8 Dependence of CG RAM area and character code Apphcahon Note A0029 August 2004 Page 19 of 23 H H I display lnspi re the Nexi Interfacing and setup ofToshiba T6963C products group 437 Address Pointer Considerations The T6963C address pointer has several functions Basically it is used to set the address in the VRAM where to read or to write data The address pointer is set by the Set Address Pointer command 24h and needs two data bytes a low address byte and a high address byte The addresses in the VRAM are 16 Bits wide To write data from the MPU into the VRAM the address pointer has to be set to the required address and a Write Data or Auto Write Data command execute To read data from the VRAM set the address pointer and execute a Read Data or Auto Read Data command The WriteRead Data commands can be executed so that the address pointer is increased or decreased automatically An Auto WriteRead Data command controls the increase of the address pointer To show data on the display set the address pointer to the appropriate address in the Text or Graphic Area in the VRAM enable the display with the Mode Set commands and execute a Write Data Command The data now stored in the VRAM area is shown automatically on the display Example To show a 16 dot line in the upper left comer of the display as a graphic Assumed that Text Home Address is set to 0000h Graphic Home Address to 020011 Graphic is enabled amp the Font Size is set to 8 by 8 Do not forget Font Size affects both Text and Graphics 1 Set Address Pointer to 0200h 2 Execute Write Data Command with increase of Address Pointer with the data byte FFh 3 Execute Write Data Command with the data byte FFh Note Do a status check before sending a command or data 438 Additional Commands The T6963C has many more commands there is a complete overview of these additional Commands in the datasheet Application Note ANVOZQ August 2004 Page 20 of23 H H I display lnspi re the Nexi Interfacing and setup ofToshiba T6963C products group 5 Example of external Character Generation This section gives an example how the external character generator can be used to display the Euro symbol The Euro symbol is not in the prede ned character set of the internal character generator ROM but with the introduction of the Euro currency in many countries in the European Union it can be helpful for a display controller to have the capability of showing it This example shows how the Euro symbol is stored in the external character generator RAM as a userde ned character and how it can be displayed Be careful the status checks are not mentioned Before the external character generator RAM can be used its area in the VRAM must be set This is set with the command Set Offset Register Let s set the character generator RAM location to E000h to E7FFh As explained in the datasheet the last 5 bits of the Offset register data byte must be 11100 to achieve this The internal character generator is also being used therefore only the second half of the external character generator memory block can be used Execute command Set Offset Register with the data bytes 1Ch 000 11100 and 00h The character with code 80h is then located at the address E400h 7 1110 0100 0000 0000 A er the setting of the CGRAM area the character data can be written The Euro symbol is constructed as shown below 00h 0000 0000 OEh 0000 1110 11h00010001 3c110011 1100 10h00010000 301100111100 111100010001 OEh 0000 1110 Figure 5 Euro 531le as quotDot Character To write the data into the CGRAM the address pointer must be set to the appropriate address Assuming that the Euro symbol is the rst character we wish to store it will have the character code 8011 the address pointer must therefore be set to E400h A er setting the address pointer the data can be written with the commands Write Data or Auto Write Data Do not forget the proper status checks To show the Euro symbol on the display set the address pointer to an address in the Text Area of the VRAM and execute the command Write Data with the data byte 80h Text Mode must be enabled The T6963C automatically knows that this is a character from the external character generator RAM Application Note A0029 August 2004 Page 21 of 23 H H I display lnspi re the Nexi Interfacing and setup ofToshiba T6963C products group 6 Summary This Application Note wants to cover the issues where the T6963C datasheet is not clear or even wrong for example the Font Size and column width relationship It is important that the Font Size according to the Text Area and Graphics Area which determine the bittopixel mapping of the VRAMtoDisplay The actual horizontal software resolution of the display is set with the Set Control Word commands These commands determine how many bytes make one row and therefore how to determine the VRAM address of the start of the next row Check this value if the display shows either no characters at the end of a row no wrap or wrap too late or characters double wrap too early Another thing to consider is the start address of the external character generator This is set by the Set Offset Register command The CGArea is 2 kByte and therefore 5 Bits are sufficient to set it in a 64 kByte memory 25 32 These ve bits are the least signi cant bits of the rst data byte of the command Most important thing Don t panic Do not let the datasheet of the T6963C or this Application Note confuse you The datasheet is not always clear However when reading it several times it becomes more logical Try also looking for code examples for the T6963C The code in the datasheet is written for a 280 micro controller and can be helpful although initially confusing Be aware that the code contains some errors Please see application note AN037 Interfacing displays with T6963C amp Touch Panel from a PIC for further code examples and explanations Apphcahon Note ANVOZQ August 2004 Page 22 of23
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