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by: Adele Schaden MD


Adele Schaden MD
GPA 3.88


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Class Notes
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This 16 page Class Notes was uploaded by Adele Schaden MD on Thursday October 29, 2015. The Class Notes belongs to CS 203A at University of California Riverside taught by Staff in Fall. Since its upload, it has received 12 views. For similar materials see /class/231745/cs-203a-university-of-california-riverside in ComputerScienence at University of California Riverside.

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Date Created: 10/29/15
CS 203A Advanced Compu rer Archi rec rure Wha r is Compu rer Archi rec rure Lec ru re 1 2 Compu rer Archi rec rure Instruction Set Architecture Organization Hardware Fundamen rals of Compu rer Archi rec rure mdahl39s Law Instructor Jun Yang auxmm L2 172 l auxmm L2 172 2 The Ins rruc rion Se r a Cri rical In rer face Ins rruc rionSe r Processor Design The actual programmer visible instruction set software hardware auxmm Archi rec rure ISA programmercompiler view functional appearance to its immediate usersystem programmerquot Opcodes adtbessing modes architected registers IEEE floating pain 39 Implementation Jarchileclure processordesignerv 2w ogicul structure or organization that performs t e architecturequot Pipelining functional units caches physical registers 39 Realization c ip chipsystem designer view physical structure that embodies the implementationquot Gates cells transistors wires auxmm Lee 172 Pentium 4 Microar chitectur e Bu Inle ace Unll L2 Cache Pentium III Die Photo ESLBBLr Bus iogic From Back Pacde FPU r MMX Fi Pt SSE BAC 7 Branch Address Caicuiator RAT 7 Register Ahas Tabiz SIMD r Packed H Pt RS 7 Reservation Station STE 7 Branch Target Buffer ID elnstruction Decode ROB r Reorder Buffer MS 7 Micrormstruction Sequencer 1st Pentium III Katmai 9 5 M transistors 12 3 6 10 4 mm m0 254m With 5 iayers of aiummum Example Organization Hardware TI SuperSPARC39 TM5390Z5O in Sun SPARCs ta tionZO integer Unit MBUS MEus control Ms auxmm Machine specifics Feature size 10 microns in 1971 to 018 microns in 2001 39 Minimum size of a transistor or a wire n either the x or y d mension Logic designs Packaging technology Clock rate Supply voltage gzzznm Le 172 Relationship Between the Three Aspects Applications and Requirements Processors having identical ISA may be very different in organization eg NEc VR 5432 and NEc VR 4122 Processors with identical ISA and nearly identical organization are still not nearly identical e g Pentium II and Celeron are nearly identical but differ at clock rates and memory systems gt Architecture covers all three aspects auxmm Le iez 39 Scientificnumerical weather prediction molecular modeling Need large memory floutingpoint arithmetic Commercial inventory payroll web serving e commerce Need integer arithmetic high IO Embedded automobile engines microwave PDAs Need low power lowcost interrupt driven Home computing multimedia games entertainment Need high data bahdwidth graphics auxmm Le iez Classes of Computers Why Study Computer Architecture High performance supercomputers Supercomputers Cray T9O Massively parallel computers Cray T3E Balanced costperformance Workstations SPARCstations Servers SGI Origin UltraSPARC Highend PCs Pentium quads Low costpower Lowend PCs laptops PDAs mobile Pentiums auxmm Le iez Aren39t they fast enough already Are they Fast enough to do everything we will EVER want AI protein sequencing grep ics Is speed the only goal Power heat dissipation battery life t Cos Reliability Etc Answer 1 requirements are always changing auxmm Le iez Why STudy CompuTer ArchiTecTure Example of Changing Designs Answer 2 technology playing field is always changing Annual Technology improvemenTs approx Logic densiTy 25 speed 20 DRAM memory densiTy 60 speed 4 o Disk densiTy 25 disk speed 4 o Designs change even if requiremenTs are fixed BUT The requiremenTs are noT fixed auxmm Le iez Having or noT having caches 1970 10K TransisTors on a single chip DRAM fasTer Than logic gt having a cache is bad 1990 1M TransisTors logic is fasTer Than DRAM gt having a cache is good Will caches ever be a bad idea again auxmm Le iez Performance GrowTh in PerspecTive Measuring Performance Same absoluTe increase in compuTing power Big Bang 2001 2001 2003 1971 2001 performance improved 35000X WhaT if cars improved of This raTe auxmm Le iez 39 LaTency response Time execLITion Time Minimize time to wait for a computation Throughputtaskseompleted per unit time bandwidth Maximize work done in a given interval 1lulency when there is no overlap among Tasks gt1luTency when there is In real processors there is always overlap pipelin rig 39 BoTh are imporTanT auxmm Le iez Performance Terminology CompuTe Speedup Amdahl39s Law X is nTimes fasTer Than Yquot means ExecuTion Timev ExecuTion Timex X is mfasTer Than Yquot means ExecuTion TimeV ExecuTion Timegtlt X 100 m ExecuTion Timex auxmm Le iez Speedup is due To enhancemenTE Timeieeie Tinem ExecuTion Time wo E Before Speedup E ExecuTion Time w E After Suppose ThaT enhancemenT E acceleraTes a fracTion F of The Task by a facTor S and The remainder of The Task is unaffecTed whaT is The Execu an fimeme and 5peedupE 7 auxmm Le iez Amdahl39s Law Amdahl39s Law An Example Exam g lea er ExTimebmre x 1F EXTlmebefure 1 SpeechME EXTlmea er 1F auxmm Leo iez auxmm Q FloaTing poinT insTrucTions improved To run 2X buT only 10 of execuTion Time are FP o s aT is The execuTion Time and speedup afTer improvemenT Ans F 01 S 2 ExTimem ExTimeMm x 101 012 0 95 ExTimeMm EXTlmebefare 1 1053 ExTimeaw 0 95 Read examples in The book LecLZ Speedup Corollary Make the common case fast CPU Performance 39 All instructions require an instruction fetch only a fraction require a data fetchstore Optimize instruction access over data access 39 Programs exhibit locality Spatial Locality Temporal Locality 39 Access to small memories is faster Provide a storage hierarchy such that the most frequent accesses are to the smallest closest memories Re rs auxmm L2 L2 2i 39 The Fundamental Law CPUquot seconds seconds instructions cycles ro ram program instruction cycle Three components of CPU Instruction count PI Clock cyclotmo auxmm L2 L2 22 CPI Cycles per Instruction Example Average CPI T tal Cycle Total Instruction Count CPI Instruction C ount CPU time Cycletimexz CPI x Ic Aw Loud m Fre 43 21 12 24 1 2 2 2 average CPI 0 43 0 42 0 24 0 48 157 cyclesinstruction 3 auxmm L2 L2 ZCPLXE where E lei Example Clock c cles Instruction mix of a RISC architecture Inst ALU Load Store Branch Freq 50 a 20 a 10 c l 2 2 Add a registermemory ALU instruction format One op in register one op in memory The new instruction will take 2 cc but will also increase the Branches to 3 cc Q What traction of loads must be eliminated for this to pay off auxmm L2 L2 24 CS 203A Advanced Computer Architecture Review Lecture 4 MIP564 Instructor Jun Yong Branches Instruction Format Role of Compiler RISC vs 6156 m 12m 1111 1 m 12m 1111 2 Outline MIP564 Registers and Data Types 32 GPRsrRO R1 R31 Ingzr MIP564 641111 7 811 32 64bquot are 32 FPRS 7 F0 F1 F31 WWIer 61b1 Hoamg pow R0 O 7 511912 31112121121151111 are supported 5p2c1a1rzg1s12rs P9 1 r Narrow vatues are 5191 Extended or Zerorextended mm 1111 3 m mm 12 1 1 The MIP564 Instruction Formats MI PS Instruction Layout AHMIPS 11511112111111 are 3211115111119 Thethree mstrucnun farms 31 21 21 11 11 1 n mE m n R39WPQ 11115 51115 51115 51115 51115 11115 21 21 21 11 n 214W 3 11115 51115 51115 111115 21 21 n r Hype The d1ffer2m ne hsre 2 5 7 up 11212111111112 111111111 7 111111 1121111221111 1211112111112911121112211121 111111 11112 ap f21d 211112 111112111112 21112 111121111111121121212112 11119212111121 11119212111121 111121111pm11uc11ar n21 mm 12 1 1 111 1 1 1 1 mgr m mm mrm 112 W1 W11 m 6 MIPS Addressing ModesInstruction Formats All instructions 32 bits wide Register1direc1 Immediate bispidcerneni Pore iaiiye 0st 22002 Lee A 7 MIPS I Operation Overview Arithmetic Logical Add AddU Sub SubU And Or Xor Nor SLT SLTU AddI AddIU SLU SLUU AndI OrI XorI LUI SLL SRL SRA SLLV SRLV SRAV Memory Access LB LBU LH LHU LW LWLLWR SB SH SW SWL SWR 0st 22002 Lee A 2 Multiply Divide Start multiply divide MFLO rd Move to HI or L0 MTHI rd MTLO rd Why not Third field for destination Hint how many clock cycles for multiply or divide vs MIPS Arithmetic Instructions Instruct071 EXamgE Meanrig am7127 add 123 1 2 3 3 operands exception possibie subtract sub 123 1 2 3 3 operands exception possible add immediate add11210012 100 o constant exception goss ble ddd un igned d du123 1 2 3 3 operands no exce ions sub u i ned bu 1 23 1 2 3 3 operands no exceptions add 1mm unsign add u 1 100 1 2 o 10 onsi n1 no exceptions H 3 z 3 diyide unsigned divu 23 o Unsigned quotient 1 remander da 2 Move from H1 inrni1 1 Hl Move from L0 mfl0l 1 Lo Used to get copy of Hi Used to get copy of L0 Which add for address arithmetic Which add for integers 0st 22002 Lee A in add 0122 12 1M o MIPS Logical Instructions I SVLL fD EXamgE Meanrig amHE and 1 23 1 2 d 3 3 reg operands Logical AND or or 123 1 2 1 3 3 reg operands Logical o xor xor 123 1 2 3 3 reg operands Logical XOR nor nor 123 1 2 l33 reg operands Logical NOR and immediate and 1210 1 2 d1 cai AND reg c nsiani or rnrnedidte ori121o 1 xor mmediaie shift iefi iog cai sii121o 1 2 1 10 Log cdi on reg constant shift rigni ariinm sra1 210 1 2 gtgt 10 shift rigni sign extend shift left leg cal siiy123 1 2 3 snin rigni iog Cal sriy123 1 2 3 snin rigni by variable snin rigni ariinrn srai 123 1 2 3 snin rigni driin by variable 0st 22002 Lee A 11 MIPS Data Transfer Instructions Instruction Comment 5w 500024 k3 Store word SH 502022 k3 Store hqu SB 41023 k2 Store byte LW k1 30022 Loed word LH 12140023 Loud halfword LHU k1 40023 Loud halfword unsigned LB k1 40023 ed byte LBU k1 40023 Loud byte unsigned o LUI I21 40 Load Upper Immediate 16 bits shifted left by 16 0st 22002 Lee A 12 Methods of Testing Condition 39 Condition Codes Processor status bits are set as a sideeffect of arithmetic instructions or explicitly by compare or test instructions 39 Condition Register Ex cmp r1 r2 r3 bgtz r1 label 39 Compare and Branch Ex beq r1 r2 label Oct 22uu2 Lee A 13 MIPS Compare and Branch Compare and Branch BEQ rs rt offset if krs s krt then PCrelative branch BNE rs rt offset ltgt Compare to zero and Branch BLEZ rs offset if krs lt 0 then PCrelative branch BGTZ rs offset gt B lt BGEZ gt1 BLTZAL rs offset if krs lt 0 then branch and link into I 31 BGEZAL gtl Remaining set of compare and branch ops take two instructions Almost all comparisons are against zero Oct 22uu2 Lee A 14 MIPS Jump Branch Compare Instructions Instructon Examge Meanrig branch on equal beq 1 2100 if e 2 go to pc4100 E ua test Pf rzafVE ancn branch on not eq bne 1 2100 if 11 2 go to Pc4100 Not eoua test Pf rzafVE set on less than sit 123 if 2 lt 3 11 else 10 Avquotpare ess marl 2s corn set less than mm slti 12100 if 2lt 10011 else 10 am are constant 2s comp set less than uns sltu123 if 2 lt 311 else 113 am are 255 than narwarlumbers set i t iinni uns sltiu12100 if 2lt 10011 else 10 compare r constant narwarlumbzrs Jump J 10000 go to 10000 Jump to target address Jump register Jr31 go to31 For swttci procedure re turn Jump and link Jal10000 31 PC 4 go to 10000 For procedure cat oa 22uu2 be 4 When does MIPS Sign Extend When value is sign extended copy upper bit to full value Examples of sign extending 8 bits to 16 bits 00001010 00000000 00001010 10001100 11111111 10001100 When is an immediate value sign extended Arithmet c instructions add sub etc sign extend immediates even for file unsigned Versions offlie Logical instructions do norsign extend LoadStore half or byte do Sign extend but unsigned versions do not Oct 22uu2 Lee 4 1o Signed vs Unsigned Comparison R1 000 0000 0000 0000 0001 R2 000 0000 0000 0000 0010 R3 111 1111 1111 1111 1111 After executing these instructions slt r4 r2 r1 if r2 lt r1 r41 else r40 slt r5 r3 r1 if r3 lt r1 r51 else r50 sltu r6 r2 r1 if r2 lt r1 r61 else r60 sltu r7 r3 r1 if r3 lt r1 r71 else r70 What are values of registers r4 r7 Why r4 r5 r6 r7 Oct 22uu2 Lee A 17 Details of the MIPS Instruction Set The 39 x quot wiiiei quot g39 39 39 you II I Branchjump and link put the return addr PC4 or a into the ink register 1231 depends on logical vs phys cal architecture All instructions change all 32 bits of the destination register ncluding lui lb h and all read all 32 bits of sources add sub and or Immediate arithmetic and log cal instructions are extended as follows eLo ica ed o32 bits l ininediates ops are zero extend ithinetic immediates ops are sign extended to 32 bits including addu data loaded by the instructions lb and h are extended as follows lbu lhu are zero extended e lb lh are sign extended Overflow can occur in these arithmetic and logical nstructions e add sub addl e It cannot occur in addu subu addlu and orxor nor shifts inult inultu div dlvu Oct 22uu2 Lee A 12 CS 203A Advanced Computer Architecture Outline Lecture 3 Instruction Set Principles Examples Instructor Jun Yang yenmm Lec 3 yenmm Lec 3 Control instructions RISC vs 6156 39 MIPS Control Operations Branch Condition taken or not Ty es Conditional branches mps Procedure calls and returns Issues Taken or not Where is the target How is the target specified Link return address Save registers gt Subroutine calls yenmm Lec 3 39 compare and branchquot instructions single instruction requires ALU op for comparison in branch pipeline restricts scheduling 39 Separate compare and branch more scheduling opportunities reuse com arison uses up a register separates condition from branch logic 39 ImExplicit condition codes Zero Negative oVerflow Carry set for freequot by ALU operations extra state to saverestore restrict scheduling implicit yenmm Lec 3 Where is the Target Where is the Target PC relative with immediate position independent target computable in branch unit short immediate sufficient 47 use lt 4 bits 94 use lt 8 bIts target must be known statically can39t jump for I Usage branchesjumps within function Arbitrary absolute specifier more bits to specify I Usage function calls long jumps within large functions Winmm Lec 3 Register short specifier can jump anywhere dynamic target OK return address Extra instruction to load register I Usage indirect calls eg DLL loaded only when invoked by program virtual functions different routines are xecute based on data types returns switches Win1mm Lec 3 Link Return Address Save or Restore Register State Used in subroutine calls Implicit register eg 31 we are down to 30 registers 0220 many recent architectures use this Fast simple sw saves register before next subroutine call Winmm Lec 3 Function calls save registers 39 System calls save registers flags PC etc Software savingrestoring calling convention ivi e work Caller saves registers in us Callee saves registers it or nested callees will LISE Hardware savingrestoring Explicit IBM STM VAX CALLS Implicit SPARC Win1mm Lec 3 CISC complex instruction set computer VAX X86 etc RISC reduced instruction set computer RISC VS CISC Berkeley RISCl Patterson Stanford Hennessy IBM 801 winmm Lee 3 winmm Lee 3 RISC vs CISC RISC vs CISC Instruction Set Design 39 The historical background 39 ChamCTZNSTICS 01 ISAS In first 25 years 194570 performance came from boil CISC RISC ieelmology and design Design eonsira nis Var39abl length S39ngle Word mall and slow memor e eompaei programs are fast lnStrUCtlon lnStrUCtlon o small no0f regisiers memoryo eran s Variable format Fixedfield o anempis io bridge the decodin features 39 39 Memory operands Loadstore architecture Complex operations Simple Winmm Lee 3 ob I22 IC c Win1mm se ieelinology and m eroproeessors in 19705 lower eosis lo on semaniie gap model high level language In nsfr39ucf o o no need for poriabiliiy same vendor applieaiion as and hardware ackwar39d eompaiibiliiy every new ISA musi carry iiie good and bad of all pasi ones suli powerful and complex nsirueiions inai are rarelyu d w power sumpiion liiglier clock raies cheaper and larger memories Lee 3 RISC vs CISC Instruction Set Design RISC vx CISC Comparison 39 Emergence of RISC Very large scale integration processor on a chip silicon real estate at a premium icrostore occupies about 70 of chip Increased difference between CPU and memory speeds Complex instructions were not used by new compilers Software changes o reduced reliance on assembly programming new ISA can be intro uce o standardized vendor independent 05 Unix became very popular in some market segments academia and research need for portability Early RISC projects IBM 801 America Berkeley SPUR RISC I and RISC II and Stanford MIPS No fair comparison exists Different compiler and OS Different implementation People try to argue that RISCs are better than CISCs But most commercially successful ISA is X86 decidedly CISC Intel39s trick Decoder translates CISC into sequences of RISC uo s microops internally microarchitecture is actually RISC winmm Lec 3 13 winmm Lec 3 IA Outline MIP564 Registers and Data Types 32 GPRs R0 R1 R31 39 Integer 64bit 8 16 32 64bit are 32 FPRs F0 F1 F31 Emmi MIPS 64 bit Floating pomt R0 2 0 single doubleprecision are supporte Special registers PC Lo HI 2 39 Narrow values are sign extended or zeroextended winmm Lec 3 IS Win1mm L2 3 The MIPS64 Instruction Formats MIPS Instruction Layout AH MIPS insiruciiuns are 32 bits iung The three insiruciiun furmcits a 26 21 16 u 6 u R I 39WPE Man 5th 5m 5m 5th Man 31 26 21 16 u LWE 3 Man 5m 5m l hw 31 26 u r thype The differenmei a gre Mquot 7 up apemtmnafvne nstructian e rs n m the saurce and desnmnan registerspecif 2r V Show sniftamaum 7 mm seiectstnevariantafMeapemtmn mm ap f2id 7 add regs Immediate address affset an immediate mine 7 targetaddress targetaddressaftneJump msmenan mum kn z wmanm may immw MIPS Addressing ModesInstruction Formats MIPS I Operation Overview All instructions 32 bits wide mew w a Imm bispiacemem El 9 WWW El 9 mm 39Arithmetic Logical Add AddU Sub SubUAnd Or Xor NorSLTSLTU AddI AddIU SLTI SLTIU AndI OrI LUI SLL SRL SRA SLLV SRLV SRAV 39Memory Access LB LBU LH LHU LW LWLLWR SB SH SW SWL SWR wmanm Multiply Divide MIPS Arithmetic Instructions 39 Start multiply divide MULT rs rt 39 Move to HI or L0 MTHI rd TLO rd 39 Why not Third field for destination Hint how many clock cycles for multiply or divide vs Insfl39uc m Exam Matting amineIf add add 123 2 3 3 operands 39exceEtion Essible subtract b 2 2 3 3 operandsexce io Essible add mmediate addi 121001 2 100 constant exce ion pgssible add unsigned addu 1 2 3 2 3 3 ope sub unsigned subu 12 3 2 3 add mm unsign addiu 121oo 1 2 100 constant no exce ions multi mult 23 Hi Lo 2 x 3 64bit signed product multiply unsignedmultu23 39 3 64bit unsigned product divide div 2 Lo quotient Hi rema nder divide unsigned divu 23 Unsigned quot ent 61 rema nder Move from Hi mfhi 1 Move from Lo mflo 1 Which add for address arithmetic Which add for integers Used to get copy of Hi Used to get copy of Lo add 9mm in 3 n mm in 3 22 MIPS Logical Instructions MIPS Data Transfer Instructions Insfrucftm ExamLz Matting UmIIEII Insfr39ucfiun Cummenf and and 123 12amp3 3regoperandsLogical mo 5w 500R4 R3 Store word or or123 12 l3 3regoperandsLogcalOR SH 502R2 R3 Storehqu xor xor123 12 3 3 regoperands Log cal x0e SB 4108 R2 Store byte nor nor 123 1 2 3 3 reg operands Log cal NOR and immediate andi 121o 1 2 61 10 Log cal AND reg constant or immediate ori 121o 1 2 1o Log cal OR reg constant or immediate xori 1 210 1 2 A1o Log cal XOR reg constant shift left logical sll 121o 1 2 ltlt 10 shift left by constant shift right log calsrl 121o 1 2 gtgt 10 shift right by constant shift right arithmsra 121o 1 2 gtgt 10 shift right sign extend shift left logical sllv 123 1 2 3 shift left by variable shift right log cal srlv 12 3 1 2 3 shift right by variable shift right arithm srav 12 3 1 2 3 shift right arith by variable Winmm L2 3 23 LW R1 30R2 Loud word LH R1 40R3 Loud hulfword LHU R1 40R3 Loud hulfword unsigned LB R1 40R3 Loud byte LBU R1 40R3 Loud byte unsigned LUI R1 40 Load Upper Immediate 16 bits shifted left by 16 Win1mm L2 3 24 When does MIPS Sign Extend Methods of Testing Condition 39 When value is sign extended copy upper bit to full value Examples of sign extending 8 bits to 16 bits 00001010 00000000 00001010 10001100 11111111 10001100 39 When is an immediate value sign extended Arithmetic instructions add sub etcsign extend immediates even for file unsigned Versions of the instruc films Logicai instructions do not sign extend 39 LoadStore half or byte do sly7 exfend but unsigned versions do not 9301004 L2 3 Condition Codes Processor status bits are set as a sideeffect of arithmetic instructions or explicitly by compare or test instructions ex add r1 r2 r3 b2 la el Condition Register Ex cmp r1 r2 r3 bgt r1 label Compare and Branch Ex bgt r1 r2 label 9301004 L2 3 MIPS Compare and Branch MIPS Jump Branch Compare Instructions a co m Part 5 a quotd Br one h InsfrucfAm Examgz Ill12min branch on equal beq 12100 if 1 2 go to PC4100 E 5 a fzsf Ft rzia v emsi B Q rs rt offset if Rrs Rrt then PCrelative branch BNE rs rt offset 0 39 Compare to zero and Branch BLEZ rs offset if Rrs lt 0 then PCrelative branch BGTZ rs offset gt BLT lt BGEZ gt BLTZAL rs offset if Rrs lt 0 then branch and link into R 31 BGEZAL gt 39 Remaining set of compare and branch ops take two instructions 39 Almost all comparisons are against zerol 9301004 L2 3 branch on not eq bne 121oo if 1 2 go to PC4100 Na equal fzsf Ft recm39ve set on less than slt 123 if 2 lt3 11 else 1o compare less 1 an 239 com set less than imm slti 121oo if 2 lt 100 11 else 1o compare ltmmsfmf 239 com set less than uns sltu 123 if 2 lt3 11else 1o am 139 I fhm quotmuralrumba set I t imm uns slt u 121oo if 2 lt 100 11else 1o compare ltmmsfsz m1 3911mede jump j 1000 Jump 1o forge add 15 jump register jr 31 go to 31 Fe wfch procedure I39z ll39rl jump and Ink jal1oooo 31 PC 4 go to 10000 For procedure call 9001004


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