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by: Adele Schaden MD


Marketplace > University of California Riverside > ComputerScienence > CS 120B > INTRODUCTION TO EMBEDDED SYSTEMS
Adele Schaden MD
GPA 3.88


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This 10 page Class Notes was uploaded by Adele Schaden MD on Thursday October 29, 2015. The Class Notes belongs to CS 120B at University of California Riverside taught by Staff in Fall. Since its upload, it has received 19 views. For similar materials see /class/231747/cs-120b-university-of-california-riverside in ComputerScienence at University of California Riverside.

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Date Created: 10/29/15
CS120B Introduction to Embedded Systems 2182003 Outline I Memory Write Ability and Storage Permanence I Common Memory Types Memory I Composing Memory I Memory Hierarchy and Cache I Advanced RAM 22muuz i mm as Embedded System Functionality Basic concepts I Three aspecw I Stores large number ofbits W 7 mx n mwords ofn bits each 7 Processin m g e kLogZm address input signais E Process 7 ZAk words E s Transformation ofdata e g 4 096 x 8 memory 7 Storage 327 its Er j M iz address input signals WWW OVY 8 t tdt al Retention ofdata mp Duty aasign s 7 Communication uses Transfer of data 7 multiport multiple accesses to diffaent A locations simultaneously Ari 2 Maya may as Q Qquot Trends Write ability storage permanence MemOIy Size double even 18 months Traditional ROMRAM distinctions F ll Wing MW law read nniy bits stored Without puwer I Memory advances drive new products RAM D t and wnteinse stored bits Witnnutpnwer e i camera bl b f 5L CPU AZD d Ch H h I Traditional distinctions blurred quota e y a af 63quot as 7 Advanced ROMs can be written to I Tradltion dlstinction for dlfferent types of memory e g EEFROM 7 ROM Read only Memory 7 Advanced RAMs can hold bits Withoutpower 39 e g NV M 7 RAM Random Access Memory Write ability 7 Manner and speed a memory can be written Storage permanence 7 Ability ofmemory to hold stored bits after they are written 5 E 6 Maya vaaz CSlZOB Introduction to Embedded Systems 2182003 Write ability Storage permanence Ranges ofwrite ability Range of storage permanence a Hig end 7 Hi d pruressurwntes to memory simply and quickly Essentially neverluses bits E g E g maskrpmgrammed ROM 7 Mlddle range a Mlddle range Rrueessurwntes to memory but sluwer llulds bits days muntns uryears atter memory39s puwer suureetumed arr E g FLASH EEFROM E g NVRAM a Lowerrange a Lower range perial EquipmmL prugammer39 mustbe used to write to memory llulds bits as lung as power suppliedtu memury 39 E g EFROM OTF ROM E g SRAM 7 Low end 7 Low end Bits stured only during rabnrauun Regns to lose bits almost immediately a erwntten E g Maskrpmgammed ROM DRAM lnsystem programmable memory Nonvolatile memo a Can be written to by processor in embedded s stem 7 Holds bits aiterpoweris no longer supplied 7 Memories in nigla end and middle range ofwrlte ability 7 a Higla end and middle range of storage permanence 8 ma ma Write ability storage permanence ROM ReadOnly Memory u E I Nonvolatile memory ETE Wkpmmgdpm deWy I Can be read from but not Written to Lireur OTE ROM 7 By aprocessor in an embedded system 9mm I Traditionally written to through programming T332 EPEOM HERO MS 7 Before inserting to embedded system I Uses mm 7 Store software program for generalpurpose processor NW mammabla SRAWDRAM program instructions can be one or more R wor s m i i Write a Store constant dataneeded by system Em VIEN guring Ema Emma Ema Emmi png gym 7 Implement combinational circuit enable 2 x mm nm on m r m mpammar mgammar v unly gnemeunlyp igil s Rm g t mouRmrsy n n eivd ufeyeles ln s blusleunented quotm E ufcyeles writes LEIEIEIS Cycles A ufcyeles H 9 in marina marina Qni Qn 8 X 4 ROM Implementing combinational function 39 H riz mal quot95 W rd5 lnlmualview I Any combinational circuit of n functions of same k 39 Vemcal lmes dam Variables can be done with 2k x n R I Connected only at circles 3 4 ROM Truth tabl warm pu ad ess utp mab L 3X8 s r WM 3x2 ROM decoder 2 il H 7 Wur f Ari I N wovdltmz qf Ax quot t Az s xi Decoder sets word 2 to 1 quotN lfaddress input is 010 l WWW Yo ammabla Data lines Q3Q1 are set to 1 Prim DUE j mentor anabl a programmed connection b Word 2 not connected w Q2 QE 3 2 quot a Output is 1010 E 2 ii 12 my oa my oa CSlZOB Introduction to Embedded Systems 2182003 Types of ROM Maskprogrammed ROM 39 I Order Increasmg Wnte ablhty Connections programmed at fabrication 7 Maskprogrammed ROM 7 Onetime programmable ROM Lowest write abimy 7 Erasable programmable ROM 7 Electrically erasable programmable ROM Highest storage permanence 7 Flash 7 Bits never change unless damaged Typically used rorrinal design ofhighvolume systems a E a Maya pinata Onetime programmable ROM EPROM Erasable programmable ROM Connections programmed after manufacture by user User provldes flle of deslred contents ofROM 7 File inputto ROM progammel39 I Programmable component is a MOS transistor 7 Transistor has oating gate surrounded by an insulator I Better Write ability 7 Erasedreprogrammed thousands oftimes I Reading is much faster than Writing Very low write ability 7 Typically written only once and requires ROM programmer device Very high storage permanence 7 bits don t change unless reconnected to progamma amp more fuses blown Commonly used in prototype or even nal products 7 cheaper then other PROM 7 harder to inadvertently modlfy through radiation or time 7 Cheaper for low Volume and faster leertormarket than Mask PROM I Reduced storage permanence 7 Program lasts about 10 years 7 But is susceptible to radiation and electric noise I Typically used during design development mm as mm as EEPROM Electrically erasable EPROM Erasable programmable ROM Programmable ROM I Programmed and erased electronically 7 Typically by using higher than normal voltage 7 Can program and erase individual words Better write ability 7 Inrsystem programmable with builtein eireuit to provide higier than normal voltage Bulltrln memory eonaolleruseoto hioe oletails 39om memory user 7 Writes very slow due to erasing and progammlng lEI39s microseconds versus lEI39s nanoseconds syquot olie 7 a Negative charges form channel betwe sou and drain Stonngloge 7 bNegatlvechargestomoveoutof as channel and get trapped in oating gate 7 CUV rays causes negative chargesto similar storage permanence to EPROM about 10 years re nel from oatlng gate Far more convenient than EPROMs but more expensive light can pass mm as CSlZOB Introduction to Embedded Systems 2182003 Flash Memory RAM Randomaccess memory Extension of EEPROM Typically Volatile memory Same amggalepmclple 7 bits are not held without power supply 7 Same write ability and storage permanaace Fast erase Read and Written to easily by embedded system 7 Large blocks ofmemory erased at once rather than one word atatime dmmg exec mm 7 Blocks typically several thousand bytes large Writes to single words may be slower sequential access like tape and disk 7 Entire block must be read word updated then mtlre block wnttm back Used in systems storing large data items in NV memory 7 E g digital cameras TV setrtop boxes cell phones Randomaccess as opposed to rw enable An A i 2n mire as mire oz RAM Internals Basic types of RAM Intemal structure more complex than R OM SRAM Static RAM 7 a word consists ofseveral memory cells each storing 1 bit 1 7 Memory cell uses lpr op to store bit mm 7 each IO datal e o e ch cell ln lts co umn r Requlres 6 lranslstors e rdwr connected to ery cell 7 Holds data as long aspower supplied M e w enrow is mable y r DRAM Dy amlc lfrdwr indicates write eaeh eell haslegie that stares input data bit 7 Memory can uses MOS hamster and ata lfrdwr indicates read each cell has luglcs that eutputs stared hit capamom store b new i M re 7 Refresh requlred due to capacitor leakag Cells reaeshedwhenread M e Typlcal refresh rate 15 625mlcrosec m D r Slowerto access than SRAM 7 Usually implemented on anoLherIC T a 21 22 mm mm Ra t Example In varla 10ns Hl16264 amp 27C256 RAMROM devrces PSRAM Pseudostatic RAM Lowcost lowcapacity memory devices DRAM With bmltrm memory refresh centroller Commonly used in 8bit microcontroller based embedded 7 Popular lowrcosthlghrdmslty altematiye to SRAM systems NVRAM Nonvolatile RAM First two numeric digits indicate device type 7 Holds data after ertemalpoweremoyed RAM 62 r Batteryrbacked RAM 7 ROM 27 s Wth ewnpermanently eanneeted battery lasang in years writes as fast as reads Subsequent digits indicate capacity in kilobits 27C256 is actually an EPROM nu limit un number efwntes unlike nenyelaale ROMrbased memury 39 e Myl memury suckhasawntecynlehmltufSElElllllll Q r SRAM Wth EEPROM or as H h stares rumplete RAM eentents un EEFROM Dr ash hefere pewertumed uff mire as mire oz CSlZOB Introduction to Embedded Systems Example HlVI6264 amp 27C256 RAMROM devices 11713 15719 716113112415 Ram 22 addr addr OE CSl 39 C514 39 0 mm m 25 Win Example TC5 5V2325FF 100 memory device A singlermd ugmuun CLK lilll mos ADSC ADV addr lt15 ngt OE CSl andcsz cs dataltzl ngt d m mm as Composing memory 7 Connect sidebyside to increase width ofwords enable En i may as 2182003 Example TC5 5V2325FF 100 memory device 2smegabit synchronous H dam Us pipelined burst SRAM addrlt15 EIgt memory device 439 Edam gt Designed to be csl interfaced with 32bit 4 35531 processors Fast single byte WE readwnte m Burst mode read MODE 7 ADsP ADsc and ADV all actlve 4 mpg 7 Output sequential memory location at 4 350 9 37 1 ADV Burst mode write CLK TCSSV ZSl Fsl 26 mining Composing memory Memory size needed o en differs from size of readily available memories When available memory is larger simply ignore unneeded highorder address bits and higher data lines When available memory is smaller compose several smaller memories into one larger memory may as Composing memory 7 Connect top to bottom to increase number ofwords added nignorder address line selects smaller memory containing dvslred word using a decoder 2 Xn ROM mm as Q l Qn CSlZOB Introduction to Embedded Systems 2182003 Composing memory Memory hierarchy 7 Combine techniques to increase number and width ofwords Want inexpensive fast memory Main memo 7 Large inexpensive slow memory stores entire progam and data Cache 7 Small expensive fast mory stores copy of llkely accessed parts of larger mem ory 7 Can be multiple levels of cache Disk outputs 31 5 mile oa 32 mile 02 Cache Cache mapping Usually designed with SRAM 7 fast more expensive than DRAM Usually on same chi Used to assign main memory locations to cache locations and determine hit or 39 S r 7 Much less cache locations than main memory locations 7 pace limited so much s aller than offrchlp main memory e faster access 1 cycle vs several cycles for main memory Thee baSIC tecmques Cache operation Dire m 7 Request for main memory access read or write e First check cache for copy hehit eupyisin eaehe quick access eaehemiss eupynutin eaehe read he Several cache design choi 7 Fully associative mapping 7 Setassociative map 39 m main memory into eaehe ces Caches partitioned into indivisible blocks or lines of 7 cache mapping replacementpolicies and write techniques adjacent memory addr 7 usually 4 or 8 addresses per line a 4 Maya Maya Direct mapping Fully associative mapping 39 Maiquot memory address diVided into 2 I A addresses stored in cache simultaneously compared elds with desired address 7 Index eaehe address number ufbits determinedby cache size Tag comparedwithtagstoredineaeheat address indicated by index iftags match cheek valid bit Validbit 7 indicates whether data in slot has been loaded from memory et 7 used to ndpartlcularword in cache llne 35 mire oa 35 mile 02 Section 61 Sequential Logic 7 FlipFlops Page 1 of5 6 Sequential Logic FlipFlops Combinatorial components their output values are computed entirely from their present input values Sequential components their output values are computed using both the present and past input values In other words their outputs depend on the sequence of input values that have occurred over a period of time This dependence on the past input values requires the presence of memory elements The values stored in memory elements define the state of a sequential component Since memory is finite therefore the sequence size must always be finite which means that the sequential logic can contain only a finite number of states So sequential circuits are sometimes called finitestate machines Sequential circuits can be a asynchronous or synchronous Asynchronous sequential circuits change their state and output values whenever a change in input values occurs Synchronous sequential circuits change their states and output values at fixed points of time which are specified by the rising or falling edge of a freerunning clock signal Clock period is the time between successive transitions in the same direction ie between two rising or two falling edges Clock period Clock frequency lclock period Clock width is the time during which the value of the clock signal is equal to l Duty cycle is the ratio of clock width and clock period Active high if the state changes occur at the clocks rising edge or Clock Width 39 39 R39 I d F 1139 d during the clock w1dth mg e 39 3 mg e 39 Active low if the state changes occur at the clocks falling edge Latches and flip ops are the basic storage elements that can store one bit of information 6 1 SR Latch s 0 Q The simplest memory element Consists of two crosscoupled NOR gates Inputs S set and R reset are normally 0 0 Q Both active high Asserting S setting Sl will make output Ql Asserting R setting Rl will make Q0 t1 2 t3 t4 t5 6 t7 8 9 110 One problem inherent in the SR latch is the fact that if both S and R are disasserted at the same time we cannot predict the latch output as in tl 0 The SR latch can also be implemented with NAND gates S Q S andR are normally 1 They are active low Section 61 Sequential Logic 7 FlipFlops Page 2 of5 62 SR Latch with Enable Similar to the SR latch but with the extra control 3 input C which enables or disables the operation 039 of the S and R inputs C When Cl the gated SR latch operates as an SR latc R Q When C0 S and R are disabled and the circuit persists in the preceding state 63 Gated D Latch D latch ensures that inputs S and R never equal to l at the same time Also SR latches are useful in control applications where we often think in terms of setting or resetting a flag to some condition However we often need latches to store bits of information and a D latch may be used in such an application Gated D latch is constructed from a gated SR latch with an inverter added between the S and the R inputs and use a single D data input nm The C control input is active high in this design but can also be active low When the C input is asserted the Q output follows the D input In this situation the latch is said to be open and the path from D input to Q output is transparent the circuit is often called a transparent latch for this reason When the C input is negated the latch closes the Q output retains its last value and no longer changes in response to D Latches are often called levelsensitive latches because they are enabled and transparent whenever C is asserted Method 2 Gated D latch can also be implemented using a multiplexer D H gt gt Q D Q c negative latch positive latch D passes to Q when C0 D passes to Q when Cl c l DJ l Q w L 41 El 159mg than Delay through one A01 gates is 20 Problem with the D latch there is a shaded window of time around the falling edge of C when the D input must not change This window begins at time tmq before the falling latching edge of C39 tmq is called the setup time The window ends at time than afterward39 than is called the hold time Section 61 Sequential Logic 7 FlipFlops Page 3 of5 64D FlipFlop A positiveedgetriggered D ip op combines a pair of D latchesl It samples its D input and changes its Q and Q outputs only at the rising edge of a controlling CLK signal When CLKO the first latch called the master is enabled open and the content of D is transferred to QM When CLKl the master latch is disabled closed and its output is transferred to the second latch called the slave The slave latch is open all the while that CLKl but changes only at the beginning of this interval because the master is closed and unchanging during the rest of the interval Advantage since the master and slave latches are never enabled at the same time the entire masterslave ip op is never transparent master latch slave latch QM Like a D latch the edgetriggered D ff has a setup and hold time window during which the D inputs must not change This window occurs around the triggering edge of CLK rising clock edge for a positiveedgetriggered ff and falling clock edge for a negativeedgetriggered ff If the setup and hold times are not met the ff output will usually go to a stable though unpredictable 0 or 1 state In some cases however the output will oscillate or go to a metastable state halfway between 0 and 1 All propagation delays are measured from the triggering edge of CLK since that s the only event that causes an output change A negativeedgetriggered D ip op simply inverts the clock input so that all the action takes place on the falling edge of the clock There are many different ways to construct ip ops but they all exhibit the following two characteristics 0 a ff will change state only on the positive or negative edge of the clock signal 0 its data inputs must not change after time 132W and before that All ffs can be divided into four basic types SR JK D and T o The SR ff has two inputs S set and R reset that set or reset the output Q when asserted o The JK ff has two inputs J and K just like the S and R However when both I and K are asserted at the same time the JK ff changes its state 0 The D ff has one input D data which sets the ff when Dl and resets it when D0 o The T ff has one input T toggle which forces the ip op to change states when Tl 1 Gajski differentiates between masterslave ff and edgetriggered ff Wakerly and many other books say the edge triggered ff is the masterslave ff Section 61 Sequential Logic 7 FlipFlops Page 4 of5 Characteristic Name FF Symbol Truth Table State Diagram Characteri tic Equations Excitation Table SR 3 Q s R Qn 7 10 QQampr S R Clk 0 0 Q WM 0 o o X R Q 0 1 0 0 1 1 0 1 0 1 1 0 0 1 The triangle indicates that 1 1 NA SR00 0I10 1 1 X 0 Lheffis triggaed by e SR01 risingege met SR Q SR 0 JK Mg 10 QQamp J K I Q 0 0 Q JK000r01 0 0 0 X Clk 0 1 0 o 1 1 X K Q 1 0 1 1 0 X 1 1 1 Qgt JK00 or 10 1 1 X 0 JK010r11 met J K QHK HKQ J K Q JK Q JK Q JKQ K QJ I JQ K K K QJQ D DQ I QQampt D D Q 0 0 H 0 0 0 Clk 1 1 o 1 1 1 1 0 0 Q D1 1 1 1 D0 QnextD T TQm H H QQampt T T Q 0 Q 7 0 0 0 a e 011 1 1 0 1 Q T0 1 1 0 T1 metTQ T QTQ R 00 01 ll 10 Q 11 110 111 1 R39Q A 1 F SR


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