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by: Adele Schaden MD


Adele Schaden MD
GPA 3.88


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Class Notes
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This 3 page Class Notes was uploaded by Adele Schaden MD on Thursday October 29, 2015. The Class Notes belongs to CS 203A at University of California Riverside taught by Staff in Fall. Since its upload, it has received 17 views. For similar materials see /class/231745/cs-203a-university-of-california-riverside in ComputerScienence at University of California Riverside.

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Date Created: 10/29/15
CS 2 Advanced Computer Archi iec iure Lec Tu re 1 Fundamentals of Computer Archi iec iure Amdahl39s Law Insfrucfor Jun Yang 926DDU2 Les 1 1 Three Differen r Compu ring Marke rs Deskfop Compufing Still the largest market in terrns Driven by optimizing pricegerformance ervers computers ihai provide largerscale services such as rehabie iongeterm hie storage and access larger memory and more Embedded Compufers Pr ce keaIiime performance requirement Memory size and power consumption 926DDU2 Les 1 2 Wha r is Compu rer Archi rec rure Compu ier Archi iec iure Insfrucfion Sef Archifecfure Organizai39ion Hardware 926DDU2 Les 1 z The Ins rruc rion Se r a Cri rical Inferface The aci39ual programmer visible insi ruci ion sef so 39ware hardware 926DDU2 Les 1 A Example Organiza rion TI SuperSPARC39m TMS390Z50 in Sun SPARCsfafionZO integer Unit MEus control MS Adapter 926DDU2 Hardware Machine specifics Feature size 10 microns in 1971 to 018 microns n 2001 Min mum size of airansisior or a w re n either the x or y d mension Log c designs Packaging technology Clock rate Supply voltage 926DDU2 Les 1 5 Relationship BeTween The Three AspecTs Measuring Performance 39 Processors having idenTical ISA may be very differenT in organizaTion eg NEC VI 5432 and NEC VI 4122 39 Processors wiTh idenTical ISA and nearly idenTical organizaTion are sTill noT nearly idenTical eg Pent um II and Celeron are nearly identical but differ at clock rates and memory sysTems gt ArchiTecTure covers all Three aspecTs enoauuz Les i CPU ExecuTion Time not nclud rig the lime waiting for 10 or running other program in a mullirprogrammed envtronmeni user CPU time system CPU time inaccurate ThroughpuT tasks completed per will lime measuring large data processing center etc enoauuz Les i Choosing Programs To EvaluaTe Perf Performance Terminology SynTheTic benchmarks e Aliempi io maicn average frequenc es of operaiions and operands in reoi workloads e e g wneisione Dhrysione r e g quicksorl puzzle Kernels ime criiicai excerpis of reoi programs 7 e g livermore loops Real programs g gcc sp ce SPECEQ e SPECZOOO enoauuz Les i X is nTimes fasTer Than Y means ExecuTion Timey ExecuTion Timex X is 11 fasTer Than Y means ExecuTion TimeV ExecuTion Timegtlt X 100 m ExecuTion Timex enoauuz Les i CompuTe Speedup Amdahl s Law Amdahl s Law Speedup is due To enhancemenTE WWW Execution time wo E Before 5 eedu E P P Execution time w E After Suppose ThaT enhancemenT E acceleraTes a fracTion F of The Task by a facTor S and The remainder of The Task is unaffecTed whaT is The Execu on finem and 5peedupE enoauuz Les i ii EXECU O lmzafrer ExTimebmre x 1F ExTimebmre 1 SpeedyME ExTimzaner 1F enoauuz Les i Amdahl s Law An Example Q FloaTing poinT insTrucTions improved To run 2X buT only 10 n o execuTion Time are ops WhaT is e execuTion Time and speedup afTer improvemenT Ans F 01 s 2 ExT mew ExTiqum x 101 012 095 ExT meMme ExTimeMm 1 Speedup 1053 ExTimEan 095 Read examples in The book 9060002 Les Corollary Make The common case fosT All insTrucTions require an insTrucTion feTch only a fracTion require a daTa feTchsTore p mize nstruction access over data access Programs exhibiT localiTy Spatial Locality Temporal Locality Access To small memories is fasTer Provide a storage hierarchy such that the most frequent accesses are to the smallest closest memories Re rs 9050002 CPU Performance The Fundamental Law seconds instructions cycles seconds CPU time xx p am program instruction cycle Three components 7 Instruction count 7 CPI 7 Clock cycle time 9050002 CPI Cycles per InsTrucTion Average CPI CPI 1 Cycle Total Instruction Count ZCPIxxF where E L F Instruction Count CPU time Cycle time x Z CPI X 1C F1 Example Instruction Type ALU Frcucnc Clockc les average CPI 043 042 024 048 157 cyclesinsTrucTion 9050002 1 1 16 Example InsTrucTion mix of a RISC archiTecTure Inst ALU Lucia Stare Branch Freq 50 20m 10m 20 c c 1 2 2 Add a regisTermemory ALU insTrucTion formaT One op in regisTer one op in memory The new insTrucTion will Take 2 cc buT will also increase The Branches To 3 c Q WhaT fracTion of loads musT be eliminaTed for This To pay off 9050002 So luTion Instr F CPI CPIxF I CPI CPIxI 5 l 5 5X 1 5X Lou 2 2 4 2x 2 42x Store 1 2 2 1 2 2 Branch 2 2 4 2 3 6 RegMem X 2 2X 10 CPI 15 1egtlt 17ext1egtlt Exec Time InsTr CnT x CPI x Cycle Time Instr Cntatd x CPIDM x Cycle t men gt Instr Cnth x CPIW x Cycle tlmemw 10 x15 gt1exx17ex1ex gtltgto2 ALL loads musT be eliminaTed for This To be a win 9060002 test 12


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