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by: Adele Schaden MD


Adele Schaden MD
GPA 3.88


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Class Notes
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This 12 page Class Notes was uploaded by Adele Schaden MD on Thursday October 29, 2015. The Class Notes belongs to CS 203A at University of California Riverside taught by Staff in Fall. Since its upload, it has received 13 views. For similar materials see /class/231745/cs-203a-university-of-california-riverside in ComputerScienence at University of California Riverside.

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Date Created: 10/29/15
CS 203A Advanced Computer Architecture Outline Lecture 2 Instruction Set Principles Instructor Jun Yang gagmm Lee 2 l Instruction formats Types of operations Operand type and size Location of operands Addressing modes 9221nn4 Lee 2 Instruction Sets Instruction Sets 39 ISA is the structure of a computer that a machine language programmer or a compiler must understand to write a correct program for that machinequot 39 What makes a good instruction set Implementability Supports fro wto hi r formanee mplementations Programmability Pre1930 Human programmabllityIA semant cally close to highlevel language HLL but with different H Post1980 Compiler progmmmability Prmitive instructions zed from wh eh solutions are synthesl u gagmm Lee 2 z 39 What makes a good instruction set UpwardForwardBackward compati bi lities make sure all written software works business reality software cost greater than hardware cost forwar compatibility reserve trap hooks to emulate future ISA extensions 9221nn4 Lee 2 A Instruction Set Architecture ISA Generic Examples of Instruction Format Widths What must be specified 39 Instruction Format length encoding 39 39 ed ow is it deco Insfruc film Decode 39 Operations data pes and sizes t are supported 39 Location of operands and result Where other than memory Ho memory operands located 39 Control instruction Jumps conditions branches Quamm L2 2 32 r6 0 4 bits Fixed Eusy Pipeliningsuperscalar Less compact Variable re compa t Mo 5 Harderbutdoableto superscalarpipeline 39Recentl a eared Hybrid ea Jaime processors use 32bit added 16bit for code compaction 9222uu4 L2 2 Effects of Instruction Formats on Code Size Typical Operations little change since 1960 39 If code size is most important use variable length Data Movement Instructions memorytomemorymove 39 If performance is most important use fixed length I tWtore r instructions Recent embedded machines ARM MIPS added optional mode to execute subset of 16bit wide instruct39on Thumb MIPSl per procedure decide performance or densit Some architectures actually exploring onthefly decompression for more density n n 7r r a memory instruction cache using special hardware Branch targets are handled through an address mapping table for uncompressed and compressed code 39in Quamm L2 2 op tofrom stack Arithmet c nte er ginary dec mal or FP Ad su rac Multiply Divide Shift shift leftright rotate leftright Log cal not set clear Control Jum pBranch unconditional conditional Subrout ne L nkage call return Interrupt trap return Synchronization test a set atomic rmw Str ng s arch translate craph cs MMX parallel subword ops 4 16bit add WZMEIEIA Lee 2 Top 10 80x86 Instructions Operations for Media and Signal Processing Rank instruction integer Average Percent total executed 1 load 22 2 conditional branch 20 3 compare 16 4 store 12 5 3 6 and 6 7 5 a move register register 4 9 call 1 10 return T Total 96 Simple instructions dominate instruction frequency 9222uu4 L2 2 SIMD single instruction multiple data vector A single instruction launch multiple narrower data operations add multiply compare shift etc See Figure 217 on Pg 110 For DSPs No exception handling for arithmetic overflow Because of realtime application Multiplyaccumulate MAC instruction Key to dot product ops for vector and matrix multiplies Different rounding modes for wide accumulators 9222uu4 L2 2 in Data Types and Sizes Location of Operands and Result Distinction between sw types and hw types sw type is property of a variableconstant liw type is property of an operation precision 64 bit Fixed point types Signed 2quotquotto 2M 1 add sub mul div tc Unsigned 0 to 2quot 1 addu subu mulu divu log cAtbitwise o s Operands for Media and Signal Processing word 32 bits i 5 double Vertex x y zcoordinates and Pixels RGBA 32 bits 9222uu4 L2 2 ii Most real machines are hybrids of these Stack mostly 6039s and 7039s java hytecodes address add to t sood code density tos implicit Memory and p pelining bottlenecks Accumulator 1 register pre 6039s lad ress add A acc lt acc memA acc acc memA x RegisterMemory extended accumulator 7039s and 8039s address add A B A s mB 3 address add A B c sood code density Asymmetric operands asymmetric work per nstruction A lt B C memBC 9222uu4 L2 2 i2 Location of Operands and Result Location of Operands and Result hgistIMgistI 60 s and onwards 3 address add Ra Rb Re Ru 1 Rb we Lucid Ra Rb Ra numpzh s or Ra Rb rnnnb Ru 7 natgaaa tareaee density Operand symmetry 7 Deterministic ien in ALUaperatians e Seneeuiingaggarmnitesete camgarisan Bytes per insir uciiun Number at instrueiiunsgt Cycie per insir uciiun mmnm kn 2 3 in as an um mmnm kn 2 lb Comparing Number of Instructions General Purpose Registers GPR Dominate Code sequence for c A a for four eiasses of instruction sets Register Register Stack Aeeumuieiur registerrmemury inadrsiure PushA Land A Land MA Laud MA Push E Add E Add ME Laud kZE Add 5mm 5 5mm 5 Pl Add kEKJEHEZ Pap c stareuza mmnm kn 2 5 After 1930 almost all machines use general purpose registers Advantages of registers r Registers are faster than memory 7 Registers are easier fur a cumpiier in use E g A1917 to e isriean da mui ipiie in mymder is see 7 Registers can naia variabies Memar waif c is reduced sa m mm is s 2d u t rsare fastervnazrugmary P P r Cude density improves r snarier identifier sinee neg mmnm kn 2 6 Two characteristics of GPR architectures Memory Addressing Examples Advantages Disadvantages Read Figure 24 on Pg95l gasmm Lee 2 Since 1980 almost every machine uses addresses to level of 8 bits byte Two questions for design of ISA Since one could read a 32bit word as four loads of bytes from sequential byte address of as one load word from a single byte address how do byte addresses map onto words Can a word be placed on any byte boundary gasmm Lee 2 Endianness Memory alignment 39 Order of bytes in words 39 Little endian stores the most significant byte MSB in the byte with the littlest address Intel 80x86 DEC Vax DEC Alpha Windows NT 39 Big endian stores the MSB in the byte with the biggest address IBM 360370 Motorola68k MIPS Spare HP PA Store Oxdeadbeef to address 0x10000000 Address 0x10000000 0x10000001 0x10000002 0x10000003 Big Endian Oxef Oxbe Oxad Ox e Little Endian Oxde Oxad Oxbe Oxef auxmm Lec 2 Keep n m nd that memory is byteaddressable so a 32bit word actually occupies fourcontiguous locations bytes ofmain memory Address 1 2 3 4 5 B 91011 mam CW Word 1 Word Z Word 3 The MIPS architecture requires words to be aligned in memory 32 bit words must start at an address that is divisible by 4 r 0 4 E and 12 are vaildwurd addresses 7 2 3 5 6 7 9 10 and 11 are natvaild Wurd addresses s Unallgned memory accesses result in a bus error Whlch you may haye unfurlunalely seen befure This restr ction has relatively little effect on highlevel languages and compilers but it makes th ngs easier and faster for the gasmm Lee 2 CS 203A Advanced Comgter Architecture Lecture 2 Instruction Sets Pipelining RI SC Vs CISC CISC complex instruction set computer VAX Intel X86 IBM 360370 etc RISC reduced instruction set computer MIPS DEC Alpha SUN Sparc IBM 801 RISC vs CISC Characteristics of ISAs NSC l SC Variable length Single word instruction instruction Variable format Fixedfield decoding Memory operands Loadstore architecture Complex operations Simple operations RISC vs CISC Instruction Set Design The historical background In first 25 years 1945 70 performance came from both technology and design Design considerations 0 small and slow memories compact programs are fast 0 small no of registers memory operands 0 attempts to bridge the semantic gap model high level language features in instructions 0 no need for portability same vendor application 05 and hardware 0 backward compatibility every new ISA must carry the good and bad of all past ones Result powerful and complex instructions that are rarely used 1709 m Top 10 80x86 Instructions Rank lnstructlon Integer Average Percent total executed 1 load 22 2 condltlonal branch 20 3 compare 16 4 store 12 5 add 8 6 and 6 7 sub 5 8 move reglsterreglster 4 9 call 1 10 return 1 Total 96 Slmple lnetructlons domlnate lnstructlon frequency RISC vs CISC Instruction Set Design Emergence of RISC Very large scale integration processor on a chip Registers loadstore ISA Microstore occupied about 70 of chip area replace microstore with registers Increased difference between CPU and memory speeds Complex instructions were not used by new compilers reduced reliance on assembly programming new ISA can be introduced standardized vendor independent OS Unix became very popular in some market segments academia and research need for portability Early RISC rojects IBM 801 America Berkeley SPUR RIS I and RISC II and Stanford MIPS ou The MIPS InsTr39ucTion FormaTs All MIPS insTrucTions are 32 biTs long The Three insTrucTion formaTs 31 26 21 16 11 6 o op rs rT r s amT LlncT R e I I I d I h f Typ 6 biTs 5 biTs 5 biTs 5 biTs 5 biTs 6 biTs 31 26 21 16 O I4 p6 I op I rs I rT immediaTe I y 6 biTs 5 biTs 5 biTs 16 biTs 31 26 O J Type I 0D I Tarqu address I The differenT fielg ihsre 26 bi op operaTion of The insTrucTion rs rT rd The source and desTinaTion regisTer specifiers shamT shifT amounT funcT selecTs The varianT of The operaTion in The quotopquot field address immediaTe address offSeT or immediaTe value TargeT address TargeT address of The jump insTrucTion 7 itype inslruminn 6 5 16 0pcode rs rt Immediate Eneddes Leads and stores 61 byles nail words words double words Ali lmrnediates 11 r op immediate Conditional blanch instructions rs is register rd unused Jump register Jump and link register rd 0 rs destination immediate a Rlype instruction 5 5 5 5 5 oncade rs rd shamt lunct FlsgistarreglslerALu dpsratdns rd e rs lunet n Function encodes the data path operation Add Sub Rea lwrile special registers and moves Jtype instruction 5 26 Opcode Oiisez added to PC I Jump and jump and link Trap and return lrom exception 2003 Elsevier Salence USA All rights reserved 8 M7102 Ib MIPS Addressing ModesInsTr39ucTion FormaTs All insTrucTions 32 biTs wide RegisTer direcT m Eils 25b ImmediaTe DisplacemenT PC relaTive Summary InsTr39ucTion SeT Design MIPS Use general purpose regisTers wiTh a load sTore archiTecTure Provide aT leasT 16 general purpose regisTers plus separaTe floaTing poinT regisTers 31 GPR amp 32 FPR SupporT basic addressing modes displacemenT wiTh an address offseT size of 12 To 16 biTs immediaTe size 8 To 16 biTs and regisTer deferred 16 biTs for immediaTe quot 39 dispO gt reaisTer deferred All addressing modes apply To all daTa Transfer insTrucTions ES Use fixed insTrucTion encoding if inTeresTed in performance and use variable insTrucTion encoding if inTeresTed in code size Fixe SupporT These daTa sizes and Types 8 biT 16 biT 32 biT inTegers and 32 biT and 64 biT IEEE 754 floaTing poinT numbers E SupporT These simple insTrucTions since They will dominaTe The number of insTrucTions execuTed load sTore add subTracT move regisTer regisTer and shifT compare equal compare noT equal branch wiTh a PC relaTive address aT leasT 8 biTs long jump call and reTurn E Aim for a minimalisT insTrucTion seT E 1709 I01 1709 Pipelining 5sfage ExecuTion 5 s rage RISC loadsfore archi rec rure 1Insfruc139ion fefch IF ge r ins rruc rion from memorycache 2Insfruc139ion decode Regis rer read ID Transla re opcode in ro conTrol signals and read regs 3Execu re EX perform ALU opera rion loadsTore address branch ouTcomes 4Memory MEM access memory if loads rore everyone else idle 5Wri rebackre139ire WB wri re resulTs To regisTer file Solu rion Overlap execu rion of ins rruc rions S rar r insfruc rion on every cycle eg The new insfrucfion can be fe rched while The previous one is decoded pipeine Each cycle performing a specific Task number of sfages is called pipeline dep rh 5 here Nonpipelined rime123456789101112131415 l IF l ID l EX lMEMlWBl IF l ID l EX lMEM WBl IF l ID l EX lMEM WB Pipelined IO 1709 Pipeline Proqress Insfn moves with all confrol siqnals addresses data items gt differenf reaisfer leanhs of different sfaaes ME 7 3 R1 9939 Jim W R2 1 e a p za sL IlL R3 Maul 0 E m quotslit 3 7 a 5 ralB Data 39 R5 memory g4 R i data uiif t desl yam Bits 11715 n A k I w Bits 1620 f dest dest d st IF ID EX Mem ID EX Mem WB 13 Pipelined Confrol Group confrol lines by pipeline sfage needed Ex rend pipeline regis rers wifh confrol bi rs Instruction IFID IDEX EXllVIEM MEMANB ll


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