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by: Ana Hilpert


Ana Hilpert
GPA 3.92


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Class Notes
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This 42 page Class Notes was uploaded by Ana Hilpert on Thursday October 29, 2015. The Class Notes belongs to EE 134 at University of California Riverside taught by Staff in Fall. Since its upload, it has received 30 views. For similar materials see /class/231768/ee-134-university-of-california-riverside in Electrical Engineering at University of California Riverside.

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Date Created: 10/29/15
Digital Integrated Circuit IC Layout and Design Week 10 Lecture 20 Midterm Due in Class Dynamic Logic SRAM Wrap up EElBA Clocked CMOS Logic CZMOS El Clocked CMOS Register Positive Edge 1 low Master enabled N1 D M1 amp M3 on Slave latched M6 and M7 off Output 0 is in charge storage mode oating HiZ state high impedance in high39 Master HiZ state N1 oatingFquot Slave enabled QM Dquot U Master D 39 l J N1 CZMOS Precharge Evaluate PE Logic General Concept Specific Example VDD CLK 0 Precharge output 2 VDD Me off Mp on 2 VDD CLK 0 Precharge Z CLK 1 Evaluate Mp off Me on Pull down 2 or not depending on logic implemented in PDN EE134 3 CLK 1 Evaluate Z AB C Domino Logic El Like falling dominoes V DD CLK0 Precharge CLK1 Logic propagates thru series of gates like dominoes falling E334 4 Domino Logic with Keeper at output a Use small Mkp EE134 Dynamic Shift Register a Nonoverlapping clock amp T T T T A0 2 A1 1 A2 A1 2high 2high EE134 NonOverlapping CLK A2 Initially CLK1 Black 1 1 842 0 0 Red CLK 1 Blue Static RAM SRAM El SRAM Cell Simple DFF Latch Word line low Pass transistors M5 and M6 olf Data latched in inverter pair DFF Latch Word line high Writing I Reading Writin Write h forc Reading BIT and BIT precharged to either VDD or VDDIZ Read my SRAM at transistor level EE134 EE134 Summary El Major Challenges Cost Power Consumption Robustness Complexity El Some new circuit solutions and design methodologies are coming EE134 Technology Scaling Comesy n Knsm zmmhy my Ema Research Roadmap eonm Node 29quot ssnm Nude 2005 MumIGnm Ema 201 5201 9 Research mum 39 mumnu mum me gt latmums m m mmnu rmmw M y oz NonplanmnGm quotPM HAghKamp mum 1an Oullnn m Emu mm must no Device Evolution 32quotquot Nude 2mm Cunvemionll rowing blim doquot in 300mm Fibs r Banana Awmn chmluy m Pnsmunm Mun nqu gt10 hminn gal5 Tapdown Approach ism limn um emll 39 I39llgraded mm so Iohm cmu lmoL Icslcv MM EE134 13 25 nm FinFET 25 um MOS transistor Folded Channel EE134 1A Cost El Mask cost in 90nm technology is over 1 M El Bugs are very expensive El Design effort increases in DSM El Cost of new tools El Nonrecurring costs dominate the price effectiveness of lowvolume ASICs El Need to have a product that can fit multiple applications customers flexibility Ema 15 Power has become a Problem m Pentium 1 V ms 85 386 39 9amp3 4 I 1 iner Walls Ema 1e The Productivity Gap E LogicTrlChip Euquot 9 Tusun Month 3 E D39 SBWYr compounded 39 a m omplexitygrowthrate 2 6 o E w E a M U quotj 39 21in compound 39 g Mb Productivity growth rate 1 nmu om vnmhmv mmnm nmrm asseeaeeeeeeeaa Source Semaiem EE134 17 Challenges in Digital Design a The Deep Submicron DSM Effect oc1lDSM Macroscopic Issues 0 TimetoMarke 0 Millions of Gates 0 HighLevel Abstractions o Reuse amp IP Portability o Predictability 0 etc 06 DSM Microscopic Problems 0 Ultrahigh speed design Interconnect 0 Noise Crosstalk 0 Reliability Manufacturability 0 Power Dissipation 0 Clock distribution Everything Looks a Little Different and There s a Lot of Them EE134 18 ABET Evaluation Course Objectives El Things that you should have learned in EE134 EE134 component or impact of engineering solutions in a global and use modern engineering tools necessaIy for EE141 Digital Integrated Circuit IC Layout and Design Week 4 Lecture 7 httpwwweeucredulrlakeIEE134htm EE134 1 Reading DWeek 1 Read Chapter1 of text DWeek 2 Read Chapter 2 of text DWeek 3 Read Chapter 3 of text DWeek 4 Read Chapter 5 of text EE134 z EE141 Review D MOS Transistor Ch 3 Modes of Operation Deep submicron MOS Latchup nish up New Ei Inverter Ch 5 Voltage transfer curve VTC a Switching Point EEK CurrentVoltage Relations A good ol Transistor v95qu Quadrant Remth VG1EIV EEK EE141 Modes of Operation Good ol Transistor El Cutoff VGS lt VT ID 0 u Resistive or Linear VDS lt Ves 39 VT 839 W V2 VGs gt Vr ID n39Cox39f39VGs Vr39VDs u Saturation VDS gt VGS 39 VT VGS gt VT C W ID unTOX39T390GS VTY11VDS EE134 5 A Model for Manual Analysis Vns gt VGs VI Saturation D n3939VGSVT2 39l139VDS G D I VDs lt VGS VI ReSistive D W V2 I k V V V D5 D 71 L GS T DS 2 with VT Vroy lelquot VSB 2 F EE134 6 EE141 CurrentVoltage Relations The DeepSubmicron Era w x 10 a V65 2 5 V Early 39Saturatlon i V65 2 0 V 7 1 5 g A 30 f 7 Linear 7 1 V65 1 5 V Relationship 5 E 0 5 VGS 1 0 V 0 5 1 1 5 2 2 5 VDS v EE134 7 10 Resistive gVelocity VDS VGS V T V65 10 V VDS V Long Channel Lzmpm WL15 EE134 1 IS 2 25 V05 V Short Channel LO25pm EE141 Regions of Operation Simplified Define VGT V657 VT VDSAT z Lfc I x lo I7m Vain Lmear Saturation I 5 g Linear C 1 7 Relationship o 5 V your Ivar Saturation o 5 I I 5 2 2 5 VDs V EE134 A Unified Model for Manual Analysis de ne VET VGS 7 VT G for VGT50IDO for VGTE 0 S g vD I O B With me mm VGT VDS VDSAT W V D IDktflVGf39Vinin39lwVDS EE134 EE141 Simple Model versus SPICE x 10 VDSVDSAT 2 W t Velocity 1 5 o W 2 0 0 D Lme 1 M VDSATVGT 0 5 GT Saturated 0 5 1 1 5 2 2 5 VDs V EE134 11 Transistor Model for Manual Analysis Table 32 Parameters for manual model of generic 025 um CMOS process minimum length device Vm V v w Vow V k39 AN A V1 NMOS 043 04 063 115 x10 006 PMOS 704 04 1 30 x 10 6 01 I keep all signs positive for PMOS and use VSG VSD ISD EE134 12 EE141 Ch 5 The CMOS Inverter A First Glance EE134 CMOS Inverter DD PMOS In Out NMOS EE134 14 EE141 Two Inverters Share power and ground Abut cells v EE134 15 CMOS Inverter FirstOrder DC Analysis VDD VDD T RP Vow Vout R 1 Vi VDD Vin 0 EE134 EE141 CMOS Inverter Properties El Full railtorail voltage swing 39 VOHVDD 8 VOL0 El Logic levels independent of transistor size Ratioless logic El Low output resistance kQ range El High input resistance El No direct current path in steady state ignoring leakage EE134 17 CMOS Inverter Transient Response VDD RF K tpHLfR nCL 069 Rn c a Lowto high b Hig htOlow EE134 18 EE141 Voltage Transfer Characteristic EEK PMOS Load Lines in WWW h 1 Vmvmr h vm 1 h h Wquot H 1 m Vny v1 VM 1 ID gt W Va er h M In h V max EEK EE141 rgturmmummy le CMOS Inverter Load Characteristics ll l A l u quotIquot us HIHIInInnnulunlmlunll quotIr quotg 7 MM n MVM 1 RW gt39iquot39 V 05 W Mquot m 39quotm WM M Van EEW 34 21 CMOS Inverter VTC Vow mr NMOS off NMO s s at w 39 Iquot PMOS res 39 lnl NMKS S sat OS sat 39 NMOS res h PMOS sat NMOS res PMO S Off EEW 34 22 EE141 Switching Threshold as a function of Transistor Ratio EE134 Determining VIH and VL V0H V0L VDD VIH VIL A g g V V V VOH VIE VM M VI V DD M g g NMH VDD VIH NML VIL VM Vent ANMOS off 2 NMOSsaI PMOS 39 N res Vin V V m NM6 sat 0L VIL VIH H 39 S S NMOS res PMOS 531 NMOS res PMOS off A simplified approach EE134 12 EE141 Inverter Gain g 1 anDSATnkaDSAT2 IDVM kn Xp mquot 1 r N VM VT VDSATnzxxn xp 0 05 1 15 2 25 EE134 25 Gain as a function of VDD 051 O EE134 26 13 EE141 Digital Integrated Circuit IC Layout and Design Week 3 Lecture 6 httpwwweeucredulrlakeIEE134htm EE134 Reading DWeek 1 Read Chapter1 of text DWeek 2 Read Chapter 2 of text DWeek 3 Read Chapter 3 of text EE134 EE141 Review Ei MOS Transistor Basic Operation Modes of Operation Deep submicron MOS EEK 3 Transistor Circuit Symbols Ei NMOS We always want Drain D Gate Body pSi substrate G lELi Source 5 n in Body tied to Source G l BS Gquot s S EEK A EE141 Transistor Circuit Symbols EIPMOS Source Gate Hi Body nwell We always want Drain D S S G Hi B S G H1 Body tied to Source D D PMOS Body Terminal B EE134 EE141 NMOS and PMOS u PMOS is complementary to NMOS El Turn it upside down and switch all signs of voltages VSD VDS VGS VSG NMOS PMOS D VSGgt o 5 Gquot G Vesgt 0 s D EE134 Threshold Voltage Concept D epl eti 011 region EE134 EE141 Transistor in Linear Mode VGs gt VDs VT Device turned on V gt V VDS lt VGS VT GS T p substrate B w v2 ID n 39COX T39VGSVT39VDS EE134 9 Transistor in Saturation VT lt VGs lt VDs VT VDSgt VGs 39 VT VGS I i tIiiiiiiiiiiiiiiiiiiiiiiiiiWitt IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII m w 39 v2 39 ID n 39 Cox 39T39 VGS VT VDs Pmdl Off EE141 CurrentVolta A good ol39 Transistor moquot ge Relations V SZZSV Resistive Saturation VGS Z 0 V Quadratic VDS VGS 39 VT Relationship VGS 1 5V VGS 1 0V EE134 El Cutoff VGS lt VT Modes of Operation El Resistive or Linear vDS lt VGS VT amp VGS gt VT w v2 ID un39cox 39T39VGS VT39VDS El Saturation VDS gt VGS 39 VT VGS gt VT ID EE134 39VGs VTZ1AVDS EE141 A Model for Manual Analysis Go o EE134 Vps gt VGS V1 Saturation 15 W a D 739I39Vss Vr2 391 39VD5 VDS lt VGS VT Resustive W V2 ID k77 V63 VT39VDS with VT VTo y 12 I5B WF CurrentVoltage Relations The DeepSubmicron Era moquot Early Saturation VGs25v VGS20V r VGS15V Relationship VGSZI 0V EE134 EE141 Velocity Saturation 0ms Constant mobility slope p Usat105 Constant velocity e 15 Viim EEiSA 15 Velocity Saturation ID M Longchannel device V V GS DD Shortchannel device Saturates sooner VDSAT VGs VT VDS EE134 EE141 lD versus VDS i0 Resistive gVelocity quot Saturatio 25 VDs V VDs V Long Channel Short Channel L10pm WL 1395 L025pm EE134 17 Regions of Operation Simplified Define VGT VGsi VT VDSAT Lg x m rm VDSAI Lmeax Saturation 5 3 Linea 0 V 7 Relationship 0 5 7 Vpxu39 Ivar Saturation I I 5 2 2 6 VDs V EE134 18 EE141 A Unified Model for Manual Analysis de ne VGT VGsi VT G for VGTSO1D0 8 G D for VGTZ 0 I 2 D Dkquot39VGT39K1 11Km39l IVDS O B quot1111 me mm VGT7 V135 VDSAT EE134 Simple Model versus SPICE VD9VDSAT 2 7 W Velocity 1 5 4 W g 0 0 D Lme 1 M VDSATVGT 0 5 GT Saturated 0 5 1 1 5 2 2 5 VDS V EE134 EE141 Transistor Model for Manual Analysis Table 32 Parameters for manual model of generic 025 pm CMOS process minimum length device Vm V r of er V k39 ANS A V1 NMOS 043 04 063 115 gtlt10 006 PMOS 704 04 1 30 X 10 6 01 EE134 SubThreshold Conduction Cutoff VDS VDD m x ponential 10 quot 6 10 39 Quadranc 39 Linear VGS V EE134 0 05 1 15 2 25 S inverse subtheshold slope ID Cox The Slope Factor qVGS N 09 nkT n1 S is AVGS for ImID1 10 S 1n10 Typical values for S 60 100 mVIdecade 22 11 Subthreshold Concepts El FETs turn off exponentially El Inverse subthreshold slope S mVIdec is the figure of merit that tells how well they shut off nkBT 60 mVdec 27 c 37 q 74mVdec 1oo c n 2 1 and typically 3 15 CI The maximum possible onoff current ratio ls Io n lmax 10VDDS Ioff El 2018 lTRS node has VDD 04V hence the static power problem ln10 5 n1 Know this if you are in an interview with a semiconductor co Outline El MOS Transistor CH 3 Equivalent resistance El CMOS Inverter VTC CH 5 El Dynamic Behavior of MOS Transistor Ch 3 EE134 Z4 MOS Transistor as 3 Switch Traversed path FIGS 2 VT DLLI ill I I I E VDS ID VGS VDD VDD2 VDD 1 t1 1 V r R 01 RI 139 R rdf7 Lah g mm 1771 am If m Rm z RWUMWUJ EE134 25 MOS Resistance 0 Solving the integral quotinn3 1 V 3 Vnn 7 J R dV li AV 6quot VDDZ VJ IDSAT1quotV 4105M 9 DD DI v W V2 mm 1 0531 570 VIM V 139 Vmn39 025 1I 0 Averaging resistances V V 2 V 5 UL up 1 7 Jxlqm R 1 z W 2 10547 i MGm min1 7 VDD2 4103111 6 EE134 26 EE141 Transistor as a Switch I LGSZ R 1 IYDD VDDz eq 7 r 7 2 IDSAT1rlDD BEAT1ATDD2 EE134 Equivalent Resistance 5 5 Ohm 4 D533 WL1 L025pm 2 1 t5 1 15 2 15 VDD Table 33 Equivalent resistance Rea WL 1 of NMOS and PMOS transistors in 025 11m CMOS process with L me For larger devices divide Req by WL Vol V 1 15 2 25 NMOS kg 35 19 15 13 PMOS kg 115 55 3s 31 EE134 EE141 MOS Capacitances Dynamic Behavior EE134 Dynamic Behavior of MOS Transistor EEiBA 30 EE141 The Gate Capacitance EE134 Polysilicon gate Gatebulk overlap Top view Gate oxide Cross section EE134 Gate Capacitance G G G iIiiliiiilililiilililililil lililililillililililil lililililillililililii CGC G CGC D iliiliiliiliiliil liliiliiliiliil D WW I Operation Region Cy C35 CM cmon CUXWLE lt i 0 i 0 i Trimle i 0 i CanLg z i CDXWLE Z i smuran39ou 0 i 23CWWLE i 0 i Most important regions in digital design saturation and cutoff EE141 Gate Capacitance VGS VosVGSVQ Capacitance as a function of VGS Capacitance as afunction of the with VDS 0 degree of saturation EE134 33 Measuring the Gate Cap 310216 39U VGS E 9 V 8 8 E 7 a 6 Q N o 5 9 N o 4 3 222215212050 05 1 15 VssW EE134 34 EE141 Diffusion Capacitance Channelslop implant NA1 Substrate NA Cdm Chmmm CLSW C 2LS W 1m CW CIXAREAC XPERIMETER mv EE134 35 Junction Capacitance abrupt junction linearjunclion 4 0 20 0 0 VD V C C 0 m 05 abrupt junction m 033 linear 39unclion J 1 VD mow J E334 36 EE141 Linearizing the Junction Capacitance Replace non linear capacitance by large signal equivalent linear capacitance which displaces equal charge over voltage swing of interest C g ijzwhrgxm K C M AVD Vmgh Vz 29 JD 7 7quot 39 lm lAm Keg WMVVWM 0Vlaw EE134 37 Capacitances in 025 gm CMOS process C 2 Co C 2 m in C m 27M IFum gt IFum IFum gt V FFum V NMOS 6 031 2 05 09 028 044 09 PMOS 6 027 19 048 09 022 032 09 EEWSA


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