ANALOG IC DESIGN
ANALOG IC DESIGN ECEN 4827
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Ecm4sz75sz7 lecture notes Two Stage OprAmp DC Soluu39on Part 1 Objectives m thas segment ofthe comse axe to 1 Renew necessary CMOS technology and deVAce chaaactensucs z Undexstand the mtemal con gmauon ofa tworstage CMOS Opramp 3 r Flguxe 1 shows a baslc worstage CMOS opr rnp con guxataon The Ieslstance R pxowdes blasmg fox the enme openmonal ampll ex M1 and M2 form a durexentaal pan and MS supphes the dttrexentaal pau wlth bias cunent I51 The mput dttrexentaal pau 15 actavely loaded wlth the cunent mlnox fonned by M3 and M4 Node 1 forms the output ofthe rst stage of the op amp The second stage conssts ofM6 whnch 15 a common does m mnpuuu not pxovlde biasing for Mo and that M6 15 blased hom the gate slde V mu Flguxel TV t M DC bias openmng pomt Numerical Example Given Process parameters no 60 pNVZ and upcox 20 pNVZ Vm The threshold voltage of NMOS devices 1V and th The threshold voltage of PMOS devices 1V Supply voltages VDD 5V and Vss 5V Device aspect ratios WLg 1 WL1 WL 100 WL3 WL4 20 Dc bias specifications IR1 11A IBl10uA IBz100uA DC Solution The rst step in nding the DC solution is to determine the value of the resistance R so that the bias current IR equals the speci ed value luA in the numerical example VDD RIR VGss Vss 1 which yields R VDD Vss VGS8IR 2 While the values of VDD Vss and IR are known the voltage Vng is not In order to solve for Vng we observe that the device M8 operates in the activesaturation region since the gate of M8 is shorted to the drain of M8 and therefore the following conditions are met 1 VGS8 Z VTN 2 VTN Z V508 Since M8 is in the active saturation region we have log IR HOW2WL8VGSS VTN 2 3 which can be solved for Vng VGS8 1IRK8 Vquot where K8 12 unC0xWL8 4 For the values in the numerical example Vng 12 V The value of Vng is then substituted into 2 and the value of R is determined to be 88 M9 The value of the gate voltage VGS can be found as VG8 VSS Vng 5 12 38V 5 Assuming that MS and M7 are in the activesaturation region the speci cations for the DC currents 131 and 132 together with the property of the current mirror can be used to nd the aspect ratios of M5 and M8 VI 5 E 10 and WM 100 6 WL8 IR WL8 IR The gates of M1 and M2 are grounded to obtain the nominal DC solution thus VGs1 VGsz Also ID1 ID IBL Since M1 and M2 are identical NMOS devices having the same VGS voltages assuming that M1 and M2 are in the activesaturation region the bias current 131 divides equally between M1 and M2 1Dl 1Dz SuA 7 At this point we can check whether the device M5 is in the activesaturation region The drain voltage of M5 is the source voltage of M1 and M2 ie the negative of the gate to source voltages ofMl and M2 VD5 VGSl VGSZ Vm M where K1 l2 unCoxWL1 8 The drain voltage of M5 is calculated to be l04V which is much larger than its gate voltage 38V Thus M5 is indeed in the activesaturation region Now continuing with the PMOS devices M3 and M4 M3 is in saturation as its gate and drain terminals are connected together Thus the source to gate voltage of M3 can be calculated as ngg thpl VIMK3 where K3 12 upC0xWL3 200uNV2 9 For the numerical example we get vSG3 116v 10 The drain voltage of M1 is VD1 VDD7 ngg 384V which shows that M1 is easily in activesaturation region The calculation of the drain voltage of M4 is done in the next le cture Comments The circuit utilizes two power supplies which are iSV in the numerical example The values of i25V or even lower supply voltages are also typical Single supply voltages V35 0 are also in common use with VDD as low as 25 V in battery powered electronic systems An NMOS transistor operates in the activesaturation region if the gatetosource voltage is greater than the threshold voltage Vm and if the gatetodrain voltage is less than the threshold voltage The activesaturation region of operation is most commonly utilized in analog circuits A PMOS transistor operates in the activesaturation region if the sourcetogate voltage is greater than the absolute value of the threshold voltage MM and if the draintogate voltage is less than the absolute value of the threshold voltage In the activesaturation region the effects of the drain to source voltage on the current of the device is neglected in the analysis so far In other words the effect of channel length modulation is not considered Na 1 i o n a I Stem icunductor The sgmamm intimation Photodiode Amplifiers Changing Light to Electricity PaulRako Strategic Applications Engineer Amplifier Group The Photodiode Simple 2 Volts Tiny current flows here 10 nanoAmperes nght Q 8 A Big Resistor 1 Meg gt Makes about a 10 millivolts here Na in u a Mmquot nrumiurmr 3 7 It 1 s39x u 2004 National Semiconductor Corporation The Photodiode No not really 2 Vans simple Light a a Big resistors make noise I n la n a I l39l39ml urnml39m mr 39 g A 8 Dark Current diode leakage flows too and is worse with temp I gt 10 millivolts is not very useful 4 2004 National Semiconductor Corporation The Photodiode Worse yet 2 Volts High impedance point difficult to interface with Light Q 8 Diodes are capacitors too so E And the capacitance 39 changes with voltage I n u a across the diode 5 2004 National Semiconductor Corporation The Photodiode Still Worse 2 Vots Light Ma To make the diode more sensitive to light you make the PN junction big 1 n I J u n a I Mm ul39rmrl39iwmr 6 V quot39 39 l quot Aquot 39 39 2004 National Semiconductor Corporation And that big junction has even more capac ance Inside the Photodiode A cap and a current source The bigger the voltage across the diode the further the junction boundaries are pushed apart and the lower the capac ance In u N a MUN M39rrud39urmr 7 39I r 3 t 39 1 2004 National Semiconductor Corporation Inside the Photodiode And a really big resistor There is also a bulk resisistivity to the diode but it is usually very high 100 MD This represents the l Dark Current In u N a Wm M39rum39rn39mr 8 II 3 i 39 1 2004 National Semiconductor Corporation Photodiode Amplifier Types Two ways to use the diode 1 The Photovoltaic Mode nght V V V NnHunal across diode 9 2004 National Semiconductor Corporation Photodiode Amplifier Types The Photovoltaic Mode No voltage across diode means no current though the big resistor No dark current Also Linear output Low Noise In in u a MWquot il39rum39ru mr 10 4 4 V 2004 National Semiconductor Corporation Photodiode Amplifier Types Use Photovoltaic Mode Where precision is more important then speed The lack of dark current removes an entire error term The lower noise makes smaller measurements possible The linear output makes calculations trivial I nl Juli a lm nrmul39urmr 11 II T 5 l 39g 2004 National Semiconductor Corporation Photodiode Amplifier Types The Photoconductive Mode Light I V 10V there is voltage across the diode In in u a himquot M39rum39urmr 12 39 4 4 7 2004 National Semiconductor Corporation Photodiode Amplifier Types Use Photoconductive Mode Where speed is more important then precision The voltage across the diode lowers it s capacitance This allows faster amplifiers Less capacitance allows a faster amplifier while maintaining stability In Juli a Mull nrmul39urmr 13 39r l 3 l 39 1 2004 National Semiconductor Corporation Biasing the Photodiode Apply a big voltage that doesn t change We want a low capacitance so put a big voltage across the diode We want fast response so 1 don t let the voltage ever change How In I u u a Mun IH39VI IHJ IM39J HJ 14 Ir 9 l 39v 2004 National Semiconductor Corporation Light 0 Volts tr As much reverse f this pin is at voltage as the diode ground so must this Ensut d pin be at ground rlu39vm M HIHNM J39UI39 V quot39 39 rquot 2004 National Semiconductor Corporation The Photodiode Ampli er This current makes Oh yeah add positive voltage here some feedback 10 Volts This pin stays at ground so output goes more chum positive with more light MW M39rum39in39mr quot39 2004 National Semiconductor Corporation The Photodiode Amplifier So it oscillates andor clips what is wrong a nght a 10 Volts 1 at la n a I Mull ul39rrurl39tu trlr 17 39 H lquot 39 2004 National Semiconductor Corporation Amplifier Stability Oscillations caused by capacitive diode oninput Photodiode looks like cap to amp v 10 Volts 1 at in n a I film ul39rrurl39iu trir 18 39 H in 39 2004 National Semiconductor Corporation Amplifier Stability Input pole freq domain or feedback lag time domain is bad Photodiode current source causes output to change But photodiode capacitor 10 Volts means feedback signal 0 mm mr will lag the actual output l a change Mechanical Analogy A gear and rack mechanical servo This gear is the amp output stage You are the amplifier frontend trying to keep the pointers the same This gear is the feedback I nl u n a I firm nrmm39rn mr V I Us 7 r Thh rackis the output vo age 20 2004 National Semiconductor Corporation mechanism Backlash here is a lag in the feedback The lag in your feedback pointer will cause you to oscillate the rack 1 at la n a I fl l ull ll39ruul39urtur l 21 2004 National Semiconductor Corporation Mechanical Analogy Input cap is like backlash in feedback mechanism 3 Backl SIN V 10 Volts In in u a hamquot nrrm 39tu mr 22 39 4 4 7 2004 National Semiconductor Corporation Mechanical Analogy Interesting note Driver backlash is like output capachance MN Backl sh 39 Q9 V Without compensation otmrmym either cap will cause 23 I H A 39 I o I 2004 National Semiconductor Corporation Compensated Amplifier gt Add a feedback cap to compensate Light a 10 Volts In in u a Wm urrmrl39urm r 24 39 1 m 394 4 2004 National Semiconductor Corporation Biasing the Amplifier The output is stable but there is a big DC offset Why Light a a 10 Volts Output never goes OiTQ fi i be39 W here even 25 n o I i g ht 2004 National Semiconductor Corporation Biasing the Amplifier Or maybe there is no output at all Why Light a 10 Volts Output stuck at zero gnaw even with maximum wlmu urnu 39m mr 39 mg 26 u I I g 2004 National Semiconductor Corporation I Biasing the Amplifier Answer Input bias current Light Q23 V 10 Volts Input pins will have small currents in or out crumw of the pin bias curreznt H A 39 2004 National Semiconductor Corporation Biasing the Amplifier Bias current may exceed photodiode current a nght a 10 Volts 15uA out of this pin reacts against 1M feedback to try ouumr and put 15 volts on outgut NW nrnmi39urmr V quot39 39 rquot 2004 National Semiconductor Corporation 39 Amplifier Input Stage Input transistors have base current Input bias J L current may V f be 15 pA but won t vary much over PNP temperature NPN Input Input Stage Stage I n la n a I NW nouriurmr 29 V 391 I I39I 39 2004 National Semiconductor Corporation Amplifier Input Stage Input JFETs have large drift Input bias current may be 15 pA but V f will double JFET every 10 C Input Stage Mu la n a Mun urrmrfmw r 30 39 1 m 394 4 2004 National Semiconductor Corporation Amplifier Input Stage CMOS parts have ESD diodes MOSFET has no DC bias current but mismatch in ESD J L diodes causes bias f current to flow in or out of pin CMOS Input Stage I nl u n a I 5W nrnud mtnr 3 1 V I Us 7 r 2004 National Semiconductor Corporation Correcting DC Bias Use resistor Light 2 LM H6642 fast LMV751 low noise 3910 VOlts Add resistor to compensate for bias ittinli ili ll lz lxt ltur nt 32 H in 39 2004 National Semiconductor Corporation Correcting DC Bias Servo out the error a nght a 10 Volts But this setup will i amp 39jfjggjw only pass AC signals 33 l o 39 2004 National Semiconductor Corporation Amplifier noise With stability and bias solved next problem is noise a nght 2 Voltage noise important on Current n0Ise this pin important on I nHunal rth inul lut itlr n 34 39 H A 39 2004 National Semiconductor Corporation Amplifier noise Low current and low voltage noise in the same part is hard JFET amplifiers have low current noise Bipolar amplifiers have low voltage noise Choppers can cause problems 1 n i u u a I w mu ni39rmdru t ur 35 39 I Ax V 2004 National Semiconductor Corporation A Composite Amplifier One solution a compound amp Run a lot of current to reduce the LM6171 is fast and voltage has I 15 volt rails for dynamic range n0Ise R1 JFETs have low current noise Nalio S I 2mm Natmna Semmunductur Curpuratmn Some Potential Parts Input Noise Input Noise Input I bias GBWP GBWPCin Device Voltage Current Capacitance max MHz MHzpF nVRtHz pARtHz pF LM H6628 2 2 15 20pA 200 133 LMH6626 10 18 09 20pA 500 556 LMH6624 092 23 09 20pA 500 556 LMH6622 16 15 09 10pA 200 222 LMH6654 6655 45 17 18 12pA 150 83 LMH6672 45 17 2 14pA 100 50 LF411A 25 001 4 200pA 4 1 LMV751 7 0005 5 100DA 5 1 LM0662 22 00002 4 001PA 14 03 typical LMV771 8 0001 4 1000A 4 1 0 I nHunaI w wu nrmm39mrnr m u 39 36 2004 National Semiconductor Corporation Conclusions Photodiode amplifiers are tricky The design should be tailored for the application DC Data etc The design requires a lot of trial and error Be prepared to do a lot of study National Applications Engineering is here to help you l nl u n a I w39l39vm nrmm urmr 37 V I Us 7 r 2004 National Semiconductor Corporation Resources AN1244 PhotoDiode CurrenttoVoltage Converters Amplifier WEBENCH Online simulation of amplifier performance Photodiode Amplifiers OP AMP Solutions by Jerald Graeme Photodetection and Measurement Maximizing Performance in Optical Systems by Mark Johnson Photodetectors Devices Circuits and Applications by Silvano Donati In u N a Will ni39mul39urmr 38 Ir 5 l 39g 2004 National Semiconductor Corporation Thank You If you have questions for our presenter please send them to our customer response center at newfeedbacknsccom The online technical journal National Edge is available at httpwwwnationalcomnationaledqel Sign up for National s monthly newsletter NewsNationa by updating your online profile at httpwwwnationalcomprofileuser infocqi 1 n J u u a I a J A 39 M um mm in Mr V 5quot I l39x 2004 National Semiconductor Corporation 3 4 a diw 53744 p a SrC 6405 M Cgm paqu h pi 30 ama JC39JLJ a Sz39rhoe Jf39dMa lM 5 RD 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TKS 4W 5 Q Smfequot V a M G KMJQEJ s 4 Courhp cud ecu4 TCsB T A quot 73m a Q TC5 Ads Abby JVVs 32 ARCS iguo coxgtq 1 quotquot 52 vsJquot ole a9 WAYJ Au A if S C T 39To A if wf4T 3 F54 gtgt 4 1 Q AOL 5 a 17 30 bowl w 30 a em C A gcawdu wdmd S 39BWOL 170 ETA SC I UUTT G4 YM 1595 7 WOVWMH mg verve Rxawwc f u Ref 7135 gnmug xng PA WE 3 Kg AXOEIAxOOau 37009ng w 11f 505 kd f gnnV 7A E focav Hy 34th sum Cabin W8C r 237 sigh I4 new V 050 1 me quot 4 MFJAP a gt T PM JINOJ h N ha a 03 oltm Farm04 mmpr f u 5 SK 349591 u H XP 90 97lt Immirofw PL Aux 23463 R 4 U Norwjnnmrvu puf ng DVFL gag 3F ZAU 4055 go gm n limo V o quotfro TLrLz JIAQSXJ an cuw 544 I V V onOM Q l fvSm L by ai ZMJ XW 74955 V n A n9 quotF W461ij T mWfiAP uve Q m 9U P f 755 rIAIQEOJ b r b l m V i n WE U x WTQWN fatsM3 H WOo T Fm v 0 UV mgr Wg rja 4mm 37375 Tram Ikmmq z 4van 2v Tn S cow JlmMu Nv alfa SdWm EtS KFSAU Wu R If 03 figd cum 1 r004 Unbx image a P 2 Ref 34 n O 3 v I n a n Fmoa 32983 mlrunxw Sb W 05647 00 wrvfdr 1 Err Pziiferfm L9 Pufjofi Pl 9 v13 f 30th gag mxrl8 69179 P b4u or 14mg Jymod a Hi My 1 S b Luxuku Jim n t h v 45 x N 44 A J19 In 13L 00 luff quotTbs f fr gx g Ly IPfJ xxxrfyng nos 4H 4 bw m J3 gt WEN hCTlTTSTJ lie x uo X 4T1 gt gc 4A5 20 H Wyn zoasrnon 10W lAk qL H O m 2043 TSa 3 1o4f1m 104T q 1 O 80 W532i 4171 N aquot 1191 gtgtL 1 T S1 LPH PM 10quot curd 39 113 gi T70 31 lt gm 4 2 42pm lt Tun 91 10c Wt 471 lt amp jw u 1 97 pc 2011 l39 jaoc z 23 mm 201 quotif AOL O iii o FVQ Tb a gt c C 4n M JH g0 C1rcj Orv fmygn at quotmth 80 1 3 H QFI m M191 9M n x qo Sip 3 T 3271 7 gm Nok ug 39 Megwsxg mitim 4M WTa wCLk A if Vimms IM 433 m TCO XV lt MWuVS CL XX 0 Mai ms 39S S FW 1753 39 T03 w2 tquot37gt 39P SLS Mgt1 shy M RF 80quot Burt3 PL 4c W5 63 Whigs W PM CWCJl39w 0 a T VFW wussW sigh Maj Hem HMCM M An MA k6 m KS mix a wk Juw vmH aka u JLgJhhf 736 23 Wow See Ye Yojes 44 D S 1 HSA atax39 oc aahawg 69 kw 3 o Q FM 763 s LJk runvans MILL Mme amp Fva Rah d aidM ahg W A4111 x C9 PM 37oc MTMAL M39I C Mo W Q Loo See ngv 4N Tq1 PM gt D a 3 00 do q5 Mylo 55 5 39la 60 0 6395 SA 7 4rk 276 0 o COMVEMSA om Teddye w TSB So W H gt vume Ema1121 th Le 43 Goo 7s gt JzTMdvKP a 4 WVCA L Mgt C M 0A TYDSHMR WW 31quot1301 7quot 4 B S39WNDHLD bwiWTwpe 5eka QMngmN IRA j 1 91 CL M10 new GM 1 L a Cc Celeb PM gt SQ Th aCQ 060x91 r we W c ws W MJ TESKSM Qmauaavk Wacoq 4 quot V W Tm N53 ECEN 4228 Notes Feedback in Electronic Circuits Frequency Response Effects 1998 Dragan Maksiinovic Do artmont of Electrical and Corn mtor Eiwiiiooriiw I I a a University of Colorado Boulder In this part of the notes we summarize the notation and the main results related to effects of feedback on the frequency response including gainbandwidth tradeoffs stability limits and compensation techniques SYMBOLS DEFINITION NOTES ULMH UH W 3W fawn few AGOUM mmVi BVV 17gtm Bandwidth frequency in rad where the mag nitude response is 31 ie v5 times smaller than the lowfrequency gain A0 Bandwidth in 215 lm5 A5 2 171L177 Opamp openloop transfer function or transfer function of any amplifier Ajw Aomw 2101 As5jw Opamp openloop frequency response A0 Aocm As Am 2 AjU l1u0 Opamp lowfrequency openloop gain opamp DC gain 20 log Ajw Opamp magnitude response in dB Frequency of the lowfrequency pole dominant 771 1 pole frequency fta A wta 1 Opamp unitygain frequency Opamp gainbandwidth product equal to the GBW GBW ta opamp unitygain frequency GBV V fga 40fp1 if all other pole and zero A in 215 are greater than f Slew rate maximum rate of change of opamp SR SR max I 0 output voltage SYMBOLS DEFINITION NOTES T 5 LG T 17 III0 Loop gain in a feedback circuit application T01 T01 Ts ij Loop gain frequency response T0 T0 Tjwwo Loop gain at low frequencies 20 log Tjw Loop gain nlagnitude response in dB lt T01 lt T01 arctan Loop gain phase response f f TVU 1 Crossover frequency unitygain frequency of aquot t J quotl the loop gain PM pM AM PM 1800 lt TOM Phase nlargin of the loop gain Tjw 4 I S Closedloop transfer function of a feedback cir C cuit application 1 I AOL ACUidcal Ideal closedloop response of a negative feedback I I I I circuit response that the circuit would have if 4C ldwl ALIhm AC I SMIPOO opamps used in the circuit were ideal ie if 14 14 Closedloo f 39 f fr dl 39k Aer1w Aer1w ACI5lsgtjw Circuit p gummy Womb 0 d on ML ACIIm ACIIm ACLUUI MIFO Closedloop lowfrequency gain of a feedback cir 20103 Am10 Bugt011 BVV cuit Closedloop magnitude response in dB of a feed back circuit Closedloop bandwidth in of a feedback cir cuit BWCL a fa for a feedback circuit with large phase nlargin PM for PMgt 45quot The n Extra Element Theorem R W Erickson The n Extra Element Theorem nEET is an extension of Middlebrook s Extra Element Theorem to the case when multiple extra elements are added simultaneously to a circuit Its major application is to write transfer functions directly as rational fractions without need to perform loop an node analysis and alge braic manipulations This is accomplished by treating each reactive component as an extra element that is added to the dc gain of the system The method gives a physical interpretation to the coef cients of L and C in the standard normalized form of the transfer function and it allows complex transfer functions to be derived nearly by inspection These results were derived by S Sabharwal who was a Caltech undergraduate who extended the basic single Extra Element Theorem The results were never published until many years later 1 T e basic nEET is described here without proof and several examples are worked Extensions involving special cases are described in another document 1 PRELHVIINARIES Given a linear network containing n inductors and m capacitors it is desired to nd the transfer function Gs ysus It is assumed that this transfer function can be written as a rational fraction as follows 7 lalsazszmanm 1 GWGch O Extensions allow derivation of Gs in other forms that involve frequency inversion The method used employs a generalization of the Extra Element Theorem in which all of the inductors and capacitors are treated as extra elements and are added simultaneously The zeroes of Gs are found with the output nulled in the presence of the input while the poles are found with the input set to zero The method allows the coef cients a1 a2anm b1 b2bnm to be found by evaluating the resistances seen looking into the ports under various conditions 11 De nitions DC state The DC state of an inductor is a short circuit and the DC state of a capacitor is an open circuit HF state The highfrequency HF state of an inductor is an open circuit and the HF state of a capacitor is a short circuit The above de nitions are extended later to handle the case of frequency inversion via de nition of nor mal and abnormal states of reactive elements The DC gain Gd G0 is fOLmd with all dynamic elements set to their DC states The transfer fmetion s coe lcients depend on how the reactive elements change to their HF states as explained below 12 General Form of the Coef cients The general form of the coef cient of sk has dimensions Hz k and is a sum of all combinations of terms of the form RXCI and LJRy which contain the proper dimensions The RC and Ry terms are fOLmd by appli cation of the nEET with injection at the terminals of the corresponding reactive element In the case of denominator coef cients the input source is set to zero For numerator coef cients the transfer fmetion output is nulled For example consider the lowpass lter of Fig 1 It is desired to compute the transfer R1 L J v1 C R2 v2 Fig 1 RLC circuit example fmetion Gs v2sv1s This transfer fmetion contains two poles and no zeroes why and can be written in the following form l 2 GO GdclerISerZsZ The dimensions of b1 are Hz The two possible terms in b1 are A and RbC 3 The dimensions of b2 are Hz The only possible term is of the form RdC 4 2 PROCEDURE In general the numerator and denominator polynomials are of the following form 1s 21 11RJCJSZ 22g f22cjeZZC R CRJ 5 L s3 222qzzf ckRywzzwchjckmwzzz camcw J l The orders of terms in the above equation are irrelevant for example it can be shown by reciprocity that RI39RJ RJ39RI The coef cients are determined as follows Coef cients of s1 R and R are the resistances seen at port 139 or j with all other ports set to their DC states Coef cients of 52 R andR without prime are the same terms in the coefficients of SI ie they are the resis tances seen at port 139 or j with all other ports set to their DC states Rj with prime is the resistance seen at port j with all other ports except part i set to their DC states Port 139 is set to its HF state Coef cients of s3 R R without prime Rquot andR with prime are the same terms in the coefficients of xi Rk with doubleprime is the resistance seen at port k with all other ports except parts i and j set to their DC states Ports 139 and j are set to their HF states etc Each term eg R1 is found by current injection at the connections to the corresponding reactive ele ment eg in place of L1 For denominator terms the transfer function input is set to zero For numera tor terms the transfer function output is nulled in the presence of the input For each coef cient it is necessary to derive only one new term the other terms are identical to the corresponding terms in a pre vious lowerorder coef cient By following the above rules the transfer function can be written directly without need for algebra Admittedly some practice is required to become facile with these rules nonetheless the effort required to write exact expressions for complex circuits can be considerable reduced 3 EXAMPLES Consider rst the simple RLC circuit example of Fig l The DC gain Gd is found with both reactive elements set to their DC states ie the inductor is set to a shortcircuit and the capacitor is set to an opencircuit Solution of the resulting voltage divider leads to 7 R2 6 GdeIJrRZ 0 The terms in the denominator polynomial are found with the input source v1 set to zero The circuit of Fig 2 is then obtained Since the circuit contains two reactive elements the denominator is a second order polynomial It can therefore be of the following form Fig 2 Finding the denominator terms 1 v RLC circuit examp e denominator l 5RA RbC 52RARdC 7 a c The term Ra is the resistance seen at the inductor port Port A when the capacitor is set to its DC state or opencircuited It can be seen that Ra is the series combination of R1 and R2 RaR1RZ 8 The term R17 is the resistance seen at the capacitor port Port B when the inductor is set to its DC state or shortcircuited It can be seen thatRl7 is the parallel combination of R1 and R2 RbR1RZ 9 For the coef cient of 52 we can choose one of the terms either R5 or Rd to be the same as the corre sponding s1 term The other term is then found using the procedure for prime terms For example let us select the term associated with the inductor port R5 to be the same as in the SI coe lcient RCRaR1 112 10 Then R d is given by the resistance looking into the capacitor port Port B with the inductor set to its highfrequency state or opencircuited It can be seen from Fig 2 t at RdRZ 11 Therefore the transfer function Gs is G 7 R2 R1RZ 12 1 L 2 R2 1 R RC LC SR1RZ 1 Z S R1RZ If desired it can be veri ed that the numerator coef cients of s and 51 are zero a second example consider the twosection RLC lter of Fig 3 Since this circuit has four reactive elements we expect the transfer function Gs v2sv1s to have four poles The DC gain Gd is equal to one The denominator polynomial is found when the input v1s is set to zero The resulting polynomial is Fig 3 Twosection R LC lter Example 2 denominator l s14 Ii ClO CZO R R s2 IiC1RhCZR C1OIiCZRClOCZO R R R 13 L L L L L L s3 101 fh zz CZRf1CZR clofCZRcl0 s4 CIR 02R This transfer function contains no zeroes Hence Gs is given by L l G L L L L C 14 1 s 1R 2 sZL1C1 CZ LZCZ s3 1R2 1 s4L1LZC1CZ A third example is given inFig 4 It is again desired to nd Gs v2sv1s This example will be worked in class Fig 4 Example 3RC circuit REFERENCES l RDMiddlebrook Vatche Vorperian and John Lindal The N Extra Element Theorem IEEE Trans on Cimuits and Systems I39 Fundamental Theory andApplications vol 45 no 9 Sept 199839 pp 919935 ECEN48275827 leemre nntes Inside a simple twnrstzge CMOS upramp transislnrrlevel view part 1 Objectives m thrs segment of the eourse are 1 t u m e haste buxldmg blocks smded m prereqursrte e1asses rneludng smglerstage MOS teehnology devree larger srgna1 equauons and operaung regrons when neeessary m 1eetures EDT a repeat of ECEN3225 students who need to refresh thrs rnaterrals should go ahead and websrte Inside a twnstage CMOS npramp unn russ o 2 Outsrde mew of tworstage CMOS Opramp 2quot m unn euss Flg o 3 Inslde vlew of the worstage CMOS Opramp Flg o 2 and Flg o 3 ean be relatedto eaeh other note that the two lnputs V and we of the Opramp are the gates of the translstors Maanol M nespeeuvely Haw dn we zpprnzch analysis nfcnmplzx circuits at theuanslstnn level lmnl rFuw h quotV M k f posslble Identifying runeu39nnal blacks in the twnrstzge upramp circuit U amp eueult the funeuon ofR ls blaslng l e setung up a eonstant ole blas eunent Ix Thls eunentls then ls repllcated at vanous othenloeauons forbl slng other ampllfler stages tluough eunentnnlnons Int e Opramp eueult ofFlg o 3 the blas cunentlh ls the lnput eunent for the cunentmln or wlth two outputs M5 andM7 2 Mall M7 comblnedtogetherform eunentnnlnons dlsh39lbutmg h to the rest lr ml H r M the nnlnon slnee MzMg M7 are sharlng the same gatersource voltage the dnver rest of the eueult leferent aspeet nauos WL of the minor output txanslstors wlth respectto the mputtranslstor ean be useolto seale the blas eunents as neeoleol more about tlus ln the quanutatlve analysls later stage lgtts the btastng eunentfot the dlfferennal pattMt and M2 Thls blas eunentts ptovtoleol by M5 whteh aets as am eunent soutee 4 Msand Mtfotm a eunentmtnotthat aets as the zc velnzd for Mt and M2 5 t m t the tnput of thts atn stage ts at node 1 whteh ts the gate ofMg the output ofthls stage ts atnoole 2 whteh ts the clean ost an M515 blased torn noolel The soutee ostts atteetly eonneeteolto the DC supply voltage VDD and henee no stgnal eotnponent 6 M7 ts the aeuve loaol fotMs 1n genetal tn 1c olestgn Very few passtve eotnponents ate useol stnee they usually oeeupy stgntfteant area and have wtole toletanees Ttanststots ate useoltnsteaol Wheneverposslble pat tha ansts ot eunent nntnots ate useolto teplteate and dtsutbute DC blas eunents as neeoleol and 2 aeuve uanststotloaols ate useol tnsteaol of passtve testsuve loaols Assumptton wete plaetng the Opramp tn anegauve feedback etteutt to make V0 zeto away torn satutauon as shown tn the etteutt below unn ens wtth negattve feedback Va we 0 Hete ts the potnt if we leave the Opramp open as tn the etteutt on the lelt even telauvely small offset voltage V0 woulol eastly dnve the Opramp tnto satutatton tegton te to one of th ou ut voltage satutatton lttntts In a negauve feedback etteutt nght the DC opetattng potnt ts Va me o 0 away torn satutauon The DC analysts wt l be p n rrn uunu r ramp A sueh as the erreurt on the nght of Flg o 4 so that the DC operahng pornt ls away from saturatron lrrnrts Salvmg or DC Izmmg h R we ean ealeulate all other DC voltages and eurrents r e the DC operahng pornt for other erreurt blocks srnall slgnal ealeulahons ofthe galn ean then be performed alter we solve for the DC operahng pornt unn euss Kg 6 5 chlaslng elreult DC Solution ln the above lrcult ls as follows V00 7 RE 7 VGSE 7V3 1 1m Io uncam WL V632 e Va 2 Comments We ean conslder the erreurtrn Flg o 5 separately from the rest othe erreurt arnp ls through the gates of M8 M5 M7 Slnce the DC gate eurrent ofMOS t e ehannel souree or olratn the blaslng erreurtrn Flg o 5 ls not affected by all m 4 g a p the voltagerloop equatrons forthe erreurtrn Flg o 5 Equahon 2 ls the eharaetenshe oforn the aehvesaturatron reglon We know thath ls m thrs operatrng reglon beeause the gate ls shorteolto dram VGD 0 whlch ls less than the threshold voltage V othe N39MOS devlce 0 Equations 1 and 2 can be solved for Ib if the device parameters and R are given In most cases the desired value of the bias current Ib would be given and l and 2 would be solved for R I zl ua7lb1 7E9 Facel a lf IE 70w 7 7 we ahaex 575m e aIZ AJIa47 506 6 4 73 ahO I 276 feed If 39 71 a congacm ap ac4zn ALAS I I aw I39 I z vi yo hcf LO ii v3 209 39W0 jam of A9 0039am4 Moe 21 gm 22 52M Madam 30125 M mf c and A9 393 a om S oae MiaJud I M6 10 Aanjzl Au a d f fan 4 w mn ange 7 7 59 dingy opj eolw aU 7 czmhc ago JILMBMZZJ 39 I70 091 Mp iJ39 we oat 4A CS Equot M a In e wv39 a 339 1 zjl l v V39 Bi f z 39 239 4137quot439 quot quot39 quotquot o 231416 at o 215 A7 5 x4 5 E A h gb39 igz 435 13 6 1711542 4 259 Mid 6am 5 wr em m 7 a am T leiP2 41 gt 4139dea l 077 4LVA I f 7 W joL 11 Mm 77539 Zooov nin at92 4 g a 7900 2 Jim00739 W45 73 gt w acts Ae WoL 57nd We gt 0 39 776 691260 Cadr 6 Z aJzawn 23914 a W74 0m Co 7 o 5759 500 VA 2927 w howA a mfyex 3 7 SI 7quot 4 70 7sz 751w 752 ehww 52 3963 7 new Mum 7 any 75 6 3 1 429 awe Sooc e C a we aw i of gen my r fIW 70 fee 2 7g o z ur lf a 411H9ul l O 7 e l lv 7 1 3 1455 I7L775 9 Amulm Dz Cascode amp Other Improved Ampli er Building Blocks ECEN 42285008 Fall 2004 Figure examples from AllenHolberg reference text unless otherwise stated ECEN 42285008 Fall 2004 1 ECEN 422mm Fall 2004 Text Figure 651 2 9 TwoStage w Cascode Input VDD m3 1 ml 2 B4 MC3 MBS I I II MC Jr MI VBIAs MB MBZ EAMs A VMV w Cascode bias ECEN 42285008 Fall 2004 9 Cascode 211d Miller Stage 97 10 Dan VDD Voul o M1 M2 quotin c Text Figure 653 ECEN 42285008 Fall 2004 r 9 Cascade Symmetrical OTA if PushPull MW Text Figure 654 ECEN 42285008 Fall 2004 9 Improve ICMR ISource Load A mblog Id Dalian VDD V503 VTN V00 V00 VDD F V563 VTN V m V r V 503 SDl Input Inpm Common Common Mode Mode Range Range mm Vss V055 VGSl M5 v VBIAS Text Figure 656 ECEN 42285008 Fall 2004 9 Folded Cascode VD D VDD I4 15 14 M4114 M5115 I A i ME J 111 112 116131 0 o I M1 M2 Vin Cascode 1 3 Current Min39or V55 a Text Figure 657 ECEN 42285008 Fall 2004 9 High gain folded cascode My 10 Dan V00 VBIASI VEIASz quotems5 quotBIAsa VBIASJ quotxxx a GreyMe er reference text Fig 630 ECEN 42285008 F 12004 8 3123 Vimsa Bias circuits for high gain folded cascode VDD VBIASIJ GreyMeyer reference text Fig 630 ECEN 422mm Fall 2004 I Issues W ICMR Analog 14 Des 356 I 3 z 1 quot i ltgt VDDV 25 avTltVgt 7 7E ltgt MW 3 E x v 15 7 quotc 3 DD E VBIAs 1 n n n n VSD3Sat 0517 M3 M4 59 A 1 A 39 0Il 1 f V39 1992 1994 1996 1998 2000 2002 2004 2006 I Ye ar Vicm M1 M2 Text Figure 761 V051 v VDSSSat I M5 ECEN 42285008 Fall 2004 Text Figure 763 9 RailtoRail Concept 5 L9 WngdvDeStgn VDD L II I IIquotI II J M6 I 39I MN3 39 MP5 39I lMN4 pch palr 39 o 39 39 error V v w to Km M2 gm gt MN N output quot stage nch air 39J P M7 quot r4 WMPH 8171eff gmN gnuquotA ng gmN n Chan u I I p channel on g p Channel on I pchannel of V V 711 0 VDSN5530 VGSNI VDD VSDP5Sat VSGPIVDD 11 ECEN 42285008Fa112004 Text Figures amp 9 Ib if MP1MP2 lt cutoff Drives 4x current in A n39Ch When One Solution 9 adaptive Ib VDD Am I Deiig cutoff p39Ch Cutoff E CEN 42285008 Fall 2004 gm Eff gmN ng szn Von VDD Vir39m Figures 766 amp 767 9 Another Solution IkHquot JOURNAL OF SLU STAITE CIIltIII IS Vol 39lt NO 7 ULY I FJQ39 ECEN 42285008 Fall 2 r Wm 10 a Compact CMOS Constantgm Rail to Rail Input Stage with gComrol by an Electronic Zener Diode Rnn I39lngcrvorst John P Two and Johan H Huiising alrci Md 1 10 v03 Zhen er absorbs 6Ire39f w hen both 3911 p ch are on To next stage M11 M12 To next stage a r a was M2 M3 M9 Hg Ruijmjl inpul mlil L J quot13921 tuner diarie in gu lmca u 1 at Lu tznnmnm 39rulue Implementation Amulogmhxgn VDD To new suagE To next mags w A r HVSS ME ME ECEN 42285008 Fall 2004 Complete Ampli er M10 M M40 V31 N121 M22 4833 5 3 19 1 SV 45 4 5 2 NH 305 M2 SDI39S M3 3053 I 39 1 SV 1512 1592 ECEN 42285008 Fall 2004 Am a In ECEN 42285008 Speci cations Ear mgtcr aparan 0111an unit Fm 313 39 106 7 006 mm2 Supplyr voltage range 7 7 27 la 6 27 06 V I Quicsccm CLUTM IL 210 215 HA I Peak output current 15 15 mA Commonmade input voltage range VSSj lo VDD8 I m5 tn VDD8 V Dutput vdltage swing r 1153 to Van1 Pigs 1 to PhD1 V Offsct voliag 3 3 m v39 CMRR dB Vt l lm l c from Vsj j v39 to Vsbtb 80 8t frum vssm v La VSSILLIV 43 43 from V55LW Io 39lr39DD HV 74 74 from Vino 11V 0 VDD39UjV from EDD 05V ta VEEtBV 7 39f0 7 70 Open loop gain 83 85 dB Unity gain frequency 1 19 MHz Unitygain phase margin 1 6 80 Slewrate 39 a 3 Vim Settlingtime 1 Ip smp39quot 03 03 15 W97 10 Pm r1 1 Class AB Output Stage Wu CD output stage Source Follower Biasmg ECEN 4228500amp Fa112004 Text Figure 71 1 17 9 Very Low Rout Feedback Wayland 39 39 39 39 39 1 VDD 39 I JM6 ltJ yin M9 l I i C VOS V out I EWGTI O I l I I M8A M10 Unbuffered op amp M6A I M13 M12 M 1 VBIAS I 39 39 39 39 39 39 39 quot quot39 V53 ECEN 422mm Fall 2004 TeXt Figure 116 18 Complete LOW Rout Amp VBIASP M17 VBjI ASN AI Amp ShortCircuit A2 Amp Protection Text Figure 718 19 ECEN 42285008 Fall 2004 Power Supply Rejection Ratio maps Vdd IPSRR39w dB I l l 15663 GB IP2 GllAv0 I J v GUAMOV I E E V DD gds7 M3 M4 I LI M1 M2ILTC1 ICU I T IPSRR UMM dB 6 E 394 I T as I 8 39 5 O 9 p T Text Figures 642 645 20 ECEN 42285008 Fall 2004 Fully Differential A mblog Id Dalian V V215 A Text Figure 731 ECEN 42285008 Fall 2004 Text Figure 732 21 9 2stage Miller Differential Out 1 Analog In ECEN 42285008 Fall 2004 V01 VI 1 Text Figure 733 22 9 FoldedCascode Differential Out Auto 10 Dex VDD M lg LJM15 M14i MS M13 mm L 9 R1 quot02 V11 M1 M2 F132 ECEN 42285008 Fall 2004 Text Figure 735 23 2stage pushpull diffout Ahalug Idv I E CEN 42285008 Fall 2004 M7 V M5 M9 l M 10 o VBN M1 V55 I VDD 0 313 L MIjI ILJMAL J M134 quot r M6 quot EMM RZCC V02 M2 Text Figure 736 quot12 AM MIZE M8 24 a 9 2stage folded cascode diffout VDD Text Figure 737 ECEN 422mm Fall 2004 25 9 1stage cascode symmetrical 39 crosscoupled high SR VDD MI 47 MI i I I I M95 K 39 quotII I M3 m M24 MINZ R M21 1 lm 0 o2 gt M1 M3 M4 Mlst 39 R2 n M27 IJ l c HMW EMIS Ch23 V128 II VBIAS I II II I Il M11Fl Msu rum II MIZ VSS Figure 7310 ECEN 42285008 Fall 2004 26 9 CMFB Commonmodefeedback Auto 10sz T0 con ection Circuitry V35 Text Figure 7313 ECEN 422mm Fall 2004 27