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# Renewable & Power Electronics Laboratory ECEN 4517

GPA 3.9

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This 135 page Class Notes was uploaded by Mrs. Lacy Schneider on Thursday October 29, 2015. The Class Notes belongs to ECEN 4517 at University of Colorado at Boulder taught by Staff in Fall. Since its upload, it has received 41 views. For similar materials see /class/231803/ecen-4517-university-of-colorado-at-boulder in ELECTRICAL AND COMPUTER ENGINEERING at University of Colorado at Boulder.

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Date Created: 10/29/15

Lecture 4 ECEN 45175517 Experiment 3 weeks 2 and 3 interleaved flyback and feedback loop 12 VDC HVDC 120 200 VDC DC DC DC AC converter inverter AC load Battery L Isolated H bridge vact 120 VTmS 39 39 yback 60 HZ dt Feedback controller Digital controller Sieijp d9 d0 converter Parallel two flybacks with With ISOanon ybaCk phase shifted gate drive Feedback controller to Signals regulate H VDC ECEN4517 1 Due dates and goals Right now Prelab assignment for Exp 4 Part 1 one from every student Due within five minutes of beginning of lecture This week in lab Feb 35 Final reports for Exps 1 and 2 due Begin Exp 3 construct and debug basic flyback power stage Next week in lab Feb 1013 Get parallel flyback power stages working at 85 W Begin simulation of ac transfer functions and feedback loop dedgn ECEN4517 2 Goals in upcoming weeks Exp 3 Flyback stepup dcdc converter VHVDC Exp 3 Part 1 Design and fabrication of flyback transformer Snubber circuit Demonstrate flyback converter power stage operating open loop Exp 3 Part 2 WM 3 VI Construct debug and demonstrate paralleled flyback converters producing 85 W Exp 3 Part 3 Design feedback loop Measure loop gain compare with simulation and theory Demonstrate closedloop control of converter output voltage ECEN 4517 3 Layout of power stage quot11an Identify loops having high didt pulsating currents Since v L didi stray inductance in these loops leads to voltage spikes and ringing on components usually the MOSFET that can exceed their peak voltage ratings Minimize the inductance of the critical loops keep area of loop small use twisted pairs add bypass capacitors ECEN 4517 4 Effect of transformer leakage inductance Ll Transformermodel Leakage inductance LI is caused by i 55 l l H imperfect coupling of primary and g l quot D1 J secondary windings LM C R i v V Leakage Inductance IS effectively in g C series with transistor 01 9 When MOSFET switches off it VT interrupts the current in LI LI induces a voltage spike across 01 Vim asset leakage inductance VB Lg If the peak magnitude of the d Vg W voltage spike exceeds the iRon voltage rating of the MOSFEI DIT f then the MOSFE T Will fail ECEN 4517 4 Protection of Q1 using a voltageclamp snubber F lyback transformer gtSJCS Vg CD T39lt aIE VTU Snubber provides a place 5 for current in leakage inductance to flow after 01 has turned off n Peak transistor voltage is clamped to V9 vS vS gt Vn Energy stored in leakage inductance plus more is transferred to capacitor Usually CS is large CS then dISSIpated In RS Decreasing RS decreases the peak transistor voltage but increases the snubber power loss See supplementary flyback notes for an example of estimating CS and RS ECEN4517 5 Overvoltage on output diode Diode turnoff reverse recovery LEI Tramformer model transition Transformer leakage inductance causes voltage ringing and overshoot on secondary diode Vg C J Leakage inductance plus diode output capacitance form resonant crrcurt eakage I39LU secondary induced voltage via vLt quot13 Silicon I diode L V30 C T ECEN4517 L inductance Ln LI VI D1 diode capacitance Area Qr Diode snubber Damp the ringing with FiC snubber network L Transformer model L D 1 2 u I Rn I I Irzms I I I I lg n l 1n v52 I I L Diode snubber quotC R v M lt Vg CD QLI VT Snubber capacitance similar in value to diode capacitance Snubber resistance similar in value to resonant circuit characteristic impedance More capacitance andor smaller resistance gt lower peak voltage larger snubber loss ECEN4517 7 Limits on maximum output power Week 1 circuit Mmmi lI DC com poncni I M395 quot n l w 7 i I I I IWMU an C lllL VHVDC 1L V ring inductance causes ac component of Whack to flow through capacitor C while the dc component flows from the battery Capacitor rms current must not exceed the rating of 442A Decreasing converter efficiency caused by snubber and other losses along with capacitor current rating limit the maximum output power How much output power can you produce ECEN 4517 8 Increasing the output power Week 2 circuit 1 i hm39l I im 1mm DC com pon cm I I I I I hilli l39j a mmA2 II DC component II l I Human 2 I C u quotanc l I il r imnury lIj39luu39kl i Vbatt C Interleaving of parallelconnected flyback converters W AC components of phaseshifted input current waveforms partially 5 B A PrOdUCG 85 W cancel out PWM output power by Less rms capacitor current per unit I end 0f Week 2 of output power ECEN 451 7 y V Exp 3 Part 3 Regulation of output voltage Via feedback VHVDC Model and measure controltooutput transfer function Gvds ban Design and build feedback loop Measure loop gain to verify phase margin and crossover frequency Demonstrate closedloop regulation of VHVDC ECEN4517 10 Negative feedback a switching regulator system Power Switching converter Load input Lil lload Sensor gain Transistor Error gate driver Signal 3 Pulsewidth Vc modulator I Gcs Compensator Reference input Vref ECEN4517 11 Transfer functions of some basic CCM converters Table 82 Salient features of the smallsignal C CM transfer functions of some basic dcdc converters Convener Ggo Gdo 00 0 Q 00 z buck D 7i C R g 00 boost 7 DR LL21e buckboost BLUE 7 DIR DD where the transfer functions are written in the standard forms 1 1 Gvds Gdo Gvgs Ggo 1 QfDO 1 QUOO Flzback push L and Cto same side of transformer then use buckboost equations DC gains 690 and Gdo have additional factors of n turns ratio ECEN4517 12 Bode plot controltooutput transfer function buckboost or yback converter example 80dBV vd H Gvd L Gvd 60 dBV quotG 2 V do wasw 3924 1de 40 dBV f0 400 HZ 20 dBV 39 1012Q 00 300 HZ 0 dBV Z 00 4 GM fz 0 Z39 l gz 20 dBdecade 20 900 40 dBV 180 1012Q I 533 Hz I 26 kHZ 270 270 10 HZ 100 HZ 1 kHz 10 kHz 100 kHZ 1 MHZ f ECEN4517 13 The loop gain Ts Loop gain 7 8 product 5123 Switching converter Load of gains around the I I I W feedback loop J W More loop gain T leads V8 7 V v to better regulation of T Sensor output voltage 2 gal Transistor Error signal gate driver 6 Compensator Reference Ts Gvds HS 608 VM mm Gvds power stage controltooutput transfer function PWM gain 1VM V pkpk amplitude of PWM sawtooth ECEN4517 14 Phase Margin A test on Ts to determine stability of the feedback loop The crossover frequencyfc is defined as the frequency where ll Tj2rtfc II 1 or 0 dB The phase margin pm is determined from the phase of Ts atfc as follows pm 180 argTertj c If there is exactly one crossover frequency and if Ts contains no RHP poles then the quantities Ts1Ts and 11Ts contain no RHP poles whenever the phase margin pm is positive ECEN4517 15 Example a loop gain leading to a stable Closedloop system 60 dB T H T L T 40 dB f p1 f Crossover 20 dB z frequency A T f0 0 dB Z 0 20 dB 90 11 17 Pm o 40 dB 180 2700 1 Hz 10 Hz 100 Hz 1 kHz 10 kHz 100 kHz argTjZa tj c 112 pm 2 180 112 2 68 ECEN4517 16 Transient response vs damping factor 2 W 1 05 0 0 5 10 15 not radians ECEN4517 17 Q vs pm ECEN4517 20 dB 15 dB 10 dB 5dB OdB 5 dB 10 dB 15 dB 20 dB Q1gtOdB pm252 Qb5gt 6dB pm 76 18 84 Measurement of ac transfer functions and impedances Network Analyzer Data Data bus Injection source Measured inputs 173 dB to computer gt ti vz 32 magnitude frequency 8 0 172 17x 17y input input A 7 7 Vy O1 0 u 1347 ltlt lt Chapter 8 Converter Transfer Functions 94 Fundamentals of Power Electronics Swept sinusoidal measurements Injection source produces sinusoid 72 of controllable amplitude and frequency Signal inputs 9x and 9 perform function of narrowband tracking voltmeter Component of input at injection source frequency is measured Narrowband function is essential switching harmonics and other noise components are removed Network analyzer measures and L ltgt lt ltltgt lt gt lt Chapter 8 Converter Transfer Functions Fundamentals of Power Electronics Measurement of an ac transfer function NetworkAnalyzer I Injection source Measured inpum Data 39 m mugs gs establishes correct oz V qUIescent operating out at i ut in at 39 p F 39 p 7 1628 pOInt 1 Injection sinusoid coupled to device DC vys G I k blocking A s Input vra dc b oc Ing capacitor VXS capaCitOr VCC Actual device input m and output voltages DC 3 I are measured as Vx bias lt gt gt A adjust and V Dynamics of blocking capacitor are irrelevant Device under test Fundamentals of Power Electronics 96 Chapter 8 Converter Transfer Functions 961 Voltage injection Block 1 19 Block 2 0 0 j 1 ea G1s es G2s xs 17s2 MS MS 223 Ac injection source vZ is connected between blocks 1 and 2 Dc bias is determined by biasing circuits of the system itself Injection source does modify loading of block 2 on block 1 Fundamentals of Power Electronics 64 Chapter 9 Controller design The Flyback Converter Lecture notes ECEN4517 Derivation of the yback converter a transformerisolated version of the buckboost converter Typical waveforms and derivation of M D VVg Flyback transformer design considerations Voltage clamp snubber Derivation of the flyback converter The yback converter is based on the buckboost converter Its derivation is illustrated in Fig 1 Figure 1a depicts the basic buckboost converter with the switch realized using a MOSFET and diode In Fig lb the inductor winding is constructed using two wires with a 11 turns ratio The basic lnction of the inductor is unchanged and the parallel windings are equivalent to a single winding constructed of larger wire In Fig lc the connections between the two windings are broken One winding is used while the transistor Q 1 conducts while the other winding is used when diode D 1 conducts The total current in the two windings is unchanged from the circuit of Fig lb however the 4 5 Q1 D1 Q1 D1 IA IA n 7 n T T H Vg L V Vg L V c 4 Q1 D1 gt1 I4 D 1 1 T C V V Li V Fig 1 Derivation of the yback converter a buckboost converter b inductor L is wound with two parallel wires 0 inductor windings are isolated leading to the yback converter d with a 1n turns ratio and positive output current is now distributed between the windings differently The magnetic elds inside the inductor in both cases are identical Although the twowinding magnetic device is represented using the same symbol as the transformer a more descriptive name is two winding inductor This device is sometimes also called a yback transformer Unlike the ideal transformer current does not ow simultaneously in both windings of the yback transformer Figure ld illustrates the usual con guration of the yback converter The MOSFET source is connected to the primaryside ground simplifying the gate drive circuit The transformer polarity marks are reversed to obtain a positive output voltage A 111 turns ratio is introduced this allows better converter optimization Analysis of the flyback converter The behavior of most transformerisolated converters can be adequately understood by modeling the physical transformer with a simple equivalent circuit consisting of an ideal transformer in parallel with the a magnetizing inductance The magnetizing transformer m ode inductance must then follow all of the P I usual rules for inductors in particular voltsecond balance must hold when the ic gt C Rv circuit operates in steadystate This implies that the average voltage applied across every winding of the transformer must be zero Let us replace the transformer of Fig ld with the equivalent circuit described above The circuit of Fig 2a is then obtained The magnetizing inductance LM functions in the same manner as inductor L of the original buckboost converter of Fig 1a When 6 transistor Q conducts energy from the tramfarmermadel in dc source Vg is stored in L M When diode D 1 conducts this stored energy is transferred to the load with the inductor voltage and current scaled according to the 1 turns ratlo39 Fig 2 Flyback converter circuit a with transformer equivalent circuit model b during subinterval I c during subinterval 2 During subinterval I While transistor Q conducts the converter circuit model reduces to Fig 2b The inductor voltage VL capacitor current iC and dc source current ig are given by VLVg Q7 i D With the assumption that the converter operates with small inductor current ripple and small capacitor voltage ripple the magnetizing current i and output capacitor voltage v can be approximated by their dc components I and V respectively Equation 1 then becomes VL Vg Q7 ig I 2 During the second subinterval the transistor is in the offstate and the diode conducts The equivalent circuit of Fig 2c is obtained The primaryside magnetizing inductance voltage VL the capacitor current iC and the dc source current ig for this subinterval are W7 Qi E a It is important to consistently de ne VLI on the same side of the transformer for all subintervals Upon making the smallripple approximation one obtains Wg Lz C n R ig0 4 The VLI iCt and igt waveforms are sketched in Fig 3 Application of the principle of volt second balance to the primaryside magnetizing inductance yields DT ViDVgDV 0 5 21 Fig 3 Flyback converter waveforms continuous conduction mode Solution for the conversion ratio then leads to V D M D 7 7 n V D 6 So the conversion ratio of the yback converter is similar to that of the buckboost converter but contains an added factor of 11 Application of the principle of charge balance to the output capacitor C leads to ic7D7R D39770 7 Solution for I yields 1 DR 8 This is the dc component of the magnetizing current referred to the primary The dc component of the source current ig is 1g 7 jg 7 D 1 D 0 9 An equivalent circuit which models the dc components of the yback converter waveforms can be constructed The resulting dc equivalent circuit of the yback converter is given in Fig 4 It contains a 1D bucktype conversion ratio 4 followed by a l 7 Dl boosttype 1 conversion ratio and an added Vg a D1 factor of 111 arising from the yback transformer turns ratio The yback converter is b commonly used at the 50100W 1 1 power range as well as in high voltage power supplies for televisions and computer monitors It has the advantage of very low Fig 4 Flyback converter equivalent circuit model a circuits corresponding to Eqs 5 7 and 9 b equivalent circuit parts count Multiple outputs can contmngideal dc transformers be obtained using a minimum number of parts each additional output requires only an additional winding diode and capacitor The peak transistor voltage is equal to the dc input voltage Vg plus the re ected load voltage Vn in practice additional voltage is observed due to ringing associated with the transformer leakage inductance A snubber circuit may be required to clamp the magnitude of this ringing voltage to a safe level that is within the peak voltage rating of the transistor Fb mck nsme39 Jaggw For quotPN S Lab 39 are 5 h l mk5 tbrwu39 obi5M 25le 0 seled LH San 39Hvd A 32 0 I 0 use quotums m Ho M J L i 15 use a P0 3330 core gtA wnrml 3913va saga139 luvus VII Sucln 05 5 unlmuA 39 HumM126 345 Pk PC M cm 1 u quotAskms lo f RANT and mu m3 39 WkJMQ G39W39 u PHme GM ecOMqu3 Aer amass St 9cbr K 04 0 CW 41 mkg uVr 190 Pant B Ahe 0 can Kn cm 4 ukmk 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394 I5 Gwen Secoka NVt area I KLKuWA quota LOVJHQ NSIEBWS Pmiwuj Qw j re nuno 239 P nlgrb Gasman3 DAlz te f lhv l Q2 0 w u Com OSS F I 1 R fr mrb ww mj Caner 555 041 ms Sendaib muoj L55 23 lat EL mmquot 5 curred lex an o PC P641 Pap C39rror D5S V5 M1 39 L 391 90x PCKS PM IJJM R EQ MS Pl 11p F1331 13 hnozmu at K RDA d1 KuwA 7 L quot1 MLT 1116 n1 I quot P 7E T T mm w L n1 gems corra c555 39 1 5 ck W uq a M1 Mm39tm39lus L SS Mkmewx Cofer 0 occurs wLeM u39onu area 5 allmk as s d Izyw 2 IIquot M Ia ckwx x cm L as LN F quotr WA 4 V WW3 Ewe Rr uas 39 113 mus at Ma mk PM 5 N39IIuml39znJ Kw coKPAQ wk Sign euj39Hx 3c Cuwru xg PR Pad Pull a BM EEc 0399 h tzwxs gormar leako e mim kme W Grim 234 J 4 39Laa Auc39kwce L2 5 eggx v Wm M 3amp5 w39rfk May 51 Q 3 um nosFET 3amp5 0 gawk curm Clom39u n Le L2 Que5 Val l39n quayALT ms sor DH 0f quC CDrM 1 Ll V7145 4 1313 T5 IQ t Peak A 43 mH wak fth excels 4k Hug r4525 9 Le osFE39r 1 Q I 4l Snukber NR m o SMALer PHW VLLS q 4quot ix 4 w Fkr Q 405 quotLANQJ sq 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3 95 i 3 3E3 Department of Energy n3quotI Ef ciency and Renewable Energy HighReliability Inverter Initiative Sigifredo Gonzalez Solar Technologies Department Sandia National Laboratories Sandia is a multiprogram laboratory operated by Sandia Corporation a Lockheed Martin Company for the United States Department of Energy under contract DEACO494AL85000 Sandia HighReliability Inverter Initiative igliiiigiiines Project Definition DOE amp Inverter DesignerManufacturers Partnership Goal Design amp Manufacturer Inverter 439 Achieve high reliability and change public perception 439 Requires corporate buyin through cost sharing 439 Focused on rectifying identified problems 439 High Volume expectation Sandie HighReliability Inverter Initiative E gagg g 39mes H Need for Initiative 3 Improve Performance 3 Achieve Sustainability 3 Enhance Reliability Sandie HighReliability Inverter Initiative E gagggignes 7quot Background Markets Impact Reliability Reliability V A ISO 9000 etc amp V Markets Manufacturing Quantity Sandie National HighReliability Inven er Initiative mummies it Developing Requirements I Basis of Systems Engineering Different Perspectives Sandia Testing Fied Sites ndustry University Document Inverter Status and Needs Sandie HighReliability Inverter Initiative E gagggignes 7quot Specific Requirements I 31 Reiabiity MTFF gt10 Years Efficiency gt 94 Cost lt 90lwatt 10000year quantities Compiance UL 1741 olEEE 929 olEEE C6241 olEEE 519 NEC FCC Part 15 Class B Sandie HighReliability Inverter Initiative E gagggtat39mes Required Phase Documentation Market Study Switching technology and device nteigent design DSP ASICs etc mproved packaging Cooing amp operating temperature margin oManufacturing technology Lightninginduced surge mitigation Sandia National laboratories E HighReliability Inverter Initiative Project Phases l Proiect Formulation 3 months3 contractors Market Analysis Requirements finalized Configuration amp archite Path to production ctu re ll Detailed Design 12 months3 contractors Prototype software modules Hardware to verify designs Fina product designprototype lll Prototypes Hardware 9 months2 contractors Fina prototype evaluat Configure for manufacturing Deveopment testing ions HighReliability Inverter Initiative Sandia National laboratories E DOE Support l Phase II funding FY03I04 Office of Solar Energy Technologies Richard King Solar Energy Technologies is funding Phase II Sandie HighReliability Inverter Initiative E gagggi39t39mes 7quot 1 Phase Awards l Ten Responses to RFQ Three Selections General Electric SatCon Xantrex Six excellent proposals resourcelimited Sandie HighReliability Inverter Initiative E gagggi39t39mes f j V Schedule Status I 3 Phasel Complete oReviewed SNL NREL ORNL zo Phase II 3 Contracts Awarded SeptemberOctober 2003 Final deliverables due in 12 months Sandie HighReliability Inverter Initiative E gagggi39t39mes Funding Status I I 50 costshare by contractors required I Phase Total DOE Cost Status 3 mo 550000 Complete 12 mo 3000000 Awarded III 9 mo 1200000 Pending FY05 committed Saiidia National HighReliability lnven er Initiative anomalies eff Inverter Reliability FiveYear Plan Sandia coordinating for DOE 15t Step Baltimore Workshop April 2003 Results Consistent with Initiative Sandie HighReliability Inverter Initiative E gagggtat39mes 39 Followon Inverter Reliability Efforts a 39 Guided by Market Initiative Lessonslearned 5year Plan May Involve additional designermanufacturers Sandie HighReliability Inverter Initiative E gagggignes Lecture 3 ECEN 4517 5517 Experiments 3 and 4 inverter system 12 VDC HVDC 120 200 VDC DC DC DC AC converter inverter AC load Battery L Isolated H bridge vact 120 Vrms 39l39 yback 60 Hz dt dt v Feedback Vref Digital controller controller Stepjup dGdc 00 WITH DC A c inverter Hbridge Wth Isolaton fyback Feedback controller to regulate H VDC ECEN4517 1 Due dates This week in lab Jan 2729 Nothing due Finish Exps 1 and 2 Next week in lecture Feb 3 Prelab assignment for Exp 3 Part 1 one from every student Next week in lab Feb 35 Final reports due for Exps 1 and 2 at beginning of lab period Do Exp 3 part 1 ECEN4517 2 Goals in upcoming weeks Exp 3 A multiweek experiment VHVDC Exp 3 Part 1 Design and fabrication of flyback transformer Snubber circuit Demonstrate flyback converter power stage operating open loop Vref Exp3Part2 WM 393 Parallel interleaved converters to achieve full output power of 85 W Exp 3 Part 3 Design feedback loop Measure loop gain compare with simulation and theory Demonstrate closedloop control of converter output voltage ECEN4517 3 Exp 4 Hbridge inverter off grid VHVDC IR3101 1R3 101 AC load 120 Vrms E x 60 Hz x El W 39 TE 7 W 2r Filtering of ac output not explicitly shown IR 3101 halfbridge modules with integrated drivers Gridtied control iact Demonstrate modified sinewave inverter Demonstrate PWM inverter Offgrid control VaCU ECEN 4517 4 Modified SineWave Inverter vacltrgt vacu has a rectangular VHVDC waveform lt DT2 gt Inverter transistors T2 gt switch at 60 Hz T 833 msec VHVDC RMS value of Vacf is Choose VHVDC larger than desired VacRMS T 1 2 Can regulate value of Vac RMS TI V000 dt m VHVDC VC RMS by variation of D a Waveform is highly nonsinusoidal with significant harmonics ECEN4517 5 PWM Inverter Average vact has a Vac sinusoidal waveform Inverter transistors H II I switch at frequency quot 39 substantially higher H I than 60 Hz Choose VHVDC larger than desired lac peak Can regulate waveshape and value of lac RMS by variation of dt Can achieve sinusoidal waveform with negligible harmonics Higher switching frequency leads to more switching loss and need to filter highfrequency switching harmonics and common mode currents ECEN4517 6 39Thebuckixxmtconve er Switch in position 1 V9 charges 1 2 inductor Switch in position 2 energy stored in inductor is transferred to output Conversion ratio V D 1 D Subnterva 1 Subnterva 2 iL iL Vg V Vg V ECEN4517 7 See also supplementary The yback converter notes on Flyback A transformerisolated buckboost converter Convener Exp39 3 web page Q1 D1 buckboost converter D construct inductor Q1 1 winding using two I i I I H parallel wires o 11 Vg L V g ECEN4517 8 Derivation of yback converter cont Isolate inductor windings the fyback converter Flyback converter having a lzn turns ratio and positive output ECEN4517 9 A simple transformer model Multiple Winding transformer i1l n1 2 n2 i2l v10 vzl 50 V30 quot3 Equivalent circuit model i139t 7111712 v10 vzt v10 v20 v30 111 n2 n3 quotquot V30 0 n1i1 t n2i2t n3i3t 1713 Ideal transformer ECEN 4517 The magnetizing inductance L M Models magnetization of transformer core material Appears effectively in parallel with windings If all secondary windings are disconnected then primary winding behaves as an inductor equal to the magnetizing inductance At dc magnetizing inductance tends to shortcircuit Transformers cannot pass dc voltages Transformer saturates when magnetizing current iM is too large ECEN 4517 Transformer core BH characteristic Bz cx I v1z dz i saturation slope 0C L M H0 who Voltsecond balance in LM The magnetizing inductance is a real inductor obeying integrate iMltr iMlt0 f0 mach Magnetizing current is determined by integral of the applied winding voltage The magnetizing current and the winding currents are independent quantities Voltsecond balance applies in steadystate iMTS iMO and hence 1 Ts O T J V1dt transformer s 0 ECEN4517 v1t L it i139t n n 13920 dz r 1 1 2 M g iMlttgt v10 LM v20 3 n3 Ideal 12 The quot yback transformer Transformer model I o A twoWinding inductor 0 Symbol is same as transformer but function differs significantly from ideal transformer 0 Energy is stored in magnetizing inductance o Magnetizing inductance is relatively small 0 Current does not simultaneously flow in primary and secondary windings o Instantaneous winding voltages follow turns ratio 0 Instantaneous and rms winding currents do not follow turns ratio 0 Model as small magnetizing inductance in parallel with ideal transformer ECEN4517 13 Subinterval 1 Transformer model I l CCM small ripple approximation leads to Q1 on D1 off VL Vg i 1 C R i1 8 ECEN4517 14 Subinterval 2 Transformer model in l 39 39 g l l l O In C VL I l l V v vL vn CT RV C F g I lg 0 CCM small ripple approximation leads to Q1 off D1 on ECEN4517 15 CCM Flyback waveforms and solution Voltsecond balance vLgt DVg D 0 Conversion ratio is 1 Q MD Vg n D Charge balance iC D D39 0 Dc component of magnetizing g current is nV I D39R Dc component of source current is 18 iggt DI D390 Conducting devices ECEN4517 16 Equivalent circuit model CCM Flyback vLDvgD39 0 I iCgtDDIZO Vg DI DVg IgltiggtDID39O 7 1D D39n g I O I Vg quotD A V ECEN4517 17 l1 n Riiv Stepup DCDC yback converter Need to step up the 12 V battery voltage to HVDC 120200 V Let s build inverter capable of producing same rated power as PV panel 85 W How much power can you get using the parts in your kit Key limitations MOSFET onresistance 90 m0 Input capacitor rms current rating 25 v 330 pF 0865 A 35 v 3300 pF 422 A Snubber loss Need to choose turns ratio as well as D f3 to minimize peak currents We will build a halfpower flyback converter that operates with D lt 05 then connect two in parallel interleaved to obtain full output power without exceeding current rating of input capacitor ECEN4517 18 Transformer model 1112112 ECEN4517 gt D1 C 19 Mt Design of CCM yback transformer 1 10 A 1 20 A A VM Vg 4 DTX gt Approach See transformer design procedures textbook chapters 14 and 15 Select core size and switching frequency Choose turns ratio n2n1 LM D and fS choose your own values don t use values in supplementary notes Select primary turns n1 so that total loss Ptot in flyback transformer is minimized F tot F fe PCU core loss plus copper loss Determine air gap length Determine primary and secondary wire gauges Make sure that core does not saturate Turn in your design prelab assignment due next Tuesday ECEN4517 20 Core loss CCM yback example BH loop for this application The relevant waveforms Ba 30 B Bmax Ema 0 H60 VMU Minor B H loop CCMfllyback examp e 0 B H loop large excitation Bz vs applied voltage 6130 VMU F0rthe rsquot dBt Vg from Faraday s law dl quot1146 SUb39ntervak dt nlAC V DT Solve for AB DB g S ECEN 4517 21 2quot 1A6 Calculation of ac flux density and core loss Power M mm Fitting an equation to the plot at right PfeKfeAB395AC m slope lge constant that depends on fS g Aclm 2 core volume At 60 C 2 26 lge 16 50 kHz 40 100 kHz with F39fe in watts Aclm in cm3 ABin Tesla loo V T W swam 3 539 From preVIous slide D B gD S 2111AC More turns a less AB a less core loss ECEN 4517 22 Copper loss Power loss in resistance of Wire Must allocate the Winding 1 allocation 0 lt O jlt 1 core Window area 01WA 11 12 0 1 between the various Winding 2 allocation Win in 0 W d gs 2 A Total WlndOW etc area WA Optimum a M Choice m n I leads to minimum total copper loss n1 j j 2 2 pMLTn11mt k nj The resultng total copper loss IS PC W mm m J 1 j lt XIKMWA 39 wl Choose Wire gauges quot1 More turns more resistance A lt 12K WA more copper loss w2 quot2 ECEN4517 23 Total power loss PtotzpcuPfe There is a value of AB Power A or n1 that minimizes loss the total power loss Ptot fe PC Ij Pfe K feAB Ac m 2 2 P pMLT 1Itot cu WAKu V DT Optimum AB AB DB 2 Prelab assignment for next week use a 1 C spreadsheet or other computer tool to compute F tot vs n1 and find the optimum n1 Then design your flyback transformer ECEN 4517 24 Effect of transformer leakage inductance Lg Tramformermodez Leakage inductance Lz is caused by imperfect coupling of primary and secondary windings Leakage inductance is effectively in series with transistor 01 When MOSFET switches off it interrupts the current in Le Lz induces a voltage spike across 01 via 1332535 leakage inductance W Lz If the peak magnitude of the d Vg t W voltage spike exceeds the 1R voltage rating of the MOSFET On f then the MOSFE T Will fail DT ECEN4517 25 Protection of Q1 using a voltageclamp snubber Snubber provides a place g for current in leakage F lyback transformer C inductance to flow after 5 V S gt S C R i V 01 has turned off V 39 g C 1 Peak tranSIstor voltage IS Q1 clamped to V9 vS E VTU VS gt Vn Energy stored in leakage inductance plus more is transferred to capacitor Usually CS is large CS then dISSIpated In HS Decreasing HS decreases the peak transistor voltage but increases the snubber power loss See supplementary flyback notes for an example of estimating CS and HS ECEN4517 26 Reminders on Exp 2 this week s experiment Layout issues Must use bypass capacitors on power supplies Place ceramic capacitor across power supply and ground pins of every IC Especially place ceramic bypass capacitor as close as possible to power and ground pins of gate driver IC Place bypass capacitor on your board across power and ground terminals that supply power to the MOSFET and power resistor Capturing oscilloscope waveforms Capture screen shots of oscilloscope waveforms for inclusion in final report Can use floppy disk or on several of the lab scopes can use ethernet cable and enter scope IP number into web browser to capture png file ECEN4517 27 Chapter 9 Controller Design 9 1 Introduction In all switching converters the output voltage vt is a lnction of the input line voltage vg the duty cycle d and the load current iload as well as the converter circuit element dcdc application it is desired to obtain a values In a converter constant output voltage vt V in spite of disturbances in vg and iload and in spite of variations in the The and converter circuit element values sources of these disturbances variations are many and a typical situation is illustrated in Fig 91 The input voltage vg of an offline power supply may typically contain periodic variations at the second harmonic of the ac power system frequency lOOHz or 120Hz produced by a recti er circuit The magnitude of vg may vga Load Switchin converter ilaada transistor gore driver 5quot 5K ulsewidth v50 modulafor 5 Fig 91 dTT s 1 switching converter vn frvg am d vgn gt W disturbances iloadn d control Input The output voltage of a typical switching converter is a function of the line input voltage vg the duty cycle d and the load current iload a open loop buck converter b functional diagram illustrating dependence of v on the independent quantities vg d and iload also vary when neighboring power system loads are switched on or off The load current iload may contain variations of signi cant amplitude and a typical power supply speci cation is that the output voltage must remain within a speci ed range for example 5V i0lV when the load current takes a step change from for example full rated load current to 50 of the rated current and viceversa The values of the circuit elements are version 102898 1009 AM Chapter 9 Controller Design Power Switching converter Load input 151 JLL vg sensor gain transistor gate driver 5 compensator reference input VVEf 1 switching converter v Va vg iload d g disturbances Va signal control input reference input I sensor I gain Fig 92 Feedback loop for regulation of the output voltage a buck converter with feedback loop block diagram b functional block diagram of the feedback system constructed to a certain tolerance and so in highvolume manufacturing of a converter converters are constructed whose output voltages lie in some distribution It is desired that essentially all of this distribution fall within the speci ed range however this is not practical to achieve without the use of negative feedback Similar considerations apply to inverter applications except that the output voltage is ac So we cannot expect to simply set the dcdc converter duty cycle to a single value and obtain a given constant output voltage under all conditions The idea behind the use of negative feedback is to build a circuit that automatically adjusts the duty cycle as necessary to obtain the desired output voltage with high accuracy regardless of disturbances in vg or iload or variations in component values This is a useful thing to do whenever there are variations and unknowns that otherwise prevent the system from attaining the desired performance A block diagram of a feedback system is shown in Fig 92 The output voltage vt is measured using a sensor with gain H s In a dc voltage regulator or dcac inverter the sensor circuit is usually a voltage divider comprised of precision resistors The sensor output signal H svs is compared with a reference input voltage vre s The objective is to Chapter 9 Controller Design make H svs equal to vre s so that vs accurately follows vre s regardless of disturbances or component variations in the compensator pulsewidth modulator gate driver or converter power stage The difference between the reference input Vrefs and the sensor output H s v s is called the error signal ves If the feedback system works perfectly then vre s H svs and hence the error signal is zero In practice the error signal is usually nonzero but nonetheless small Obtaining a small error is one of the objectives in adding a compensator network GJS as shown in Fig 92 Note that the output voltage vs is equal to the error signal ves multiplied by the gains of the compensator pulsewidth modulator and converter power stage If the compensator gain GJS is large enough in magnitude then a small error signal can produce the required output voltage vt V for a dc regulator Q how should H and vmfthen be chosen So a large compensator gain leads to a small error and therefore the output follows the reference input with good accuracy This is the key idea behind feedback systems The averaged smallsignal converter models derived in chapter 7 are used in the following sections to find the effects of feedback on the smallsignal transfer functions of the regulator The loop gain Ts is defined as the product of the smallsignal gains in the forward and feedback paths of the feedback loop It is found that the transfer function from a disturbance to the output is multiplied by the factor l1Ts Hence when the loop gain T is large in magnitude then the in uence of disturbances on the output voltage is small A large loop gain also causes the output voltage vs to be nearly equal to vre s H s with very little dependence on the gains in the forward path of the feedback loop So the loop gain magnitude H T H is a measure of how well the feedback system works All of these gains can be easily constructed using the algebraonthegraph method this allows easy evaluation of important closedloop performance measures such as the output voltage ripple resulting from 120Hz recti cation ripple in Vg or the closedloop output impedance Stability is another important issue in feedback systems Adding a feedback loop can cause an otherwise wellbehaved circuit to exhibit oscillations ringing and overshoot and other undesirable behavior An indepth treatment of stability is beyond the scope of this book however the simple phase margin criterion for assessing stability is used here When the phase margin of the loop gain T is positive then the feedback system is stable Moreover increasing the phase margin causes the system transient response to be better behaved with less overshoot and ringing The relation between phase margin and closed loop response is quanti ed in section 94 Chapter 9 Controller Design An example is given in section 95 in which a compensator network is designed for a dc regulator system The compensator network is designed to attain adequate phase margin and good rejection of expected disturbances Lead compensators and PD controllers are used to improve the phase margin and extend the bandwidth of the feedback loop This leads to better rejection of highfrequency disturbances Lag compensators and PI controllers are used to increase the lowfrequency loop gain This leads to better rejection of lowfrequency disturbances and very small steadystate error More complicated compensators can achieve the advantages of both approaches Injection methods for experimental measurement of loop gain are introduced in section 96 The use of voltage or current injection solves the problem of establishing the correct quiescent operating point in high gain systems Conditions for obtaining an accurate measurement are exposed The injection method also allows measurement of the loop gains of unstable systems 92 Effect of negative feedback on the network transfer functions We have seen how to derive the smallsignal ac es 16 1 MB L2 transfer functions of a switching converter For v gs 139s 07s i C V15 51 iltsgt example the equivalent circuit 7 mOdel 0f the bUCk conVener Fig 93 Smallsignal converter model which represents can be written as in Fig 93 variations nggtdgtandi10ad This equivalent circuit contains three independent inputs the control input variations 3 the power input voltage variations g and the load current variations 1 10 The output voltage variation 7 can therefore be expressed as a linear combination of the three independent inputs as follows 93 GAS a73 t Gng 20 ZWU EMU 91 where converter controltooutput transfer function Gas Vg0 mfo VS W Gvg3 A converter linetooutput transfer lnction d 0 load 0 Chapter 9 Controller Design Z Ws 7 VU converter output impedance loads Z 00 vg The Bode diagrams of these quantities are constructed in chapter 8 Equation 91 describes how disturbances 17g and i and propagate to the output 17 through the transfer function Gvgm and the output impedance Zoms If the disturbances 13g and land are known to have some maximum worstcase amplitude then Eq 91 can be used to compute the resulting worstcase openloop variation in 17 As described previously the feedback loop of Fig 92 can be used to reduce the in uences of g and ma on the output 17 To analyze this system let us perturb and linearize its averaged signals about their quiescent operating points Both the power stage and the control block diagram are perturbed and linearized W40 m 020 M V20 V2 920 etc In a dc regulator system the reference input is constant so ft 0 In a switching amplifier or dcac inverter the reference input may contain an ac variation In Fig 94a the converter model of Fig 93 is combined with the perturbed and linearized control circuit block diagram This is equivalent to the reduced block diagram of Fig 94b in which the converter model has been replaced by blocks representing Eq 91 Solution of Fig 94b for the output voltage variation 17 yields G Gm VM Gvg Z A A c 7 out V 2f 1 HGGM VM l Vg 1 HGGW VM and 1 HGGV VM 93 which can be written in the form A 7 A 1 T Gvg 1 Zout V W F W Vg W and W 9394 with TS HSGCSGVdS VM loop gain Equation 94 is a general result The loop gain Ts is de ned in general as the product of the gains around the forward and feedback paths of the loop This equation shows how the addition of a feedback loop modifies the transfer functions and performance of the system as described in detail below Chapter 9 Controller Design 11 d dc 1 Mn g l i ago In gay 0 0o 11 two use 47 reference VM inpu pulsewidth mo ulafor H A mvm r1 sensor gain I gonna load current VAX aclme vananun pulsewidth A mo 14 afor vWs V X s v s output voltage duty cycle Varlatlun Varlatlun converter power stage H s VG IH J sensor ain Fig 94 Voltage regulator system smallsignal model a with converter equivalent circuit b complete block diagram 921 Feedback reduces the transfer functions from disturbances to the output The transfer function from g to a in the openloop buck converter of Fig 93 is Gvgs as given in Eq 91 When feedback is added this transfer function becomes 0s Gvgs gs ate0 1 Ts flood 0 from Eq 94 So this transfer lnction is reduced via feedback by the factor l1Ts If the loop gain Ts is large in magnitude then the reduction can be substantial Hence the output voltage variation x i resulting from a given g variation is attenuated by the feedback 95 loop Chapter 9 Controller Design Equation 94 also predicts that the converter output impedance is reduced from ZoraS to as Zs iloadS VAre0 1 To v g 0 96 So the feedback loop also reduces the converter output impedance by a factor of llTs and the in uence of load current variations on the output voltage is reduced 922 Feedback causes the transfer function from the reference input to the output to be insensitive to variations in the gains in the forward path 0f the loop According to Eq 94 the closedloop transfer function from Q40 to 7 is 70 1 TO awn fe Hs 1 Ts 9397 IIWZO Ifthe loop gain is large in magnitude ie H T H gtgt 1 then 1T rs T and T1T rs TT l The transfer function then becomes 70 H 1 Ms quot Hm 9398 which is independent of GJS VM and Gvds So provided that the loop gain is large in magnitude then variations in GJS VM and Gvds have negligible effect on the output voltage Of course in the dc regulator application vref is constant and 040 0 But Eq 98 applies equally well to the dc values For example if the system is linear then we can write 1 T0 H E WHHOYMO 9399 So to make the dc output voltage V accurately follow the dc reference Vref we need only ensure that the dc sensor gain H 0 and dc reference Vref are wellknown and accurate and that T0 is large Precision resistors are normally used to realize H but components with tightlycontrolled values need not be used in G0 the pulsewidth modulator or the power stage The sensitivity of the output voltage to the gains in the forward path is reduced while the sensitivity of v to the feedback gain H and the reference input vmf is increased Chapter 9 Controller Design HTH z r 20dBdec fc 72MB Emmy fwmy r40dBdec 1Hz min 10on lkHz 10in 100kHz f Fig 95 Magnitude of the loop gain example Eq 910 93 Construction of the important quantities 11T and T1T and the closed loop transfer functions The transfer functions in Eqs 94 7 99 can be easily constructed using the algebraonthegraph method 4 Let us assume that we have analyzed the blocks in our feedback system and have plotted the Bode diagram of H Ts H To use a concrete example suppose that the result is given in Fig 95 for which Ts is TsT0 1Qwiplz1wi 910 This example appears somewhat complicated But the loop gains of practical voltage regulators are often even more complex and may contain four ve or more poles Evaluation of Eqs 95 97 to determine the closedloop transfer functions requires quite abit of work The loop gain T must be added to l and the resulting numerator and denominator must be refactored Using this approach it is dif cult to obtain physical insight into the relationship between the closedloop transfer functions and the loop gain In consequence design of the feedback loop to meet speci cations is difficult Using the algebraonthegraph method the closedloop transfer functions can be constructed by inspection and hence the relation between these transfer functions and the loop gain becomes obvious Let us rst investigate how to plot H T1T H It can be seen from Fig 95 that there is a frequency fc called the crossover frequency where H T H 1 At frequencies less thanfc H T H gt 1 indeed H T H gtgt 1 forfltlt fc Hence at low frequency 1T rs T and T1T rs TT 1 At frequencies greater thanfc H T H lt l and H TH ltlt 1 forfgtgtfc So at high frequency 1T 1 and TlT rs Tl T So we have Chapter 9 Controller Design Cmssuver frequency 2 7 20dBdec fc 01113 171 fpz ZOdB 1 1 T 7 40dBdec 40l 3 1H2 IOHZ IOOHZ lkHZ IOkHZ lOOkHZ Fig 96 Graphical construction of the asymptotes of H Tl T H Exact curves are omitted T H 1 fOVHTHgtgt1 T forHTHltlt1 911 The asymptotes corresponding to Eq 911 are relatively easy to construct The low frequency asymptote for f lt fc is 1 or OdB The highfrequency asymptotes for f gt fc follow T The result is shown in Fig 96 So at low frequency where H T H is large the referencetooutput transfer function 0 s 1 M H 1 1243 Hs 1 Ts Hs 9 12 This is the desired behavior and the feedback loop works well at frequencies where H T H is large At high frequency f gtgt fc where H T H is small the referencetooutput transfer function is f s 1 M H To 6406110 943 1543 H s 1Ts H 3 VM This is not the desired behavior in fact this is the gain with the feedback connection removed H gt 0 At high frequencies the feedback loop is unable to reject the disturbance because the bandwidth of T is limited The referencetooutput transfer function can be constructed on the graph by multiplying the T1T asymptotes of Fig 96 by 1H We can plot the asymptotes of H 11T H using similar arguments At low frequencies where H T H gtgt 1 then 1T rs T and hence 11T rs 1T At high frequencies where H T H ltlt 1 then 1T cs 1 and 11T cs 1 So we have 1 H forHTHgtgt1 1Ts 1 forH TH ltlt1 914 Chapter 9 Controller Design frequency 1 1T le 10Hz 100Hz lkHz 10kHz 100kHz f Fig 97 Graphical construction of H l l T H The asymptotes for the TS example of Fig 95 are plotted in Fig 97 At low frequencies where H T H is large the disturbance transfer function from g to lt V m Gng 5 915 04s 1Ts m Again Gvgm is the original transfer function with no feedback The closedloop transfer function has magnitude reduced by the factor 1 H T H So if for example we want to reduce this transfer function by a factor of 20 at 120Hz then we need a loop gain H T H of at least 20 gt 26dB at 120Hz The disturbance transfer lnction from g to 7 can be constructed on the graph by multiplying the asymptotes of Fig 97 by the asymptotes for Gvgm Similar arguments apply to the output impedance The closedloop output impedance at low frequencies is 65 Zola z Zeal 916 The output impedance is also reduced in magnitude by a factor of lH T H at frequencies below the crossover frequency At high frequencies fgtfc where H T H is small then 11T cs 1 and 03 Gvgs Ggs 1 T s Gng as 2mm eimw HT 2W 917 Chapter 9 Controller Design This is the same as the original disturbance transfer function and output impedance So the feedback loop has essentially no effect on the disturbance transfer functions at frequencies above the crossover frequency 9 4 Stability It is well known that adding a feedback loop can cause an otherwise stable system to become unstable Even though the transfer functions of the original converter Eq 91 as well as of the loop gain Ts contain no right halfplane poles it is possible for the closedloop transfer functions of Eq 94 to contain right halfplane poles The feedback loop then fails to regulate the system at the desired quiescent operating point and oscillations are usually observed It is important to avoid this situation And even when the feedback system is stable it is possible for the transient response to exhibit undesirable ringing and overshoot The stability problem is discussed in this section and a method for ensuring that the feedback system is stable and wellbehaved is explained When feedback destabilizes the system the denominator 1Ts terms in Eq 9 4 contain roots in the right halfplane ie with positive real parts If Ts is a rational fraction ie the ratio NsDs of two polynomial functions Ns and Ds then we can write gKZ E 1 l DU 9 18 1 Ts H amp Ns Ds 39 135 So TS1Ts and l1Ts contain the same poles given by the roots of the polynomial Ns Ds A bruteforce test for stability is to evaluate Ns Ds and factor the result to see whether any of the roots have positive real parts However for all but very simple loop gains this involves a great deal of work A simpler method is given by the Nyquist stability theorem in which the number of right halfplane roots of Ns Ds can be determined by testing Ts 12 This theorem is not discussed here However a special case of the theorem known as the phase margin test is sufficient for designing most voltage regulators and is discussed in this section 941 The phase margin test The crossover frequency fc is defined as the frequency where the magnitude of the loop gain is unity Chapter 9 Controller Design H T039271fJH1 gt OdB 919 To compute the phase margin pm the phase of the loop gain T is evaluated at the crossover frequency and 180 is added Hence pm 180 4an 920 If there is exactly one crossover frequency and if the loop gain Ts contains no right half plane poles then the quantities l1T and T1T contain no right halfplane poles when the phase margin de ned in Eq 920 is positive Thus using a simple test on Ts we can determine the stability of T1T and l1T This is an easytouse design tool iwe simple ensure that the phase of T is greater than 7180 at the crossover frequency When there are multiple crossover frequencies the phase margin test may be ambiguous Also when T contains right halfplane poles ie the original openloop system is unstable then the phase margin test cannot be used In either case the more general Nyquist stability theorem must be employed The loop gain of a HTH 6MB TH 4T typical stable system is 4MB fpl WWW shown in Fig 98 It can be ME f2 eequotcy seen that B T 0 ATO39ZTLfJ 7112 Hence 72MB 7790 pm 180 7 112 68 4013 m 480 Since the phase margin is 470 positive T1T and le 10Hz 100Hz lkHz IOkHz IOOkHz l1T contain no right half f plane poles and the feedback Fig 98 Magnitude and phase of the loop gain ofa stable system System is Stable The phase margin pm is positive GOdB The loop gain of an HTH er unstable system is sketched 40 in Fig 99 For this 13 f 214332 example ATO39ZTLfJ OdB z T 0 7230 The phase margin is 72mm 790 pm 180 7 230 750 MB 180 The negative phase margin lt 0 7270 implies that T1T and l1T each contain at least IHZ IOHZ 100m f H2 10km 100ml one right half39plane POIe Fig 99 Magnitude and phase of the loop gain of an unstable system The phase margin pm is negative Chapter 9 Controller Design 942 The relation between phase margin and closed100p damping factor How much phase margin is necessary Is a worstcase phase margin of 1 satisfactory Of course good designs should have adequate design margins but there is another important reason why additional phase margin is needed A small phase margin in 7 causes the closedloop transfer functions T1T and l1T to exhibit resonant poles with high Q in the vicinity of the crossover frequency The system transient response exhibits overshoot and ringing As the phase margin is reduced these characteristics become worse higher Q longer ringing until for pm S 0 the system becomes unstable Let us consider a loop gain Ts which is wellapproximated in the vicinity of the crossover frequency by the following function we m Magnitude and phase asymptotes are plotted in Fig 910 This function is a good approximation near the crossover frequency for many common loop gains in which H T H approaches unity gain with 4mm H TH f T i e T a720dBdecade slope w1th H H mm f Joinsdecade f an add1tlonal pole at MB frequency f 022717 Any f2 Q I I rZOdB f1 add1t10nal poles and zeroes 4MB 740dBdecade 0 are assumed to be T 790 510 i 790 sufficiently far above or W f2 below the crossover 10 f 7180 7270quot frequency such that they f haVe negligible effeet 011 the Fig 910 Magnitude and phase asymptotes for the loop gain T system transfer functions of Eq39 93921 near the crossover frequency Note that ang gt 00 the phase margin pm approaches 90 ASf2 gt 0 pm gt 0 So as f is reduced the phase margin is also reduced Let s investigate how this affects the closedloop response via T1T We can write T S 1 1 922 l T s l i 32 1TS 1w0 w0wl using Eq 921 By putting this into standard quadratic form one obtains T S 1 9 23 1 Ts 1 s i 2 Q60 0 Chapter 9 Controller Design 7 7 40dB T where a 7 600602 7 27 H H g Q wo wo MB 20dBd d i i 7 sea e w w 17 M 1 So the closedloop response contains f WTQ foJZ quadratic poles at fc the geometric mean of f0 and f2 These poles have a 4MB 4odBdecade low Qfactor when f0 ltlt f2 In this case we can use the lowQ Fig 911 Construction of magnitude asymptotes of approximation to estimate their the closedloop transfer function T 1 T for the lowQ case frequencies Q a we a j 7 w 9 24 Magnitude asymptotes are plotted in Fig 911 for this case It can be seen that these asymptotes conform to the rules of section 93 for constructing T1T by the algebraon thegraph method Next consider the highQ case When the pole frequency f2 is reduced reducing the phase margin then the Qfactor given by Eq 923 is increased For Q gt 05 resonant poles occur at frequency fc The 60GB 5 T magn1tude Bode plot for the case f lt ma H H 7 20dBdecade f0 1s g1ven 1n F1g 912 The MB frequency fc continues to be the dB Qff 0 geometric mean of f2 and f0 and fc j 51312 f0 l 720dB now coincides with the crossover 6 40dBdmde unitygain frequency of the H T H 4MB f asymptotes The exaCI Value Of the Fig 912 Construction of magnitude asymptotes of the closedloop transfer function T 1 T for closedloop gain T1T at frequency fc is equal to Q ftfc As shown in Fig 912 this is identical to the value of the lowfrequency 720dBdecade asymptote the highQ case ftf evaluated at frequency fc It can be seen that the Qfactor becomes very large as the pole frequency f2 is reduced The asymptotes of Fig 912 also follow the algebraonthegraph rules of section 93 but the deviation of the exact curve from the asymptotes is not predicted by the algebraonthegraph method These two poles with Qfactor appear in both T1T and llT We need an easy way to predict the Qfactor We can obtain such a relation by nding the frequency at which the magnitude of T is exactly equal to unity We then Chapter 9 Controller Design Fig 913 Relation between loop gain phase margin pm and closedloop peaking factor Q evaluate the exact phase of Tat this frequency and compute the phase margin This phase margin is afunction of the ratio ftfg or Q2 We can then solve to nd Q as a function of the phase margin The result is Q lcos pm sin pm 4 pmtan1 114Q 2Q 925 This function is plotted in Fig 913 with Q expressed in dB It can be seen that obtaining real poles Q lt 05 requires a phase margin of at least 76 To obtain Q 1 a phase margin of 52 is needed The system with a phase margin of 1 exhibits a closedloop response with very high Q With a small phase margin T000 is very nearly equal to 71 in the vicinity of the crossover frequency The denominator 1T then becomes very small causing the closedloop transfer functions to exhibit a peaked response at frequencies near the crossover frequency Figure 913 is the result for the simple loop gain de ned by Eq 921 However this loop gain is a good approximation for many other loop gains that are encountered in practice in which H T H approaches unity gain with a 720dBdecade slope with an additional pole at frequency f2 If all other poles and zeroes of Ts are suf ciently far above or below the crossover frequency then they have negligible effect on the system transfer functions near the crossover frequency and Fig 913 gives a good approximation for the relation between pm and Q Chapter 9 Controller Design Another common case is the one in which H T H approaches unity gain with a AOdBdecade slope with an additional zero at frequency f2 As f is increased the phase margin is decreased and Q is increased It can be shown that the relation between pm and Q is exactly the same Eq 925 A case where Fig 913 fails is when the loop gain Ts three or more poles at or near the crossover frequency The closedloop response then also contains three or more poles near the crossover frequency and these poles cannot be completely characterized by a single Qfactor Additional work is required to nd the behavior of the exact T1T and l1T near the crossover frequency but nonetheless it can be said that a small phase margin leads to a peaked closedloop response 943 Transient response vs damping factor One can solve for the unitstep response of the T1T transfer function by multiplying Eq 923 by 13 and then taking the inverse Laplace transform The result for Q gt 05 is 4in1 For Q lt 05 the result is m 1 wanlrgul 926 m a at17 2 eggle 1 V 6027601 wliall aw These equations are plotted 2 erwzz 9 27 with col a2 in Fig 914 for various 7 values of Q According to Eq 9 23 whenfg gt 4f0 the Q factor is less than 05 and the closedloop response contains a lowfrequency o5 and a highfrequency real pole The transient response in this case Eq 927 0 5 10 15 contains decaying O c radium 1 f f Fig 914 Unitstep response of the secondorder system Eqs 9 exponemla unctlons 0 26 and 927 for various values of Q time of the form Chapter 9 Controller Design 49W 928 This is called the overdamped case With very low Q the lowfrequency pole leads to a slow step response For f 4f0 the Qfactor is equal to 05 The closedloop response contains two real poles at frequency 2fg This is called the critically damped case The transient response is faster than in the overdamped case because the lowestfrequency pole is at a higher frequency This is the fastest response that does not exhibit overshoot At not TE radians t 12fc the voltage has reached 82 of its nal value At not 27E radians t lfc the voltage has reached 986 of its final value For f lt 4f0 the Qfactor is greater than 05 The closedloop response contains complex poles and the transient response exhibits sinusoidaltype waveforms with decaying amplitude Eq 926 The rise time of the step response is faster than in the criticallydamped case but the waveforms exhibit overshoot The peak value of 0t is peak on 1 e4 492 929 This is called the underdamped case A Qfactor of 1 leads to an overshoot of 163 while a Qfactor of 2 leads to a 444 overshoot Large Qfactors lead to overshoots approaching 100 The exact transient response of the feedback loop may dilTer from the plots of Fig 914 because of additional poles and zeroes in T and because of dilTerences in initial conditions Nonetheless Fig 914 illustrates how highQ poles lead to overshoot and ringing In most power applications overshoot is unacceptable For example in a 5V computer power supply the voltage must not be allowed to overshoot to 7 or 10 volts when the supply is tumed on ithis would destroy all of the TTL integrated circuits in the computer So the Qfactor must be suf ciently low o en 05 or less corresponding to a phase margin of at least 76 9 5 Regulator design Let s now consider how to design a regulator system to meet specifications or design goals regarding rejection of disturbances transient response and stability Typical dc regulator designs are defined using specifications such as the following 1 Effect of load current variations on the output voltage regulation The output voltage must remain within a specified range when the load current varies in a prescribed way This amounts to a limit on the maximum magnitude of the closedloop output impedance of Eq 96 repeated below Chapter 9 Controller Design 93 20123 930 iloadcy f39efzo 1 To vg If over some frequency range the openloop output impedance Zom has magnitude which exceeds the limit then the loop gain Tmust be suf ciently large in magnitude over the same frequency range such that the magnitude of the closedloop output impedance given in Eq 930 is less than the given limit 2 Effect of input voltage variations for example at the second harmonic of the ac line frequency on the output voltage regulation Speci c maximum limits are usually placed on the amplitude of variations in the output voltage at the second harmonic of the ac line frequency 120Hz or lOOHz If we know the magnitude of the recti cation voltage ripple which appears at the converter input as cg then we can calculate the resulting output voltage ripple in v using the closed loop linetooutput transfer function of Eq 95 repeated below 7 3 GV s 68 1 31 931 mfo The output voltage ripple can be reduced by increasing the magnitude of the loop gain at the ripple frequency In atypical good design H T H is 20dB or more at 120Hz so that the transfer function of Eq 931 is at least an order of magnitude smaller than the openloop linetooutput transfer function H Gvg H 3 Transient response time When a speci ed large disturbance occurs such as a large step change in load current or input voltage the output voltage may undergo a transient During this transient the output voltage typically deviates from its speci ed allowable range Eventually the feedback loop operates to return the output voltage within tolerance The time required to do so is the transient response time typically the response time can be shortened by increasing the feedback loop crossover frequency 4 Overshoot and ringing As discussed in section 943 the amount of overshoot and ringing allowed in the transient response may be limited Such a speci cation implies that the phase margin must be suf ciently large Each of these requirements imposes constraints on the loop gain Ts Therefore the design of the control system involves modifying the loop gain As illustrated in Fig Chapter 9 Controller Design 92 a compensator network is added for this purpose Several wellknown strategies for design of the compensator transfer function GJS are discussed below 951 Lead PD compensator This type of compensator transfer function is used to improve the phase margin A zero is added to the loop gain at a frequency fz suf ciently far below the crossover frequency fc such that the phase margin of Ts is increased by the desired amount The lead compensator is also called a proportionalplusderivative or PD controller fat high frequencies the zero causes the compensator to differentiate the error signal It o en finds application in systems originally containing a twopole response By use of this type of compensator the bandwidth of the feedback loop ie the crossover frequency f6 can be extended while maintaining an acceptable phase margin A side effect of the zero is that it causes the compensator gain to increase with frequency with a 20dBdecade slope So steps must be taken to ensure that H T H remains equal to unity at the desired crossover frequency Also since the gain of any practical amplifier must tend to zero at high frequency the compensator transfer function GJS must contain high frequency poles These poles also have the beneficial effect of attenuating high frequency noise Of particular concern are the switching frequency harmonics present in the output voltage and feedback signals If the compensator gain at the switching frequency is too great then these switching harmonics are ampli ed by the compensator and can disrupt the operation of the pulsewidth modulator see section 77 So the compensator network should contain poles at a frequency less than the switching frequency These considerations typically restrict the crossover frequency fc to be less than approximately 10 of the converter switching frequency In addition the circuit designer must take care not to exceed the gainbandwidth limits of available operational amplifiers The transfer function of the lead compensator therefore contains a low frequency zero and several highfrequency H G H Gd poles A simplified example containing a single highfrequency pole is given in Eq 932 and f 1 z illustrated in Fig 915 45 decade I 1 0 m GAS G50 932 4 Co 1 Slw elw f Fig 915 Magnitude and phase asymptotes of the PD compensator transfer function Go of Eq 932 Chapter 9 Controller Design The maximum phase occurs at a frequency fmm given by the geometrical mean of the pole and zero frequencies fmax f2 To obtain the maximum improvement in phase margin we should design our compensator so that the frequency fmm coincides with the loop gain crossover frequency fc The value 933 of the phase at this frequency can be shown to be 7 2 J 2 4Ch2mxtan391 E 934 This equation is plotted in Fig 90 maximum 916 Equation 934 can be PM lead inverted to obtain 1 l sin 9 45 J 17 sm 9 935 where 9 ZGCVWM Equations 934 and 932 imply that to 15 optimally obtain a compensator phase lead of 9 at frequency f6 the pole and zero frequencies should be chosen as follows 0 l l l l 1 10 100 1000 1 09 Fig 916 Maximum phase lead 9 vs frequency ratiofp fz for the lead compensator f e f Z 5 l sin 9 f 7 f l sin 9 p E 1 Sin 9 936 When it is desired to avoid changing the crossover frequency the magnitude of the compensator gain is chosen to be unity at the loop gain crossover frequency fc This requires that G00 be chosen according to the following formula G0 937 mm It can be seen that G50 is less than unity and therefore the lead compensator reduces the dc gain of the feedback loop Other choices of G60 can be selected when it is desired to shift the crossover frequency f6 for example increasing the value of G60 causes the crossover frequency to increase If the frequencies f and fz are chosen as in Eq 936 then fwax of Eq 932 will coincide with the new crossover frequency 20 The Bode diagram of a typical T 3 containing two poles is illustrated in Fig 917 The phase margin of the HTH HTH loop gain original Ts is small the frequency fc is since crossover substantially greater than the pole frequency f The result of adding a lead compensator is Fig 917 Chapter 9 Controller Design compensated gain original phase asymptotes f Compensation of a loop gain containing two poles using a lead PD compensator The phase margin pm is improved also illustrated The lead compensator of this example is designed to maintain the same crossover frequency but improve the phase margin 952 Lag PI compensator This type of compensator is used to increase the lowfrequency loop gain such that the output is better regulated at dc and at frequencies well below the loop crossover 938 and illustrated in Fig 918 an inverted zero is frequency As given in Eq added to the loop gain at frequency fL Gs Ga1 938 If fL is sufficiently lower than the loop crossover frequency fc then the phase margin 7 is unchanged This type of compensator is also or PI controller fat low frequencies the inverted called a proportionalplusintegral zero causes the compensator to integrate the error signal r 20dB decade fL 1sz 0 4 Go 7 90 45 decade fLJU f Fig 918 Magnitude and phase asymptotes of the Pl compensator transfer function GC of Eq 938 To the extent that the compensator gain can be made arbitrarily large at dc the dc loop gain T0 becomes arbitrarily large This causes the dc component of the error signal to approach zero In consequence the steadystate output voltage is perfectly regulated and the disturbancetooutput transfer functions approach zero at dc Such behavior is easily Chapter 9 Controller Design 4MB H T H obta1ned 1n pract1ce w1th the GENT compensator of Eq 938 20dB H T H T fL f0 0 realized using a quot 39 MB 0 f f operational ampli er 0 rZOdB 90 Although the PI 4 Tu 40dB 0 compensator 1s useful 1n nearly 10fL all types of feedback systems if 10 f0 P r90 it is an especially simple and 480 effective approach for systems le 10Hz 100HZ lkHz 10kHz 100kHZ originally containing a single pOIe39 For the exalnple 0f Fig39 Fig 919 Compensation ofa loop gain containing a single pole 9 19 the original using a lag Pl compensator The loop gain magnitude is increased uncompensated loop gain is of the form Ms l 00 939 The compensator transfer function of Eq 938 is used so that the compensated loop gain is Ts Tum Goa Magnitude and phase asymptotes of TS are also illustrated in Fig 919 The compensator highfrequency gain GM is chosen to obtain the desired crossover frequency If we approximate the compensated loop gain by its highfrequency asymptote then at high frequencies we can write Tue Gm i jg 940 At the crossover frequency f f6 the loop gain has unity magnitude Equation 940 T predicts that the crossover frequency is f Tqumfo 941 Hence to obtain a desired crossover frequency f0 we should choose the compensator gain Gm as follows G L M 0 13 942 The comer frequency fL is then chosen to be sufficiently less than f6 such that an adequate phase margin is maintained Magnitude asymptotes of the quantity 1 1 TS are constructed in Fig 920 At frequencies less than fL the PI compensator improves the rejection of disturbances At dc Chapter 9 Controller Design where the magnitude of Go 40dB approaches in nity the MB magnitude of 1 1 T tends to zero Hence the closedloop disturbanceto 72MB output transfer functions 4MB such as Eqs 930 and 9 31 tend to zero at dc le 10Hz 100Hz lkHz 10kHz 100kHz f Fig 920 Construction of H l 1 T H for the Pl compensated example ofFig 919 953 Combined PID compensator The advantages of the lead and lag compensators can be combined to obtain both wide bandwidth and zero steadystate error At low frequencies the compensator integrates the error signal leading to large lowfrequency loop gain and accurate regulation of the lowfrequency components of the output voltage At high frequency in the vicinity of the crossover frequency the compensator introduces phase lead into the loop gain improving the phase margin Such a compensator is sometimes called a PID controller A typical Bode diagram of a practical version of this compensator is illustrated in Fig 921 The compensator has transfer function 0 s 1 TL 1 E 1 mi 1 0 9 43 The inverted zero at frequency fL functions in the same manner as the PI compensator The GAS Gm zero at frequency fz adds phase lead in the vicinity of the crossover frequency as in the PD 40dB ll Go ll 20dB Mfr 102 4210 45 dec compensator The 4MB prIo 9ocd2x 0 highfrequency poles at 90 fw 90M Jofpz 790 ZG f10 frequenc1es jg and 32 c L 7180 must be present in practical compensators f 10 cause the gain to YOU Fig 921 Magnitude and phase asymptotes of the combined PID compensator transfer function GC of Eq 9 43 23 Chapter 9 Controller Design off at high frequencies and to prevent the switching ripple from disrupting the operation of the pulsewidth modulator The loop gain crossover frequency fc is chosen to be greater thanfL andfz but less than and 22 954 Design example To illustrate the design of PI and PD compensators let us consider the design of a combined PID compensator L for the dcdc buck 50HH rm converter system of Fig J LI 922 The input voltage vg I Vg for this system has 28V mm nominal value 28V It is am desired to supply a A regulated 15V to a 5A load 5 The load is modeled here with a 39 resistor An accurate 5V reference is Fig39 92239 DeSign example available The first step is to select the feedback gain H s The gainH is chosen such that the regulator produces a regulated 15V dc output Let us assume that we will succeed in compensator VM 4v designing a good feedback system which causes the output voltage to accurately follow the reference voltage This is accomplished via a large loop gain T which leads to a small error voltage V cs 0 Hence Hv rs vref So we should choose 7 7 7 E 7 3 944 The quiescent duty cycle is given by the steadystate solution of the converter D Vg 0536 28 945 The quiescent value of the control voltage V0 must satisfy Eq 7135 Hence V DVM214V 946 Thus the quiescent conditions of the system are known It remains to design the compensator gain 603 A smallsignal ac model of the regulator system is illustrated in Fig 923 The buck converter ac model is represented in canonical form Disturbances in the input voltage and Chapter 9 Controller Design La 1n the load current are D2 I D L modeled For i J genera11ty reference my a C m R mm voltage variations T 34 are included in the diagram in a dc voltage regulator these variations are GD normally zero The openloop converter transfer e 1 functlons are H i Fig 923 System smallsignal ac model design example d1scussed 1n the previous chapters The openloop controltooutput transfer function is Gm 1 L1 2LC SF S 947 The openloop controltooutput transfer function contains two poles and can be written in the following normalized form GAS G40 2 1 S Qo Do 0 948 By equating like coefficients in Eqs 947 and 948 one finds that the dc gain comer frequency and Qfactor are given by Gd0 28v no 1 7 7 71kH f0 27 2mLC Z C R 95 195dB Qquot L 3 949 In practice parasitic loss elements such as the capacitor equivalent series resistance esr would cause a lower Qfactor to be observed Figure 924 contains a Bode diagram of Gvds39 The openloop linetooutput transfer function is 7 l GVgSTD 1 L 2LC 3 s R 950 This transfer function contains the same poles as in ivyS and can be written in the normalized form Chapter 9 Controller Design 60dBV e H Gm H 4 Gm mm H Gvd H GM 28Vgt29dBV 190 i 1953913 20dBV f0 zgvd 10quot ang900Hz OdBV l 0 720dBV 7 790 40dBV 7180 101Zg fn11kHz 7270 1Hz 10Hz 100Hz lkHz 10kHz 100kHz Fig 924 Converter smallsignal controltooutput transfer function Gvd design example 1 1 S if Qowo 00 951 with Ggu D The openloop output impedance of the buck converter is SL 1 s4 sZLC R 952 Gng GgO ZWSRHH sL Use of these equations to represent the converter in blockdiagram form leads to the complete system block diagram of Fig 925 The loop gain of the system is To Gm Gm Ho 953 Substitution of Eq 948 into 953 leads to G H m s 01 1 V D 1 s day 0 Qo Do 0 954 flours 111 05 20 rte variation Fig 925 System block diagram design example 26 Chapter 9 Controller Design OdB 7 The closedloop H m u ZOdB d1sturbancetooutput ll Tu H Tuo 233 7439iB Z 5 lg 9395 19513 transfer functions are 3 f0 lkHz iven b E s 95 g y q 2MB 740 dBdecade and 0 lO Efn 900HZ 40dB 39 0 The 1 Tu 790 uncompensated loop ain T s with unit 480 g 0 y miffriknz compensator ga1n 1s 7270 le 10Hz 100HZ lkHz 10kHZ 100kHz sketched 1n F1g 926 f With Go 1 Eq Fig 926 Uncompensated loop gain Tu design example 954 can be written 1 TuS T140 S S 2 1 l Qowo l 955 where the dc gain is Tue 233 gt 74dB M 956 The uncompensated loop gain has a crossover frequency of approximately 18kHz with a phase margin of less than five degrees Let us design a compensator to attain a crossover frequency of fc SkHz or one twentieth of the switching frequency From Fig 926 the uncompensated loop gain has a magnitude at SkHz of approximately Tun f0 f02 0093 gt 7206dB So to obtain unity loop gain at SkHz our compensator should have a SkHz gain of 206dB In addition the compensator should improve the phase margin since the phase of the uncompensated loop gain is nearly 7180 at SkHz So a lead PD compensator is needed Let us somewhat arbitrarily choose to design for a phase margin of 52 According to Fig 913 this choice leads to closedloop poles having a Qfactor of 1 The unit step response Fig 914 then exhibits apeak overshoot of 16 Evaluation of Eq 936 with fC SkHz and 9 52 leads to the following compensator pole and zero frequencies 1 7 sin 52quot j SkHz 1Sin 520 17kHz j SkHz 145kHz 1 7 S111 To obtain a compensator gain of 206dB gt 107 at SkHz the lowfrequency compensator gain must be Chapter 9 Controller Design 40dB HGCH GED f AG 2MB HGCH GE 2 F i f 00113 7 777777 7 fzfp rrrrrrrrrrrrrrrrrrrrrrrrrr 7201113 IMO 10 90 0 fIo 40dB 0 26 790 7180quot le 10HZ 100Hz lkHz 10kHz 100kHz f Fig 927 PD compensator transfer function Go design example 2 60 T1 g 37gt113dB 0 fp 958 A Bode diagram of the PD compensator magnitude and phase is sketched in Fig 927 With this PD controller the loop gain becomes S 1EZ Helmet The compensated loop gain is sketched in Fig 928 It can be seen that the phase of Ts is TU T140 G50 approximately equal to H T H Q0 95 195113 52 over the frequency range of 14kHz to 17kHz Hence variations in component T0 86 187dB values which cause the crossover frequency to deviate somewhat from 5kHz should have little impact on the phase le lOHZ 100Hz lkHZ 10kHz 100kHz margin In addition it f can be seen from Fig Fig 928 The compensated loop gain oqu 959 928 that the loop gain has a dc magnitude of TuUGCU gt 187dB Asymptotes of the quantity 1 1 T are constructed in Fig 929 This quantity has a dc asymptote of 7187dB Therefore at frequencies less than lkHz the feedback Chapter 9 Controller Design loop attenuates output voltage by 187dB example suppose that the input QU95 1953913 H TH T0 86gt187dB disturbances For voltage Vg contains a 100Hz variation of amplitude 1V With 720dB I I 40dB no feedback loop th1s d1sturbance would propagate to the output according to the openloop transfer function Gvgm given in Eq 961 At IOOHZ this 1Hz 10Hz 100Hz f lkHz 10kHz tranSfer funaion has a gain Fig 929 Construction of H l l T H for the PD essemially equal to the dc compensated design example of Fig 928 asymptote D 0536 Therefore with no feedback loop a 100Hz vaiiation of amplitude 0536V would be observed at the output In the presence of feedback the closedloop line tooutput transfer function of Eq 95 is obtained for our example this attenuates the 100Hz variation by an additional factor of 187dB gt 86 The 100Hz output voltage variation now has magnitude 0536 86 0062V The lowfrequency regulation can be further improved by addition of an inverted zero as discussed in section 952 A PID controller as in section 953 is then obtained The compensator transfer function becomes 1 g 1 Gs Gm 960 The pole and zero frequencies fz and fp are unchanged and are given by Eq 957 The midband gain Gm is chosen to be the same as the previous G00 Eq 958 Hence for frequencies greater than fL the magnitude of the loop gain is unchanged by 40dB H Go H 20dB the The loop continues to exhibit a inverted zero 10f Z 7 45 dec 10 45 dec fL fIJo crossover frequency of 90mm 5kHz fw fLIo So that the inverted zero does not 10Hz 100Hz lkHz 10kHz signi cantly degrade the Fig 930 PID compensator transfer function Eq 960 29 100kHz 7180quot 100kHz phase margin let us somewhat arbitrarily choose fL to be onetenth of the crossover frequency or 500Hz The will then increase the loop inverted zero gain at frequencies below 500Hz improving the low frequency regulation of the output voltage The of Fig 931 obtained The magnitude of loop gain is Chapter 9 Controller Design Fig 9 31 100Hz lkHz 10kHz 100kHz f Construction of H T H and H 11 T H with the PIDcompensator of Fig 930 the quantity 1 1 T is also constructed It can be seen that the inverted zero at 500Hz causes the magnitude of 1 1 T at 100Hz to be reduced by a factor of approximately 100Hz 500Hz 15 The total attenuation of 1 1 T at 100Hz is 327dB A 1V 100Hz variation in Vg would now induce a 12mV variation in vt Further improvements could be obtained by increasing fL however this would require redesign of the PD portion of the compensator to maintain an adequate phase margin The transfer linetooutput function is constructed in Fig 932 Both the openloop transfer function Gvgm Eq 951 and the closedloop transfer function Gvgm 1 TS are constructed using the algebraonthegraph method The two transfer at frequencies greater than the frequency At than the functions coincide crossover frequencies less mm k 20dB OdBe rIOOdB Fig 9 openloop GVg l d l Gvg C 036 00p 1 T 1Hz 1on 100Hz lkHz 10kHz 100kHz 32 Comparison of openloop linetooutput transfer function GVg and closedloop linetooutput transfer function of Eq 9 61 crossover frequency f6 the closedloop transfer function is reduced by a factor of TS It can be seen that the poles of Gvgm are cancelled by zeroes of1 1 T Hence the closed loop linetooutput transfer function is approximately Chapter 9 Controller Design D 1Ts Tqum 11m1m 961 So the algebraonthegraph method allows simple approximate disturbancetooutput closedloop transfer functions to be written Armed with such an analytical expression the system designer can easily compute the output disturbances and can gain the insight required to modify the element values such that system specifications are met 96 Measurement of loop gains It is good engineering practice to measure the loop gains of prototype feedback systems The objective of such an exercise is to verify that the system has been correctly modeled If so then provided that a good controller design has been implemented then the system behavior will meet expectations regarding transient overshoot and phase margin rejection of disturbances dc output voltage regulation etc Unfortunately there are reasons why practical system prototypes are likely to dilTer from theoretical models Phenomena may occur which were not accounted for in the original model and which significantly in uence the system behavior Noise and EMI can be present which cause the system transfer functions to deviate in unexpected ways Block A Bloc2 21a W 0392 G10 00 m 22a GZW V Ha Fig 933 It is desired to determine the loop gain Ts experimentally by making measurements at point A So let us consider the measurement of the loop gain Ts of the feedback system of Fig 933 We will make measurements at some pointA where two blocks of the network are connected electrically In Fig 933 the output port of block 1 is represented by a Theveninequivalent network composed of the dependent voltage source G Ive and output impedance Z 1 Block 1 is loaded by the input impedance Z 2 of block 2 The remainder of the feedback system is represented by a block diagram as shown The loop gain of the system is Chapter 9 Controller Design 223 T GI 210 20 G20 H S 962 Measurement of this loop gain presents several challenges not present in other frequency response measurements V a Block I Block 2 dc bias 0 a J Ml v0 0 W W Gzsvsos 0 w HKV Fig 934 Measurement of loop gain by breaking the loop In principle one could break the loop at point A and attempt to measure Ts using the transfer lnction measurement method of the previous chapter As illustrated in Fig 934 a dc supply voltage VCC and potentiometer would be used to establish a dc bias in the voltage vx such that all of the elements of the network operate at the correct quiescent point Ac voltage variations in vz are coupled into the injection point via a dc blocking capacitor Any other independent ac inputs to the system are disabled A network analyzer is used to measure the relative magnitudes and phases of the ac components of the voltages W and vxm MS 20 re0 v g0 TN 963 The measured gain Tms differs from the actual gain Ts because by breaking the connection between blocks 1 and 2 at the measurement point we have removed the loading ofblock 2 on block 1 Solution of Fig 934 for the measured gain Tms leads to TN G10 G20 H S 964 Equations 962 and 964 can be combined to express Tms in terms of Ts ms Ts 1 215 220 MS Hence Tms rs Ts provided that Z2 gtgt Z1 966 Chapter 9 Controller Design So to obtain an accurate measurement we need to nd an injection point where loading is negligible over the range of frequencies to be measured Other difficulties are encountered when using the method of Fig 934 The most serious problem is adjustment of the dc bias using a potentiometer The dc loop gain is typically very large especially when a PI controller is used A small change in the dc component of vx can therefore lead to very large changes in the dc biases of some elements in the system So it is difficult to establish the correct dc conditions in the circuit The dc gains may drift during the experiment making the problem even worse and saturation of the error ampli er is a common complaint Also we have seen that the gains of the converter can be a function of the quiescent operating point signi cant deviation from the correct operating point can cause the measured gain to differ from the loop gain of actual operating conditions 961 Voltage injection An approach which avoids the dc biasing problem 3 is illustrated in Fig 935 The voltage source vzt is injected between blocks 1 and 2 without breaking the feedback loop Ac variations in vzt again excite variations in the feedback system but dc bias conditions are determined by the circuit Indeed if vzt contains no dc component then the biasing circuits of the system itself establish the quiescent operating point Hence the loop gain measurement is made at the actual system operating point Bloccl 7 0 Block2 0 34 5 Gwen 00 m 22a 6150 0 w Fig 935 Measurement of loop gain by voltage injection The injection source is modeled in Fig 935 by a Thevenin equivalent network containing an independent voltage source with source impedance 253 The magnitudes of vz and ZX are irrelevant in the determination of the loop gain However the injection of vz does disrupt the loading of block 2 on block 1 Hence a suitable injection point must be found where the loading effect is negligible Chapter 9 Controller Design To measure the loop gain by voltage injection we connect a network analyzer to measure the transfer function from V to vy The system independent ac inputs are set to zero and the network analyzer sweeps the injection voltage vz over the intended frequency range The measured gain is MS GAS ref 0 g 0 967 Let us solve Fig 935 to compare the measured gain Tvs with the actual loop gain Ts MS y given by Eq 962 The error signal is 025 HU G25 20 968 The voltage s can be written 7 to 7 60 W 7 Rs 20 Mg where 173 215 is the voltage drop across the source impedance Z 1 Substitution of Eq 9 68 into 969 leads to 7 to 7 7 s 60 Ho 60 7 Rs 20 No But 173 is S m 971 Therefore Eq 970 becomes 1 0 73 35 G1S G23 713 213 Z S 2 972 Substitution of Eq 972 into 967 leads to the following expression for the measured gain Tvs Ms 7 G10 60 Ho 213 223 973 Equations 962 and 973 can be combined to determine the measured gain TVS in terms of the actual loop gain Ts Tvs 7 Ts 1 w 215 223 223 9 74 Thus TVS can be expressed as the sum of two terms The rst term is proportional to the actual loop gain Ts and is approximately equal to Ts whenever H Z 1 H ltlt H Z 2 H The second term is not proportional to TS and limits the minimum Ts that can be measured Chapter 9 Controller Design with the voltage injection technique If Z 1 Z 2 is much smaller in magnitude than Ts then the second term can be ignored and Tvs rs Ts At frequencies where Ts is smaller in magnitude than Z 1 Z 2 the measured data must be discarded Thus TvsTs provided 139 IZlsltltZzs and ii Tsgtgt 975 Again note that the value of the injection source impedance Z is irrelevant As an example consider voltage A injection at the output of an operational 30f ampli er having a 509 output quot 7 V impedance which drives a 5009 effective W s I 5009 load The system in the vicinity of the 7 injection point is illustrated in Fig 936 So 213 509 and 223 5009 The ratio Z 22 is 01 or 720dB Let us Fig 936 V01tageinject10n example further suppose that the actual loop gain Ts contains poles at 10Hz and 100kHz with a dc gain of 80dB The actual loop gain magnitude is illustrated in Fig 937 Voltage injection would result in measurement of Tvs given in Eq 974 Note that 213 1ZZS711gt083dB 976 Hence for large H T H the measured mm H TV H deviates from the actual loop gain by less than ldB However at high frequency where H T H is less than 720dB the measured gain di ers signi cantly Apparently TV Contains tWO highfrequency 001B HT H zeroes that are not present 1n Ts 72mm V V Depending on the Qfactor of these 4MB H T H 10HZ 100HZ lkHZ 10kHZ 100kHZ IMHZ zeroes the phase of TV at the crossover frequenc could be Fig 937 Comparison of measured loop gain TV and in uenced To ensure that the phase actual loop gain T voltage injection example The measured gain deviates at high frequency Chapter 9 Controller Design margin is correctly measured it is important that Z 1 Z 2 be suf ciently small in magnitude l9 2 0 3 215 3439s 00 GIWEG 62s0s0s Trs Hrs Fig 938 Measurement of loop gain by current injection 962 Current injection The results of the preceding paragraphs can also be obtained in dual form where the loop gain is measured by current injection 3 As illustrated in Fig 938 we can model block 1 and the analyzer injection source by their Norton equivalents and use current probes to measure ix and iy The gain measured by current injection is Tm 3 zs fe V 977 It can be shown that ms Ts 1 225 225 213 213 978 Hence ms 2 Ts provided 139 Z20quot ltlt 213 and Z s T gtgt 2 zz S 213 iy 2 ix 979 Cb So to obtain an accurate measurement of the loop gain by current R injection we must nd a point in the network where block 2 has suf ciently small input impedance Again note that the injection source impedance Z does not affect the measurement In fact we Fig 939 Current injection using Thevenin in Fig 939 The network analyzer injection source is represented equivalent source can realize i by use of a Theveninequivalent source as illustrated Chapter 9 Controller Design by voltage source v z and output resistance RX A series capacitor C b is inserted to avoid disrupting the dc bias at the injection point 963 Measurement of unstable systems When the prototype feedback system is unstable we are even more eager to measure the loop gain ito nd out what went wrong But measurements cannot be made while the system oscillates We need to stabilize the system yet measure the original unstable loop gain It is possible to do this by recognizing that the injection source impedance Z does not in uence the measured loop gain 3 As illustrated in Fig 940 we can even add additional resistance R m effectively increasing the source impedance Zx The measured loop gain Tvs is unaffected Block I T 72 Bloc2 Rm Z Z 0 7 f L j 0 41 W Grow v0 m 00 22a GZW O 9 Hrs I39 Fig 940 Measurement of an unstable loop gain by voltage injection Adding series impedance generally lowers the loop gain of a system leading to a lower crossover frequency and a more positive phase margin Hence it is usually possible to add a resistor Rm that is suf ciently large to stabilize the system The gain Tvs Eq 9 67 continues to be approximately equal to the original unstable loop gain according to Eq 975 To avoid disturbing the dc bias conditions it may be necessary to bypass Rex with inductor L m If the inductance value is suf ciently large then it will not in uence the stability of the modi ed system 97 Summary of key points 1 Negative feedback causes the system output to closely follow the reference input according to the gain 1 H s The in uence on the output of disturbances and variation of gains in the forward path is reduced 2 The loop gain Ts is equal to the products of the gains in the forward and feedback paths The loop gain is a measure of how well the feedback system works a large loop gain leads to better regulation of the output The crossover frequency fc is the Chapter 9 Controller Design frequency at which the loop gain T has unity magnitude and is a measure of the bandwidth of the control system 3 The introduction of feedback causes the transfer functions from disturbances to the output to be multiplied by the factor l1Ts At frequencies where T is large in magnitude ie below the crossover frequency this factor is approximately equal to lTs Hence the in uence of lowfrequency disturbances on the output is reduced by a factor of lTs At frequencies where T is small in magnitude ie above the crossover frequency the factor is approximately equal to l The feedback loop then has no effect Closedloop disturbancetooutput transfer functions such as the linetooutput transfer function or the output impedance can easily be constructed using the algebraonthegraph method 4 Stability can be assessed using the phase margin test The phase of T is evaluated at the crossover frequency and the stability of the important closedloop quantities TlT and l1T is then deduced Inadequate phase margin leads to ringing and overshoot in the system transient response and peaking in the closedloop transfer functions 5 Compensators are added in the forward paths of feedback loops to shape the loop gain such that desired performance is obtained Lead compensators or PD controllers are added to improve the phase margin and extend the control system bandwidth PI controllers are used to increase the lowfrequency loop gain to improve the rejection of lowfrequency disturbances and reduce the steadystate error 6 Loop gains can be experimentally measured by use of voltage or current injection This approach avoids the problem of establishing the correct quiescent operating conditions in the system a common difficulty in systems having a large dc loop gain An injection point must be found where interstage loading is not significant Unstable loop gains can also be measured REFERENCES l B Kuo Automatic Control Systems New York PrenticeHall Inc 2 J D Azzo and C Houpis Linear Control System Analysis and Design Conventional and Modern New York McGrawHill Inc 1995 3 R D Middlebrook Measurement of Loop Gain in Feedback Systems International Journal of Electronics vol 38 no 4 pp 485512 1975 4 R D Middlebrook DesignOriented Analysis of Feedback Amplifiers Proceedings National Electronics Conference vol XX October 1964 pp 234238 Chapter 9 Controller Design PROBLEMS Derive both forms of Eq 925 The flyback converter system of Fig 941 contains a feedback loop for regulation of the main 64 3 output voltage V An auxiliary output produces voltage V The dc input voltage vg lies in the range 280V S vg S 380V The compensator network has transfer function Gcs G0 1 g where Gm 005 andf1 03127 400Hz a What is the steadystate value of the error voltage vet Explain your reasoning isolated 39i gate driver b Determine the steadystate value of the main output voltage V reference V 73V m We c Estimate the steadystate value of my the auxiliary output voltage V Fig 941 In the boost converter system of Fig 942 all elements are ideal The compensator has gain Gcs lOOOs Boost converter a Construct the Bode plot of the loop gain Ts magnitude and ra1ru g phase Label values of all 50w corner frequencies and Q Vg I C V R 3 factors as appropriate 48quot 58HF 129 b Determine the crossover 7 ffzookHz Hsi frequency and phase margin compensator c Construct the Bode diagram of the magnitude of l1T using the algebraonthegraph method Label values of all corner frequencies and Q factors as appropriate reference input Fig 942 d Construct the Bode diagram of the magnitude of the closedloop linetooutput transfer function Label values of all corner frequencies and Qfactors as appropriate A certain inverter system has the following loop gain S 16 s s s 1 F11 F21 F3 and the following openloop linetooutput transfer function e l G s7G0 W E s s 1E1E TS To Chapter 9 Controller Design where Ta 100 031 500 rads 032 1000 rads Dz 4000 rads 033 24000 rads Ggg 05 The gain of the feedback connection is Hs 0 l a Sketch the magnitude and phase asymptotes of the loop gain Ts Determine numerical values of the crossover frequency in Hz and phase margin in degrees b Construct the magnitude asymptotes of the closedloop linetooutput transfer function Label important features c Construct the magnitude asymptotes of the closedloop transfer function from the reference voltage to the output voltage Label important features The forward converter system of Fig 943 is constructed with the element values shown The quiescent value ofthe input voltage is Vg 380V The transformer has turns ratio n1 n3 45 The duty cycle produced by the pulsewidth modulator is restricted to the range 0 S dt S 05 Within this range dt follows the control voltage vct according to 1 W d0 7 VM with VM 3 volts a Determine the quiescent values of the duty cycle D the output voltage V and the control voltage V6 b Sketch a block diagram which models the small signal ac variations in the system and determine the transfer function of each bloc Fig 943 c Construct a Bode plot of the loop gain magnitude and phase What is the crossover frequency What is the phase margin d Construct the Bode plot of the closedloop linetooutput transfer function magnitude Label important features What is the gain at 120Hz At what frequency do disturbances in vg have the greatest in uence on the output voltage Wlt ltgt In the voltage regulator system of Fig 943 described in problem 95 the input voltage vgt contains a 120Hz variation of peak amplitude 10V 21 What is the amplitude of the resulting 120Hz variation in vt Chapter 9 Controller Design b Modify the compensator network such that the l20Hz output voltage variation has peak amplitude less than 25m V Your modification should leave the dc output voltage unchanged and should result in a crossover frequency no greater than lOkHz Design of a boost converter with current feedback and a PI compensator In some applications it is desired to control the converter terminal current waveform The boost converter system of Fig 944 contains a feedback loop which causes the converter input current igt to be proportional to a reference voltage vm The feedback connection is a current sense circuit having gain Hs 02 volts per ampere A conventional pulse width modulator circuit Fig 762 is employed having a sawtooth gignj g A waveform with peakpeak amplitude of 5 VM 3 volts The quiescent values of the inputs are Vg 120 volts me 2 volts All elements are ideal ref 21 Determine the quiescent values Fig 944 D V and Ig b Determine the smallsignal transfer function f S G s g A 30 c Sketch the magnitude and phase asymptotes of the uncompensated Gcs 1 loop gain d It is desired to obtain a loop gain magnitude of at least 35dB at l20Hz while maintaining a phase margin of at least 72 The crossover frequency should be no greater than f5 lO lOkHz Design a PI compensator which accomplishes this Sketch the magnitude and phase asymptotes of the resulting loop gain and label important features e For your design of part d sketch the magnitude of the closedloop transfer function 123 0616 Label important features Design of a buck regulator to meet closedloop output impedance specifications The buck converter with control system illustrated in Fig 945 is to be desigied to meet the following specifications The closedloop output L impedance should be less than 029 over the entire frequency range 020kHz To ensure that the transient response is vg wellbehaved the poles of the closed 100v loop transfer functions in the vicinity of the crossover frequency should have Qfactors no greater than unity The gate driver quiescent load current LOAD can vary from 5A to 50A and the above specifications must be met for every va ue of ILOAD in this range For simplicity you may assume that the Flg 945 lmH t 1 load C x Z 20mm V Rzmdjrvdl39 compensator VM4V Chapter 9 Controller Design input voltage vg does not vary The loop gain crossover frequencny may be chosen to be no greater than 10 or lOkHz You may also assume that all elements are ideal The pulsewidth modulator circuit obeys Eq 7132 21 What is the intended dc output voltage V Over what range does the effective load resistance R LO A D vary b Construct the magnitude asymptotes of the openloop output impedance ZWJS Over what range of frequencies is the output impedance specification not met Hence deduce how large the minimum loop gain Ts must be in magnitude such that the closedloop output impedance meets the specification Choose a suitable crossover frequency fc c Design a compensator network Gcs such that all specifications are met Additionally the dc loop gain Ts should be at least ZOdB Specify the following 1 Your choice for the transfer function Gcs ii The worstcase closedloop Q iii Bode plots of the loop gain Ts and the closedloop output impedance for load currents of 5A and 50A What effect does variation of RLOAD have on the closedloop behavior of your design d Design a circuit using resistors capacitors and an op amp to realize your compensator transfer function Gcs Design of a buckboost voltage regulator The buckboost converter of Fig 946 operates in the continuous conduction mode with the element values shown The nominal input voltage is Vg 48V and it is desired to regulate the output voltage at 715V Design the best compensator that you can which has high crossover frequency but no greater than 10 of the switching frequency large loop gain over the bandwidth of the feedback loop g and phase margin of at least 52 lt a Specify the required value of H Sketch Bode plots of the 522 uncompensated loop gain magnitude and phase as well as the magnitude and phase of your proposed compensator transfer function Gcs Label the Fig 946 important features of your plots VM 3V compensator b Construct Bode diagrams of the magnitude and phase of your compensated loop gain Ts and also of the magnitude of the quantities T 1 T and I 1 T c Discuss your design What prevents you from further increasing the crossover frequency How large is the loop gain at lZOHz Can you obtain more loop gain at lZOHz The loop gain of a certain feedback system is measured using voltage injection at a point in the forward path of the loop as illustrated in Fig 947a The data in Fig 947b is obtained What is Ts Specify Ts in factored polezero form and give numerical values for all important features Over What range of frequencies does the measurement give valid results Chapter 9 Controller Design 039 7 v1 M TC 5 J Gr0 s oyu My 1 10kQ ZnF b 60 H TV H 40dB 20dB OdB rZOdB 4 TV 90 0 90 180 100HZ lkHZ 10kHZ 100kHZ IMHZ f Fig 947 Lecture 8 ECEN 4517 5517 Experiment 4 inverter system 12 VDC HVDC 120 200 VDC DC DC DC AC converter inverter AC load Battery L Isolated H bridge vact 120 Vrms 39l39 yback 60 HZ dt dt v V Feedback ref Digital controller controller Sfepjup dG39dC 00 Verter DCAC inverter Hbridge Wth Isolaton fyback Feedback controller to regulate H VDC ECEN 4517 1 Due dates Right now Prelab assignment for Exp 4 Part 2 one from every student Due within five minutes of beginning of lecture This week in lab March 46 Experiment 3 report due one per group Next week in lecture March 11 Preliminary project proposal due one from every group The following week in lecture March 18 Midterm examination ECEN 4517 2 Exp 4 Part 3 Hbridge inverter off grid VHVDC 1R3 101 1R3 101 AC load 120 Vrms E I 1r 3 lac l T l 1 W 1 Filtering of ac output not explicitly shown IR 3101 halfbridge modules with integrated drivers Exp 4 Part 3 offgrid Inverter Gridtied control iacw Eignuornes tgate modified sinewave inverter Offgrid control VaCU Demonstrate PWM inverter extra credit ECEN4517 3 Modified SineWave Inverter vacltrgt vacu has a rectangular VHVDC waveform Inverter transistors T2 gt switch at 60 Hz T 1667 msec lt DT2 gt VHVDC RMS value of Vact is Choose VHVDC larger than desired V5103 S T i 2 h Can regulate value of Vac RMS T V000 dt D VHVDC VC RMS by variation of D a Waveform is highly nonsinusoidal with significant harmonics ECEN 4517 4 PWM Inverter Average vact has a Vac sinusoidal waveform u Inverter transistors I H SWitCh at frequency w a W 7 w substantially higher than 60 Hz Choose VHVDC larger than desired lac peak Can regulate waveshape and value of VaC RMS by variation of dt Can achieve sinusoidal waveform with negligible harmonics Higher switching frequency leads to more switching loss and need to filter highfrequency switching harmonics and common mode currents ECEN 4517 5 The IR3101 halfbridge module Module contains power MOSFET and diodes gate drivers bootstrap power supply MOSFET ratings 450 V 18 A Use VCC 12 V Connect 100 pF 25 V bootstrap capacitor between VB and V0 Logic signals Hin and Lin control upper and lower MOSFET drivers These signals must not both be high at the same time Need deadtime of at least 200 nsec ECEN4517 lt HII 22 lt 39l LJ39ILAJNH m m o VB VDD I I 8 11 l H 1c Driver 779 v0 l l L 7 fl l 6i COM Controlling the inverter MSP430 generates logic signals to control the four gate drivers Control MSP430 Timer B VHVDC 12V Vref 39 Timer B Y I39 39 t n to yback 0U goa ad U 5 ref 8 d controller MSP430 inverter duty cycle to obtain V5m 120 V rms ECEN 4517 7 Gate drive timing Download new zip file on Exp 4 page deadtime Insert your code in mainc as usual The ADCs and DACs function as before Interrupts are used to program Timer B to generate gate drive T 1667 msec signals on P41 to P44 Timer B counts from zero to 8MHz46OHz 33333 Event times between 0 and 33333 correspond to one complete ac output period of 160 1667 msec The switching times are set by entries in the EventTimes vector ECEN 4517 8 Project Design and demonstrate components of a solar power system Each team should build a converter that includes PWM and feedback Several teams will collaborate to produce multiple converters that fit together in a single cart Demonstrate projects at ECE Expo at end of semester Prelab assignment due next week Research your project and submit short initial proposal Some ideas follow ECEN 4517 9 DC motor power flow power flow Variablespeed rive ACDC lowharmonic recti er singlephase or 3phase 120Vrms 60Hz Utility AC line 0739 3phase windpowered ator Feec mck Feec mck controller controller Solarpanel 123915V Dc DCDC B DCDC t atte V 1 7y converter DCAC 120Vrms g tracker Vb Step up Inverter Von ogz load V3 39439 M VOC Feec mck peak power controller VgQ point power flow 13 I Q I 3 SC Audio H ighfrequency Switching DCAC Ampli er resonant DCAC inverter Fluorescent amp I ballast Basic non isolated converters Buck converter Q1 ram JJL I39m Vg D1 2 C we Boost converter it L D MD VVg MD D 39 Step down Requires oating gate drive MD11 D 39 Stepup 39 Ground referenced gate drive Basic non isolated converters Buck boost converter Q1 DI MD Dl D JLL m n Step up or down T averting Vg L C R V Requires oating gate drive H bridge converter MD 2 2D 1 39 Step down Bipolar output Requires oating gate drives Basic non isolated converters SEPIC MD Dl D Step up or down v Noninverting Ground referenced Vg L 2 Q1 2 T gate drive Cuk converter L1 53 p I Q I u a MD D1 D Step up or down Vg Q1 JEDl C2 2 R i v O Inverting 39 Ground referenced gate drive HQ O Buck derived isolated converters Forward converter O MD D n3n1 39 Maximum duty cycle is limited 39 Ground referenced gate drive MD nD Requires current mode control 39 Ground referenced gate drive Others full bridge half bridge two transistor forward More isolated converters Flyback converter MD nDl D 39 Ground referenced gate drive 39 Based on buck boost MD nl D 39 Alternating gate drive current mode control 39 Ground referenced gate drive V lt More isolated converters Isolated SEPIC MD nDl D Ground referenced v gate drive Based on SEPIC Isolated Cuk L1 C C MD nDl D V Q 1 39 1 v 39 Ground referenced g gate drive 7 0 Based on Cuk l n Low harmonic rectifiers Can employ boost flyback SEPIC Cuk and other converters having boost capability to control and regulate ac input current to follow ac voltage BOOSZ example Boost converter igt it L VI J D1 vact e I vgt Q1 C Vl R A Vvaa Iiga dt l Controller Controller varies dc Controller approaches such that l I Z V I R 39 Average current control e R emulgted resistance 39 Critical conduction mode control e 39 Current mode control 39 Discontinuous conduction mode

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