New User Special Price Expires in

Let's log you in.

Sign in with Facebook


Don't have a StudySoup account? Create one here!


Create a StudySoup account

Be part of our community, it's free to join!

Sign up with Facebook


Create your account
By creating an account you agree to StudySoup's terms and conditions and privacy policy

Already have a StudySoup account? Login here

Modern Computer Architecture

by: Roman McCullough

Modern Computer Architecture CMPSCI 635

Roman McCullough
GPA 3.57


Almost Ready


These notes were just uploaded, and will be ready to view shortly.

Purchase these notes here, or revisit this page.

Either way, we'll remind you when they're ready :)

Preview These Notes for FREE

Get a free preview of these Notes, just enter your email below.

Unlock Preview
Unlock Preview

Preview these materials now for free

Why put in your email? Get access to more of this material and other relevant free materials for your school

View Preview

About this Document

Class Notes
25 ?




Popular in Course

Popular in ComputerScienence

This 10 page Class Notes was uploaded by Roman McCullough on Friday October 30, 2015. The Class Notes belongs to CMPSCI 635 at University of Massachusetts taught by Staff in Fall. Since its upload, it has received 12 views. For similar materials see /class/232279/cmpsci-635-university-of-massachusetts in ComputerScienence at University of Massachusetts.


Reviews for Modern Computer Architecture


Report this Material


What is Karma?


Karma is the currency of StudySoup.

You can buy or earn more Karma at anytime and redeem it for class notes, study guides, flashcards, and more!

Date Created: 10/30/15
Cache Basics CMPSCI 635 Modern Computer Architecture Univ ofMass Amherst Lecture Outline l A briefhistory of computer memories I The memory hierarchy l Cache Basics I Motivation l Cache metrics l Cache implementation I Set associativity of cache Early Memories l Vacuum tubes relays l Cathode ray tubes l Acoustical delay lines I Magnetic drums l Magnetic cores I Punch cards I Openereel tape Modern Memory l Semiconductor based RAM l Magnetic disk I Magnetic or optical tape l Optical disk CDs DVDs I Magnetoeoptical disk I Flash memories Memory Technology I Memory technology is mature I Any new technology has a lot of catching up to do to be competitive I New memory technologies have become much more difficult to introduce I Memory needs are currently driven by entertainment industry DRAM vs SRAM I Dynamic RAM DRAM is implemented using capacitors to store charge I DRAM must be periodically refreshed due to capacitor leakage I SRAM uses ip ops that do not need refreshing thus SRAM is faster I SRAM is more complex and expensive DRAM vs SRAM SRAM DRAM 5 SELECT SELECT B E PLATE DRAM in Detail plailu r 1 m ll H L Memory Hierarchy We use a memory hierarchy so that we can get varying amounts of cost per performance in a system A m sasaanap nun Jed Isao Performance increases The Performance Gap myth CPU Memon Performance log scale 193 Time years 2005 The Performance Gap truth I CPU performance cannot increase exponentially with respect to memory I Access time to main memory is typically N100 cycles I This gap is very signi cant I Opening gaps are between on and off chip memory and registers and L1 cache Caches I Probabilistic attempt to keep useful data closer to the CPU I Important because of the performance distance between CPU and main memory I Higher in the memory hierarchy than main memory so it is faster and more costly I Operates on the assumption that memory accesses exhibit omlz39g Basic Properties of Cache l Inclusion copies of a value exist in all levels below I Coherence all copies are the same I Locality programs access a limited portion of the address space during any window in time I May not strictly hold at all times Cache Parameters l Access time CPU to memory I Size bytes l Cost per unit byte l Transfer bandwidth sustained l Unit of transfer aka line size bytes moved I Set associativity Hit ratio l Probability that an access hits at a given level I A hit is an access to something already in cache I Miss ratio 1 iHit ratio l Access frequency is the product of the hit ratio for a given level and the miss ratios of all levels above it I Cache performance is not completely dependent on hit ratio Average Access Time I Sum of access frequencies for all levels multiplied by their corresponding access times I Assumes no bypass l Assumes that data remdes m the lowest level data is always present I Good design depends on simulation Average Access Time Average Memory Access T1me L1 H1t hrne L1 M155 rate L1 M155 penalty L1 M155 penalty L2 H1t hrne L2 M155 rate L2 M155 penalty L2 M155 penalty L3 H1t hrne L3 M155 rate L3 M155 penalty Example In 1000 memory references there are 40 misses in L1 and 20 misses in L2 Assume all are reads with no bypass L1 Hit time 1 cycle L2 Hit time 10 cycles Miss penalty 100 cycles Xhat is the average memory access time Answer L1 Local m155 rate L1 Local m155e5 Total references 401000 4 L2 Local m155 rate L2 Local m155e5 L1 Local m155e5 2040 50 Average Memory Access Time L1 H1tT1me L1 M155 Rate L2 H1tT1me L2 M155 Rate L2 M155 Penalty 1 4 10 50 100 34 clock cycles Reducing Avg Access Time I Make memory faster costly l Reduce cache miss rate I Try to exploit more om29 l Change cache parameters I OpthlZe code I Make cache bigger I More elaborate schemes later Programmed Transfer I We explicitly specify transfers from main to secondary memory I We can also explicitly specify transfers from registers to memory I No language exisE to provide information for better management of cache l Compilers can be used to optimize for the cache Linguistic Issues l Languages restrict compiler context I Higher level constructs could enable scheduling of more trans e l Compiler might reorder accesses to improve locality l Currently done for loops between functions is hard irregular structures are even harder Types of Locality l Temporal recently accessed data tends to be accessed again in the near future I Spatial data accesses tend to be close together I Sequential instructions also some data tend to be accessed in consecutive order Spatial Locality l Widely found in codes I Array accesses l Instruction streams l Spatial locality implies temporal locality but not v1ce versa l Exploited by larger line size I Similar to sequential locality Temporal Locality l Tends to hold for many codes I Arrays 111 loops l Linked lists I Local variables constants l Exploited by smaller line size I Does NOT imply spatial locality Sequential Locality l Especially true of instructions I Subset of spatial locality l Locality differences between data and instructions argue for split instruction separate from data caches Distinguishing Localities l Spatial hit A hit that occurs on a word already in cache that has not been previously accessed l Temporal hit A hit that occurs on a word already in cache that Q been previously accesse l Eviction erases history with respect to these de nitions Lines in Cache l A line stores a memory block which is comprised of contiguous words I Increased line sizes increase the probability that contiguous data is moved into the cache on a miss I Increased number oflines decrease the probability that a speci c line is evicted Basic Cache Structure l Comprised of lines which store contiguous blocks l Each line has a tag high order bits to keep track of which memory block is present I Position in cache is determined by low order bits except in fully associative Fully Associative Cache Fully Associative KL I Pros I Any memory block can go anywhere in cache l Cache can be fully utilized I High hit rate does not suffer con ict misses l Cons I Requires one comparator per line impractical I Fan in delays for compare and access I Replacement algorithms become impractical Direct Mapped tag ndEX ufst data out Direct Mapped SL I Pros I Only one comparator I Direct fetch and test of tag I Fast access I Cons I Low utilization I Many con ict misses I Lower hit ratio Cache Associativity I Cache can be divided into sets I K ways divide cache into sets with K lines per set I Number of sets is S I LK where L is number of lines in the cache I A block may go anywhere its associated set I Associativity is directly related to con ict misses 4way Set Associative tag ndEX ufst K way Associative I An effective balance between the speed of direct mapped and the performance of fully assoc I K wide comparator almost as fast and cheap as direct mapped I Hit ratio is almost like fully associative I Up to K blocks with the same mapping may be in cache at once without conflicting Example I 4way set associative cache with 16K 4word lines 1 word 4 bytes l 256K byte capacity I 4K sets I 4 ways 4 comparators l Each memory address can map to 4 locations in cache Next Lecture I More on reasons for miss I Cache traces l Running an example on I Generaung I Analyzrng l Statistical correctness of


Buy Material

Are you sure you want to buy this material for

25 Karma

Buy Material

BOOM! Enjoy Your Free Notes!

We've added these Notes to your profile, click here to view them now.


You're already Subscribed!

Looks like you've already subscribed to StudySoup, you won't need to purchase another subscription to get this material. To access this material simply click 'View Full Document'

Why people love StudySoup

Steve Martinelli UC Los Angeles

"There's no way I would have passed my Organic Chemistry class this semester without the notes and study guides I got from StudySoup."

Kyle Maynard Purdue

"When you're taking detailed notes and trying to help everyone else out in the class, it really helps you learn and understand the I made $280 on my first study guide!"

Jim McGreen Ohio University

"Knowing I can count on the Elite Notetaker in my class allows me to focus on what the professor is saying instead of just scribbling notes the whole time and falling behind."

Parker Thompson 500 Startups

"It's a great way for students to improve their educational experience and it seemed like a product that everybody wants, so all the people participating are winning."

Become an Elite Notetaker and start selling your notes online!

Refund Policy


All subscriptions to StudySoup are paid in full at the time of subscribing. To change your credit card information or to cancel your subscription, go to "Edit Settings". All credit card information will be available there. If you should decide to cancel your subscription, it will continue to be valid until the next payment period, as all payments for the current period were made in advance. For special circumstances, please email


StudySoup has more than 1 million course-specific study resources to help students study smarter. If you’re having trouble finding what you’re looking for, our customer support team can help you find what you need! Feel free to contact them here:

Recurring Subscriptions: If you have canceled your recurring subscription on the day of renewal and have not downloaded any documents, you may request a refund by submitting an email to

Satisfaction Guarantee: If you’re not satisfied with your subscription, you can contact us for further help. Contact must be made within 3 business days of your subscription purchase and your refund request will be subject for review.

Please Note: Refunds can never be provided more than 30 days after the initial purchase date regardless of your activity on the site.