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VLSI Circuit Design

by: Mrs. Damaris Hyatt

VLSI Circuit Design CSE 60462

Mrs. Damaris Hyatt
GPA 3.79

Peter Kogge

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Peter Kogge
Class Notes
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This 0 page Class Notes was uploaded by Mrs. Damaris Hyatt on Sunday November 1, 2015. The Class Notes belongs to CSE 60462 at University of Notre Dame taught by Peter Kogge in Fall. Since its upload, it has received 65 views. For similar materials see /class/232741/cse-60462-university-of-notre-dame in Computer Science and Engineering at University of Notre Dame.

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Date Created: 11/01/15
Introduction to CMOS VLSI Design Lecture 43 Verilog Continued Lecture by Peter Kogge Fall 2009 University of Notre Dame Using some slides by Jay Brockman Notre Dame 2008 and David Harris Harvey Mudd College httpwwwcmosvlsicomcoursematerialshtml CMOS VLSI Design Slide 1 Registers CI Verilog registers much like C variables Once assigned a value they keep it Until another value is assigned CI Defined by reg ltmsbgtltlsbgt ltregnamegt If no then default size is 1 bit Initial value is x CI Typically assignments tied into events like clocks CMOS VLSI Design Slide 2 DUB Timesensitive Assignments assign statements are continuous Written once executed continuously Changes in left hand side immediately reflected in righthand signal Sometime we want to execute some statements procedurally like a C program ie Start statements at some point in time And then in some order Especially important for controlling registers Single pass behavior is executed only once Cyclic behavior is triggered whenever something happens CMOS VLSI Design Slide 3 Program Blocks Often more than 1 statement needs to be executed in a time sensitive assignment Such statements grouped into blocks ltstatementgt ltstatementgt begin ltstatement blockgt end All statements in block are executed in order ie one at a time top to bottom Assignments within block are said to be blocking assignments Next one cannot start until last completes including updates fork ltstatement blockgt join All statements in block are executed in garallel ie in any order CMOS VLSI Design Slide 4 Procedural Assignments ltregnamegt ltexpressiongt CI Note no quotassignquot CI When statement executed register takes on value from expression Actually an update event is scheduled CI Update event is done BEFORE next statement in program order CMOS VLSI Design Slide 5 A LevelSensitive D Latch module Dlatchinput D CLK output Q Q CLK D Q endmodule CMOS VLSI Design Slide 6 A D Latch with 3 Reset module DlatchwResetinput D CLK Reset output Q Q Reset O CLK D Q endmodule CMOS VLSI Design Slide 7 DUB Single Pass Beha vior Execute only at specific time ie time0 Typically used by test benches for startup Typically uses procedural assignments initial ltstatementgt Example initial begin 0 10 Reset 5 Reset 0 end What is the waveform Reset l CMOS VLSI Design Slide 8 Cyclic Beha vior Statement to be executed at specific times Eg at clock pulses always ltsensitivity listgt ltstatementgt is optional event control operator ltsensitivityIistgt is list of signal names means use all nets amp variables read by procedure s statements Whenever any one of signals in sensitivitylist changes ltstatementgt is executed And only then Kind of change is immaterial unless signal name preceded by posedge execute only on a O to 1 negedge execute only on a 1 to O CMOS VLSI Design Slide 9 Example A 4 bit Shift Register E D C B A gt r r clktrtrtrm reset I I I Module shiftreginput E clk reset output D C B A reg A B C D note these output port defined to be regs always posedge clk or posedge reset begin if reset begin AOBOCODOEO end else begin gt r What happens if we reorder these UOUJIZD end end CMOS VLSI Design Slide 10 Nonblocking Assignments ltregnamegt lt ltexpressiongt CI Lefthand side MUST be a register CI Order of such assignments within block is immaterial They ALL HAPPEN AT ONCE Actually all updates from lt queued at same time And not executed till no earlier events CI Better match to real circuits always posedge clock begin regl lt2 exprl Allexpress10ns evaluated reg2 lt exprz M then all assignments happen end W CMOS VLSI Design Slide 11 Repeat Shift Register Example E D C B A gt r r r CHEVTVIVIVT Module shiftreginput EWNote simpli ed syntax output re C B A always posedge clk or posedge reset begin if reset begin AltOBltOCltODltOEltO end else begin Alt B B lt c NOW What happens C lt2 13 if we reorder these D lt E end end CMOS VLSI Design Slide 12 Example Clock Generation Reg clk always begin Clk lt 1 H 5 Alternatively Clk lt2 0 5dkltm 5 end CMOS VLSI Design Slide 13 Memory reg ltWordsizegt ltmemorynamegt ltmemsizegtltmemsizegt CI ltWordsizegt is ltmsbgtltlsbgt CI ltmemsizegt is ltlowindexgtlthighindexgt CI Example define register darray as 2D array of 16 bit words reg 150 darray 0127O127 CI Selecting a word from an array Assume abyte is an 8 bit set of wires abyte darray6432125 takes 8 bits from 32ncl column of 64th row CMOS VLSI Design Slide 14 Other Verilog Constructs CI Comments Single line Block CI Identifiers start with letter or follow by letters digits or case sensitive CI Parameters are runtime constants defined within a module Parameter ltnamegt ltvaluegt ltnamegt ltvaluegt CMOS VLSI Design Slide 15 More See Quick Reference Card CI Builtin modules and or nand nor xorxnor One output first argument One or more inputs rest oft arguments CI di splay statement verilog eqvt of printf display ltformat stringgt text ltist of varnamesgt ltformatcodegt in text says how to format next var in list time is current time executed as any other statement in a block references variable values AS THEY ARE THEN see httpWWWhpccccssotonacukhpcitoolsVlogrofpdf CMOS VLSI Design Slide 16 Case Statement case ltexpressiongt ltcaseitemgt ltcaseitemstatementgt default ltcaseitemstatementgt endcase CI ltcaseitemgt is a constant that is matched against that from the ltexpressiongt If match then do the ltcaseitemstatementgt And exit case statement after completion If not try next case CI default is optional for no matches CMOS VLSI Design Slide 17 If Statement if ltexpressiongt ltthenstatementgt else ltelsestatementgt end CI else is optional CI nesting permitted as in else if CMOS VLSI Design Slide 18 F or Statement for ltinitialassignmentgt ltConditionexpressiongt ltupdatestatementgt begin ltloopstatementsgt end CI ltinitialassignmentgt and ltupdatestatementgt are some form of assignment CI All iterations of ltloopstatementsgt conceptually done AT SAME TIME CMOS VLSI Design Slide 19 Other Loops repeat lteXpreSSi0 gt while ltconditiongt begin begin ltOOPSl 6i1 19 7719 71 Sgt ltloopstatementsgt end end wait ltexpressi0ngt ltstatementgt CI All iterations of ltloopstatementsgt conceptually done AT SAME TIME CMOS VLSI Design Slide 20 Alternative Module Port Declaration Style module ltmodulenamegtltvariablelistgt input ltsubset of variable istgt Give 10 here output ltsubset of variable istgt rather than in module ltdefinitions of internal signalsgt ltassignments to internal signals amp output portsgt endmodule CMOS VLSI Design Slide 21 Timescale CI timescale lttimeunitgtlttimeprecisiongt lttimeunitgt and lttimeprecisiongt of form ltnumbergt ltspacegt ltunitgt With ltunitgt as 8 ms us ns ps fs From this point on for delays 1 time unit lttimeunitgt for precision of internal time calculations use lttimeprecisiongt CMOS VLSI Design Slide 22 Module Ins tan tia tion Options CI Previously ltmoduletypegt ltinstancenamegt ltlistofsignaInamesgt CI In place of ltlistofsignaInamesgt use list of ltportnamegtltnet namegt CI Optionally add ltparameterassignmentlistgt after ltmoduletypegt Associate values with parameters within module de nMon Overwrites parameter ltnamegt valuegt inside de nMon CMOS VLSI Design Slide 23 Typical Design El File with list of module definitions El Typically first one is a testbench Glues together other pieces in a way that allows appropriate operation to be demonstrated Includes initial code to start up amp reset system Includes code to generate clocks amp other common control signals module TestBench no ports reg ltin list 39 all input ports to DUT wire ltout listgt s from DUT module DeviceUnderTestinput ltin listgt output ltoutlistgt endmodule initial begin code to change values of regs in ltin listgt end endmodule CMOS VLSI Design Slide 24 Finite State Machines Inputs Combinational pgtms Logic I Next State Clock State Reglster module FSMinput clock Inl mInn output 01 mOm reg state nextstate parameter m statei bxxxx always posedge clock begin state lt nextstate case state statei begin nextstateltstatej Ok lt m end CMOS VLSI Design Slide 25


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