VLSI Circuit Design
VLSI Circuit Design CSE 40462
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This 0 page Class Notes was uploaded by Mrs. Damaris Hyatt on Sunday November 1, 2015. The Class Notes belongs to CSE 40462 at University of Notre Dame taught by Peter Kogge in Fall. Since its upload, it has received 22 views. For similar materials see /class/232738/cse-40462-university-of-notre-dame in Computer Science and Engineering at University of Notre Dame.
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Date Created: 11/01/15
Introduction to CMOS VLSI Design Lecture 73 Logical Effort Lecture by Jay Brockman University of Notre Dame Fall 2008 Modified by Peter Kogge Fall 2009 Based on lecture slides by David Harris Harvey Mudd College httpwwwcmosvlsicomcoursematerialshtm Outline El Introduction El Delay in a Logic Gate El Multistage Logic Networks El Choosing the Best Number of Stages El Example El Summary 6 Logical Effort Slide1 5 Logical Effort CMOS Vle Design Slide 2 Re view Normalized Delay El Assume gate G1 is driving some of other gates G2 El Normalized Delay gate delay relative to Fanout number of such gates being driven Delay of a gate G1 parasitic delay effort delay Parasitic Delay delay if gate G1 is driving m Function of diffusion capacitance in gate Delay seen when G1 drives no other circuits Effort Delay delay due to capacitance of circuits driven by G function of the number of gates of type G2 being driven the input capacitance presented by a G2 gate EU I CMOS Vle Design fanout of 1 inverter drives one inverter with no parasitic capacitance of value 3RC R eqvt resistance of unit nmos transistor in saturation C eqvt capacitance of gate of unit nmos transistor CMOS Vle Design Normalized Parasitic Delay El Inverter has 3 units of diffusion capacitance 2 from pmos 1 from nmos El Parasitic delay of inverter is T 3RC El Normalized Parasitic Delay of a gate is p3RC p is parasitic delay from Elmore model El To convert to psec multiply by parasitic delay of an inverter in chosen technology CMOS Vle Design Normailzed Effort Delay El h fanout or electrical effort property of circuit equivalentG1 gates being driven by G1 ComCin where Cout total load capacitance presented by G2 inputs Cin input capacitance G1 presents on its sources When gates G2 those being driven are type G1 then h of copies El g logical effort to drive a gate of type G2 effort required to drive one gate vs perfect inverter how many eqvt invertors one G2 gate looks like Input cap of G2 gateInput cap of inverter Input cap of G2 gate3 El Inverter has logical effort 1 CMOS Vle Design Summary Rise Time of loads Input Cap per load R Fall Time is similar 911M y hCin of G2s Logical effort of type G2 delay RCdiH hRCin relativedelay RCdi Hr hRCin gtllt pGl h ng 3RC CMOS Vle Design Common Gates gL0gical Effort pNorrnalized Parasitic CMOS Vle Design ninput NAND Gates l n 3nC l sec n C Rn Rn Rn a WI 1 10 yo yo 3nC ninput NAND gate parasitic delay parasitic delay NZ2 52NRC SLOW l l l ll CMOS VLSI Design Scaling Transistors El What if all transistors in gate G got Wider by k Denote as gate Gk El Parasitic delay of Gk delay of unloaded gate Diffusion capacitance increases by k Resistance decreases by k Result No change El Effort delay ratio of load cap to input cap f drive same of Gk as before no change f drive same of G1 as before decrease by 1k El Result fanout to type G1 gates increases by k CMOS VLSI Design MultiStage Logic Networks Relative Input Capacitance a sed on gate design amp transistor size g11 g253 9343 941 1 h1 x10 h2 yX h3 zy h 202 m Multistage logic network gi logical effort to drive a gate of type i input capcap of inverter h1 fanout of gates of type i load capinput cap Question ifdelay thru one gate is p hg can we write delay thru multistage as some PHG CMOS VLSI Design Overall Delay I3 delay Zdelayi where delayi delay thru l th stage of logic delayi Pi hi 9i pi function only of gate type at stage i gi function only of gate type at stage i input capcap of inverter hi depends on gates at stage i1 total load on gate iinput cap of gate delay 2pi hi 9i 2pi 2hi 9i Can we write Zhi gi as some HG I3 DU CMOS VLSI Design De nitions El Path Logical Effort G H g El Path Electrical Effort H Compaq Paths that Branch Branch point El No Consider paths that branch El Individual terms 91 92 1 inverters 90 h1 151556 E El Patthfort h2 90156 El Path Terms 90 G I39lgi1x1 1 l H ComCin 905 18 m GH 18 gi1 9553 9543 941 h1xl10 h2ylx h3zly hA 20z F g1h1gzh2 36 2GH GH Question Can we write F GH 5 Logical Effort CMOS Vle Design Slide 13 5 Logical Effort CMOS Vle Design Slide 14 Branching Effort Multls ta ge Delays El Introduce Branching Effort El Path Delay D Edi 2 BF P Accounts for branching between stages in path El Path Parasitic Delay b ConpathCoffpath PZpi El Path Effort Dela Conpath N t y DF B b equot H 1 HQ BH El Now we compute the Path Effort F GBH 5 Logical Effort CMOS Vle Design Slide 15 5 Logical Effort CMOS Vle Design Slide 16 Designing Fast Circuits D 2d DF P El Delay is smallest when each stage bears same effort fA Zg39hizFLN I El Thus minimum delay of N stage path is DNFtP El This is a key result of logical effort To find fastest possible delay Doesn t require calculating gate sizes 5 Logical Effort CMOS Vle Design Slide 17 Gate Sizes El How wide should the gates be for least delay fghgcc7 C Cm g1 Aouf El Working backward apply capacitance transformation to find input capacitance of each gate given load it drives El Check work by verifying input cap spec is met 5 Logical Effort CMOS Vle Design Slide 18 Example 3stage path El Select gate sizes x and y for least delay from A to B 5 Logical Effort CMOS Vle Design Slide 19 Example 3stage path Logical Effort Electrical Effort Branching Effort Path Effort Best Stage Effort Parasitic Delay Delay DUNNIon 5 Logical Effort CMOS Vle Design Slide 20 Example 3stage path Wu w 41 3 I Logical Effort G 435353 10027 Electrical Effort H inggih39 Branching Effort B 3 2 6 2 Path Effort F GBH 125 B t St 2 2 es I age Effort f F 5 WM Thug ParasItIc Delay P 2 3 2 7 TM Delay D 35 7 22 44 F051 D 96 37 5 Logical Effort CMOS Vle Design Slide 21 Example 3stage path El Work backward for sizes y x 5 Logical Effort CMOS Vle Design Slide 22 Example 3stage path El WoElgzac war or sizes y453 15 H x 152 53 10 W sac 17 3 N 5 Logical Effort CMOS Vle Design Slide 23 U EU I I Choosing Best of Stages Goal estimate delay amp choose transistor sizes Many different topologies combinations of gate types that implement same function We know in general NANDs betterthan NORs Gates with fewer inputs better than more inputs Typical shortcut estimate delay by of stages Assuming constant gate delayquot and thus shorter paths are faster THIS IS NOT ALWAYS TRUE Adding inverters at end with increasing sizes can speed up circuit esp when high load CMOS Vle Design Example p 178 El How many stages should a path use Minimizing number of stages is not always fastest El Example drive 64bit datapath with unit inverter lnmalDrNer D DatapathLDad an 64 ea 64 I I I I 1 2 a 4 N f D 5 Logical Effort CMOS Vle Design Slide 25 Best Number of Stages p 178 El How many stages should a path use Minimizing number of stages is not always fastest El Example drive 64bit datapath with unit inverter lnmaanver Y Y D NF1 N P V v N641 N N atapathmad 1164 E64 D 65 5 Logical Effort CMOS Vle Design Slide 26 General Derivation El Consider adding inverters to end of n1 stage path How many give least delay N 7 n1 Extralnverters Logic Block L quot1 mslages goo gt1 DZNFN ZpiNnlpim PatthfortF 1v i1 6 D F FLN 0 Ntotal stages wiLhNn1 pmquot Inverters 0 do not change logical effort L El Define best stage effort p F do addpmsmc delay pm p1 1np 0 5 Logical Effort CMOS Vle Design Slide 27 Best Stage Effort El pm p1 1np O has no closedform solution El Neglecting parasitics pinV 0 we find p 2718 e El For pinV 1 solve numerically for p 359 CI Again these p values are best logical effort per stage when you have logp F stages 5 Logical Effort CMOS Vle Design Slide 28 Sensitivity Analysis El How sensitive is delay to using exactly the best number of stages 3 g 15L M 125 12 115 E 1D 9 p44 U W AjDQ tuales optimalN 24 lt p lt 6 gives delay within 15 of optimal We can be sloppy I like p 4 I on Logical Effort CMOS Vle Design Slide 29 1st Example Revisited El Ben Bitdiddle is the memory designer forthe Motoroil 68W86 an embedded automotive processor 39 u design the decoder for a registerfile M I El Decoder specifications aiming 16 word registerfile Each word is 32 bits wide Each bit presents load mitsized transistors True and complementary address inputs A3O Each input may drive 10 unitsized transistors El Ben needs to decide How many stages to use How large should each gate be How fast can decoder operate Wing iapnaaa al v 5 Logical Effort CMOS Vle Design Slide 30 What Does This Mean 16 word register file There are 16 separate row lines Branching factor of 16 at end Each word is 32 bits wide amp each bit presents load of 3 unitsized transistors I I The load on each row line is 323 True and complementary address inputs A30 Any address input needed for only 8 row lines El Each input may drive 10 unitsized transistors Total input capacitance from 1st stage gates on inputs 10 I 5 Logical Effort CMOS Vle Design Slide 31 Number of Stages El Decoder effort is mainly electrical and branching Electrical Effort H Branching Effort B Cl If we neglect logical effort assume G 1 Path Effort F Number of Stages N 5 Logical Effort CMOS Vle Design Slide 32 Number of Stages El Decoder effort is mainly electrical and branching Electrical Effort H 323 10 96 Branching Effort B 8 El If we neglect logical effort assume G 1 3 Stage Gate Sizes amp Delay in 7quot WV Logical Effort G 1 63 1 2 Path Effort F GBH 154 Stage Effort f F 3 536 PathDeIay D3f141221 Gate sizes 2 961536 18 y 182536 67 Path Effort F GBH 768 NW mm AM WT Number of Stages N log4F 31 7 gimp El Try a 3stage design iiwmm 5 Logical Effort CMOS Vle Design Slide 33 5 Logical Effort CMOS Vle Design Slide 34 Comparison Re VleW of De nitions El Compare many alternatives with a spreadsheet Design N G P D NAND4INV 2 2 5 298 NAND2NOR2 2 209 4 301 INVNAND4INV 3 2 6 221 NAND4INVINVINV 4 2 7 211 NAND2NOR2INVINV 4 209 6 205 NAND2INVNAND2INV 4 169 6 197 INVNAND2INVNAND2INV 5 169 7 204 NAND2INVNAND2INVINVINV 6 169 8 216 5 Logical Effort CMOS Vle Design Slide 35 Term Stage Path number of stages 1 N logical effort g G H g electrical effort h 20 H 003 branching effort kW 31 h effort f gh F GBH effort delay f DF Z parasitic delay p P ZR delay dfp DZdDFP 5 Logical Effort CMOS Vle Design Slide 36 Method of Logical Effort 1 Compute path effort 2 Estimate best number of stages F GBH 3 Sketch path with N stages N1 g4F 4 Estimate least delay L 5 Determine best stage effort D NFN P fFt 6 Find gate sizes C glam m f 5 Logical Effort CMOS Vle Design Slide 37 Limits of Logical Effort El Chicken and egg problem Need path to compute G But don t know number of stages without G Simplistic delay model Neglects input rise time effects El Interconnect Iteration required in designs with wire El Maximum speed only I Not minimum areapower for constrained delay 5 Logical Effort CMOS Vle Design Slide 38 Summary El Logical effort is useful forthinking of delay in circuits Numeric logical effort characterizes gates NAN Ds are faster than NORs in CMOS Paths are fastest when effort delays are 4 Path delay is weakly sensitive to stages sizes But using fewer stages doesn t mean faster paths Delay of path is about Iog4F FO4 inverter delays Inverters and NAN D2 best for driving large caps El Provides language for discussing fast circuits But requires practice to master 5 Logical Effort CMOS Vle Design Slide 39
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