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# VLSI Circuit Design CSE 60462

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This 0 page Class Notes was uploaded by Mrs. Damaris Hyatt on Sunday November 1, 2015. The Class Notes belongs to CSE 60462 at University of Notre Dame taught by Peter Kogge in Fall. Since its upload, it has received 18 views. For similar materials see /class/232741/cse-60462-university-of-notre-dame in Computer Science and Engineering at University of Notre Dame.

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Date Created: 11/01/15

Introduction to CMOS VLSI Design Lecture 26 Logic Delay Peter Kogge Joseph Nahas University of Notre Dame Fall 2009 Slightly modified and rearranged from original 2008 slides by Jay Brockman Based on lecture slides by David Harris Harvey Mudd College h ttpwwwcmosvsicomcoursematerialshtml CMOS VLSI Design Outline for Today El RC Delay Models Capacitance RC Delay Effective Resistance Inverter Delay 2C Logic Delay CMOS VLSI Design Slide 3 Outline El Introduction El MOS Capacitor El nMOS lV Characteristics El pMOS lV Characteristics El Gate and Diffusion Capacitance El Pass Transistors El RC Delay Models 2C Logic Delay CMOS VLSI Design Slide 2 Capacitance El Any two conductors separated by an insulator have capacitance El Gate to channel capacitor is very important Creates channel charge necessary for operation El Source and drain have capacitance to body Across reversebiased diodes Called diffusion capacitance because it is associated with sourcedrain diffusion 2C Logic Delay CMOS VLSI Design Slide 4 Gate Capacitance El Approximate channel as connected to source CI Cgs 8oxWLtox CoxWL CpermicronW CI Cpermicmn is typically about 2 fFum L and tOX both scale with process SiO2 gate oxide good insulator 80x 3920 2C Logic Delay CMOS VLSI Design Slide 5 RC Delay Model CI Use equivalent circuits for MOS transistors Ideal switch capacitance and ON resistance Unit nMOS has resistance R capacitance C Unit pMOS has resistance 2R capacitance C CI Capacitance proportional to width CI Resistance inversely proportional to width d kc S Ikc d R Q 2Rk 9 Ek lt gt d IkC S gr Q iEk lt gt 9L I EEC kc S kc s l d 2C Logic Delay CMOS VLSI Design Slide 7 Diffusion Capacitance D Csb Cdb CI Undesirable called parasitic capacitance CI Capacitance depends on area and perimeter Use small diffusion nodes Comparable to Cg for contacted diff 12 Cg for uncontactecl Varies with process SSSSS e2 SSSSS e1 i m 2C Logic Delay CMOS VLSI Design Slide 6 CMOS R and C Capacitance SourceDrain Channel Interconnect CapaCItance OnResistance Capacitance and Resistance A gt AlgReq 2C Logic Delay CMOS VLSI Design Slide 8 Driving Another Gate 2C Logic Delay CMOS VLSI Design Falling Output 1 2C Logic Delay capacitor charged CMOS VLSI Design CL V out Slide 9 Slide 11 Between Cells 2C Logic Delay CMOS VLSI Design Slide 10 Falling Output 2 Rug vol it R F t capacitor discharges through NMOS 2C Logic Delay CMOS VLSI Design Slide 12 Rising Output 1 out capacitor discharged 2C Logic Delay CMOS Vle Design Slide 13 Solving El How long does it take to discharge the output from starting voltage V0 to voltage V1 Kirchhoff s current law at output Rp IR 71 E v H tit t1 V1 1 C Ii 736 it Icl L to Va V t 7 to iBC39Un V1 7111M V BC 111 4 V1 2C Logic Delay CMOS VLSI Design Slide 15 Rising Output 2 V out capacitor charges through PMOS 2C Logic Delay CMOS VLSI Design Slide 14 Delay Definitions Vin Propagation delay input 500 waveform 0 1p tpHL tpLH2 tpHL tpLH 4 t V out 0 output I waveform 39 50 Slg nal slo pes t i 2C Logic Delay CMOS VLSI Design Slide 16 RC Propagation Delay Estimation Effective Resistance El Shockley models have limited value Not accurate enough for modern transistors V Too complicated for much hand analysis m assume vm rise time is 0 El Simplification treat transistor as resistor Replace ldSVds V95 with effective resistance R t 7 o At Rcm Lquot Ids VdSR i1 R averaged across sWItching of digital gate V tPHL R0111 Vvdd El Too inaccurate to predict current at any given time out 12 But good enough to predict RC delay RC391112 GQHC tEl ti ZC Logic Delay CMDS VLSI Design Slide 17 ZC Logic Delay CMDS VLSI Design Slide18 Switching Voltages Approximating Output Resistance alsx lEI VDDZ 3VDD4 VDD vGS 25V 1 R R 1 V R eq Vgs Vds as V 215 V 2 I vGS 2ov E I A t 1 I vGS 15v M I v 10v v v 39 GS 39 V as M o quot I i i i i Vds Vii2 o 05 1 15 1 25 V t vDe v R VDD 25V 85K9 in t1 410mr 4220M 2C Logic Delay CMDS VLSI Design Slide 19 2C Logic Delay CMDS VLSI Design Slide 20 Approximating R0N Equivalent Resistance 5 C 50 ff 4 At 027 us A 3 RAt069 C78 K9 6 E 39 Z 1 mo gt 7 2 k 0 01 0 2 0 s 0 036 07 033 09 10 Time n5 2C Logic Delay CMOS Vle Design Slide 21 Inverter Delay Estimate El Estimate the delay of a fanoutof 1 inverter 2C Logic Delay CMOS Vle Design Slide 23 RC Values El Capacitance C C9 Csb Cdb 2 fFMm of gate width alues similar across many processes for minimal gate length V El Resistance as mm 5 V ID 550 pApm 035 pm 33 V Von c A 31m til Reqzojs VDDIdsar0c A 130nm 15V Req 7 Kg im in 06 pm process 90 nm 12 V Req 2 Kg im in 90 nm process El Unit transistors May refer to minimum contacted device 42 A Or maybe 1 Mm wide device Doesn t matter as long as you are consistent 2C Logic Delay CMOS Vle Design Slide 22 Inverter Delay Estimate El Estimate the delay ofa fanoutof 1 inverter 2C Logic Delay CMOS Vle Design Slide 24 Inverter Delay Estimate El Estimate the delay of a fanoutof1 inverter E20 RE 126 12c 126 12c ASE ma H H Hm R g 0 E go be 2C Logic Delay CMOS VLSI Design Slide 25 Inverter Delay Estimate El Estimate the delay of a fanoutof1 inverter E26 RE 126 Elm 126 12c ESE R lo go Ri 6 i0 d 6RC 6 7 KQ2 fF 84 ps 06 pm process 6 2 KQ2 fF 24 ps 90 nm process 2C Logic Delay CMOS VLSI Design Slide 27 Inverter Delay Estimate El Estimate the delay of a fanoutof1 inverter E20 RE lzc I2c 126 12c ASE var H H mm R g 6 E gc Ea 2C Logic Delay CMOS VLSI Design Slide 25 d6RC Compare three delay cases F 2 E 54 In Out A 1 27 2mweserm reassess ls Case 1 Case 2 or Case 3 Faster 2C Logic Delay CMOS VLSI Design Slide 28 Delay Case 2 20 l 5 i I 13 a I 54c 6C 13c Delay Case 1 4 L R 0 mi 3c R192 9c V V quot 3 V T 9c V V T 27c d112RC d236I3RC12RC d2108I9RC12RC dd1d2d336RCltlt84RC d 84 RC CI Note the geometric progression in size 3X per stage CI The delay for each stage is the same cMos VLSIDesign SIIdeZB 20 Logic Delay cMos vle Design slideso zc Logic Delay Delay Case 3 sc i 54c 32c k R116 2 7 16C 4c V 27c 4 d19RC d29RC d5129l16 RC81 RC d3 9RC d4 9RC dd1d2d3d4d5441 RC El Case236 RCltCase344 RCltCase1 84 RC El You can have too much of a good thing Sllde31 20 Logic Delay cMos VLSIDesIgn Introduction to CMOS VLSI Design Lecture 2A MOSFET Characteristics Peter Kogge Joseph Nahas University of Notre Dame Fall 2009 Slightly modified and rearranged from original 2008 slides by Jay Brockman Based on lecture slides by David Harris Harvey Mudd College h ttpwwwcmosvlsicomcoursemateri alshtm CMOS VLSI Design Outline for Today El Introduction El MOS Capacitor El nMOS lV Characteristics 0 Introduction CMOS VLSI Design Slide 3 Outline El Introduction El MOS Capacitor El nMOS lV Characteristics El pMOS lV Characteristics El Gate and Diffusion Capacitance El Pass Transistors El RC Delay Models 0 Introduction CMOS VLSI Design Slide 2 Introduction El So far we have treated transistors as ideal switches El An ON transistor passes a finite amount of current Depends on terminal voltages Derive currentvoltage lV relationships El Transistor gate source drain all have capacitance C AVAt gt At CH AV Capacitance and current determine speed El Also explore what a degraded level really means at A elE a nmos nmos4 pm os pm 054 0 Introduction CMOS VLSI Design Slide 4 CMOS R and C Gate Capacitance SourceDrain Channel Interconnect Capacrtance OnReSIstance Capacrtance and Resistance A Req A 0 Introduction CMOS VLSI Design Slide 5 Terminal Voltages v El Mode of operation depends on V9 Vd Vs iv vgs vg vs 1 ng Vg Vd Vs 39 Vd Vds Vd Vs Vgs 39 ng Vds El Source and drain are symmetric diffusion terminals By convention source is terminal at lower voltage nmos Hence Vds 2 0 El nMOS body is grounded First assume source is 0 too El Three regions of operation Cutoff Linear lt Vds Saturation Vgs 39 39 0 Introduction CMOS VLSI Design Slide 7 MOS Capacitor El Gate and body form MOS capacitor El Operating modes Accumulation Depletion Inversion depletion region 0 imam region depletion region eeeeeeeeeeeeeee C 0 Introduction CMOS VLSI Design Slide 6 nMOS Cutoff El No channel Vgs lt VT Accumulation Depletion El Ids 0 3 I 636363696363 4 6666666669669666 t e and b 0 Introduction CMOS VLSI Design Slide8 nMOS Linear El Channel forms Vgs gt VT Inversion El Current flows from d to s e39 from s to d El IdS increases with VolS Vds lt Vgs VT El Similar to linear resistor 0 Introduction CMOS VLSI Design Slide 9 Water Model C Sequin VGS El Sourcedrain each have deep container of fluid Applying positive voltage lowers top of container El Gate has plunger Starts at height VT above surface Positive voltage lowers plunger VS039 39VDs 0 Introduction CMOS VLSI Design Slide 11 nMOS Saturation El Channel pinches off Vds gt Vgs 39 VT El IdS independent of VGIS El We say current saturates El Similar to current source e eeeee e V W V eeeeeeeeeeeeeoee as as t ptypeboqy b 0 Introduction CMOS VLSI Design Slide 10 Regions of Operation VGS lt VT VGs gt VT VDS lt VGs39VT cutoff no current current linear w1th VDS 0 Introduction CMOS VLSI Design Slide 12 Regions of Operation cont VDS VGS39VT VDS gt VGS39VT Vcs lt VT v v v quotpinchoffquot saturated cutoff 0 Introduction CMOS VLSI Design Slide13 IV Characteristics El In Linear region ds depends on How much charge is in the channel How fast is the charge moving 0 Introduction CMOS VLSI Design Slide 15 MOS IV Characteristics I I IDS I VDS I 0 Introduction CMOS VLSI Design Slide 14 Dimensions 0 Introduction CMOS VLSI Design Slide 16 Calculating MOS IV Relations Charge in Transit charge in transit I f V gt V D tranSIt tlme GS T r transit time 39 J 39 Q charge in transit 7 u electron mobility CG gate capacitance Q CG VGS VT 8 permittivity of oxide LWL VGS VT E electric field tox 0 Introduction CMOS VLSI Design Slide 17 0 Introduction CMOS VLSI Design Slide18 Transit Time IDs at Onset of Linear Region Assumes constant gatetochannel voltage V VGS gt VT D S across channel charge in transit an51t tlme usW E voltage Lt VGS VTXVDS distance L I L L L2 k39ZOGS 39 VTXVDS 1quot 7 velocity LE uVDS 0 Introduction CMOS VLSI Design Slide19 0 Introduction CMOS VLSI Design Slide 20 Accounting for Channel Voltage Variation VGS gt VT VDS Vii 0X VGS VT Vx T dx dx2 ME MLquot MdV dx sde dQ dV dQ Msde I 7 7 dxl T I VGS VT Vx 0 Introduction CMOS VLSI Design Slide 21 Accounting for Channel Voltage Variation VGS gt VT VD S V W V 2 I k VGS VTVDS VDSZ I 5 VGS VTVDS 2 0 Introduction CMOS VLSI Design Slide 23 Accounting for Channel Voltage Variation VGS gt VT VDS V V x gt 39 L V0 f Idx Mfw f VGS VT VdV 0 0X 0 2 L W VGS VTVDS V35 MSW V 2 I ZUXL VGS VTVDS 5 0 Introduction CMOS VLSI Design Slide 22 Exam p le El We will be using a 06 pm process for your project From AMI Semiconductor tox100A10nm p 350 cm2Vs VI 07 V a 39 so 88510 M Fcm Plot dS vs VdS Vgg012345 Use WL 42 A 350 33993983985304413120K toxL 1010 L L v 0 Introduction CMOS VLSI Design Slide 24 D 3 NMOS Characteristics V052 W I VGS VTVDS 2 SATURAJ39ION39 0 Introduction CMDS VLSI Design Slide 25 Saturation VB 1 VGS VTVDS 2 j 9 Wm 13VGS VT Vm 0 VDS VGS VT VG VT2 ISAT 3 2 0 Introduction CMDS VLSI Design Slide 26 Introduction to CMOS VLSI Design Lecture 26 MOSFET Delay Peter Kogge Joseph Nahas University of Notre Dame Fall 2009 Slightly modified and rearranged from original 2008 slides by Jay Brockman Based on lecture slides by David Harris Harvey Mudd College h ttpwwwcmosvsicomcoursematerialshtml CMOS VLSI Design Outline for Today El RC Delay Models Capacitance RC Delay Effective Resistance Inverter Delay 0 Introduction CMOS VLSI Design Slide 3 Outline Introduction MOS Capacitor nMOS lV Characteristics pMOS lV Characteristics Gate and Diffusion Capacitance Pass Transistors RC Delay Models UUUUUUU 0 Introduction CMOS VLSI Design Slide 2 Capacitance El Any two conductors separated by an insulator have capacitance El Gate to channel capacitor is very important Creates channel charge necessary for operation El Source and drain have capacitance to body Across reversebiased diodes Called diffusion capacitance because it is associated with sourcedrain diffusion 0 Introduction CMOS VLSI Design Slide 4 Gate Capacitance El Approximate channel as connected to source CI Cgs SOXWLtox COXWL C W Cl C permicron permicron is typically about 2 fFum SiO2 gate oxide good insulator 80x 3920 0 Introduction CMOS VLSI Design Slide 5 RC Delay Model CI Use equivalent circuits for MOS transistors Ideal switch capacitance and ON resistance Unit nMOS has resistance R capacitance C Unit pMOS has resistance 2R capacitance C CI Capacitance proportional to width CI Resistance inversely proportional to width d kc S Ikc d R Q 2Rk 9 Ek lt gt d IkC S gr QHIEK lt gt 9L I EEC kc S kc s l d 0 Introduction CMOS VLSI Design Slide 7 Diffusion Capacitance D Csb Cdb CI Undesirable called parasitic capacitance CI Capacitance depends on area and perimeter Use small diffusion nodes Comparable to Cg for contacted diff 12 Cg for uncontactecl Varies with process SSSSS e2 33 e SSSSS e1 0 Introduction CMOS VLSI Design Slide 6 CMOS R and C Gate Capacitance SourceDrain Channel Interconnect CapaCItance OnResistance Capacitance and Resistance A gt AlgReq 0 Introduction CMOS VLSI Design Slide 8 Driving Another Gate Between Cells E i Hi 114 MXJ m p gt 0 Introduction CMOS VLSI Design Slide 9 0 Introduction CMOS VLSI Design Slide 10 Falling Output 1 Falling Output 2 Vim RP Vout V in Vout Rn CL t t t t capacitor charged capacitor discharges through NMOS 0 Introduction CMOS VLSI Design Slide 11 0 Introduction CMOS VLSI Design Slide 12 Rising Output 1 out capacitor discharged 0 Introduction CNIOS Vle Design Slide 13 Solving El How long does it take to discharge the output from starting voltage V0 to voltage V1 Kirchhoff s current law at output Rp IR 71 E v H tit t1 V1 1 C Ii 736 it Icl L to Va V t 7 to iBC39Un V1 7111M V BC 111 4 V1 0 Introduction CNIOS VLSI Design Slide 15 Rising Output 2 Vin Vout t t capacitor charges through PMOS 0 Introduction CNIOS VLSI Design Slide 14 Delay Definitions Vin t Propagation delay input 500 waveform 0 1p tpHL tpLH2 tpHL tpLH 4 V out 0 output I waveform 39 50 Slg nal slo pes 10 r t 3 4 0 Introduction CNIOS VLSI Design Slide 16 RC Propagation Delay Estimation Effective Resistance El Shockley models have limited value Not accurate enough for modern transistors V Too complicated for much hand analysis m assume vm rise time is 0 El Simplification treat transistor as resistor Replace ldSVds V95 with effective resistance R t 7 o At RCln L I Vdis i1 R averaged across sWItching of digital gate V tPHL R0111 Vvdd El Too inaccurate to predict current at any given time out 12 But good enough to predict RC delay RC391112 GQHC tEl ti 0 Introduction CMDS VLSI Design Slide 17 0 Introduction CMDS VLSI Design Slide18 Switching Voltages Approximating Output Resistance alsx iEI VDDZ 3VDD4 VDD vGS 25V 1 R R 1 V R eq Vgs vds is V 215 V 2 I veg 20v 3 I A t 1 I vGS 15v M I 1 av v v 39 GS 39 V as M o quot I i i i i Vds Vii2 o 05 1 15 1 25 V t vDe v R VDD 25V 85K9 tn t1 410mr 4220M 0 Introduction CMDS VLSI Design Slide 19 0 Introduction CMDS VLSI Design Slide 20 Approximating R0N Equivalent Resistance 5 4 C 50 ff At 027 ns 8 3 RAt069 C78 K9 gt Z 1 e k 0 OI 0 7 0 s 0 036 07 033 09 10 Time n5 0 Introduction CMOS Vle Design Slide 21 Inverter Delay Estimate El Estimate the delay of a fanoutof 1 inverter 1 1 0 Introduction CMOS Vle Design Slide 23 RC Values I Capacitance C C9 C5 Cd 2 fFum of gate width Values similar across many processes El Resistance R z 6 Kgmm in 06um process Improves with shorter channel lengths El Unit transistors May referto minimum contacted device 42 A Or maybe 1 pm wide device Doesn t matter as long as you are consistent I Introduction CMOS Vle Design Slide 22 Inverter Delay Estimate El Estimate the delay ofa fanoutof 1 inverter 0 Introduction CMOS Vle Design Slide 24 Inverter Delay Estimate El Estimate the delay of a fanout of 1 inverter Inverter Delay Estimate El Estimate the delay of a fanout of 1 inverter 12G 129 2v 2 In lac In I2c 2v 2 12 112C 120 12c g V lo 1 g Y EC 1 R3 5 3 R5 c c r l E r E l E E d 6R0 0 Introduction CNDS VLSI Design Sllde 25 0 Introduction cMos VLSI Design Slide 26 Compare two delay cases Delay Case 1 2 54 a 1 54 1 2c 1 27 J V 27c 2 6 13 54 V 2 f 1 3 9 27 A d 84 RC ls Case 1 or Case 2 Faster 0 Introduction civics VLSIDesIgn Sudan 0 Introduction cMos VLSI Design siioeza Delay Case 2 1 13c 1 54 6C 13c L L R13 3c R19 9c V 9c V V 27c v v i v i d112RC d236I3RC12RC d2108I9RC12RC dd1d2d336RCltlt84RC CI Note the geometric progression in size CI The delay for 5 stages would be 44 RC slower than 3 stages 0 Introduction cMos VLSIDesIgn snaezs

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