VLSI Circuit Design
VLSI Circuit Design CSE 40462
Popular in Course
Popular in Computer Science and Engineering
This 0 page Class Notes was uploaded by Mrs. Damaris Hyatt on Sunday November 1, 2015. The Class Notes belongs to CSE 40462 at University of Notre Dame taught by Staff in Fall. Since its upload, it has received 28 views. For similar materials see /class/232747/cse-40462-university-of-notre-dame in Computer Science and Engineering at University of Notre Dame.
Reviews for VLSI Circuit Design
Report this Material
What is Karma?
Karma is the currency of StudySoup.
Date Created: 11/01/15
MultiStage Circuits Summary Assume you are given a circuit with the following characteristics 0 N stages oflogic The path that is of interest goes through N circuits Gl Gn where Gi is the type of the ith gate in the path pi is the parasitic delay due to a gate of type Gi gi is the logical effort presented by Gi on the output of some circuit that drives one of its inputs Si is the size or width of all transistors in gate Gi as a multiplicative factor 0 Thus the input capacitance presented by Gi on any circuit that drives it is giSi o The extra capacitance that is placed on the output of each gate Gi is Couti Thus 0 Coutn is the capacitance placed on the output of the path thru Gn that represents the load 0 Couti 1n represents the total load placed on the output of Gi by all circuits including the ones not on the designated path If there were h copies of Gi1 on the output of some Gi and the path ran thru one of them then this Couti is hCini1 The input capacitance presented by any gate Gi on whatever it is attached to is Cini o This is in units of standard unit inverters 0 Thus Cini 3 giSi if we allow the transistors in Gi to be scaled wider The branching factor bi is defined as the ratio of all the capacitance presented to the output of gate Gi the onpath offpath capacitance or just Couti to the capacitance presented by the Gi1 that is on the path of interest the on path capacitance or just Cini1 Assume we are given Coutn and Cinl and want to compute the size of the transistors that minimize delay Steps Note we include solutions to the example on page 177 below each step Gl is a 2input NADNA G2 is a 3 input NAND and G3 2 input NOR with Cout345 and Cinl8 Note that XCin2 and yCin3 1 Compute the optimal delay as follows a Lookup page 167 amp 168 or compute the gi and pi for each gate Gi in the path 0 gl43 g253 g353p12 p23 p32 b Compute the branching factors bi ISiSnl o bl3XX3b22yy2 c Compute G Hi1ngi 7 the product of all the g s o G 435353 10027 d Compute H Cout nCin1 o H 458 e Compute B Hi1n1bi Note the n1 o B 32 6 f Compute F GBH o F 100276458 125 g Compute f FuN o f 125A13 5 h Compute P 2i17npi o P 2 3 2 7 Minimal delay is P 11 f in units of unit inverters o delay 7 35 22 V 2 Now we want to compute the Cini for llti nl a Cinn gnC0utn f o y Cin3 g3Cout3f 53455 15 b Repeat for each i n2 n3 Note that Couti biCinil o Cout2 b2Cin3 2y 2Cin3 215 30 o X Cin2 g2Cout2f 53305 10 c and check if glCoutl f matches what you were given for Cinl o Coutl blCin2 3Cin2 310 30 o Cinl glCoutlf 43305 8 AND THIS CHECKS 3 Now we want the sizes of each transistor in Gi remembering that in general Cin 3g SizeFactor The 3 is there to normalize for an inverter a Si Cini3gi o S3 Cin3g3 15353 3 7 so each transistor in G3 must be 3 times wider than for a unit 2 input NOR which has 1 wide nmos amp 4 wide pmos for a scaled gate with 3 13 wide nmos and 34 12 wide pmos o S2 Cin2g2 10353 2 7 so each transistor in G2 must be 2 times wider than for a unit 3 input NAND which has 3 wide nmos amp 2 wide pmos for a scaled gate with 236 wide nmos and 22 4 wide pmos o Sl Cinlgl 8343 2 7 so each transistor in Gl must be 2 times wider than for a unit 2 input NAND which has 2 wide nmos amp 2 wide pmos for a scaled gate with 224 wide nmos and 22 4 wide pmos 4 You can also check that the normalized delay thru each gate adds up to the total where delay ip igi CoutiCini o delayl p1 glCoutlCinl 2 43308 7 delay2 p2 g2Cout2Cin2 3 533010 8 delay3 p3 g3Cout3Cin3 2 534515 7 Total is 7 8 7 22 NH This checks with the result of Step 1 Introduction to Topics El What is an Analog Circuit C M El The Current Mirror El Transistor Matching 39 El The Current Mirror cont I g n El The Differential Amplifier El The Common Source Amplifier El The Operational Ampli er El Transistor Small Signal Model Common Source Example El The Common Drain Source Follower Amplifier El Simulation I Joseph Nahas Frequncy Response AC un39versny 0f None Dame El DigitaltoAnalog Conversion Fall 200 L08 Analog Design CMOS VLSI Design Slide 2 Digital to Analog Conversion Digital to Analog Converter Types El Switched Current Source El Switched Current Source Transistor Design El R2R Ladder Layout El SigmaDelta Size Clock Driven El R2R Ladder Operation Layout Size El Size Comparison of Switched Current Source to R2R Ladder L08 Analog Design CMOS VLSI Design Slide 3 L08 Analog Design CMOS VLSI Design Slide 4 Switched Current Mirror D to A Layout VDD RL llL m4 m4 m4 m4 0 VDUT m3 m0 m2 m3 m1 2390 l Io lzio Mo 8 m3 m2 m0 m3 molt1c w m1 m2lt139 gt39t m3lt339 gt m4lt70gt m7lt10gt m8lt30gt m4 m4 m4 m4 m5lt1OJ m6 m9lt70gt dlt0 dlt1 dlt dlt3 Switching transistor connected to source of current mirror Dummy switching transistor on reference transistor L08 Analog Design CMOS VLSI Design Slide 5 L08 Analog Design CMOS VLSI Design Slide 6 Layout 3A 5A m4 m4 m4 m4 3A m3 m0 m2 m3 m1 How Large are the Transistors in 018 um CMOS 3 m3 m2 m0 m3 m4 m4 m4 m4 A 01 um L08 Analog Design CMOS VLSI Design Slide 7 L08 Analog Design CMOS VLSI Design Slide 8 How well do the currents have to match Matching in two CMOS Technologies E 4 a h 3 5 r a 2 u E 5 a in t 3 E u at 3 39 A V 39 x L Length umlS 01WluLn lzml Lenghum15 d Nxdth um g 2A A 25 Fig 4 313 pm of I magma vs L and w for an anOS mg 5 an plat Br 1 mismalch vs geometry graded aha cunqu mirror 1cxolm 013pm CMOS Lechuvlugy no nmos at I 10M 0 25am BiCMOS technology CI Note similar characteristics in plots of matching vs L and W El In this case the 13 um technology is better than the 025 um technology In general small is not always better 0 How accurate is 8 com pared to 1 2 4 L08 Analog Design CMOS VLSI Design Slide 9 L08 Analog Design CMOS VLSI Design Slide 10 018 nmos L3umW 1 um Area asafunctlon of bits 2 a 3 more nnn n2n m m min 1nn 12a Mn 16quot m Vds V L08 Analog Design CMOS VLSI Design Slide 11 L08 Analog Design CMOS VLSI Design Slide 12 R2R Ladder D to A D0 D1 D2 D3 RZR Ladder Digital to Analog Converter OVOUT L08 Analog Design CMOS VLSI Design Slide 13 L08 Analog Design CMOS VLSI Design Slide 14 2 Bit R2R Ladder D to A Converter R2R Ladder D to A D30 vOUT 0000 932 vDD DO D1 D10 VOUT DO D1 D2 D3 0001 1032 VDD 00 38 vDD 0010 1132 vDD 01 43 vDD 0011 1232 vDD R 2 10 58 vDD 0100 1332 vDD 2R 2R V V V 11 68 VDE 0101 1432 vDD 0110 1532 vDD R OVom OVOUT 0111 1632 vDD 2R 1000 1732 VDE 1001 1332 VDD VDD2 1010 1932 VDD 1011 2032 VDD 1100 2132 VDD 1101 2232 VDD 1110 2332 VDD 1111 2432 VDD L08 Analog Design CMOS VLSI Design Slide 15 L08 Analog Design CMOS VLSI Design Slide 16 The RZR Ladder Switch El What is the resistance of mo then D0 Where is the nmos transistor operating is asserted What region of the transistor quot 1 characteristics is m0 operating D0 via 2R We e We 2 LEI1E 3 W5uu m0 3 dressers nnn n2n nw 6 mm 1nn 12a Mn 16n 1am Vds V L08 Analog Design CMOS VLSI Design Slide 17 L08 Analog Design CMOS VLSI Design Slide18 What is the resistance of the nmos transistor Resrstor Layout Gutdellnes Vg5us 1 Poly Resistor and 0D Resistor Guideline 1 the total resrsrance of tlle resistor ts calculated based on the equation and data lrsred m SPICE model vgs 1 e dncummr 601810511001 v 54 l VS1s 2 For poly resrsmr It IS strongly recommended that the resistor ldrh 2 l o and me resrsmr square va5a a n r NW2 5 For 0D resrstor u rs strongly mortmredded that me resrsrur width 2 2 o um and me Vs resrsmr square number 2 5 We vds 3 was r M was r n u a R NW 5 Man and Plv combmauuus tespecu To obtain precrse resrsrance dummy laers mmzv amp E 4 DMZP2V are requrred szv P2 P 39 are derrved from logical operation please ensure correct Imam implants in case the resrslor traverses NVV PW39 or lsv 3 3V the dummy Iayus struuld follow me unplanl destgu rules related to poly resrstor shown below equal to film 5 It rs strongly recommended that tit mmunum clearaute of the resxstor to tinrelated implant regtons be 0 Minn a 39 39 V 7 L08 Analog Design CMOS VLSI Design Slide19 L08 Analog Design CMOS VLSI Design Slide 20 PPoly Resistor Guidelines Model Parameters for ppoly nosal n Prlemnmimr mmo sz vm param nomRSPPLYNOSBL311 S 17013710797001 v19 param sdevRSPPLYNOSBL653 s 17013407527001 v19 gm param tclrpplynosal13BOe6 5 17013710797001 v19 39 param thrpplynosal5311ei9 5 17013710797001 v19 Pal loll param nom RS NPLYJIOSBIFZBZ S T Ol imisPiool v1 9 param sdevRSNPLYNOSBL663 s 17013407527001 v19 param tclrnplynosal1102e3 5 17013710797001 v19 param thrnplynosal1747e6 5 17013710797001 v19 L ineiaied implamxegwns Unrxdakd Loa Analog Design cMos VLsIDesign Slide21 LoeAnangDesign cMos vle Design Slide22 PPoly Nosal Resistor Resistor Spacmg 13A 4 3A gt 10 um 2umX10 um 5squares5311n1555n Minimum Recommended Size Res or Lee Analog Design cMos VLsIDesign sligezs LoeAnangDesign cMos VLSI Design Slide24 RZR Ladder D to A D0 om D2 D3 O L08 Analog Design CMOS VLS39 Deskquot Slide 25 Resistor Layout 01234567891011121314 L08 Analog Design CMOS VLSI Design Slide 26 Area as a function of bits L08 Analog Design CMOS VLSI Design Slide 27 Comparison of Current Source to RZR L08 Analog Design CMOS VLSI Design Slide 28