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Logic Design and Sequential Circuits

by: Mrs. Damaris Hyatt

Logic Design and Sequential Circuits CSE 20221

Mrs. Damaris Hyatt
GPA 3.79


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This 0 page Class Notes was uploaded by Mrs. Damaris Hyatt on Sunday November 1, 2015. The Class Notes belongs to CSE 20221 at University of Notre Dame taught by Staff in Fall. Since its upload, it has received 19 views. For similar materials see /class/232749/cse-20221-university-of-notre-dame in Computer Science and Engineering at University of Notre Dame.

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Date Created: 11/01/15
CSE 20221 Logic Design Combinational Logic in Verilog Jay Brockman Department of Computer Science and Engineering Department of Electrical Engineering University of Notre Dame Logic Design Combinational Logic in veriiogi Brockman ND 2008 Hardware Description Describe hardware structure and behavior using a hardware description language Verilog simulation analyze behavior over time synthesis generate circuits for a given technology The devil is in the details Subtle mistakes can have a major unintended effect My goal equip you with a simple yet exible and reliable methodology quot enough detail to avoid getting bitten but also avoid being confusing I Logic Design Combinational Logic in Verilog 2 Brockman ND 2008 Approach Logic Design Combinational Logic in Verilog3 There are lots of ways of describing the same piece of hardware correctly in Verilog Different textbooks Xilinx wizards etc adopt different coding styles Some approaches are more errorprone than others My preferred approach is based on paranoia Pick language features to use in a given situation based on avoiding subtle bugs Frankenstein lecture slides Main coding style based on Mike Ciletti s Starters Guide to Verilog 2001 highly recommended Topic ordering and examples based on Vahid s Verilog for Digital Design companion to textbook but different coding style Use Xilinx tools and examples where appropriate Brockm an ND 2008 Structural and Behavioral Descriptions Logic Design Combinational Logic in Verilog4 Structural description text equivalent of a schematic modules connected by wires at their ports Behavioral description describes behavior inside a model use variables arithmeticlogical operators amp control ow statements if else case Verilog models use both Brockm an ND 2008 Xilinx Schematic Symbol Library Components H AND2 Logic Design Combinationai Logic in Veniog 5 0 BBQ XOR3 Brockman ND 2008 Structural Description Full Adder quot ii D SUM gt Logic Design Combinationai Logic in Veniog 6 module fu11adderA 5 cm can sum in ut 1quot A 5 output cou39r SUM wire xan11 wire xan12 wire xan13 x018 xLx11 10c1 1103 12 A 0SUM Annz xLx12 10c1 1103 ox1xn13 Annz xLx13 10A 11 c110 ox1xn12 Annz xLx14 1003 11A ox1xn11 om x1x15 10x1xn13 0 coin T endmodule Brockman ND 2008 Structural Description Ripple Carry Adder module rippleadd2 A B cou39r SUM input 101 A B output cou39r output 10 SUM wire XLXN30 XLXN36 fulladder XLXI1 AA0 BB0 CINXLXN30 COUTXLXN36 SUMSUM0 fulladder XLXI2 AA1 BB1 cmxmm35 coumcou39r sumsum1 ND XLXI3 GXLXN30 endmo u 5 Logic Design Combinationai Logic in Veriiog 7 Brockman ND 2008 Specifying Connections by Port Order module rippleadd2A B cou39r SUM V input 10 A B module fu11adderA sf cm c UT SUM output c couT output 10 suM endmodule wire XLXN30 XLXN5 A0 B0 XLXN30 XLXN36 SUM0 fulladder XLXI1 A1 B1 XLXN36 couT suM1 fulladder XLXI2 GND XLXI 3 XLXN30 5 Logic Design Combinationai Logic in Veriiog 8 Brockman ND 2008 Language Rules Logic Design Combinational Logic in Verilog9 Verilog is a case sensitive language with a few exceptions Identifiers spacefree sequence of symbols upper and lower case letters from the alphabet digits 0 1 9 underscore symbol only for system tasks and functions Max length of 1024 symbols Terminate lines with semicolon Single line comments A singleline comment goes here Multiline comments Do not nest multiline comments like this from Ciletti Brockman ND 2008 Data Types Two families of data types for variables Nets wire and others we won t use for now establish structural connectivity Registers reg and others we won t use for now act as storage containers for the waveform of a signal Default size of a net or reg variable is a signal bit Logic Design Combinational Logic in Verilog10 Vectors ordered collections of signal bits wire a signal bit wire 7 0 b vector descending order reg 06 segments vector ascending order Brockm an ND 2008 Representation of Numbers Sized numbers specify the number of bits that are to be stored for a value Base specifiers b or B binary d or D decimal default 0 or O octal h or H hexadecimal Examples 839b10011101 Use underscore for readability 3239HABCD Pads 0s Note Unsized numbers are stored as integers at least 32 bits Logic Design Combinational Logic in Verilog11 from Cilem Brockman ND 2008 Ve rllog Keywords always end initial output rtran tranif l and endcase inout parameter rtranifO tri assign endfunction input pmos rtranif l triO begin endmodule integer posedge scalared tri l buf endprimitive join primitive small triand bufifO endspecify large pullO specify trior bufif l endtable macromodule pull l specparam trireg case endtask medium pulldown strength vectored casex event module pullup strongO wait casez for hand rcmos strong l wand cmos force negedge real supplyO weakO deassign forever nmos realtime supply l weak l default fork nor reg table while defparam function not release task wire disable highzO notifO repeat time wor edge highz l notif l rnmos tran xnor else if or rnmos tranifO xor Logic Design Combinational Logic in Verilog12 from Cilem Brockman ND 2008 Preview Behavioral Modeling with Verilog Basic idea Write a program that determines what values to assign to which signals when Three types of behaviors for composing abstract models Single pass behavior Keyword expires a er the last statement executes use only in testbenches Cyclic behavior Keyword always executes again repeatedly atter the last statement executes 39 39 quot39 39 39 ogic and quot39 synchronous logic Continuous assignment Keyword assign assign results of expression to a signal combinational logic only Lugic Design CumbmatiunalLugicmvenlug13 amckman No max SinglePass Behavior initial Statement module stimuli2bits reg A 5 initial begin A e nd endlllodul e Lugic Design Cumbmatiunal Lugic invenl u m amckman No max Full Adder Testbench module fulladdertb reg A B CIN wire COUT SUM fulladder UUT A B CIN COUT SUM initial begin A0B0 CIN0 200 A 0 B 0 CIN 1 200A 0 B 1 CIN 0 200A 0 B 1 CIN 1 200A 1 B 0 CIN 0 200A 1 B 0 CIN 1 200A 1 B 1 CIN 0 200 A 1 B 1 CIN 1 end endmodule Logic Design Combinational Logic in Venlog l5 Brockman ND 2008 Cyclic Assignment The always statement One way to describe a module39s behavior uses an quotalwaysquot procedure x always Procedure that executes repetitively YDF in nite loop from simulation start vent control indicating that statements ute when values change e should only exec X module myand X Y F changes chan e kno n as an event Sometimes called sensitivity lisf input x y We ll say that procedure is sensitive to X output F and w reg F wait until quotF X amp Yquot Procedural statement that sets 39 XorY FtoANDofXY always X y changes amp is builtin bit AND operator assigns value to variable begin g Declares a variable data type which E X amp Y holds its value between assignments and Needed for F to hold value between F lt x AND y assignments endmodule Note quotregquot short for quotregisterquot is an unfortunate name A reg variable may or from Vahid may not correspond to an actual physical register There obviously is no register Logic Design Combinational Logic in Venlog 16 inside an AND gate Brockman ND 2008 Cyclic Assignment Full Adder module fulladderalways A B CIN SUM COUT input A B CIN output SUM COUT reg SUM COUT J sensitivity list amp and always A B CIN I or begin SUM A A B A CIN N nOt cout AampB BampCIN AampCIN A xor end endmodule Execute always block whenever a signal in the sensitivity list changes value All signals on the lefthand side LHS of an assignment in an always block must be declared as reg variables Logic Design Combinational Logic in Verilog17 Brockman ND 2008 Cyclic Assignment 4Bit Adder module adder4 A B SUM input 30 A B output 30 SUM addition reg SUM multiplication 1 I a 134 pf 3B diViSion modulo endmodule L power always statement fires if any of the bits ofA or B change Logic Design Combinational Logic in Verilog18 Brockman ND 2008 Vector Concatenation 4Bit Adder with Carry 30 A input CIN output 30 SUM output COUT module adder4withcarry A B CIN SU39M COUT input reg 30 SUM reg COUT reg 40 A5 B5 SUMS always A B CIN begin A5 1 39b0 A concatenation operator 135 l39bO B SUMS A5 B5 CIN SUM SUMS 3 0 F COUT SUM54 end endmodule Logtc Desrgn Combrnatronat Logtc m Ventog 19 Brockman ND 2008 Cyclic Behavior with if Statement Comparator module unsignedcomparatora b gt lt eg input 30 a 13 output gt lt eg reg gt lt eg unsrgnedcomparator always a 13 Ease 914 if a lt b begin gt0 t1 eq0 49 end else if a gt b begin EM sq gt 1 it 0 e 0 end else begin gt 0 lt0 eg1 end endmodule Logtc Desrgn Combrnatronat Logtc m Ventog 2o Brockman ND 2008 Cyclic Behavior with if Statement Multiplexor module mux2x1a b s f input a b 5 output f reg f always a b s if 5 0 f a else f b endmodule Logic Design Combinational Logic in Verilog21 Brockman ND 2008 Multiplexor with Vectors module mux4x4ifd0 d1 d2 d3 s f input 30 d0 d1 d2 d3 input 10 s output 30 f reg f always d0 d1 d2 d3 s if s1 ampamp s0 0 f d0 else if s1 0 ampamp s0 1 f d1 else if s1 1 ampamp s0 0 f d2 else f d3 endmodule Logic Design Combinational Logic in Verilog22 Brockman ND 2008 case Statement Multiplexor module mux4x4cased0 d1 d2 d3 s f input 30 d0 d1 d2 d3 input 10 s output 30 f reg f always d0 d1 d2 d3 s case s 0 f d0 1 f d1 2 f d2 3 f d3 endcase endmodule Logic Design Combinational Logic in Verilog23 Brockman ND 2008 case Statement Decoder module decoder2x4case I D input 10 I output 03 D bits in ascending order for example reg D always I D case I 0 D lt 4 b1000 1 D lt 4 b0100 2 D lt 4 b0010 3 D lt 4 b0001 endcase endmodule case statements are a very convenient way to implement truth tables Logic Design Combinational Logic in Verilog24 Brockman ND 2008


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