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by: Louisa O'Kon I


Louisa O'Kon I
OK State
GPA 3.58

James Stine

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James Stine
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This 0 page Class Notes was uploaded by Louisa O'Kon I on Sunday November 1, 2015. The Class Notes belongs to ECEN 6263 at Oklahoma State University taught by James Stine in Fall. Since its upload, it has received 18 views. For similar materials see /class/232899/ecen-6263-oklahoma-state-university in ELECTRICAL AND COMPUTER ENGINEERING at Oklahoma State University.

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Date Created: 11/01/15
I ECEN 6263 Advanced VLSI Design I High Speed Pipeline Implementation Part 3 Pass Transistor Logic Pass transistor logic is slightly slower than domino logic because it must compromise between passing rising and falling edges quickly Pass transistor logic is much easier to design than domino logic because carefully timed precharge clocks are not necessary Pass transistor logic consumes less area and power than domino because high activity pre charge clocks do not have to be distributed to each individual gate Fig 647b0tt0m p 346 Partial swing pass transistor logic LEAP is faster than full swing pass transistor logic CMOSTG because the reduced transistor count significantly reduces loading Recall that the input voltage to the inverter without the keeper only reaches Vdd VTquot which is insufficient to completely turn off the pFET in the inverter and causes DC power consumption A weak keeper is added as shown to eliminate the DC power consumption by pulling the inverter input voltage all the way to Vdd The keeper must be weak because the pass nFETs must be able to overcome the keeper The keeper increases delay by increasing the load on the inverter input and output The keepers can be eliminated on critical delay paths to reduce worst case delay at the expense of additional power Keepers should always be used on noncritical delay paths to reduce power consumption High Speed Pipeline Implementation Part 3 December 5 2006 page 1 of6 I ECEN 6263 Advanced VLSI Design I Recall also that the rise time of the nFET pass transistors is slow because the nFETs are not good at passing l s The average delay can be reduced by using low skew low Vim big nFET small pFET inverters X h l t m A low skew inverter can respond much more quickly than a high skew inverter to a slow rising edge The difference in response to a fast falling edge is small A low skew inverter with Z WpWn l is usually a good choice since Vim lt VddZ because ofthe higher pFET channel sheet resistance Fig 647middle p 346 Dual rail partial swing pass transistor logic CPL Dual rail with keeper is faster than single rail with keeper because the dual rail keeper is turned on earlier than the single rail keeper dual rail 3 39 Z 39 V17 without keepers with keepers The single rail keeper is turned on after an inverter delay and the dual rail keeper is turned on directly by the fast falling edge out of the pass nFETs Design Example Fig 1017a p 651 and eq 104 p 646 Building block for the valency2 tree adders High Speed Pipeline Implementation Part 3 December 5 2006 page 2 of 6 I ECEN 6263 Advanced VLSI Design I Domino Logic lti ltl Pk lj PileI Gk l l Pik i lt7 Partial Swing Pass Transistor Logic The logic equations 104 must be rewritten into a form that can be implement with a MUX This is relatively straightforward for P13 PijPikPk1j PikPk1jPik390 PIV can be implemented as follows Ptk 131 Piik Pik Pk lj odd leve1s even levels We are being conservative and adding an inverter bulTer at each level Rewriting the equation for GIU is more complicated Note that propagation and generation have been de ned to be mutually exclusive P at GE bl t G aibi t GiPi 0 High Speed Pipeline Implementation Part 3 December 5 2006 page 3 of 6 I ECEN 6263 Advanced VLSI Design I This implies that the block propagate and generate functions are also mutually exclusive GijPij GiPiGiZljPiPiZlj PiGilePile PWP J1Gjiijij mmg qg 0 The equation for GIU can be rewritten as Gij GikPika1j Pale xing 1313kale mGik l39Pthk lj which can be implemented using a MUX for GIU as below Ptk Ptk Ptk J Gk l Gtk odd levels even levels All of the pass transistor circuits require 13316 as well as Ptk Could use an inverter in each stage but adds serial delay W High Speed Pipeline Implementation Part 3 December 5 2006 page 4 of 6 I ECEN 6263 Advanced VLSI Design I Faster to have a separate 3136 and Ptk gate at each level Then Ptk 3136 and Gtk all have about same delay A dual rail implementation for 1 3116 and Ptk is combined with the Gtk gate Ptk 13HC Piik 131316 pm Pl J lt7 13k1Jr I 13 Tl odd levels even levels High Speed Pipeline Implementation Part 3 December 5 2006 page 5 of 6 I ECEN 6263 Advanced VLSI Design I Static CMOS odd levels even levels High Speed Pipeline Implementation Part 3 December 5 2006 page 6 of 6 I ECEN 6263 Advanced VLSI Design I High Speed Pipeline Implementation Pipeline Register Implementation The previous example shows the necessity for a very ef cient pipeline register design It should have small area power and delay The tradi tional choice has been to make the pipeline register out of one of the clocked dynamic D FF s fig 71 p 405 However the increased leakage current in deep submicron processes greatly reduces the charge storage time making dynamic storage impractical In this case static designs are used fig 71 p 405 The multiphase clock with inverter designs are particularly attractive since it is easy to size up the transistors to reduce delay if necessary High Speed Domino Logic Fig 647 p 346 Logic Families Last semester we explored how to size transistors in static CMOS logic gates to minimize delay Similar techniques can be applied to all the logic families Recall that we had to minimize the worst case delay between propagating a rising edge and a falling edge in static CMOS gates The optimum transistor sizes had to be a compromise between mini mizing rise time delay and fall time delay This is true of all of the logic families except domino logic gates Domino logic has the distinct advantage of only needing to minimize the fall time delay of the precharged gate output There is no rise time delay because the precharged gate output is already high at the beginning of the evaluation period The precharge time delay is hid den using clocking techniques that will be discussed later Fig 627 p 335 Recall that precharged gates cannot directly drive another precharged gate that uses the same clock Fig 628a p 335 The usual solution is to add a static logic gate usually an inverter between the precharged gates Fig 628b p 335 The resulting domino logic gates operate correctly Note that evalua tion produces a possible high to low edge on precharged outputs W and Y and a possible low to high edge on the static outputs X and Z The critical delay path only goes through the precharged gate pull down circuit and the static gate pull up circuit Fig 628c p 335 Delay can be reduced by sizing up the static gate pull up circuit The static gate pull down circuit is left near minimum size to reduce capacitive loading The authors call these highskew gates not to be confused with clock skew and label them with the H High Speed Pipeline Implementation November 12 2006 page 1 of4 I ECEN 6263 Advanced VLSI Design I Fig 629 p 336 More complex high skew static logic gates can be used with domino logic The static logic gate complexity is usually limited since the critical delay path is through the slow pFETs in the pull up circuit Static NAND gates are preferable since they do not have series combinations of pFETs in the pull up circuit Fig 646 p 345 The static logic gate can be replaced by a precharged plogic gate NP domino is attractive since the capacitive loading of the static gate pull down can be reduced resulting in smaller delays Unfortunately this logic form is much more suscepti ble to noise than standard domino So it is infrequently used Precharged gates are much more susceptible to noise than static logic gates when the out put is floating high A A 4 O A A H Every time the input rises above the noise margin VTquot the output partially discharges Each successive noise pulse degrades the output further This cumulative degradation does not happen in a static gate because the pFETs in the pull up circuit restore the output value back to Vdd between noise pulses V V Not only is the output susceptible to partial discharge the oating output is also suscepti ble to capacitive coupling to other noise sources anywhere in the chip Unreliable opera tion is likely if the noisy output Y were directly connected to another precharged gate as is done with NP domino Standard domino uses a static gate between precharged gates so that we can take advan tage of the larger and adjustable noise margin of the static gate V I A a I I Vin Vout 1 VMI4L gt F VMMH H I 39 I I gt Vin VTquot Vim Vdd VTP Vdd large Wp Vout A I I Vin Vout VMwL H I I VIVMH I gt VTn Vim Vdd39 VTp Vdd m large Wn High Speed Pipeline Implementation November 12 2006 page 2 of4 I ECEN 6263 Advanced VLSI Design I Since the input to the static gate comes from the precharged gate the maximum noise mar gin VWH for the noisy oating high input the low input is not so noisy since it is not oating is achieved with a lowskew static gate Unfortunately this con icts with the desire to minimize delay with a highskew static gate Vian V L inv VYHA VYL A highskew gate still has high enough noise margin that it can be used in most cases However the need to maintain suf cient noise margin limits the size of the skew factor Fig 624 p 333 Another way to make faster domino logic is to use the unfooted style The foot transistor is present to make sure that there is no path to ground through the nFETs during precharge If the inputs are not low enough to turn off the nFETs during precharge the output may not be precharged correctly The outputs of a domino gate for example X and Z in fig 628b do not go low until after the precharge starts Thus it is risky to use unfooted domino unless special clocking techniques are used Keepers Fig 633 p 338 Keepers help to solve two problems 1 Keepers prevent leakage currents from discharging oating high outputs 2 Keepers partially restore oating high outputs between noise pulses which reduces noise vulnerability Unfortunately keepers increase delay 1 Keepers are turned on during precharge Keepers must be overcome by the nFETs to pull the precharged gate output low during evaluate which steals current that would otherwise be available to drive the capacitance at X Keepers must be low current devices long length to reduce delay To minimize capacitive loading on X the keeper must be minimum width fig 634a p 338 High Speed Pipeline Implementation November 12 2006 page 3 of4 I ECEN 6263 Advanced VLSI Design I 2 The gate of the keeper transistor also loads the domino output Y The capacitive load ing on Y can be minimized by splitting the long channel keeper into two transistors g 634b p 338 Fig 635 p 339 Keepers for dual rail domino gates are faster since they are turned off during precharge and only turn on when the opposite output goes low However di eren tial keepers are less effective at countering noise during the rst part of evaluation Fig 639 p 341 Keepers can also help to counter charge sharing noise Fig 640 p 341 Extra precharge transistors may be necessary to eliminate charge shar ing High Speed Pipeline Implementation November 12 2006 page 4 of4


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