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# CMOS ANALOG CIRC DES ECEN 5363

OK State

GPA 3.58

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This 0 page Class Notes was uploaded by Louisa O'Kon I on Sunday November 1, 2015. The Class Notes belongs to ECEN 5363 at Oklahoma State University taught by Chriswell Hutchens in Fall. Since its upload, it has received 11 views. For similar materials see /class/232901/ecen-5363-oklahoma-state-university in ELECTRICAL AND COMPUTER ENGINEERING at Oklahoma State University.

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Date Created: 11/01/15

oma S rsity HIGH TEMPERATURE BIAS GENERATOR DESIGN Presented by Chris Hutchens Transistor The Bias Generator Equation VBl and VB4 VB3 and VB4 Stacking Low VT and High VT devices Stacking zero VT and Low VT devices Startup Circuit Backgound 1 1 plus a small number m1a Square Root of 1 plus a small number lia 1i Square Root of 1 divided by plus a small number Example Veff difference of two NMOS transistors L 2112 Equal ID and S32 and 845 lid 2 AVQb AIe a AVW AV Ma 1 71 1 liai AVaeff AVaeff AVab 13 V1 1l1 K6 O80 aejf Startup la thur VB4 Stack B s VBl Point 1 a Square Law CAN TRANSITION TO MODERATE INVERSIOh Square Law M39s AV gt 250 to 300mV 2 IKPAVGf 1 in Square Law f1W 11 T 12 f2w KPAVeffZ2 L 2 In Square Law 2 1 is proportional to p Cox 2 1 andAV AV Rz xflfz 1 3 2 1R M1AVRgm21AVRAV27M gm is set by selecting R and device geometry Point 1b Current Setting or Long Channel Bias DESIRED to Stabilize gm Constant Self Gain IRzAVZ AVlzLAVZRzAVz AVI 2 2 AV 2 S gmz 1 Amjz p Low TempCoR ie pos tempCo combined with a neg tempCo M1 VB1 VDD 39 IVTPLI39 Veff VB4 Vss VTNL Veff Improved Matching Reduced 1f noise Improved PSRR Higher gain M2 Point 1c Constant Veff or V swing Long Channel Bias DESIRED to Stabilize Veff S gmz 21 S1SRKPAVDD MOS Resistor I R ve 2 12 R ve lwlm R 1gm lm 1IB5VDD VT gm Wm BRNDD VT Veff 10 SRSVDD VT VB1gt CONSTANT Ve for Constant VDD Point 1b Current Setting r Long Channel Bias DESIRED to Stabilize gm Red d Vas and Higher gain LOW Headroom PMOS or NMOS Loops Linear Resistors constant gm A Temperature MOS Resistor o Constantselfgain wit Temperature 0 Trimming I R avgquot2 12 R vNm 1 42 XWLILL kp ve hz 10uA LIIL R 19m m I 39 I gm Vm A 10uA 39v nf w 4 m L IAN I Elwyn Interdigitate 2 Point 2a Cascode or Signal Transistors Bias WM L I mx4xWLILL b m2 4 SILs wLLL m V33 V34 VTNs Vefr VTNs 5M W ILS w quot 1 4xw5 s Vss VTNL Veff VTNs 2Veff VTNsVeff2 I quot 4 w IL u V55 VTNL 2 Veff 4quotde I I 1 10uAle 4x4 And I 4stL5 v34 20 F V34 VDD VTNL Veff 4xWLIL B4 I 39 39 t d39 39tat 4 39 55quot EXWLILL n er Igl e aquot Veg VDSSAT and SM 1 0 to 200 mV wwlto24 10ms kpn 150uA W VDD gt I w 39 where SM is 100 to 200 mV MUST REQUIREME 39 I WsILs gt Long Channel Resistor is Better Choice Point 23 Cascade or Signal Transistors Bias V33 V34 VGS3 39 VGS4 V33 V34 VTNS 2Veff VTNs Veffl2 Vss VTNL Veff VTNs zveff VTNsIVe 2 Vss VTNL 32 Veff M3 M4 And V34 VDD39 IVTNL VDSSAT SM where SM is 25 to 200 mV MUST REQUIREMENT Point 3 Cascade or Signal Transistors V055 VB3 Vss VTNL 2 Veff And M3 m V34 Vss VTNL 2 Veff VDSSAT 100mV to 250mV MUST REQUIREMENTl 7quot Selecting W 2 verse J ngers provides a 83 decrease in Ve Selecting W 48 verse 32 ngers provides a 20 decrease in Ve f Now for a Veff of 250mV of the safety margin on the current source becomes 103 or approximately 250mV Point 4a Gain CONTANT with Temp A gmdiffgo go 2le gmm defKPAVzf I AV41 JSTQJSRKPAVDD Proportional to mobility 40 decrease Temp 30 TO 200 0C A a Sdiff 39KP 39 AVE Am1 SRKPAVDD 1 Point 4b Gm dependent on Temp 1 AV 1 JJSRKPAVDD gmm 2 2 AVE7 AVE7 s gde a 21 SNJSRKPAVDD Bandwidth a gm Point 5a Gain decreases with Temp and R dependency Agmdiffg0 g0 Ae ID gmd ff SdtffKPAVe IAV17 j Proportional to mobility 40 lRTemp 30 TO 200 0C Sm KP AVeff AV17S1 Point 5b Gm and BW CONSTANT with Temp I 2AEI MJ m 2 g 17 AVe AV eff 2 S gde a y Bandwidth 0 gm Point Ga Startup th Required Bias Loop gain lt 1 Required Very Small Possibility but still possit Many Versions 2 Possible Solutions Point 6b Startup Loop Gain gt 1 AAfgl gmRm gmR6gt1 R gt 6gm 3 AVI Select R gt 10 AVI for VDS feedback gt VTL VT5p VTL This ensures that the follower will shut off R I VTL gt VDD R gt4 VDD VTL Check for Strong Pull down Point 6c Startup Loop Gain gt 1 for all conditio Bias Loop gain lt1 Low frequency stable gm 1 ng lt1 1 gman gmp gmn2 CST gt10 CBS High frequency stability gmnl gmp O gmp gmnz CR gtgt CPA gt1 At high frequency therefore This ensures stabile reliable start mx4xWr m2 1 uu n 10 uAII 4xWLI LL 39 lnter digitate 4 Len lt 55 Wequot lt 024 1DuAlle 10uAeg 4x 4xW5IL5 2 0 VE4 WLI L 8xWLI LL gm 10mskpn 150uA A Wles gt3977 Impr ved Start up th Use MOS R with C 18 3rd amp 4th Leg provides VBZ ampVB3 Point 7 Subthreshold and Modera39 Subthreshold 12 AV I1 E IseAUT IR 11 156 AU L 1 L 2 1LN RLN E f2 R f2 I VS is proportional to the thermal Voltae Vs R1 RLN Elna E R Is 2BnuT2 PTAT Current Ln f1ff2 f1f2 ratio typically 4 or 8 Lnn Point 7 Subthreshold and Moderate Inv Moderate Inversion M1 in subthreshold and M2 AV 0V Ie lR L 1 S in Subthreshold AV 0 I2 E ILN21e A ILN21eAUT L 2 S L 2 S atVGs VT f gt115 f ZISLNZP Ln mm f1 f2 LNZ2e R LNZ2e4 IR gt 4 Rgti 1 VS is proportional to the UTZ Caution VsRI RIs LN22 I 2snUT2 20 Point 7 Subthreshold and BJTs Moderate Inversion M1 in subthreshold and M2 AV 0V 391 I2 VBE1 V352 IRB I 11 Isley quotU in BJTs or VBE quot39UT IRBnUTLN L inUTLN L Is1 Is2 U AE U U 1 n T LN 2 TLN3 T2 RB AE1 R3 R3 M1 M2 Q1 8 S m AE IPTAT 7 Cunth I Proportional To Absolute Temperature R B 8A5 RB 21 I proved 22 and BJTs v 16 16 Point 7 Subthreshold MOS n 39L Kkq quot14100085 VREF or Band Gap Reference 12 I VBE1 VBEZ IRB VBEnUTLJVL 1 1 GRBnU s RB CTAT L T s1 quot39UTL z Ljvg 2 AEI RE RE 1 PTAT RB VREF IPTAP ICTAPM Rm L RB L RB 5 Q1 02 35 8 AE aVREanUT ML AE2 6U M6VDI RB 6T AE 6T L 6T aUT z0085 aVDI z 16 6T C 6T C W 0 23 For zero TC 16 16 nLnKkq nLnK0085 Substrate o well diodes or lateral BJTs or MOS 24 l R 5va 12 R V4Nm l 42 xwLILL kp Ve Z 10uA R 1l mMm WLLL 39 J h ng l dIIIIeI whim 4qule El T Point 10 Use of Long channel 4x mx4xwLlLL I ll regions Cascode m2 4 minyLme o Decreased 1f and thermal noise 4 s I quot quot l 0 Improved matching 5 0 Increased VA o PSRR improved 0 r0 and gain 0 Choice of cascode type depends on application circuit and best VA 10uA eg 10 4 VB4 I VB4 4waL 8 LILL Inter digitate 4 Lm lt 55 Wequot lt 024 gm 10ms kpn 150uAl A VDD gt v11 4mquot L Distribution I Long Channel Wlesgt l is proportional to p Cox IR AV2AR gmzlAVzAR mm 2 gm2 R0 25 gm is set by R I R 3va 12 R VgnNm R 1gm m ohms VB4 I Point 11 What do you want at I 3 gm V2quot 10uA have 4xwlpl L quot reg39 quots lnterdigitate 2 PTAT bias WW39J LL Constant gm I quot39 f fd39 pl 4 Constant AV or Constant Vpp miquotquot39 quot 4 Wins 12 onstant gain is not feasible in Subthreshold VAUr 1 s PTAT provides constant gm or constant BW in Subthreshold I I 4stIL n L mm 89 m 10uAlieg gm K U but PTAT bias current in subthreshold is 10 WI 4 T 4stlLs f1 n U E IzLN T MWLI 200fF fZ R L L 4xWLIL NEE I Inter digitate 4 Lequot lt 55 L L I w lt 024 R biased Square is constant gm or constant BW gm 1oms an 150uAl VDD gt IV Wequot Wle nn What about Moderate InverSIon s gt 26 R Increase c Increased Power but faster Point 12 Be aware of slow bias nodes All regions To Circuit VREFeiHI W 0 quotSlow is relativequot 0 Add extra C low 2 long recovery l Trim Active is best but not low power 0 Nice use of low VT devices Trim Pot Engineering 27 CCCD Workshop 2003 Lund Oct 23 WEAK INVERSION IN ANALOG AND DIGITAL CIRCUITS En39c AVittoz CSEM Centre Sulsse d Electroquue et de Mlcrotecnnlque SA JaquetrDroZ lCH 2007 Neucnatel Switzerland eric vittozcsem on o Behaviour and model of MOS transistors in weak inversion 123 0 Examples of analog circuits 0 Exploratory analysis ofweak inversion logic 45 E WWI 2cm Qi VTo Weak inversion page 2 MOS TRANSISTOR DEFINITIONSI nchannel A VD D B il39v nJ p local substrate symbols width length of the channel gate capacitance per unit area kTq 26 mV at 3000K local nonequilibrium voltage in channel channel voltage quasiFermi potential of electrons at source end of channel V vs at drain end of channel V VD local mobile inversion charge in channel electrons gate threshold voltage for VO CSEM E Vittoz 2003 Weak inversion page 3 DRAN CURRENTI VD 0 Given by ID B dV With BZHCOX VS Cox strong inversion slope factor n 12 to 16 v v aquot weak inversion 2nUTexp Z exponentlal OX T umobility VV L ll Q ICOX VG39VTO 39 V 0 Vs VD V V MEG T0 Pinchoff voltage n 0 Weak inversion already possible for VSO if Vglt V70 quotsubthresholdquot CSEM E Vittoz 2003 Weak inversion page4 DRAIN CURRENT IN WEAK INVERSIONI vertical axis magnified QC OX QCox lo CSEM E Vittoz 2003 Weak inversion page 5 IFORWARD AND REVERSE CURRENTSI GigCOX QBCOX QBCOX Drain current ID forward reverse current IF current IR V VS VD VD t IDVGVS VD FVGVS FVGVD IF IR 0 Drain current is the superposition of independent and symmetrical effects of source and drain voltages basic property of longchannel transistors independent of current 6 Transistor saturated if IRltltIF then IDIF CSEM E Vittoz 2003 Weak inversion page 6 DRAN CURRENTEXPRESSION IN WEAK INVERSIONI VP39V VP39VSD QCOX 2nU7e T ltlt 2nUT thUSI IER 3 e UT t 0 Definition specific current of the transistor IS 2nBU72 10 to 300 nA for WL 0 Introducing VPE VGVT0n and ID IF IR this yields VG39VTO Vs VD IDISe nUT e UTe UT forIFandIRltltIS IF IR CSEM E Vittoz 2003 Weak inversion FORWARD CHARACTERISTICS IN WEAK INVERSION I page 7 VG IDIDOequot UT eFT eUT VS 0 output VGVS const ID NF 1 0 7 0123456 A 7 l5 saturation VD39VS UT VD39VS ID1e39 UT minimum VDSSat 0 transfer from gate Vs VD const exponential slope 1n CSEM E Vittoz 2003 m where IDOIS e39 nUT 0 transfer from source VG VD const log D DO 3 UT Ls IDe UT exponential slope 1 Weak inversion page 8 ICONTINUOUS MODELS WEAKSTRONG INVERSION I a From charge analysis 7811 IFR FR 1 S VPVsp F U7 2 cannot be inverted to express IFRVP VSD VP39VSD 2UT gt 91 b Interpolation formula T R n2 1 e S Both converge asymptotically towards IFi VP39VSD IS e UT for VPVSD UT weak inversion 2 IF R VP39VS D for VPVSD UT strong inversion IS 2UT 0 Only 3 parameters Vro n inside VP and IS or B to model the current from weak to strong inversion CSEM E Vittoz 2003 J Weak inversion CONTINUOUS MODELS WEAKSTRONG INVERSION I page 9 FR th 3 T 102 W 5 1 VP VGVT0n 5 ID IF R 0102 weak 104 m 20 O 20 4O volggge UT 0 De nition Inversion coefficient IC the larger of IFIS and IRIS weak inversion IC 1 moderate inversion IC 2 1 VDSsat2 stron inversion IC 1 9 2UT CSEM E Vittoz 2003 J Weak inversion page 10 I TRANCONDUCTANCE FROM WEAK TO STRONG INVERSION I 0 Transonductance gm from gate in saturation weak inversion asymptote gmlDnUT modela g 10 gm2BIDn nUTImTO8 D 06 04 02 0 weak moderate strong39 3 I 001 01 1 10 100 quotDIS 0 gmID decreases with increasing inversion coefficient IC 0 gmID is maximum in weak inversion CSEM E Vittoz 2003 Weak inversion exponential min VDssat max gmID gmD linear page11 SUMMARY OF FEATURES OF WEAK INVERSION 0 Largesignal DC model VG39VT0 1 ZQ IDISe nUT e UTe UT translinear circuits and log domain lters 2 max Ionloff for given voltage swing intermodulation in RF front ends t It max intrinsic voltage gain min39 98 6 V0 89 min input noise density for given ID quot39 m39n gate capac39tance max bandwidth for given kTC and ID 2 t min input offset voltage max output noise current for given ID max current mismatch 1 gm 39ndependent on L dominated by VTmismatch A2ALT0 nU HUT D T Low speed fTs 21tL2 CSEM E Vittoz 2003 Weakinversion page12 EVOLUTON OF C WITH SCALEDDOWN PROCESSES 0 Scalingdown of process dimension scaling by factor k all voltages decreased by k except U 7 analog circuits VDSSat must be decreased by k thus VDSsat2 2 IC decreased by k digital circuits VB decreased by k thus 2 Con VEn m decreased by k2 0 Weak inversion approached for constant temperature T VDSsat 21tL2 weak inversion with L100nm fT gt4 GHz 0 Transition frequency fT increased by k CSEM E Vittoz 2003 Weak inversion page 13 LOWVOLTAGE CASCODE IN WEAK INVERSION 2 VDSSat 4 to 6U7 per transistor All transistors in weak inversion with B2 14 B3 P and B5 M substrate 0 Model in weak inversion yields I V031 UTIn P 1 2M for P M 8 I VDS15UT thus V02 10U7 sufficient to saturate T1 and T2 CSEM E Vittoz 2003 Weak inversion page 14 IEXTRACTION OF UTAND CURRENT REFERENCEI 1 V T 3 T6 T4ET3 source 1 l 2 sink TZEKT1 T5 1 V T1 R VR Q unstable 1 0 For T1 and T2 in weak inversion VR 522 UTnK 0 Selfstarting if leakage of T2 larger than that ofT1 CSEM E Vittoz 2003 Weak inversion page 15 CURRENT GENERATION WITHOUT RESISTORI 0 Resistor replaced by transistor T3 in conduction 10 39 T5 T3 T4 T7 and T5 T1 T3 and T9 in strong inversion with 38 AB9 A 1 to have T8 in conduction Ii T2 and T1 in weak inversion with 32 K51 yields I 2nBSUAIn2K I33An2K 0 Reference current I proportional to specific current I38 0 Useful to bias transistors at inversion coefIC independently of process 0 If mobility T392 then compensation by U I l3 independent of T CSEM E Vittoz 2003 J Weak inversion page 16 I MOS TRANSISTOR OPERATED AS A PSEUDORESISTOR I 1112136 Consequence of basic property ID FVS FVD 0 Networks of transistors with same gate voltage are linear with respect to currents thus equiv for currents to a resistive prototype with G1RS ground in res prototype correspond to saturated transistors example of application currentmode linear attenuator eg R 2R 0 ln weak inversion linearity of currents even for different gate voltages with G1R VG I I SIeXp n UT CSEM E Vittoz 2003 Weak inversion page17 simple example of pseudoR network in weak inversion I CALCULATION OF HARMONIC MEAN I 1413 ground O N DJ J GN GN GN 0 k GN INV Wk 4 5 Gk Gk Gk Qi1llfIGk 0 air 61 WANG V V resistive prototype pseudoresistive version 0pseudoground 1 Series combination of G G 21Gi harmonic mean 1 Ihm Same volta e across G and 6 thus I g 21H N 0 Can be used as a fuzzy AND gate CSEM E Vittoz 2003 Weak inversion page 18 ITRANSLINEAR CIRCUITS I With bipolartransistors With MOS transistors in weak inversion 1617 VGI 39 VSi 2VGI 39 VSi 397LL i 1 I VGi Ii and 39 directions OfBEi 0 If and are alternated then pairs of equal EVBE EVBE VG gt VGin for each pair I and then VBEI39 UTIn SI 0 OthenNise separate wells connected to sources to impose V3 0 any sequence E VG both sides of equation E 0 Precision degraded by VTo mismatch CSEM E Vittoz 2003 Weak inversion page19 BASIC CONSIDERATIONS FOR WEAK INVERSION LOGIC I 5 supply voltage 0 Dynamic power consumption den fC AV VB lo ic swin 0 Weak Inversion model can be rewritten as g g ks IDIOGnUT 16 nUT exponential in VGS with maximum gmID thus minimum swing AVfor given Ionoff hence minimum den for given off VT0n1VS with I0 IS e39 nUT adjustable by VS 0 Assumptions on process 1 Threshold VTO close to 0 VS cannot be too negative 2 Triple well true twin well separate local p and n substrates adjustment of IO by V3 for n and pchannel CSEM E Vittoz 2003 Weak inversion page 20 ISTABLE STATES OF omos FLIPFLOPI 0 Simplifying assumptions nnnpn 0n0p0 V invener 0 Normalized voltages vk VkUT I p T 8 gt 02 Vi C V0 g 6 39 v T v V 8 lg V 396 2 4 E 2 39C c 2 cu bistable for VB gt 191 UT C E V aow 95 swing for V3 4U7 0 2 4 6 8 normalized supply voltage VB CSEM E Vittoz 2003 page 21 Weak inversion STATC CURRENT AT LOGIC STATES 0 Since VL VBVH gt0 static current lstat at each state is larger than l0 12 I stat 1391 r 09 08 1 2 4 6 gt 8 normalized supply voltage VB 0 Istat lt4 above 0 for V3 2 4 the difference can be neglected thus 0 Static power Pstat 2 IOVB CSEM E Vittoz 2003 Weak inversion page 22 STANDARD TRANSITIONS IN HOMOGENEOUS SYSTEMI Chain ofinverters I 2Td I VH V02 V04 V06 V08 VL lgt lgt lgt lgt lgt lgt lgt lgt 4 i i 3 V Von Vin1 O1 0 1 2 3 normalized time tTO 0 Characteristic time T0CUT0 0 Transitions become standard after a few stages 0 Normalized delay time TdTO only depends on V3 and n CSEM E Vittoz 2003 page 23 Weak inversion DELAY TIME FOR STANDARD TRANSITIONSI Td 70 0 Approximation 01 7dECVB E CVB Ion I VBnU or log e39VBnUT 001 d 3 4 5 6 7 8 9 1011 forcalculofPStat normalized supply voltage VB gt 0 Td decreases approximately exponentially with increasing VB CSEM E Vittoz 2003 Weak inversion page 24 PROPORTION OF SHORTCIRCUIT CHARGE FOR STANDARD TRANSITIONS 3 4 5 6 7 8 9 1O normalized supply voltage VB gt 0 Shortcircuit charge Qsc lt 14 capacitor charge QC negligible thus dynamic power den 2 fQCVB 2 fCVE 39 static power Pstat StatVB E IOVB CSEM E Vittoz 2003 Weak inversion page 25 POWERDELAY PRODUCT 0 De nition duty factor or 2f Td g 1 proportion of time during which the gate is in transition 2 0 Then total power P den Pstat gt P v230c2 e39VBn d PTd T 10 002 5 T g 8 n 16 01 390 2 O Q 6 E gt 2 4 005 5 2 003 C F 001 E o 0003 0 2 4 6 8 1O 12 normalized supply voltage VB gt 0 den dominates for large or gt min VB for min PTd 0 Stat dominates for small 0c gt increase V3 to increase Ionloff CSEM E Vittoz 2003 J Weak inversion POWERFREQUENCY RATIO 0 By reusing 0c 2f Td Plf CnUT2 normalized total power 1000 gt 100 A O Pf CnUT2 VBn21 e39VBn INEd uf9KBfa Y IE1 V x 4 1 m 10 x 0394 63 77 parameter or x 1 P x 194 K a 2 1O3 P dyn 63 JQ 1 2 4 6 8 1O 12 normalized supplyslope factor vBn gt 0 VBOpt and Pm increase for decreasing 0c At P min i P dyn P stat Increasing IO does not allow to reduce VB significantly for Td const 0 For or gt 5 power reduction by gt20 compared to den at 1V CSEM E Vittoz 2003 14 page 26 J Weak inversion page 27 MAXIMUM SPEEDI 0 Since ng and lonmaxg Con IS inv coeff spec current thus Ion V C Td 39 E B mln Con 0 Limit of weak inversion Icon 21 thus Process C Tdminweak VB E 0 Higher speed can only be obtained by entering moderate or strong inv CSEM E Vittoz 2003 Weak inversion page 28 EFFECT OF ENTERING MODERATE AND STRONG INVERSIONI using continuous model of ID AVGSBTO HUT 0 More voltage swmg needed C param to obtain Ionloff E IonOff 5 20 from continuous current model 8 gt o 101 1 1o1 102 1 quotonquot inv coeff lCon 0 Degeneration of logic states V VB4 n1 reduction of logic swing large increase of static current stat loss of bistability more supply voltage needed O Nwh o 1 2 3 4 Ic0n CSEM E Vittoz 2003 J Weak inversion INUMERICAL RESULTS 0 Simple inverter replaced by 3input NANDgate approx equivalent to inverter with L 3time that of nch transistor C 6time that of min inverter includes CinterconnectC2 4 U CB page 29 parameter min channel length equiv spec current equiv load capac specific energy Pf for oc1 VB4UT denf at VB1V fmaX1 for oc1 and VB4UT P min at fmax2 ID0min for 0t001 and VBOpt6nUT fmaX2 for oc001 and VBVBOpt process A process B unit 180 nm 200 400 nA 4 fF 42 aJ 44 aJ 146 022 fJ 4 fJ 500 MHz 022 256 MHz 325 563 nW CSEM E Vittoz 2003 Weak inversion page 30 I PRACTICAL CONSIDERATIONS AND LIMITATIONS I 0 Lowvoltage power source should be proportional to UTPTAT need for powerefficient adapter from higher supply voltage 0 Asymmetry pn asymmetry may result in speed reduction 0 Mismatch dominated by threshold mismatch SVT may result in speed reduction proportional to 8VTVB 0 Short channel effects should not drastically degrade the results 0 Gate leakage current should be alleviated by very low VB 0 Adjustment of IO oer to required value control by V3 with charge pump in loop 18 ngt1 needed no SOI corresponds to threshold adjustment unavoidable at very low VB 0 System architectures and applications CSEM E Vittoz 2003 Weak inversion page 31 SYSTEM ARCHITECTURE AND APPLICATIONS 0 Duty factor or must be maximized to reach minimum Pf where f is the average transition frequency thus avoid idling gates contrary to traditional CMOS culture new architectures needed maximally active gates of minimum speed max delay time Td particular problem with RAMs short Td but sparse activity how new constraints should result in novel solutions partition the system in blocks of comparable or and Td optimum VB and I0 for each block separate IO control 0 Maximum frequency much lower than for strong inversion best applicable when no high local speed is required mparallelize de but same power if same or m units with Pm digital image processing CSEM E Vittoz 2003 Weak inversion page 32 CONCLUSION 0 Weak inversion permits very low supply voltage VB approached with scaleddown VB IC V5 limit for scaleddown VB 0 Analog VBgt1OUT 250 mV provides maximum gmID bipolarlike behaviour can be exploited in new schemes 0 Digital VBgt 4UT 100mV transistor not a switch but a current modulator Ionloff new architectural approaches for max duty factor or ultimum asymptotic limit for low powerdelay 0 Low speed but keeps increasing with 1L2 in scaled down processes CSEM E Vittoz 2003 Weak inversion page 33 REFERENCES 1 EVittoz and J Fellrath quotCMOS analog integrated circuits based on weak inversion operationquot IEEE J SolidState Circuits volSC12 pp224231 June 1977 2 EVittoz quotMicropower techniquesquot in Design of VLSI Circuits for Telecommunications and Signal Processing JEFranca and YPTsividis Editors Prentice Hall 1991 3 CEnZ FKrummenacher and EVittoz quotAn analytical MOS transistor model valid in all regions of operation and dedicated to lowvoltage and lowcurrent applicationsquot Analog Integrated Circuits and Signal Processing Vol8 pp83114 1995 4 RM Swanson and J DMeindlquotIonimplanted complementary MOS transistors in lowvoltage circuitsquot IEEE J SolidState Circuits volSC7 pp 146153 April 1972 5 E Vittoz quotWeak inversion for ultimate lowpower logicquot to be published in LowPower Electronic Design ed C Piguet CRC Press LLC 2003 Chapter 16 6 E Vittoz C EnZ and F Krummenacher quotA basic property pf MOS transistors and its circuit implicationsquot Workshop on Compact Modeling WCM MSM2003 Febr 2327 San Francisco pp 246249 Slide of presentation can be downloaded at wwwnanotech2003comWCM2003htmlSlides 7 MA Maher and C Mead quotA physical chargecontrolled model for the MOS transistorsquot Advanced research in VLSI Proc of the 1987 Stanford Conference MIT Press Cambridge MA 1987 8 A Cunha et al quotAn MOS transistor model for analog circuit designquot IEEE JSolidState Circuits vol33 pp 15101519 Oct 1998 9 H Oguey and S Cserveny quotMOS modelling at low current densityquot Summer Course on quotProcess and Device Modellingquot ESAT LeuvenHeverlee Belgium June 1983 10 HJOguey and DAebischer quotCMOS current without resistancequotIEEE Journal of SolidState Circuits vol 32 pp 1 1321 135 July 1997 11 KBult and GGeelen quotA inherently linear and compact MOSTonly current division techniquequot Dig ISSCC Tech Papers February 1992 pp 198199 12 EVittoz and XArreguitquotLinear networks based on transistorsquot Electronics Letters vol29 pp297299 4th Febr 1993 13 EVittoz OPseudoresistive networks and their applications to analog collective computationO Proc MicroNeuroO97 Dresdepp163173 14 T Delbchk quotBump circuit for computing similarity and dissimilarity of analog voltagesquot Proc of International Joint Cnf on Neural Networks vol1 pp I 475479 1991 15 B Gilbert quotTranslinear circuits a proposed classi cationquot Electron Letters vol11 p 14 1975 16 A Andreou and K Boahen quotNeural information processing IIquot in Analog VLSI Signal analInformation Processing M Ismail and T Fiez editors pp358409 McGrawHill 1994 17 EVittoz quotAnalog VLSI implementation of neural networksquot published in the Handbook of Neural Computation Institute of Physics Publishing and Oxford University Press USA 1996 18 V von Kaenel et al quotAutomatic adjustment of threshold and supply voltage for minimum power consumption in CMOS digital circuitsquot Proc IEEE Symposium on Low Power Electronics San Diego 1994 pp7879 CSEM E Vittoz 2003 J Time Domain Frequency Domain Circuit Modes Example C Hutchens Chap4 Handouts EM Measurement errors quantization noise Thermal 1f Phase noise alternate form of thermal and f C Hutchens Chap4 Handouts Noise is just another signal error like CMRR and PSRR 1 as 40 dBlDec 1If Corner White 01 1039D 10 13901 1 02 13903 13904 165 Root Spectral Density Key concept Thermal or White noise Constant value ie 1 uV le 1f noise vnf f KVf ie 32 quHz Vno 1V2 ff lznw C Hutchens Chap4 Handouts 3 Definitions vmms 1m mt dt11 2 Imms 1m inza dtim PdiSS Vnrms2 1 Q 1 ohm for simplicity SNR 10 Log Signal PwrNoise Pwr even if R i 1 9 it cancels SNR 10 Log Vp22 me52 SNR 20 Log Vp 2 mes dBm Refencing of signals to 1 mW or 2236 mV across a 50 Q resistor Types of noise Thermal 1f quantization distortion and EMI We are concerned with only thermal and 1f in this context C Hutchens Chap4 Handouts 10 bit ADC EX Find the SNR of a sine wave which spans the full scale range of a 10 bit ADC assuming a perfect ADC and all other noise sources have been properly managed VFS 2828 V Quantization SNR 20 Log VFs22VFs2 where n is the number of bits or 10 SNR 20 Log stzvznstzn 12 20 n Log 2 20 Log 62 SNR 602 n 176 dB 619 dB Note All electronics Buffer amplifiers Track and Holds Comprators etc must preserve this SNR by being at least 6 to 9 dB down C Hutchens Chap4 Handouts 5 Thermal and 1f noise generators are assumed to be uncorrelated Therefore V2no V2 V2n2 V2n3 V2nn and likewise for noise currents Inca Vn l v Vn2t t EX if two noise sources have uncorrelated voltage of 5 and 10 uVs respectively the total noise generated is Vno 5E62 10E62 112uV This is a Stochastic problem C Hutchens Chap4 Handouts 6 1 as 40 dBlDec 1If Corner White 01 1039D 10 13901 1 02 13903 13904 165 Root Spectral Density Key concept Thermal or White noise Constant value ie 1 uV le 1f noise vnf f KVf ie 32 quHz Vno 1V2 ff lznw C Hutchens Chap4 Handouts 7 WT or t ant vmt C vnot C L V2no J I V2ni l EX V2 is white and has a root spectral density of 20 nVHz Find the total noise from DC to 100kHz Assuming a Brickwall filter 105 1o5 v2no l Ajoa v2ni l 1 202 dfi 4x 107 W2 0 0 Note input noise terms from multiple sources can be combined Math before or after filtering lf Ajoo were a 1st Order filter the it would be weighted as follows I fx 112 fo where fo 121 R C Know Now repeating the above example for a 1st Order filter v2no l Ajoa v2ni l n2 202 dfi 207 x 107 W2 C Hutchens Chap4 Handouts 8 Ip Observation a function proportional to 1lx results in equal power over each decade For 1f noise the noise total noise power doubles ever decade BW increases by 10 and x VznozIAGOJMVZni l 1 1f dfi Lnff10f Ln10 23 Never Open the BW any wider than is essential to achieve the desire task to avoid degrading performance by added noise Know and understand This is a matched filter problem C Hutchens Chap4 Handouts 9 uVNHz 20 7 vnt 20 7 20 1f 1f Corner L White 20 uVNHz 200 r Vnu 20 W 20 C Hu 10 102 103 10 10B 107 tchens Chap4 Handouts Piecewisze calc of noise Pwr 10 N21 1 200112 df 184 x 105 W2 1 103 N22 1 20 2 df 36x 105 W2 10 1o4 N231 20 f1O3 2 df 133x108nV2 1o3 10 N23 1 i2001 f105 2 df 588 x 109nV2 1o Vonrns 775uV rms Quick Est 2002 712 f0 V2002 712 105 793 nVrms Vonrns 10 Resistors V2Rf 4kT R Thermal 1K9 40 nVHz Rm Temp W Diodes 2df 2q ID Shot rd rd Vt nID No noise do rd E Irma BJT Fi 2q 398 KIBf ICIIBGwN V2if 4kTrb1gm mt lm MOS 2if 4kT 23 gm shot V2if KWLCoxT 1f h Vn1t Active MOS device currents can be W C converted to a2 equivalent input voltage by diViding by gm k Boltzmans Constant Commit to memory vziTo KWLCoxt 4kT 23 gm Understand the difference BJT vs MOS amp resistors C Hutchens Chap4 Handouts 2 Assuminga RC I 39 39 Vin Vout 9 EX v2ni is white filter Find the total noise f 00 v2noLP i Ajoa2 olv2ni df where Ajoa 11 jffo T 0 J feff 752 fo where fo 127 R C and k Boltzmans Constant Vin Vout 7T 1 sz kTc v2noLP M2 k TIC or For a 1 de Cap the noise floor is at z 64 uV As a perspective 1VI214 61 uV OBSERVATIONS In dependent of BW a 1 de Cap preserves a 61 uV noise floor To increase the BW the only alternative is to decrease Rs inc gm or V den MOS switch size 12 C Hutchens Chap4 Handouts NF 0 A For a FET assuming gate J dBB m current is 0 and 1f can be R 1 e 391m10uA neglected areful 4 rB 100 3 100 2 V2i6qf 4kT 3 Afgm JFET Is R0 0 This fails under NF SN S SNASNS 1 NA NS RF considerations NF 1 v2ieqf R I2ieqf 4kT R where Vzier 4kT rb 1gm IZier 2Q Is KIBf lcIBGmN Jthe der NF wr t R cRHmaqetis wmgn m Vt Ice MB 1 2ICQ rB Na 13 Determine fKnee For a MOSFET assuming gate current is 0 4kT 23 V Zieq 2 I gm Thermal N0se 10 1f mgDec uVNHz K 32 1lfCorner 2 f I V n1ff W 1f Noise White 10 Setting both noise terms equal and solving forf 1039D 10i 01 02 03 164 13905 f 3KfKPAV fKnee Z 2 Cgs4Tk 8CoxL Tk Increase L to reduce fknee C Hutchens Chap4 Handouts 4 Noting that ZEfTA gs fKnee Proportional to fTA Analog fTA 3KPAV SqLaw fTA M amp velsal f TA 4 7T39COX L27 47rCoxL And substituting gmCgs 7rKffTA Knee ZTk in ALL REGIONS of operatiod39t uVNHz 11f Corner White C Hutchens Chap4 Handouts 01 105 mi 13901 13902 13903 1 04 1 05 f A c y 1 vznxf K WLCoxf 4kT 23 ng x 12 5 Ivonan gm1 ro where x 12 Ivonanl gm3 390 Where X 34 Tail noise gain is negligible gm52 gm3 V0 quot40 V Careful ONLY true for Small signalll v2onT 2gm1 r02 v2n1 2gm4 ro2V2n3 Total Output Noise gm IRMS addition 1glquotlus superposition Vzieqn 2V2n1 2V2n3 gm3 gm12 For the white noise term To referto the input divide by diff pair gain v eqn 1613 kT9m1 kTgmg 9mg l9m12 Interpretation gm 0C WL A V therefore make W1 W2 as large as possible since L will be restricted by BW or gain also A V 16 C Hutchens Chap4 Handouts 1 V2ieqn 2V2n1 2V2n3 gm3 gm12 V2ieqn 2 Kn WI Coxf1 2 Kp WLCox Z Mn Alp Vzieqn 2Cox f Kn W L 1 nup L1K3 W1L23 C Hutchens Chap4 Handouts n ch Typ dominates 1f noise for L1 L3 and AV is Typ 100300mV at lengths lt 025um Inc L3 reduces the second term as long as OTA BW can be maintained input noise is independent of W3 Inc W1 helps both 1f and white noise Longer L1 increases noise at a faster rate in the second term than reduced in the first 17 Integrating from f1 to f2 V2ieqn 23 Kn W L 1 MnHp L1K3 W1L23 where a 1 Cox Ln f2f1 Note a 1 Cox Ln f2f1 for f2 10 f1 23 Cox Constant power per decade and approximately 72 dBDec increase Every extra decade of 1If bandwidth hurts 10X more power loss of gt1bit of DR Thermal noise will be greater still C Hutchens Chap4 Handouts 1 8 Symbolic Input equivalent thermal noise Symbolic Input equivalent 1f noise Solve for the Knee frequency Compare to the diff pair by finding the ratio of the thermal and 1f noise of the folded cascode to the diff pair Assume all devices are beta matched andboth have the same GBP equal CLs Which gives the lowest noisewatt Which gives the best gainwatt Which gives the greater output common mode rangewatt Which gives the greater output swingwatt P9P C Hutchens Chap4 Handouts LOCOS Process Flow 025 um 801 0r SOS 2 NMOS Devices 2 PMOS Devices 1 Cap Full Dielectric Isolaticns of Devices Dr C Hutchens Device Symbol plus Parasitics Pa asitics Tenth Year 80 taught at OK STA TE Now used by Most IC manufactures except Intel Recent AMD production Starting SOI Material 200 to 300 mm Dia Wafer 900 AthalonsWafer X 100 Wafersrun 3 runsday 270000 chips 10 Weeks 70 days to completions 19 Million chips or 1 Billion StressRelief Oxidation Initial Implant Establish known baseline Set nominal n or p Substrate doping level Nitride Deposition Silicon 450 A Nitride SiOZSi Etch ISL mask NOTE Nitride protects th 8181an reglon from Si Island to be 0x1d1z1ng 1n the next I oxidation step FOX I Multiple photoresist E PhomreSiSt E Islands f0 Transistors LOCOS Oxidation Note increased height of FOX Si HZO Heat SiO2 8102 22x45 nm S1 S102 045 Rat1 Si 7115ng 3 m f v U mi Etch Nitride Stress Relief Oxide Initial Oxide Deposition Capacitor function gate oxide growth Dry 02 heat Thermal Oxide difqu time99 temp825 dry02 press100 hcl0 difqu time10 temp825 nitro press100 hcl0 G Cap Implant DF mask Depletion mode N MOSFET SD Implants SD Photo resist blocks doping when energy level is set appropriately SD 39SD Gate to be HHHHH HHHHH If milligram PWELL Implants 2X NMOS Threshold voltage Nominal and High Screening oxide 50 A deposit oxide thick0005 divisions3 Channel Doping for NF ET implant boron dose6e12 energy8 tilt7 rotation0 nominal N NWELL Implants 2X PMOS Threshold voltage Nominal and High Screening oxide not a thermal oxide 50 A deposit oxide thick0005 divisions3 Channel Doping for PFET implant phosphor dose6e12 energy40 tilt7 rotation0 nominal P Gate Oxidation TOX in Cgs 1 Remove screening Oxide 2 Grow thermal gate Oxide Snm gate oxide grown difqu time27 temp825 dry02 press100 hcl0 diffus time10 temp825 nitro press100 hcl0 TOX J Poly Deposition and Implant nploy Set Gate work function Threshold Voltage implant phosphor dose150e15 energy40 pearson diffus time5 temp825 nitro pressl00 implant phosphor dose150e15 energy20 pearson diffus time2 temp750 nitro pressl 00 POL 1600 A Poly Deposition and Implant pploy Set Gate work function Threshold Voltage implant bf dosel 00e15 energy45 pearson difqu time5 temp750 nitro pressl00 implant bf dosel 00e15 energy25 pearson difqu time2 temp750 nitro pressl 00 implant bf dosel00e15 energy15 pearson POL 1600 A Poly Etch and MDD IMPLANT typical 0f4 1 Set Gate geometry L the 025um this process 2 Reduce punch through implant arsenic dose40e l 3 energy15 tilt45 rotation0 amorph latratioll 0 latrati02l 0 implant arsenic dose40el3 energy15 tilt45 rotation90 amorph latratioll 0 latrati02l 0 implant arsenic dose40el3 energy15 tilt45 rotation180 amorph latratioll 0 latrati02l 0 implant arsenic dose40el3 energy15 tilt45 rotation270 amorph Drain latratioll 0 latrati02l 0 Gate Oxide 850 A typical 0f4 Spacer adds to CGDO of model Deposit Spacer Oxide 850 A ratedepo achinePECVD oxide deposit achinePECVD time85 cvd deprate100 stepcov060 Etch pacer Oxide 1050 A and TOX 50A etch xide dry thick0090 silicon dry thick015 Spacer Oxide 850 A Overlap Cap and birds beak r a I Gate Gate Cobalt Silicidation of Silicon D S and Gate Decrease Resistance SD and Gate to 46 ohms sq deposit cobalt thick16 nm divisions3 Gate diffus time35 temp550 nitro press100 Gate i Si 5102 BOX 1450 A Process Simulation Normal NMOS TomPlot V2E15R II P D FHEV VtEWV weir Toots mum Propertiesr Heir Aim ATHENA 3mm mm mnspZSSOLNZsh39 32mm 2 1mm mnsp2580LN25quot Gate p 01y 3393 quotmquot 39quotquotSFZSS LquotZSquot quot492 v 7137mm quot492 yinHa n24 4186 in ma mm OX1de Spacer TOX SD CoSr quot Diode Junction Vice Chang Si Island i BOX S ub strate x x nnnnnn r 1mm inn I I I I I I I I MiliiiIiHIiiiliiil nnznmnusnm an an an ms nu n2 an n1 n2 an no as Mlcmns Mlcmns Mlcmns This is the ONLY properly scaled diagram in the presentation Process Simulation Normal NMOS PD vT 045 ID VDD33V 14mAum NGate 6E18cm3 PChannel 1E17cm3 NLDD 3E18cm3 LOV 13nm Lov gt23Tox1 RLDD 5000 ohmssq Note1Chan et al wwVIvHIn Process Simulation HVT NMOS FD vHTN 095 ID VDD33V 11mAum PGate 2E19cm3 PChannel 2E15cm3 NLDD 8E17cm3 LOV 20nm Lov gt2 3Tox RLDD 10k ohmssq Process Simulation Normal PMOS PD vT o42 ID VDD33V 051 mAum vGS o5112233 PGate 3E19cm3 W W NChannel 39 5E17Cm3 PLDD 3E18cm3 quot L0V 12nm LOV gt23Tox 39 quot RLDD 10K ohmssq wj 39 Process Simulation HVT PMOS FD vHTN 096 ID VDD33V 044mAum NGate 2E20cm3 NChannel 2E16cm3 PLDD 8E17cm3 m LOV 20nm Lov gt23Tox W RLDD 20k ohmssq 39 4L3 Feedback E ViS VoS I3S 6S 1 VoS 6S A8 2 Sub 2 into 1 and rearranging As 1 ASBS 3 Vis Km V06 KS C Hutchens Chap4 Handouts 1 Feedback Let Bs be CR or high pass C F 55 SCRJ1 SC F C Hutchens Chap4 Handouts if KS A 1 ASBS 3 KSf0f A gtoo 4 Feedback pole becomes zero 4L1 T T Intentional Feedback Most often neg 1 Vis Assume infinite input impedance and 0 output impedance M B 2 24s K 2 1 AsBs Zs ZFs For B resistive or capacitive R1 g Ks 1R or Ks 1C F I Conclusion accuracy and high gain are important C Hutchens Chap4 Handouts 3 Review from Le control systems A quotOpen Loop Gainquot B quotfeedback factorquot X V or AB 5 quot Loop Gainquot T K a quotclosed Loop gainquot X0K A i1KMl X1 1AB B 1T 1T feedback term Xf tracks Xi with error signal e where beX gtX 1T asTapproachesoo C Hutchens Chap4 Handouts Intentional Feedback Con39t f W5 Benefits for Design 0 Gain Desensitization Reduction of Distortion Partial In loop noise suppression Broadbanding Impedance adjustment Concerns o A must be gtgt K or 1IAB lt settled error 0 Excess phase may result in instability or oscillation C Hutchens Chap4 Handouts 5 Distortion and Noise Errterm if i Xis Xos B Err can be due to tanhx of BJT X2 of MOS injected from P8 or device intrinsics 1 interstage 2 input X0 AXl BXOM1 EW X0 Atanh xi B x0 tanh391XoA Xi on X AA1Xierr 1 X Err xiBx0aXoAxoA3 XoA5 0 1A1AB B quot A1 quotMust Consider the source of error C Hutchens Chap4 Handouts 6 Distortion and Noise N i991 Noisez niss if Xis 03 From MGF 1 noise at the input output of B and input of B appear as signal AA Xin1 2 HighAi andAgoodfor X A1 141A feedback 1 141 A B 3 Input distortion is limited However Output distortion Is a concern quotMust Consider the source of error C Hutchens Chap4 Handouts Broadbanding Ts BsAs or MGF loop gain As is BsAs 1 A SBS Let Bs B and A003 ADC1jmwA KS KUw ADC K 1ADCB 1AADCB 1AADCB JwA1 AWE new BW aoA1 BADC B o BW mAand B 1 BWmA mAADc mA1ADc C Hutchens Chap4 Handouts Gain Bandwidth Product KjaK 1Alt1ADCB Does ADC M K M 1 B ADC Expanding K equals ADC on ADC 03A GBPA True in this case C Hutchens Chap4 Handouts Gain Bandwidth Product ADCGZ aA G1 G2 A NuieKdapandsnanmbnth 47102 1R2JR GBP BW z wAA 2GBPA C1 C2 C1 C2 GB M g C2 wA C1 GBPA K GBPA C2C1C2 C1C2 K1 BW same as for inverting Case However GB is less by approx K1K unity GBP is 50 less C Hutchens Chap4 Handouts Design Issues of a noiseless OTA DC accuracy is 1AB ltlt allowable error ls sampled noise v ltlt allowable error 1 Settling error ltlt allowable error m lt 1 LnQ m LLn2b1 wsdB V 3113 err I Full power Bandwidth Egt Z fop acceptable Common mode range acceptable C Hutchens Chap4 Handouts NuleKdependsoanarbuth GEPA 11 Gain Bandwidth Product errr v Let Y1 G sCl yF GF sCFand sCL K 1 2 4 8 and 16 Accuracy 00125 Settling time 25nS Determine C and BWsdB Avol GBP and gmeff Assume a noiseless Fully Differential Cascode Amp and that CL is equal CIIK Plot your results for Avol GBP and gmeff verses K 12 C Hutchens Chap4 Handouts Specifying an OTA I L ACE 777777777777 quot1C E gt z fop 77fquot 1 V 1 lt WM 0 Ln2b1 K1EI w3dB err w3dB What we know Accuracy 2n bits eg 213 or 00125 33V process Vp m 11 V Vrms m 0707V BW 20KHz fs 44KHz K closed loop gain 1 1AB gt 800125 640000 GBP gt K KK1 fs 2103 In 2131 12 44 KHz 96 14 MHz Ceff C CL C 00 CF C Hutchens Chap4 Handouts 45L J TT 4 9 Chapter 6 Advanced Mirrors Bias and 0 Ms ADVANCED MIRRORS BlASNG SINGLE SIDED OTAS FULLY DIFFERENTAL OTAS C Hutchens Chap 6 Handouts 1 Advanced C urrenl Mirrors Assume all Drain Currents and Transistor Lengths lt e and W4 W1 and W3 W2 39 Select W1n2 W4n2 W3 W2 and W5 W3n12 Now Veff Veffs Veff2 AV Avs n1 AV AV1 AV4 n Ves V04 VG1n1Av vTN VDSZ VDss V05 n AV VTN AV Now VD1 gt AV1 AV2 2 AV Finally VDs4 gt AV4 n AV Therefore VDs4 V03 39 VDss AV VTN 39 AV VTN C Hutchens Chap 6 Handouts 4L1 T T Wide Swing Constant gm Bias Ck r 1113 39M 39 m MID y quotV213 Lungquot I I I M15 Mla IM1 MBI J Mj39 az39 III113 m 1 lM4 L E M12 Ema i CasaccdeBias SmupLM EiasLnnp W1 W3 W4 W24 4W5 W12 W13 W15 W16 W17 C Hutchens Chap 6 Handouts 3 Wide Swing Bias 0f Cascade ths 1 W6 W7 W4 W24 ISink W4Wm4 ISource WGWm7 Bias Stringold Cascogink amp source C Hutchens Chap 6 Handouts 4 45L J T T Boosted Mirrors and Cascades WES Im B oosted Mirror Boosted Amp 1 0 5913 Wigs m3dB F3 gms cgs Av 1 3 gm H2 AC3 A sAm1f1 1 s 9 Emits IEIAS is assumed ideal C Hutchens Chap 6 Handouts gill Wide Swing Enhanced output mirror 41 w IE 3 W M3 W I I I 3M1 Wilt IIJII 139 M1le roI39LA H492 9 Vo gt 2AV VB VB is derived form the previous Bias circuit IB and 4B are cascode sources derived from the Bias Circuit The feedback loop M8 MA and M4 provide the impedance boost B results in an offset current at the drain of M4 C Hutchens Chap 6 Handouts Folded Cascaded using Wide Swing Mindr A P V131 VBZI Vin M1 21 W1 W2 W7 W8 W52 W8 W9 W3 W4 2W11 2W10 Av gm2Igout 5 CL 031 gm1lCL Where CL Cl Co Dvov gm72 Cgs7 Cdb9Cdb11 and gm1OCgs10 Csb10 Cdb4 C Hutchens Chap 6 Handouts 7 Example folded Cascade it Given CL effective 1de Acceptable noise floor gtgt 64uV rms V 25 PDISS lt 100 mW GBP 01666 GHz VPP 4V Select AV 0250mV Assume kp kn3 32uAF and set Cascode Current equal diff pair currents Set Recover current 130 of IBsettIe increase Slew Rate for l5 l6 lt l1 l2 lTotal 2 IB IT 2 lemme 6 I therefore I lt Pass2 V 8 2500uA gm GBP CL 166 MHz1de 166 uS I5 21 B AV12 gm AV1 43 uA Select 60uA W1 W2 L1gmAv1kporfor L1 2um Wgt 40 um Slew Rate l5CL 6OVuS Full pwr BW cop l5CL Vp gt 30 MHz Potential Constraints GBP Noise floor PDISS Gain Slew Rate Load and Supply voltage Phase Margin is always a requirement specified or otherwise C Hutchens Chap 6 Handouts 8 C urrenl Mirror 0 TA VBI El 2 I MAampB I Vin vin O M1 M2 3 I 1K M M3AampB 5AampB 4AampB Avdiff K gm1gout 5 CL CDT K gm1CL Where CL Cl Co Dnondom gms1KCgsB CdbsA be aware 0f gm72Cgs7A Cdb7B C Hutchens Chap 6 Handouts 9 Closed Loop OTI Errors F GBP fLJn f3dB f3dB funK1 K equal closed loop gain Slew RateFull power Bandwidth SR ItaHCLequ Avol Vos Noise input refered CMRR AvolAvcm gmdiffgmcm PSRR gmdiffgmxx where xx vdd vss and vcm for fully differential pair devices 033dB 3 Du C Hutchens Chap 6 Handouts 4L 1 T T iii 10 4L 1 T T Linear Sellinn Reviewed Closed Loop QT Vo 5CL39 CF 90 39 Vx S CF gm Vx 0 Vx 39VinC S Vx S 098 Vx 39 V0 5 CF 0 3 CFCl Cgs CFz1CCF 1 Closed loop gain K CllCF Clequiv CL CFCI CgsCI Cgs CF 0Du gmClequiv GBP Clequiv z CL CFCI CI CF CL 3 CI COsde B Du tset 1 Ln accuracy 1 Ln VFsAV 1 Ln VFsZ where E 1 033C153 and n is the desired number of bits of dynamic range C Hutchens Chap 6 Handouts 1 1 Fully Differential folded Cascade r VBI M Ii vml IL 6 V132 5 IE IE Me CMFB r M9 r C Vm M1 M2 j Vm I FLH Ago 39 V133 M11 M10 M V134 3 M4 I 21 21 I Note CMFB Ckz BW must be gt OTA BW I M7 and M8 have been split in two and total Cascode current must be C Hutchens Chap 6 Handouts 12 4L 1 T T FULL YDFFERENTAL CURRENTMRROR 0 it Avdiff K gm1gout 5 CL 031 K gm1CL Where CL CI Co wnondom gmB1KCgsB CdbsA be aware 0f gm7Cgs7A Cdb7B a compensation capacitor frequently must be added to CL to ensure an adequate phase margin C Hutchens Chap 6 Handouts 13 4L 1 T T FULL YDFFERENTAL CURRENTMRROR 0 if Avdiff K gm1gout 5 CL39 Dr K Qm1CL39 Where CL39 CI Co Dnondom2 QmS2KCgsB CdbsA anc Dnondom1 Qm7Cgs7A Cdb7B a compensation capacitor frequently must be added to CL to ensure an adequate phase margin C Hutchens Chap 6 Handouts 14 Avdi K 9m1gout 5 CL 031 K gm1CL Where CL 01 Co wnondom gmb1KCgsa CdeA whereb x is n and p for both mirrors a compensation capacitor frequently must be added to CL to ensure an adequate phase margin C Hutchens Chap 6 Handouts 15 4L 1 T T Commom Mode Feedback not shown 1K AM K 9m1gout 5 CL 031 K gm1CL Where CL CI Co wnondom gmx1KCgsM CdbCC whereb x is n and p for both mirrors a compensation capacitor frequently must be added to CL to ensure an adequate phase margin C Hutchens Chap 6 Handouts 16 M5 I Avdiff 2 gm1gout 5 CL Dr K gm1CL Where CL CI Co Bn Bp mnondom gmbCgsB CdbsA where x is n and p for both cascode pairs C Hutchens Chap 6 Handouts 17 4L 1 T T C anthious TmeCommon Mode Feedback sir ID5D2D3I8II8I2l N0teM1M2M3M4 AV gm1 gm2 2 and swing is limited by diff pair as well as linearity C Hutchens Chap 6 Handouts 18 4L 1 T T C anthbus TmeCommon Mode Feedback 1 Dada ngCo CL where Co 20de 0985 and x 235 GBP gt OTA GBP N16 T7 ID5D2D3I5II5I2l NoteM1M2M3M4M5M5M7 AV gm1 gm2 and swing is limited by diff pair reported linearity 001 Source degen proves improvement but swing is still limited to lt OTA swing 19 C Hutchens Chap 6 Handouts 4L 1 T T C anthbus TmeCommon Mode Feedback ii Voul N11 M 39V Dada ng2Co CL M8AampB MQMB where Co 20de 0985 and x 35 GBP gt OTA GBP VAchA1VTN15II5I2l NoteM1M2M3M4 M5M5 AV gm1 2 gm mgdB of follower ckt must be gtgt GBP of OTA Source follower drop can be severly limiting C Hutchens Chap 6 Handouts 20 gill C antnious TimeCommon Mode Feedback E at I Objectives I Wideband with out ringing PM gt 7590 degrees I Accept Rail to rail swing Typ gt OTA Vo peak to peak I High linearity Equal that of the OTA C Hutchens Chap 6 Handouts 21 4L 1 T T Contnious TimeCommon Mode F eea bac C8 14 to110 CC select C8 to minimize charge injection VBIAS Vocm 39 VB4 GBP SC Loop gt OTA GBP Switches to V0 must be Tgate C Hutchens Chap 6 Handouts 22 gill Current Feedback Amp if 31 32 33 34 C0 Compensation G1 G2 gtgt gmz gm4 and buffer Go is gtgt 31 G2 Vin From Vin Vn in closed loop operation Hal V0 VinR1 R2R1 39if R0Go 5 CC if G2Vo 39VinG1 G2 AOL R1 R2R11 R2C0 033dB 03t 3200 C Hutchens Chap 6 Handouts 23 Current Conveyor C Hutchens Chap 6 Handouts 4L 1 T T Current Feedback Amp 1 31 32 33 I34gm1gtgt G CO Com G1 G2 gtgt gmz gm4 and buffer is gtgt G1 G2 Dada ng2Co CL where Co 20de 0985 and x 35 GBP gt OTA GBP 24 CASCODE OTA Constraining Equations VBI VR N 7l M 0 Noise floor Cs kT kT2n32 gt VN VFS h Were C CgHCF and a is the topology and transistor weighting factor For the folded cascode above 7 takes on 39 quot A h the quot quot 39 L 39 39 his case gm1 would be replaced by gm3 VFS is the full scale peak to peak signal swing and n is the equivalent number of bits Note DR602 n Otherwise 1de is a nice starting place o Open loop gain AVOL ECEN 5363 PAGE 1 OF M 4 A m z VOL g 1V0 dHrlldAIf This approximation assumes all gm s and AVs in the signal path are approximately equal where goampg g2zampamp 8 10 8 10 I 0 GBP GBP gm1 MW gKPAVCm o Slew Rate 5211227fCLe Vpr 2 SRMM AVe 27Wpr Le Le or 2 fP lt I gml AVe AVe Z VPCLe Z VPCLE VP 0 Nondominant poles 7716 a d 6 2Cgs6Cdb9Cdb11 ECEN 5363 PAGE 2 OF 11 w d 8mm 10 Cgs10Csb10Cdb4 gmL a ndg Cgs8 Ca b6 Cds8 Design Approach Step 1 go to the application There is very little range in the choice of AV 1 25mV to 400mV other than subthreshold and one must select AV ie14 Volt and go to the application for o n the effective number of bits of DR ie 602dBbit o fp which sets the slew rate or the slew rate itself 0 033113 the application 3dB BW or GBP where GBP 03313 and i is the feedback fraction or factor Km A1ABz1B closed loop or application gain mm GBP 1rCL closed loop 3dB frequency Careful i gt 2 for inverting gains of 1 In the event that additional settling accuracy is required to n bits ie sampled systgmes then 03313 must be increased as follows w3dBCL H w3dBCLLn2nl which in turn push out the OTA GBP requirement 0 AVOL The open loop gain where Km A1ABz1B1 1ABwhere 1AVOL is the error term and V V 1AVOL lt2 OFltW ECEN 5363 PAGE 3 OF 11 Step 2 l A A 01 O 2n1 Am gt10 V P Use the dynamic range ie number of bits or required noise floor to calculate C and the required CLOSED LOOP gain to determine CF from the noise equation The minimum transistor width and minimum OTA gain Minimum gain is used to determine an acceptable L and must take into account 3 feedback factor C1 CF and CL from the application are know at this point From application closed loop gain and accuracy requirements nd AVOL Use the open loop gain equation to nd a minimum value for 7 Use A to determine the minimum L andor gain simulations to determine L This is very dif cult to do without real data When determining an acceptable L you must select a AVe L is now known at this point The Pellgrom numbers should be used to con rm adequate area for matching of Ws Cs and Rs or set the Ws and Cs as well This includes W1 W2 W3 W4 W5 and W7 Use fp the nyquist rate C39s C1 CF and CL from application and Vp from the application to calculate the D5 using the slew rate equation Use any settling requirements and required application closed loop gain KFB and CLeff to nd W1 from the GBP equation All bias currents are knownestimated at this time At this time you may have to adjust Wto maintain the desired AVe gain or signal swing From 1 noise3 offset and 4 GBP above there is a minimum value off W1 and from 4 above a minimum value on l5 All constraints must be meet All geometry estimates are knownestimted at this point Con rm the phase margin using the PM equation below While design is an iterative processes one must rely models as well as have a exible plan since the successful design space is very small compared to all possible parameter combinations ie transistor geometry combinations ECEN 5363 PAGE 4 OF 11 where typ D1 IDs and Cy is the total C at the nondominant pole node and CLeff is the total equivalent load at the output and X 275 700 PM respectively and CLT Cde Cde CL 700 PM should be a minimum across corners in most applications Step 3 Check first pass Use the remaining equations to confirm the acceptance ie CMR peaktopeak swing and location of the nondominate poles Note that in broadband design you will not be able to approach the process fT As a result you may have to seek out other process options abandon the design or scale back expections 0 CMR 5 VCMltVDD VBZ l 5 VCM39ltVSS VTVT3 53 VOMAX VOW SVDDAV5AV8 Or VOWSVBZ VTP VOMIN VOMIN Z V83 VTN VOMIN 2 53 AVS AVID ECEN 5363 PAGE 5 OF 11 Note it is possible to make M3 and M4 longer without harming the ac signal path significantly you will only increase the Cub term 0 Noise check CT 7 22n C1 gt 2 7 2 ViN VFS 12 VW 1l4kT23 gm12 2Eg ml 51 41le f 2 2 gm gm3 12 W 1 MmHairWig KPAV 12 VW s 4kT232LW3F1AV 4kTRmm r2 2 On many Occasions where W1 W2 W3 W4 and W5 W7 f feedbackfa ctor gm 1 Bandwidth 27 C W 12 12 VON 4kT23gm12 zL ML zLML mle Wamp Kgm3 Kgm6 2 27 CW 12 VaN kT23CW 2 26 23 1 4 le feedbacl factorm 12 VaN kT23CW 2 311 51 4 le feedbacl factorm gm gm3 0 Typical Geometry constraints W1 W2 are very close to We W7 W3 W9 W52 GBP transistor W3 W4 2W1o 2 W11 Ifyou choose to make m3 and m4 longerthe will not match 2W10 2 W11 but will be quotbetaquot related W W7 W3 W9 W52 PMOS mirror devices ECEN 5363 PAGE 6 OF 11 and W3 Wr4 are long channel recovery transistors D5 log Im Slewing currents You are now ready to start SPICE simulations ECEN 5363 PAGE 7 OF 11 Boosted Cascode Nested gainboosting cascode OTA Nested gainboosting OTA as shown in was proposed by 11 to achieve high gain The structure can be expanded to n levels to achieve gain as high as gm r0 Figure 412 Concept of nested gainboosting cascode OTA As an example 2level nested gainboosting OTA was used to investigate the power efficiency factor The small signal model ofthe close loop of 2level nested gainboosting OTA is shown in below The small signal model of closed loop 2level nested gainboosting OTA ECEN 5363 PAGE 8 OF 11 In the Figure above all the transistor output conductances are ignored Cm cm are the total parasitic capacitors at the transistor input nodes The nodal analysis yields following equations Vin V1 SC V1 SCp1V1 Vouz SCf gm1V1V2 SCp3 V4 V2 5sz gm2 V4 V2 gm3V2 V3 SCp4 gm4V3 0 2 V4 5sz gm4V3 0 V1Vouz SCf gm2V4 V2Vout SCL Assuming Cm is small enough to be ignored and Cr CCs f solving the above yields the close loop transfer function below gml 3bZ 11 as 3 cs s C V014 Cy Cf C5 CLeff 6133 bsz 031 1s fg39quot1 CLejf in CPICPZCP3 gmlgngm3 b CPZCP3 nggm3 CP3 c gm3 Where the dominant pole ofthe is given by gml de gm1 f 3 CL 7 CLsz CLeff There is one RHP lowest frequency zero given by 21 m iml f ECEN 5363 PAGE 9 OF 11 From the closed loop transfer function there are three polezero doublets in the transfer function at or approaching can This is similar to the foldedcascode OTA mam m where n 123 In order to move the doublets away from the unitgain bandwidth the boosted amplifier cannot be allowed to become too small as this will harm the settling time of the boosted cascode OTA The boost and their cascades are typically set to be one fourth of the main OTA Design Procedure Assume that we have 1 a closed loop BW objective 2 a noise floor requirement or SND ratio requirement 3 a full power bandwidth 4 a closed loop gain requirement 4 a settling requirement or you can determine it and 5 an offset requirement Select a AVE Use the DR or noise requirement to determine Cs where n is the number of effective bits of DR kT 2n32 gt 2 VNi VFS2 S Use the application closed loop gain K to determine Cf Adjust the value of C5 and Cf using gain accuracy requirements and the Capacitor matching coef cients Determine gm1 from the following gml f gm1 f CLsz 3013 CL 7 Cr CrtCs f ECEN 5363 PAGE 10 OF 11 Again as need or alternatively determine the required gm1 For a SC circuit the fads requirement as a result of the required settling time can be written as follows Ln2n32 Ln2n3Zf 2mg 27 239 gm1 fgdgiCL fo where fs 2ts is the sampling frequency and t5 is the sample and settling period or approximately 2 the sampling period and n is the number if bits of dynamic range Determine the minimum gms including gm1 from the noise floor or SND requirements using 4kT 1 a 1 gm1 LNL CsCgs Cf Cs Cf V quotamp f where Note a is a weighting factor for all devices contributing to the noise and the fact that CMOS device rarely follow the theory Using the full power bandwidth constraint and AVE to determine the tail current and again gm1 211 gm1 AVe 27rVPC Z VPCLe fplt Le Select the maximum of all calculated gm1s and using the doublet and a selected scaling factor eg 4 determine an L that places the double 4X gm1 39 f hIgherthan 3013 CL CL fC wdoubie m where n 23 ECEN 5363 PAGE 11 OF 11 and calculate the lowest frequency zero H gml Cf All rst pass device WLs can be calculated 21 Determine or confirm that you device areas are adequate to achieve all Vus matching requirements via the Pellgrom numbers As necessary scale all device Ws up accordingly Now is also a good time to calculate 1f noise and recalculate the equivalent input noise Determine the required boosting from L and the open loop gain requirement AVOL 2quot 2quot 2 MAWquot 1 AVquot AVOL gmll o z This approximation assumes all gm s and AVs in the signal paths are approximately equal AVOL The open loop gain equals Km A1ABz1B1 1ABwhere 1AVOL is the allowable error term and V P 2n1 1AVOL 1AVOLflt V orlt 2 Finally CMR and Vpp must be evaluated ECEN 5363 PAGE 12 OF 11

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