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# CMOS ANALOG CIRC DES ECEN 5363

OK State

GPA 3.58

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This 0 page Class Notes was uploaded by Louisa O'Kon I on Sunday November 1, 2015. The Class Notes belongs to ECEN 5363 at Oklahoma State University taught by Chriswell Hutchens in Fall. Since its upload, it has received 31 views. For similar materials see /class/232901/ecen-5363-oklahoma-state-university in ELECTRICAL AND COMPUTER ENGINEERING at Oklahoma State University.

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Date Created: 11/01/15

4L1 T T Review of System Theory Feedback Mason Gain Formula Zero Value Time Constant Blackman Impedance Formula Additional Feedback lssues Words to live by In analog design gain matching and feedback mater C Hutchens Chap4 Handouts 1 Where are we going Observations to look for age 1 88M Small signal model is symbolic good for insight But a Components are bidirectional b It isn t easy to go from SSM to gain mag and phase or impedance magnitude and phase We will attempt to keep it painless c Contains NO device geometry or model data 2 Block Diagrams 88 provide insight a ie feedback is obvious But ONLY if it includes ie ng 3 Using Mason39s Gain formula and Blackman39s Impedance formula you can go fron block diagram to Transfer and impedance functions 4 Transfer functions to Stability analysis 5 3 thru 4 provide DC gain input output admittance impedance dominant and nondominant poles and phase margin 6 These are in turn rewritten in terms of model parameters and geometry which makes them useful for design C Hutchens Chap4 Handouts 2 4L3 Feedback E ViS VoS I3S 6S 1 VoS 6S A8 2 Sub 2 into 1 and rearranging As 1 ASBS 3 Vis Km V06 KS C Hutchens Chap4 Handouts 3 4L1 T T Small Signal Modes CS I 74 0 Z W Writing f D 4mg 1 Out utnodee uation V 1C9 P cI I E T 7 Cf gm V93 0 gm1 Vi Vo gds ZLS V0 39 Vi 5 cf 3 where I is assumed ideal and ZLs includes Cam CL 2 Feedback node equation 0 Cgssvi Vi 293 Vi Vo 3 Cf Now sCf gm Ygs G As sCfgdyYLs S sCfngJYgs Ms sCf where ng gtgt CfS sCf ngJ Ygs C Hutchens Chap4 Handouts 4 SSM Con t 7quot 9 Assuming 39 0 2g of V0 0 WT 39 YsG39 gmgtgtgds Y ssC39 2 g g 1 L L V AAA 1C 0 I gmv E SC 7 g As f gm sCfgdSsCL C Bs s fs sCfsngSsGg G Then Ks 8 sCfCgSGg sCf gm C sC KsGs A Gs 5 g L 1AsBs 1 SCfgm sCfs sCfgdysCL sCfsngJsGg KsGs sCf gmlsCfngxGg lsCf ngx GglsCf CLgerlsCf ng sCf C Hutchens Chap4 Handouts 5 4L1 T T 88 Common Source Con t it Then Ks g sCf gmsCf ngJ Gg sCf ngGg lsCf ngJ GngsCf CL ngj scfiscf gmj Ks GgSCfgm lsCf ngJ GngsCf CLngJ sCflsCf ng Obsenations We have a third order system with a zero What is the dominant pole Source Impedance can cause rolloff and instability can occur DC gain from s O C Hutchens Chap4 Handouts 6 Common Source Assume Gg approching co and Cf ng ltlt CL or Cgs it How do we know when this is true ng 9 VB ls cf 0 v Zg Cf gml i 39 A Z Z S gm gds CL Vi I legs 1 s 7 T gm Vgs gds 7 Now substituting device parameters W5 3a 1S wCGDo AKPVZL1AV1 KPIVVLIAV 1 1 11 pole at gdS CL and zero at gm ng and GBP 0 gm CL We can now design a circuit with the latter C Hutchens Chap4 Handouts 7 gill 88 Common Source Con t sir Then assuming G9 is finite Ks Gg sCf gm lsCf ngJ GngsCf CLgdyJ sCflsCf ng We have a second order system with a zero What is the dominant pole Source Impedance can cause poor settling gds 363X10753 I 9075 X1074A e 13 Cgs 2333 X 10 F p 45455 ReZk nun Gg 00188 CL lpfarad RePk XXX k e 0 40 Cck 001pfarad OSkpfarad C Hutchens Chap4 Handouts 8 Mason39s gain formula Signal flow has a variable associated with a node equal to the sum of all the signals entering the node has a gain associated with each block between nodes Definitions Source input node signals flow only away Sink output node signals flow only inward Path continuous connection of branches from one node to another arrows in same direction Loop closed path in which no node is encountered more than once FonNard path a path connecting a source input node to a sink output node in which no node is encountered more than once C Hutchens Chap4 Handouts 9 Mason39s gain formula Definitions continued Path gain product of gains along the path Loop gain path gain of a loop Nontouching loops have no nodes in common C Hutchens Chap4 Handouts gill Mason39s gain formula E 1 P 1 9 Ks Zzpkwk XPIA1 P AP k1 Where p is the number of forward paths A 1 sum of all individual loop gains sum of all nontouching loops take two at a time sum of all nontouching loops take three at a time sum of all nontouching loops take four at a time Ak value of A for that part of the system that does not touch the kth forward path Pk path gain of the kth forward path C Hutchens Chap4 Handouts 1 1 gill Mason39s gain formula E 4 We assume only one input and one output at a time For the special case of zero nontouching loops which is frequently the case in CMOS VLSI 131PzPp l A KS P P P KS 1 2 p 1 4 5 g m 1 I l Where I is the gain of each nth individual loop C Hutchens Chap4 Handouts Mason39s gain Cascode Ex Vt 0L l m V gmb urls Note bdy is gnd Gate 0 ygbsVg s ngVg Vd SCgsVg Vs Source KS ysSVs ngm Vg gdsO s Vg gmVgs gmbVs Drain 0 vdYLs gds SCL stS ngdgmng vsgmb gds stS vgnga C Hutchens Chap4 Handouts I I E Mason 5 gain Cascode Ex Cont Note bdy is gnd Vg 2 ngdvd sC V Iygbsngd ngS1 gs s Source vs 2 is vggm ngs gdgvdyss gm gmb gdg ngs1 Drain vgltngd gm vsltgm gmb gds sts gt YLS gds SCL stS ngdJ Vd C Hutchens Chap4 Handouts Mason39s gain Cascode Ex Con39t NOTE All blocks are unidirectional Alternate feedback paths are from parasitics ms ngs scgd sch Gs Yss gm gmb gds ngS YL39SYLSgdS SCL stS ngd C Hutchens Chap4 Handouts Mason39s gain Cascode Ex Con39t 39i3 A V a 1 G S Partial Sanity Check Assume gds 00 Cds Cgs ng 0 YbS ggb s 8mm 8mm 2 gmgmbZL39ltsZslts R YL39ltsGlts YL39ltsYsltsgmgmb 1gmgmbzslts W ins gm W ms in sCLi Note as Zs approaches 00 AR approaches ZL39 We can always Xfer function from block diagram by inspection IT MAY NOT BE TRIVALH EXTREMELY VALUABLE IN OPTIMIZING CKT PERFORMANCE C Hutchens Chap4 Handouts Feedback loops All Loo re a node or touch each other 1 A gtB gtA 2 A gtC gtA 3 A gtC gtB gtA 4 A gtB gtC gtA 5 B gtC gtB Forward Paths ii gtA gtB gtvd ii gtA gtC gtB gtvd ele mg either path breaks all loops C Hutchens Chap4 Handouts 1 7 gill Mason39s gain Cascode Ex Con39t E Loop Gains Product of all loops T L1 gds Yssgmgmbgds ngS GSYL39S ngsgm ngs YbSGS SCgs Sng gmgds GSYbSY S ngd gm ngsgds gm gmb CSYbSY S ngdngd gm GsYbs L4 C Hutchens Chap4 Handouts gill Mason39s gain Cascode Ex Con39t Path Gains j a f gds gm SCds GSYLS 2 ngsngd gm GSYbSYLS Mason Gain Formula EXACT EQUATION P1 ARS1 L EPIJFLPZL L 1 2 3 4 5 A S gdsgmgmbstSYbsngsngd gm R GSYb S gds gm SCds hfbsgds SCgs SCgs ngSgmngdgdS gdsgmgmbstSngdgm 5ng 19 C Hutchens Chap4 Handouts 4L1 T T Mason39s gain Cascode Ex Con39t Mason Gain Now assuming that Cds 0 andor is part of YL bdy at gnd gds gm gmbYb S SCgs Sng ARS GSYbSY S gals gm gmb Ybsgds SCgsgm SCgsY S SCgs gm Sng gds gals gm gmblgcgd gm Sng Now we a 2nd Order numerator and a 3rd Order dominator Continue this effort by assuming Ybs equal zero or a large Cap what is the result C Hutchens Chap4 Handouts 20 gill Mason39s gain Cascode Ex Con39t MGF EX now assuming Ybs can be set to quot0quot in the band of interest Lest t large C L1 gdSYSSgm 877 gds SCgs GsYL39s L2 through L5 0 P1 gds gm gmb stS GsYL39s P2 nonexistent gds 87 gmb R s GltsgtYLltsgt gds gm gmb1gds Now Assuming gm gtgt gds and gs and gm gmb gm39 w39 s gm39sCs stJlgL gds sCL ngdJ gnfgdg AR S 2 g gm39 1 A s DC R gnfgL gds gnf gig gL C Hutchens Chap4 Handouts 2 1 Cascode Ex with device parameters gds MD gm z BAV gL gds MD CL n Cgs n aox WL gtgt ng and ng CGDO W AV A H Rs AVsa0xWL CJ 2CJ 22UD sCL gm39gds DC 1 I ARS N MD for a single transistor or ARS N HD for a caSCOde load Now if ii gmdiff vi and gL MDp feed by an up stream transistor vs N gmdi 2 2 vds AV N 21D a gm 1 AVW 22 C Hutchens Chap4 Handouts MGF and ZVT HW Using MGF determine the transfer function of the simple diff amp below Assume M1 equal M2 M3 equal M4 the tail current is ideal and Cdb ltlt Van Van R Rs V I W W va i ideal Cgs Determine the dominant pole Find the dominant pole using the ZVT method Compare the results You will need to write KNE at d1 d2 s1s2 C Hutchens Chap4 Handouts 23 4L1 T T Zero Value Time Constant gt Useful Method for determining the dominant Pole of circuits with quotnioi zer dominant poles The presents of a nearby zero causes 2 VT to fail Consider a circuit containing only G39s C39s resulting in poles p1 p2 pn 1 p rim rigw k1 k1 G k pdom where C is the value of the kth capacitor in the circuit and Gk is the value of the transco tance between nodes of the circuit that Ck is connected to Step 1 ID C39s Step 2 Solve for G or R connected to each C Step 3 Evaluate for the dominate 7335 pole a C Hutchens Chap4 Handouts 24 Zero Value Time Constant EX 0 Rg of Va 7T 1095 EHch Vi VW E T gm V93 Rg 32 Va Vi INv 1 g S C C1 3 J gm Vgs 7 Let 01 equal 095 c2 of and C3 CL39 Cdb CL G1 Gg by inspection as well as G3 gds Vgs 139ng and Vgs Vx ix gm Vgs ds Solving for vxix R3 rdy Rg Rg rm Rg ng ds C Hutchens Chap4 Handouts 25 Zero Value Time Constant EX 0 R9 of V0 Of 0 vi 1 s E I I CgS EHch Vi VW E T gm V93 Vu Rg 32 Vi N o i g S C 01 3 J T gm Vgs 39 PM z 1RgCgs CL39rdy Cfrdy Rg ng Pdo39quot z CL39rds Cfrds Rglu for Cf ng Typically 1 gs PMN fCL39rds d CL39 C Hutchens Chap4 Handouts 26 Bias Networ Va M2 7 CL Vi a Him C1 C951 C2 ng1 C3 2Cde C4 Cgsz C5 ng2 Assume ZL is ideal By inspection 91 Gg C Hutchens Chap4 Handouts C6 CL39 27 Bias Networ Va Vi gw am 92 Vgs1 39ix R9 Tm Vgs2 O39Vx ix gm39ix R9 Vx g gm VX ix g gm 2 g 2 v X 1 ng 93 g Vgs10 VgsZ039VX ixnggm Vx ix V ng 2ggm C Hutchens Chap4 Handouts 28 AMA 0 Vit 94 V952 39ix RB39 0 Vgs1 0 ix 39gm39ix RB 39VX VX g gm VX ix m g4 g g vx 1 ng B 95 96 Vgs1 0 V952 39ix RB39O Vgs1 0 V952 0 ixgz i g2 i g2 Vx g5 2 21 RBgl Vx g6 2 2 C Hutchens Chap4 Handouts 29 ZVTC Cascode EX Cont G ggV 2g 2 ngZ 1ngg 11 thru 16 N a g3 ggm 3 ZCdb ZCdb gd2 2 120 RBgl gv g l w 2 2 Dominant pole C Hutchens Chap4 Handouts Arbitrary SS circuit with at least 1 controlled source Assume the input is connected to another circuit Not OC or SC o Xi takes on a voltage or Current BIR states 0 Zab zabo 1 Tscl1 Tee 0 Where Zab is the impedance between ab with cont source removed 0 Select controlled source to make life easy 0 Tsc orXiI X where vabo and aXi is replaced with test source XX 0 To ain X where ibo and aXi is replaced with test source XX 0 gt 1 Control voltage pick anyone C Hutchens Chap4 Handouts BIR Cascode Ex Determine Z or Y out Assuming 29 0 in the band of interest z ab ZLsllrds zss Where YLS 5Cdb ng CL and Ys gdiff gds S Cdb Cgs TSC gt vab 0 and gm vgs replaced by vx C Hutchens Chap4 Handouts BIR Cascode Ex T Network 8m 8 quot T 2 SC ix vs vsgds g2 SCgs Cdbvs Toc gt iab 0 and gm vgs replaced by ix but vs 0 g2 gall gds C2 Cgs Cdb CL ng Cdb CL C Hutchens Chap4 Handouts BIR Cascode Ex Tquot Network ole gm vs 2 125 Vsgds g2 SCz g2 gdi gds C2 Cgs Cdb C L ng Cdb CL 1 gm Z 20 1T dj1 az ab so SCL H SC2g2 r S gdsg2sC2 Where from previous YLs sCL39 and Yss 92 5 C2 C Hutchens Chap4 Handouts 34 4L1 T T BIR Cascode Ex gm Ta 1 Z Z01T 2 rdsjl sCL H S02 2 gals g2 sCz Now for CL gtgt Cdb or Cgs and gdsl ltlt gdmz gdS approx equal g2 gdz gals C2 Cgs Cdb C L CL gm TSC ngs SC2 Sanity Check DC gm Zn 2 2rs 1 HMS 1 d 2 d C Hutchens Chap4 Handouts 35 BIR Hw Using BIR determine the impedance looking back into the 75 Wilson Current Mirror shown below Assume all devices are equal Try Using both gmz V952 and gma Vgs3 as the reference source Does it make a difference Van B ideal 9L2 M1 C Hutchens Chap4 Handouts 36 4L3 Feedback E ViS VoS I3S 6S 1 VoS 6S A8 2 Sub 2 into 1 and rearranging As 1 ASBS 3 Vis Km V06 KS C Hutchens Chap4 Handouts Feedback Let Bs be CR or high pass C F 55 SCRJ1 SC F C Hutchens Chap4 Handouts if KS A 1 ASBS 3 KSf0f A gtoo 4 Feedback pole becomes zero 38 r s wulp Nate bdy tS gnd Note bdy t5 gnd ii Vs gdsl ngm gdsVs 39 V0 1 ngm gdsvo Vs VoGL 2 Now for gdsl ltlt gdS and solving 2 for v8 and substituting into 1 G g L ds gds gm vogds gds 8777 3 then A GL gdS and B gds Neg feedback gdsl results in Pos feedback What does the ng and C918 path or Cdb path do C Hutchens Chap4 Handouts 4L1 T T Intentional Feedback Most often neg 1 Vis Assume infinite input impedance and 0 output impedance m Z M B 2 24s 1 AsBs Zs ZF s For B resistive or capacitive R1 g Ks 1R or Ks 1C F I Conclusion accuracy and high gain are important C Hutchens Chap4 Handouts Review from Le control systems A quotOpen Loop Gainquot B quotfeedback factorquot X V or AB 5 quot Loop Gainquot T K a quotclosed Loop gainquot X0K A i1KMl X1 1AB B 1T 1T feedback term Xf tracks Xi with error signal e where beX gtX 1T asTapproachesoo C Hutchens Chap4 Handouts 41 Intentional Feedback Con39t f Vi W s Benefits for Design 0 Gain Desensitization Reduction of Distortion Partial In loop noise suppression Broadbanding Impedance adjustment Concerns o A must be gtgt K Excess phase may result in instability or oscillation C Hutchens Chap4 Handouts gill Gain Desensitization E r6 Sens with A Sens with B Kzi1 1 i T a z B 1T B1T aA 1AB2 AA 8K 1 T AK AA 2 z 1AB2AA 1 AA 1 63 B 1T AB K A A1ABA1T 1AB g ampBZ1TampZamp K A 32A B 1AB quotHigh Gain and Price feedback C Hutchens Chap4 Handouts Distortion and Noise Errterm if i Xis Xos B Err can be due to tanhx of BJT X2 of MOS injected from P8 or device intrinsics 1 interstage 2 input X0 AXl BXOM1 EW X0 Atanh xi B x0 tanh391XoA Xi on X AA1Xierr 1 X Err xiBx0aXoAxoA3 XoA5 0 1A1AB B quot A1 quotMust Consider the source of error C Hutchens Chap4 Handouts Distortion and Noise N i991 Noisez niss if Xis 03 From MGF 1 noise at the input output of B and input of B appear as signal AA Xin1 2 HighAi andAgoodfor X A1 141A feedback 1 141 A B 3 Input distortion is limited However Output distortion Is a concern quotMust Consider the source of error 45 C Hutchens Chap4 Handouts Broadbanding Ts BsAs or MGF loop gain As is BsAs 1 A SBS Let Bs B and A003 ADC1jmwA KS KUw ADC K 1ADCB 1AADCB 1AADCB JltwAlt1 AME new BW 1 BADC B 0 BW mA and B 1 BW m DAADC mA1ADc 46 C Hutchens Chap4 Handouts Gain Bandwidth Product KjaK 1Alt1ADCB Does ADC M K M 1 B ADC Expanding K equals ADC on ADC 03A GBPA True in this case 47 C Hutchens Chap4 Handouts Gain Bandwidth Product ADCGZ aA G1 G2 A NuieKdapandsnanmbnih 47102 1mm GBP BW z wAA 2GBPA C1 C2 C1 C2 GB M g C2 wA C1 GBPA K GBPA C2C1C2 C1C2 K1 BW same as for inverting Case However GB is less by approx K1K unity GBP is 50 less C Hutchens Chap4 Handouts Output Resistance 1 Unity Buffer Thevenin snort independent voltage sources it 17 It thiGo vtAV2 0 Output Node Solving for itVt gout Gi Go1 A gout GOA or rout In general goutz GoAB Series fb gouty GoAB Shunt fb C Hutchens Chap4 Handouts Thevenin Output Resistance 1 Unity Buffer Thevenin snort independent voltage sources It Vt Gi Go Vt AV2 O Output Node Solving for itVt gout Gi Go1 A gout GOA or rout In general goutz GoAB Series fb gouty GoAB Shunt fb C Hutchens Chap4 Handouts 4L1 T T Impedance Transformation a Younger a quotquoti m Cousf f A mm the Wilson 39 M WW ckt The above ckt is very interesting from the perspective of drain 3 it is shunt fb or r0 PA 939 rd53 rdsl 0quot 90 gdsIilA us However from the source of 3 it is series fb See previous plate Note G0 gm without fb and A A and gout gmsuA Use BIR to provide both the above as well as the generalize for series feedback C Hutchens Chap4 Handouts CMFB Or Matching N and P MOS currents 1010quot CMFB What is the effect of mismatch between the PMOS current source and an NMOS current sink Effect of mismatch between N and P MOS device currents Verr due to the transistor mismatches in D1 and D2 is given by Vop In r0 A IRo Amplifier Review single sided R Amplifier Review pseudo differential a n if EEEJJ gt lt 4g EH Amplifier Review differential Common Source Amplifier amp CMFB b Fully differential FD circuits REQUIRE common source CS amps and commonmode feedback CMFB for proper operation Setting the DC value of the high gain typically output nodes FD amplifiers typically consist of CS circuits configured as differential pairs They model with similar properties of their singlesided counter parts plus CMR amp CMRR CS and CMFB amps are a key aspect of FD amplifiers Why CMFB j For the case of a FD amplifier with current source loads implemented by PMOS transistors the commonmode level isine ned Iquot defined Why CMFB I Fi M3 3b f o mmon Mode Level lquot l i 39 ITaiI ITaiI CM ths depend on how close DM3a and DM3b match BOTH each other and Inn2 Why Mismatch Hail2 is implemented by a NMOS source and M3a and M3b by a PMOS sink Given that we are expecting delta gtgm Vos DxKPxWL AVTWL encompassing the bias generator and OTA There is little hope of practical matching even excluding PVT temperatures As a result either one of both if M3 or Mtail enter triode WHY Why CMFB I Fi M3 3b f o mmon Mode Level lquot l i 39 ITail ITail The high impedance node DC Q points are difficultimpossible to set SingleEnded amp FF Op Amps and OTAs Amplifiers Small mismatches temperature process shift etc VQ approach VDD or VSS Tail transistor in triode or M35 in triode Soution negative feedback use in single ended circuits CMFB circuits are singled ended CMFB feedback circuitry fixes the DC th CMFB Solution negative feedback use in single ended Circuits CMFB Circuits are singled ended CMFB feedback Circuitry fixes the DC th Common Mode Level CMFB 0 characteristics of a FD Amplifier VODIF I I Desired Common Mode Set Level or th Max Gain Max Signal range CMFB Vocm is set by adding negative Correction Amp amp Sense th feedback circuit to maximize gain amp Signal swing of FD OTA FD Amp 1 V Correction Am VCMSET Conceptual CM FB Architecture Stabiity CL PHASE MARGIN for H1sH2sH3s lt 70 Avo Application driven Basic Operation 1 Sensing the output CM level Vocm Vo Vo Vdiff cho Vdiff cho cho 2 Comparison with a voltage reference ie VCmO VCM SET Feed back error correcting level to the ampli er bias circuitry 3 System Check for stability across corners CMFB Vocm is set by adding negative Correction Amp amp Sense th feedback circuit to maximize gain amp Signal swing of FD OTA b1 ltlgt2 Basic Operation 1 Sensing the output CM level Vocm lo lo ldiff lcmo ldiff lcmo lcmo 2 Comparison with a current reference ie IREF VCmO VCM SET T Feed back error correcting ransconductance Approach level to the amplifier blaS circuitry Conceptual CM FB Architecture 3 SYStem CheCk for Stability Stabiity CL PHASE MARGIN for across corners H1sH2sH3s lt 70 Avo Application driven CMFB CM sense CirCUits cho alvodif azvodif a3v0dif m F cho cho a11forA32 a 3 1 2 VLI Vo E21 1 7 7 F CMFB Correction Amp Circuits CMFB example v DiffAmp 39 A r CMFB example equired V VB v 39 Identical Arch V81 0 H 5 sDo in VB139 Local Bias gtVB2 Generator VBS gtVB439 VB4 g I b O 390 an n 39 i r chi gate Swwlch ch 01 CM V07 Vo Diff Amp Correction and CM Sense Amp

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