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by: Louisa O'Kon I


Louisa O'Kon I
OK State
GPA 3.58

Louis Johnson

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This 0 page Class Notes was uploaded by Louisa O'Kon I on Sunday November 1, 2015. The Class Notes belongs to ECEN 5263 at Oklahoma State University taught by Louis Johnson in Fall. Since its upload, it has received 28 views. For similar materials see /class/232904/ecen-5263-oklahoma-state-university in ELECTRICAL AND COMPUTER ENGINEERING at Oklahoma State University.

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Date Created: 11/01/15
I ECEN 5263 Digitial VLSI Design I Designing Large Transistors Gate Resistance In normal size transistors the channel resistance is so large that other parasitic resistances can be neglected Such is not the case with large transistors with large widths and small channel resistance lt w i T L For wide transistors the poly line forming the gate gets long so that there may be a signif icant resistance inside the gate which causes large delays for the gate voltage to propagate across the width of the transistor We can model this effect by thinking of the transistor as several smaller transistors in parallel with nonzero poly resistance between the gates SPICE does not include this effect unless you model it this way The transistors on the left representing the part of the big transistor that is closest to the incoming gate signal turn on and off faster than the transistors further to the right Thus the drain current is partially on until the gate voltage signal propagates across the transis tor poly line and only then does the big transistor fully turn on or off The poly line forms a RC transmission line the C is the gate capacitance which has the same Elmore delay as D gtC g 2 R Poly G W Rah C 2 g T C g 2T l p S CgZ and we will make the conservative assumption that the gate signal must get all the way across the FET to turn it on or off The two resistances can be de ned in terms of sheet resistances as L Rch RschVV R Poly R s PODZ Designing Large Transistors January 16 2009 page 1 of9 I ECEN 5263 Digitial VLSI Design I Note that the current charging or discharging the gate ows at right angles to the channel current which is why the poly resistance is proportional to W L Let us consider the effect that the gate resistance has on a full CMOS logic gate driving another full CMOS logic gate The fall time delay tdfn to turn off the nFET in gate 139 and the fall time delay td to turn on the pFET in gate 139 the rise time delay is similar can be calculated from the following equivalent RC delay circuit R ippoly td tdf CgiPZT Tcgipz Rinpol y tdfn I cgmzT TCgmZ C 2 g0 ln 1 df RU lnchCgiZ ln2 Cnode Cgip Cgin l dfn ltdfRinpolngin2 tdfp tdfRiPP01ngiP2 where tdf is the normal node delay to the gate inputs The extra delay due to the finite poly resistance is l dfn 4 1 df Rinpolngin2 Islp 4 tdf RxppolycgipZ and we want these extra delays to be much smaller than a typical gate delay 11g Designing Large Transistors January 16 2009 page 2 of9 I ECEN 5263 Digitial VLSI Design I Rinpolycgin n 1g Rippolycgtp T g l W C Rmmtam W C R WipL n mg L smoly L If we use F04 delay of about 30RschannelCgA2L2 as a typical gate delay and put in numbers for typical processes we have W m WW 0 1007 Wm Wip lt 307 Thus the width of the poly gate should be smaller than about 307 which is a much more severe limitation than the length of poly interconnect which must be less than about 2007 This is because the gate capacitance poly over thin oxide is about 25 times larger than the poly interconnect capacitance poly over thick oxide If we want a transistor with a width greater than about 307 we cannot design it as a single large transistor but as a parallel combination of smaller transistors Using the same kind of design style as our data path cells we might try something like but this has considerable wasted area between transistors and there is no room to run a horizontal metal line for the gate signal running the gate signal through the poly lines is too slow The usual design for very large transistors looks something like the following layout This layout saves area by using the same sourcedrain contacts for two adjacent small FETs Designing Large Transistors January 16 2009 page 3 of9 I ECEN 5263 Digitial VLSI Design I Contact Resistance The di usion contact resistance is highly process dependent but is usually in the range of 10 A 1009 This is the resistance of the minimum size contact When larger contacts are desired several minimum size contacts are used in parallel top layer metal 1 1 47 bottom layer diff If there are 71 contacts then can Reff n and we want this to be much smaller than the channel resistance Refchh R L lon RschVV RCOVIK N W RsachZX 2007 quotU n gt m Thus we only need one contact for every 607 of transistor width to make sure that the contact resistance is negligible This is many fewer contacts than we have been using one contact for every 47 Designing Large Transistors January 16 2009 page 4 of9 I ECEN 5263 Digitial VLSI Design I Diffusion Resistance Having only a few contacts signi cantly increases the resistance of the sourcedrain diffusions because the current paths are now much longer H S H can k We cannot use our simple resistance formulas since the current paths are not parallel Solving Poisson s equation for the current paths gives the following approximate resis tance for the part of the diffusion between each contact pair S c on 2 Rdi m 04 01 3 RS di We want this resistance to be smaller than the channel resistance between contact pairs 27 Rdiff RschS Con Scon04 OIIScon Rsch 2x 6x RS M R SW 0 60x24 i 2 120k 5 25x 30x Rs diff Sum lt 40 This requirement is slightly more severe than keeping the contact resistance small which allowed Sum lt 607 Diffusion Capacitance Reduction The layout style with fewer contacts and larger spac ing between contacts has an advantage in reducing the di usion area This can lead to a reduction in capacitance if the spacing is large enough H S mi gtI can CI Cdlm 1Z MMHm4xjWn4x6xFW Designing Large Transistors January 16 2009 page 5 of9 I ECEN 5263 Digitial VLSI Design I where n W S c 0 is the number of contacts Compare this with the old style n i 5x T Cdif Z 5W1 3W10xw For a capacitance reduction we want Cdi l lt Cdiij Putting in the numbers for a typical process gives Sum gt 87 There is a window for con tact spacing between about 87 and 407 in our process that allows for reduced diffusion capacitance without increasing the diffusion resistance signi cantly A design style that allows for capacitance reduction and allows for large effective transistor widths might look like the following D Designing Large Transistors January 16 2009 page 6 of9 I ECEN 5263 Digitial VLSI Design I Effective Channel Width When calculating the resistance of the dog legged gate count the corners as half a square of resistance or conductance as appropriate For example gate current channel current ew count runners count half square of half square of resistance conductance X39v Rpoly 11l11Rspoly 1 1 2 11 11 1 1 R channel 2 R Schanne1 In the performance optimization equations we have always assumed that the channel length is a constant 27 and we approximate the channel resistance as R Rschanne1 channel When the channel has doglegs as above the channel resistance formula no longer strictly applies but must be modi ed as shown above Rather than rewrite all of our optimization equations we can use an effective channel width We which is defined so that Rehannel Rs0hamel 27L Weff for the channels with doglegs in them For the example above 1 We 1 1 1 11 11 Rommel Rschannel27t 2 2 Rschannel 1 1 Weff 2x11 11 We 107 which allows us to construct a large transistor with the required width Designing Large Transistors January 16 2009 page 7 of9 I ECEN 5263 Digitial VLSI Design I Latch up Protection Large FETs are more susceptible to latchup than smaller FETs because of the large current magnitudes As with smaller FETs latchup is caused by dif fusions with contacts to power or ground becoming forward biased with respect to the well or substrate This is caused by excess current from switching transients being injected from the drain diffusions into the well or substrate and causing ohmic voltage drops in the well or substrate near the power and ground contacts p substrate Latchup is prevented by providing alternate current paths for the injected currents that do not go through the power ground contacts for the transistors One solution is to have a butting substratewell contact next to all power ground contacts as we did for small tran sistors Designing Large Transistors January 16 2009 page 8 of9 I ECEN 5263 Digitial VLSI Design I Simple butting substrate contacts do not work as well with the large folded transistors In this case it is probably a better idea to use guard rings Guard rings are much more effec tive in preventing latchup The guard rings must be contacted to metal frequently to avoid voltage drops in the guard rings n np k RR p substrate no poly here Frequent contacts are needed to collect current injected into guard rings Designing Large Transistors January 16 2009 page 9 of9 I ECEN 5263 Digital VLSI Design I Minimizing Delay in Complex Logic Circuits Minimizing Path Delay We would like to choose transistor widths to minimize delay but what delay should be minimized In our examples there are 2 delays for the inverter 4 for the NAND and 10 for the ORNAND The delay speci cations for most logic designs are that a certain block of logic should have a worst case delay less than some maximum allowed delay This is NOT the same as specifying a worst case delay for each logic gate Recall that minimizing the inverter pair delay gave different optimum widths than minimizing the worst case single inverter delay Instead we should minimize the worst case delay on all paths through the entire logic block Finding the worst case delay paths is a very dif cult problem for large circuits Consider a combinational logic circuit with N inputs We will restrict ourselves to chang ing one of the inputs at a time while leaving the otherN 1 inputs unchanged There can be a rising or falling edge on each input If there is at least one path from each input to at least one output then the number of delays Ndelays must be greater than 2N However there can be different paths depending on the values of the otherN 1 inputs This increases the number of possible paths by a factor of 2N391 2Nlt Ndelays lt 2NzN 1 NZN Recall our 3input OAI gate There were 3x23 24 possible paths which we considered previously Many of these potential paths were uninteresting in that no change in the out put occurred but we had to consider all possible paths to be sure that we had not missed one that could turn out to be the worst case delay path In general it is an NPcomplete problem to nd the worst case delay paths It is practi cally impossible to consider all the paths when N is large Instead the designer uses his intuition to pick the most likely candidates for the worst case delay paths A possible design procedure is as follows 1 Choose initial transistor widths near the minimum allowed 2 Simulate up to N2N times to nd the worst case delay If the worst case delay meets the design spec stop 3 Choose new transistor widths usually wider to reduce the delay along the worst case delay paths Go back to step 2 Atypical delay path looks similar to g 416 p 174 If there are several logic gates along the path it may take a large number of iterations of the design loop to meet the specs We need some way to speed up the design process We Minimizing Delay in Complex Logic Circuits October 12 2009 page 1 of 10 I ECEN 5263 Digital VLSI Design I can use our approximate delay equations to estimate the worst case delays which should be much faster than using a simulation like SPICE in step 2 Furthermore instead of just guessing new transistor widths in step 3 we can use our delay formulas to pick new widths in a manner which should converge to the optimal minimum delay solution There are two delays associated with each path through the circuit Just as for the single logic gates we can start with a rising edge or a falling edge At the next logic gate output the rising input produces a falling output and a falling input produces a rising output To be consistent with the single gate delay de nitions let as define a falling path delay to mean the edge that produces a falling output and the rising path delay produces a rising output For a path with N logic gates in it tdfPATH tdrN71tdfN tdrPATH i tdfN71 i tdrN For example the path in g 416 with 4 logic gates in it tdfPATH tdrl 512 tdr3 tdf4 tdrPATH td tdr2tdf3 Hm Both of these path delays must meet the delay speci cation for the logic block This is di erent than requiring the risefall delays to be the same for each logic gate Further more delays on other paths must also meet the delay spec This usually results in all the longest path delays being the same as the speci ed maximum delay Since the path delays are nonlinear functions of the transistor widths there is usually no closed form solution for the optimum transistor widths However this problem can be solved numerically with nonlinear optimization techniques We will study a few simple cases where additional simplifying assumptions yield a closed form solution This will allow us to gain insight into choosing near optimal transistor widths Multi Stage Buffer Example Suppose we want to design a multistage buffer out of a chain of inverters Cloadout Cloadin V invN invNl invl V The input inverter has an input capacitance of Cload n and the output inverter must drive the load capacitance C loadwut An inverter chain is often used to bulTer a large capaci tance C loadwut while making it look like a much smaller capacitance Clauden Minimizing Delay in Complex Logic Circuits October 12 2009 page 2 of 10 I ECEN 5263 Digital VLSI Design I With only a single input and single output there is only one path with two delays corre sponding to a rising or falling output The contributions to the path delays from each logic gate 139 are Isli tdm thri RoutriCloadi From our previous work we know the parasitic risefall delay and output resistance for the ith inverter thfi RoutfiCloadi 1 Wm i Wm Wmin Wmin rd 1K K At RC 1 f0 2 WW WW WW 0 t W W W W 7 t pt mm mm rd 7 1Kquot 2K At2 RC 1 m W120 W120 W120 0 l Let us assume that the wires connecting the logic gates are short enough that the wire resistance can be neglected but long enough that the wire capacitance cannot be neglected Then each inverter is loaded by the wire capacitance and the input capacitance of the next inverter Cloadi Cwirei i Cmui 1 From our previous work we know input capacitance for the i1th inverter W W 1 1 Cini71 m W pt C H1111 so that l Wni We 139 Wmin t 1K K At df 2 WW WWJ W W W mmRCwireiwC Wni Wmin W W 11K quot P At 2 WM C 1 W Cf KWminWniilWFIDAI P Wni W W W rm 1KW 2KW mmm PU PU W C i 2 wRCwirei i Wnii 1 i Wpi71 1KMWquot Hm C Wmm Wnuil WMFIQAI pt Minimizing Delay in Complex Logic Circuits October 12 2009 page 3 of 10 I ECEN 5263 Digital VLSI Design I The path delays are tdfPATH Z td i 2 lm 139 odd 139 even tdrPATH Z ElmW Z td i 139 odd 139 even The results are more clear if we transform variables to nd the optimum W and 21 where W W W t ni PU Zi WynWm so that Wi WW 7 zi1 7 i 139 WP zi1 C 1 UKWminwiil rm zi1 51KT At Cwirei tdri 7 Zi Wi t 2 girdi We want to minimize the path delays with the constraint that the risefall path delays are the same The method of Lagrange multipliers can be used for this constrained minimiza tion The optimal transistor sizes can be found by differentiating the weighted path delays with respect to the transistor sizes 1 cm 7 tdfPATH 1 7 tdrPATH 0 i d Elm tdPATH1 m tdrPATH 0 l d mlm tdPATH1 m tdrPATH 0 The last equation insures that the risefall path delays are equal Minimizing Delay in Complex Logic Circuits October 12 2009 page 4 of 10 I ECEN 5263 Digital VLSI Design I The weighted sum of the path delays is m tdPATH1 m tdrPATH Z Mdi u m dm iodd Z limtdfimtdri ieven 2 Z mlim td i iodd 2 Z limmftd i ieven i so that the optimum is found from 139 odd 1 0 d Wilm tdfPATH 1 7quot tdrPATHl 2 At 17mm Z 1 Zi1 11 Wi1 C 2 Wge K Wmin Wt1 7m17m Zil 2At Z Wi m17m2Z1 CAWWN Wt Zl C JFK WminWi71 WM limmZ21Zill Wi t 0 d mt 1 t E dfPATH mdrPATH t 2 mAt717m At 2 2139 17m 2139 iZTEZodd Forz39 even just interchange m and lm 2 C Wt limmZZ1 2KWmmwil WM mlimZLHZH11 Wi t m 2139 2limzzeven 2Zodd Minimizing Delay in Complex Logic Circuits October 12 2009 page 5 of10 I ECEN 5263 Digital VLSI Design I The results look less complicated if we write C KWmin WP1 r z39odd W W Wi1 C 1K Wmwi1 Tieven where 2 mlimZ Zoddl FE 0d limmZeZevenl H Recall that the output inverter must drive a load capacitance C loadwut E rCloadoutK WInin W2 C W1 Also recall that the input inverter input capacitance must be Cload n WN WminC Cloadin WN Cloadin Wmin C Although there is no simple general solution a closed form solution for the transistor widths in the multistage buffer is possible if the following assumption is made C wtret T K Wmin ltlt Wt1 This is a good assumptions for large transistors but may not be very accurate for transis tors near minimum size Then the size ratios are all the same except for the factor V Wi 7 1 r 1 odd Wi 1 1 Wi71 I even r Wt Minimizing Delay in Complex Logic Circuits October 12 2009 page 6 of10 WN 1 WN I ECEN 5263 Digital VLSI Design I rCloadout Wmin W1 CloadoutWmin rW2 C W1 rCload out Wmin W3 C W1 C W r loaCdout VainNeven 1 N odd Cloadout Wm C W1 Let us de ne the size ratio as S SE Cloud out W t 139 even i 1 Wmin C W1 1C1 dg t W1 Ev MC on Wmin S 5W I S S LW1LCloadoutW S3 C WN71N even 1WN71Nodd 2 LCloadmut W S C min mm DIN rN2 rNZCI d t W1Neven OHW Neven SN 7 1 mln rN712 W rN712 C W1 N odd Wm N odd Minimizing Delay in Complex Logic Circuits October 12 2009 page 7 of 10 I ECEN 5263 Digital VLSI Design I WN is the size of the input transistor rNZCloadmut T Wmin N even W ClaudinW N C mm VN712Cload out 74 C Wmin N odd rN2Cloadout N even SN 7 Cloadin rN712CloadoutN Odd Cloadin lN 12 C r Cloud out Neven loadin r171N2Cloadout1NN Odd Cloadin We nish by requiring the two path delays to be equal V deA39l39H drPA i H 7 2 2 Z hardmi Z Eltd n 139 odd t i even i Z zi111ltm Lag 1l11ltE At Z Zi i 2 W ieven 272 Z Oddzodd1l11ltsm iodd 20 2 27Z 1 Z Z M1zeven 1 1K rSAt even Neven 2 7 Z C lN AT oddZOdd1l1Kr12 loadgoutg At 2 Z odd 2 Cloadin 2 7 Z C lN 1Z evenzeven Kr324 Cload out At even loadin Minimizing Delay in Complex Logic Circuits October 12 2009 page 8 of 10 I ECEN 5263 Digital VLSI Design I 2 7 Z C lN oddZOdd1l1Kr12 loadgoutg Zodd 2 Cloadin 2iZeven 1 32 Cloadout lN Z l1Kr Z even even 2 Cl oad in N odd 2 7 Z 7 C lN N1 oddZOdd1l1K r1 1N2 load0ut At 2 Zodd 2 Cloadin 27Z 7 C lN N 1 Z evenZeven11Kr3 lN2 loadout lAt 2 even Cloadin 2 7 Z 7 C lN N1 oddZOdd1llK r1 1N2 loadgoutg 2 Zodd 2 Cloadin 12 7Zeven 1 371N2 Cloadout lN Z 1 1Kr 2 Zeven even 2 Cloadin There is no simple solution when N is odd but when N is even there is a simple solution 1 m 2 Zodd Zeven r l S Cloud out1N Cloadin Optimum S and N Instead of a xed number of inverters in the buiTer it is interesting to consider varying the number of inverters N to nd the number of inverters that gives the minimum delay for a xed loads C Dadon and Cloa out For even N SN Cloadout Cloadin C N1nS 1n load out Cloadin 1nCloadout N Cloadin 1113 Minimizing Delay in Complex Logic Circuits October 12 2009 page 9 of 10 I ECEN 5263 Digital VLSI Design I and the minimum delay is N 27 2 l tdfPATH tdrPATH 5TfA 1 1KSAt 1nCload out 1E1KSAt Note that the delay is proportional to the log of the load capacitance ratio if we choose N correctly We can now nd the optimum size ratio S from PATH 0 6S 1nCloadout C i lgadun 12 1l1 K SAt In S S 2J5 2 lnCloadout Cloadin 2 7 J5 JE1At 0 1115 2J5 1 1 1 7 1K S 10 lnSS2 i l K lnS 2S 1 This last transcendental equation can be solved numerically to nd the optimum S 318 forK 0 and S 359 forK 1 Any size ratio in the range 3 lt S lt 4 should give near optimal minimum delay Minimizing Delay in Complex Logic Circuits October 12 2009 page 10 of 10 I ECEN 5263 Digital VLSI Design I Simple Gate Characteristics DC In the following analysis punch through and body effect are neglected VA gt 0 VT VTo We will point out later when it is necessary to enclude these e ects The standard CMOS inverter Vdd S VGSn Vin V V VDSn Vout in out D VGSp Vin 7 Vdd S VDSp Vout 7 Vdd Gnd Inverter Voltage Transfer Curve DC VGSn VTn Vout V 7 V A I in 7 Tn Vdd a I saturation VD Sn VDSmm o E V 7 VTnEsatnLn i 39 out ViniVTnAnEsatnLn ohmlc nMOSFET operating regions V V Vin VTn gt 0 Tn dd VDSp VDSsatp V 7V Vini Vddi VTpEsatpr out dd V39inindiVTpiApEsatpr pMOSFET operating Regions VTP lt 0 Simple Gate Characteristics DC January 20 2006 page 1 of10 I ECEN 5263 Digital VLSI Design I Easily obtained solutions are available for regions A C and E Vin lt VTn gt nMOSFET cutoiT pMOSFET ohmic S X nonlinear R D V Vm 10m 0 gt IDn iIDpi IDquot 0 in cutoff l gt 0 2 VGSp 7 VTp VDSp 7 VDSp2 b t 7 u DP p 17 VDSpEsatpr gt VDSp 0 gt Vout Vdd Vin gt Vdd VTp Vdd39 lVTpl gt nMOSFET ohmic pMOSFET cutoff V I Vin I D a Iout 0 gt IDn iIDpi s lIDpl 0 in cutoiT gt IDn 0 VGSn 7 VTnVDSn 7 V SnZ but IDquot n 1 VDSnEsaan gt VDSn 0 gt Vout 0 Simple Gate Characteristics DC January 20 2006 page 2 of10 l ECEN 5263 Digital VLSI Design I Vin Vim where Vim the value of Vin at which output rapidly changes between high and low From regions of operation both FET s are in saturation IDquot IIDpl since Iout 0 5 5 EnVDSsamUGSn VTn EFTDssatp VGSp VTp 2 2 El Esaan Vin 7 VTn J EsatprVin 7 Vdd7 VTp J 2 7 VTn I lt39t Eiman 2 lVin 7 Vdd7 VTpl ApE satpr This cubic equation has a solution that is too complicated but there is a simple solution in the velocity saturation and pinch off saturation limits Pinch off saturation limit 2 2 nVin7 VTn 7 pVin7 Vdd7 VTp 2 Aquot 2 AP 7 positive J nAnVin VTn7 lipAA Vdd 7 VTP 7 Viquot quantities V nAnVTn yApVdd VTP m nAn HipAP This unique value of Vin is Vim Velocity saturation limit rtEsaanVin 7 VTn7 pEsatprlVin 7 Vdd7 VTpl rtEsaanVin 7 VTn7 pEsatpr Vdd VTp 7 Vin V nEsatnLnVTn 7 pEsatpr Vdd VTp m rtEsaan 7 pEsatpr Again this unique value of Vin is Vim Simple Gate Characteristics DC January 20 2006 page 3 of10 I ECEN 5263 Digital VLSI Design I Even though the general solution for Vim is very complicated we can nd a simple equa tion for the conditions necessary to adjust Vim from setting the drain currents equal we have to be whatever we want Starting again 2 2 El EsaanVinv 7 VTn J 7 EsatprVinv 7 Vddi VTp J 2 Vinv 7 VTn I lt39t Eiman 2 lVinv 7 Vddi VTpl I lApl Esatpr 2 pEsatpr 7 Vim7 VTn JUVMV 7 Vddi VTpl ApEsatpr n nEsaan Vim7 VTn dirtE39satrtL Vinv 7 Vdd7 VTP2 7 80x zvsat 7 80x Recall that lESmL 7 u L 7 2 thW so that everything cancels on the tax L H tax left side of the above equation except the ratio of the W s 2 EVE 7 Vinv 7 VTn JUVMV 7 Vddi VTpl ApEsatpr W vaiVTnAnEsatnLn Vinv7Vdd7VTp2 n This means that we can achieve any desired value of Vim by adjusting the ratio of the widths of the pFET and nFET in the inverter This will be useful later in several circuit applications of the inverter Summary Vout A CMOS inverter Vi I l Vin Vdd I Vin Vdd VTp I V m 171V Simple Gate Characteristics DC January 20 2006 page 4 of10 I ECEN 5263 Digital VLSI Design I Noise Margin Fig 228 p 99 Fig 227 p98 V out f Vou V0H Vdd for Vin lt VTn V VOH m OHmiIf unity gain points 7 V0Lmax Vout VOL 0 for Vin gt Vdd VTp VOL I Vin I VILIriaX l V d d I VTn i Vdd VTp I VIHmin Valid logic levels must have lt unity gain to avoid amplifying noise VILmaX VIHmm VOLmaX VOHmj11 depend on details of FET ID VDS curve NML VILmax 39 VOLmax NMH VOHmin 39 VIHmin quite large noise margins are usually achieved with CMOS gates Simple Gate Characteristics DC January 20 2006 page 5 of10 I ECEN 5263 Digital VLSI Design I Pseudo nMOS To reduce transistor count replace active pMOSFET switch network by passive resistor device A nonlinear resistor y A B Pseudo nMOS NAND CMOS NAND The electronic properties of the more complicated pseudo nMOS gates are similar to the pseudonMOS inverter Vdd S VGSn Vin 4 D V VDSn Vout D out VGSp Vdd Viquot l S V V V DSp outi dd Gnd Inverter voltage transfer curve V VGSn VTn out A Vin VTn Vdd I a I saturatron VD Sn VDSmm o E V 7 VTnEsatnLn out ViniVTnArrEsatnLn I ohm1c nMOSFET operating regions V gt Vin VTn gt 0 VTquot dd Simple Gate Characteristics DC January 20 2006 page 6 of10 I ECEN 5263 Digital VLSI Design I V out Vdd h VDSp VDSsatp o m1c V V 7 Vdd VTPEMIPLP outi ddi 7 V 7 V 7A L saturation dd Tp pEsatp p V m pMOSFET Operating Region VTI lt 0 Vin lt VTn nMOSFET cutoff pMOSFET ohmic Vdd Vow Idn 0 Iout 0 i gt iIdpi 0 gt Vout Vdd gt VOH Vdd Vin near Vdd nMOSFET ohmic pMOSFET sat Vdd S a E FL 7V 7V 2 IID I p sat p dd Tp J I4 D V P 2 7 VddiVTPAPEWPLP D r i a 7 Vin7 VTnV0ut7AnVZm2 Vin S IDni n 1 VoutEsaan 10m 0 3 IIDpl IDn Simple Gate Characteristics DC January 20 2006 page 7 of10 I ECEN 5263 Digital VLSI Design I Solving for V0 ut AnVMI7VI 7 VT iIDEi V 4 DE 0 2 m n nEsaan a n The solution to this quadratic equation is I ViniVTn IDI 2An1 DP nEsatnLn 1 7 1 7 out A I 2 D n nViniVTn I FIL nEsatn n If Vin is from the output of another gate then Vin VOH Vdd gt Vout VOL iID i Vddi VT P V 7 n rtEsaan 1 1 2AnIIDE 0L7 A 7 7 I 2 n MVWVT IDpl n n nEsaan l1 I D We want VOL ltlt Vddi VTquot L nEsatnLn gt LIDPIIIIZ m E ltlt 1 D n l V 7V L n dd Tn nEsaan The usual choice is in N N 4 n for pseudo nMOS not CMOS PseudonMOS logic is an example ofratioed logic Note this is entirely di erent than CMOS where VOL 0 regardless of the beta ratio Simple Gate Characteristics DC January 20 2006 page 8 of10 I ECEN 5263 Digital VLSI Design I Pass Transistors nMOS 0 V i i oating output is unconnected in Vdd JG L 7 0 S D Vout VGS Vdd390gtVTn 4 li gt transistor on i independent of Vow since ID steady state 0 gt VDS steady state 0 gt Vow steady state 0 gt nMOSFET good for passing 0 Vdd J VGS Vdd 39 Vout gt VTn Vdd D S Vout gt transistor on only i if V lt V V w I I out dd Tn As current charges capacitor voltage rises until transistor turns off gt Vow steady state Vdd VTquot gt nMOSFET poor for passing Vdd pMOS Vdd V i i oating output unconnected m page 9 of10 Simple Gate Characteristics DC January 20 2006 I ECEN 5263 DigitalVLSl Design I 0 L Vdd S D V VGs 0 39Vdd lt VTp I l gt transistor on i independent of Vow ID steady state 0 gt VDS steady state 0 gt Vow steady state Vdd gt pMOSFET good for passing Vdd 0 0 D S IVWI VGS039VouIltVTp 4 li gt transistor on only i Vout gt 39 VTp iVTpl As current discharges capacitor voltage falls until transistor turns off gt Vow steady state lVTpl gt pMOSFET poor for passing 0 Fig 231 p 102 series pass transistors Fig 232 p 102 transmission gate resistance Fig 233 p 103 tristate inverter Simple Gate Characteristics DC January 20 2006 page 10 of10 I ECEN 5263 Digital VLSI Design I Power Dissipation Chip power dissipation budget air cooled packages cheap lt 10Wchip heat sinks or cooling uid expensive lt 100Wchip Static Power Dissipation CMOS IDCmOSPDCEO There is small power dissipation from leakage currents Ileak lt luAcm2 Fig 435 p 232 Pseudo nMOS if pFETs always on V l on E i Ronp Ron n on off or two possible states for nFETs off on On average 12 of nFETs are on at any given time V21 1 1 gt 13 39 Vdd I 39 DC 2 0quot 2R0npR0nn for each gate and the total static power dissipation is 13 N ii DC gates 2R0npRonn where Ngam is the number ofpseudo NMOS gates Typical values are 01 10 mWgate Power Dissipation August 20 2004 page 1 of 10 I ECEN 5263 Digital VLSI Design I Dynamic Power m Fig 436 p 234 There are two components to the switching transient current 1 load capacitor chargedischarge through one FET 2 short circuit between power ground through both FET s Assume that the input risefall times are very fast so that both transistors are never on at the same time the short circuit current is negligible iii 3 Cloud T Cloud output low to high output high to low Vm I 0 T 2 T Vout t IF A t I Power is dissipated only in the transistors not the capacitor We are approximating zero current and therefore zero power dissipation in the nFET for 0 lt t lt T2 and in the pFET for T2 lt t lt T The average dynamic power dissipation is Power Dissipation August 20 2004 page 2 of 10 I ECEN 5263 Digital VLSI Design I 0 3 H T g0 itvtdt 1 T 2 1 T I V 611 I V 611 TJ Q Dp DSp TIT2 Dn DSn where dV IDp icloada 0M VDSp 7Vdd7 Vout dV IDn icloada 0M VDSn Vout Therefore 1 2 dV 1 1 dV 1 Pd Cloada OM Vddi Voutdt is TZicloada OM Voutdt These integrals over time can be converted to integrals over voltage as in the following 2 dV Vam z J 5 Walt J39 Vaultl 1 Vdd 1 0 Pd 540 CloadVdd7 V014tdV0ut iJ V icloadVouthout dd T 2 2 T is the switching period can be different for every gate Define f 1 T as switching frequency can be di erent for every gate 13d Cloadngf T total cap voltage switching with chang swing frequency ing voltage Power Dissipation August 20 2004 page 3 of 10 I ECEN 5263 Digital VLSI Design I Note Power consumption reduced by l Vdd2 gt reduce voltage swing reduce power supply 2 only the load capacitance counts not capacitance on power ground lines gt rearrange circuit topology to reduce load capacitance 3 f gt reduce switching frequency reduce clock rate The dynamic power dissipation is the dominant mode of power dissipation in full comple mentary CMOS circuits Every logic family has dynamic power dissipation but it is usu ally not the dominant mode for gates with DC power dissipation Let s compare CMOS with pseudo NMOS P NMOS PDC CMOS gt f The load capacitance for NMOS is smaller than CMOS which makes the dynamic power consumption for NMOS smaller than CMOS but the DC power consumption of CMOS is orders of magnitude smaller than NMOS Total CMOS power dissipation is smaller when 1 3CMOS lt 13 DCNMOS 1 3NMOS V2 C dCMOSVdflt 1i C NMOSVde 0a 2R0npRonn 0a l l lt f 2R0npRonnCloadCMOSTcloaANMOS l flt Ntrtf Tgttrtf As long as the switching period is larger than the sum of the rise and fall times CMOS cir cuits have a power dissipation advantage In clocked systems the switching period is close to the clock period which is usually about 100 times typical gate rise and fall times This allows CMOS gates to dissipate about 100 times less average power than pseudo NMOS CMOS Short Circuit Power Dissipation We have been assuming up to this point that the input signals change so fast that the nFETs are never on at the same time the pFETs are on For more slowly changing inputs this is not the case There will be a path from power to ground through the partially turned Power Dissipation August 20 2004 page 4 of 10 I ECEN 5263 Digital VLSI Design I on FETs for a short time for any input waveform with a nite risefall time Let s assume a very slow risefall time for the input so that almost all current goes through both FET s and not into the load capacitance l IDI IDp m iIDn W Vdd VTP inv N A r I Dquot sat limits current When the input voltage rises there is no current until the input voltage reaches VTquot and the nFET turns on at t1 Since we are assuming capacitive loading effects to be small the out put voltage follows the DC voltage transfer curve into the region where the nFET is in sat uration This situation continues until the input voltage reaches Vim at t2 A similar situation occurs when the input is falling 2 7 n EsatnLnVint 7 VTquot IDn 7 3 t lttlttt lttltt VinarVTnHA Eani 1 2 5 6 When the input rises to Vim the output falls rapidly so that the pFET saturates The pFET stays on until the voltage rises to Vdd lVTpl where the pFET turns off at t3 and there is no more current A similar situation occurs when the input is falling Power Dissipation August 20 2004 page 5 of 10 I ECEN 5263 DigitalVLSl Design I 2 I 7 P ES IJLPV IquotITVddTVTP J t lttltt t lttltt D 77 2 3 4 5 P 2 lVint7VddiVTplApEwtpr The average short circuit power dissipation is 1 T PM oaDpIDSPHMVDSM ifo 54 but the circuit is constructed so that I VDsp VDSnl dt VDsp VDSn Vdd39 Therefore VddT P50 T 0 dt DC szlmdt J13 lIDpldt J15 lIDpldt J39t andt t1 t2 t4 IS The time dependence enters into I Dquot and I D only through Vina during the times needed for the integrals Vina varies linearly with time over these periods assuming a smooth ramp input so that the integrals over time can again be changed to integrals over voltage 2 Vmt2 1 j dt j de 1 VMOI CUm E where V t1lttltt3 dVin tr 5 V i t4lttltt6 If The rst integral in the expression for 1330 is Power Dissipation August 20 2004 page 6 of 10 I ECEN 5263 Digital VLSI Design I VW 2 LidJ39tZ dt Lid EsaanVin7VTn J dVin T 1 Dquot T 2 ViniVTnAnEsaan Vddtr Tn I gt GnUinvi VTn ng where 7 nEsatnLn V2 2 V GnV Z Vfld3 ArrEmanV AnEman 1111 W The other integrals can be evaluated in a similar fashion so that I I PM rT GnVinv7VTnGpVddil39 ilVTplnlgd mv where 5 m L V2 V GPV AFEMWLPW APEMWLPfInO de If we rewrite the short circuit power in terms of the switching frequency f as before F50 tr tfGnVinv 7 VTn GpUddi Vinv 7 iVTPi we see that it has the same frequency dependence as the dynamic capacitive switching power Pd but it is also proportional to the rise and fall times of the input waveform not the output The short circuit power is completely wasted whereas the dynamic power 13d is consumed while doing useful work driving the output capacitance The input rise and fall times should be kept short enough so that P SCltlt Pd which implies that Cloud 7 VTquot GPVdd7 V 7 lVTpl quotV mv I I r fltlt GnVi This relation can be written in a more useful form if we replace C load by the rise and fall times at the output the rise and fall times we have been discussing are the rise and fall times at the input tr0ut t out 2Ronp Rom39tCload which gives I I Edam t om 2Ronp Ron GizaWW 7 VTn GpUddi Vinv 7 iVTp rin irt Power Dissipation August 20 2004 page 7 of 10 I ECEN 5263 Digital VLSI Design I Using typical values for a 06m process and Vim VddZ we have out gtgt 2 tr H M trin i tfin Z 62x103 253x10 6 088x10 6 X z s 1 10 This demonstrates that the input rise and fall times can be as much as an order of magni tude slower than the output rise and fall times before we start worrying about short circuit power PowerPerformance Trade off The power dissipation in CMOS and other logic families too circuits increases as the transistor sizes increase decm Cn WnCP WpCI FSCocGnGP WquotWP The power consumption does not vary in exactly the same way as the area because 1 The coef cients of Wquot and W are di erent in the power equations 2 The dynamic power dissipation is also proportional to the switching frequency This means that we can make gates larger that do not switch very often without increasing the power very much Recall that the circuit delay decreases as the transistor sizes increase As we increase tran sistor sizes to improve speed we must pay a price in additional power consumption in addition to the increase in area Conversely if we decrease transistor sizes to try to con serve power then we must pay a price in additional delay Power Ground Line Sizing Sizing power and ground lines is done with di erent criterion than normal signal wires The power and ground lines carry much higher currents than signal wires because the cur rent passing through every gate in the chip must eventually come through the power and ground nets Also the power and ground lines are supposed to stay at a constant voltage and therefore may have a large capacitance This allows very wide metal lines to be used to handle the large currents The metal lines must be wide enough to handle the metal migration and ohmic drop problems discussed below Metal Migration Aluminum is used almost always to form the metal lines in integrated circuits The metal atoms are bound very loosely in solid aluminum It is possible for the metal atoms to be knocked out of their normal position by the conduction electrons collid Power Dissipation August 20 2004 page 8 of 10 I ECEN 5263 Digital VLSI Design I ing with the atoms Once an atom is moved from its original position the wire becomes slightly thinner at that point V 1 0 metal atom A This increases the current density at that point which makes it more likely that another atom will be knocked away in the same vicinity An open circuit failure can eventually be produced if enough metal atoms are moved This phenomenon is called metal migration Metal migration occurs above a critical current density of about Jmm lmAum2 in alumi num t metal line thickness 7 l process constant I t I lt J Wmt mm or I W gt m J mmt Typically 05um lt tlt 10um so that um Wmgt12m A X in agreement with Weste and Eshraghian p238 The current is usually estimated from the dynamic power dissipation 13d I a Z CgateVddfgate gates Power Dissipation August 20 2004 page 9 of 10 I ECEN 5263 Digital VLSI Design I where the summation is over the gates that draw current through that section of the power or ground line Ohmic Voltage Drop Vdd I N GND 1 N We want the ohmic voltage drop AV to be a small fraction of the power supply voltage Vdd Let s choose AVlt 01 Vdd Then Lm AV Rsmetal 1lt 01Vdd Wm W gtRsmetal Lm m 01Vdd Typically Rsmetal S 019 Vdd 5V so that mem gt Wm 5000mA mA Supply Line Width The power and ground line widths must be large enough so that both metal migration and ohmic drops are not a problem Comparing the two inequalities ohmic voltage drops are more of a problem for long lines If Lm gt 1000 um then ohmic drops are a more serious problem than metal migration and below this length metal migra tion is more serious Global power ground lines are most often sized to avoid ohmic drops and local lines are sized to avoid metal migration global ohmic drop Vdd r l local metal migration GND Power Dissipation August 20 2004 page 10 of 10 I ECEN 5263 Digital VLSI Design I Logic Gate Delay Estimation In the previous section we calculated Elmore delays from the transistor diagrams using estimates of the channel resistances and node capacitances In this section we extend these ideas to show how to get the channel resistances and node capacitances from stick diagrams Note that this allows estimating delay before layout is actually done which gives us the opportunity to explore design alternatives without requiring a layout for each alternative Three examples are shown below In the tables the only cases shown are those that produce a change in the output Inverter VDD A Y A C Y T C Y Y Gnd A Y My t l RnACY l r RPACY 2input NAND VDD Aw Y A Logic Gate Delay Estimation September 23 2009 page 1 of 12 I ECEN 5263 Digital VLSI Design I tdY RnAC1RnARnBCY 4 H RPAC1RPACY RnA RnBCY H gt4 gt4 lt RpBCY 3input ORNAND A ol C ol wl TC2 Y H TCY H w tdY RnAC1RnA RncCY C2 4 O H RPAC2 RPA RPBCY C1 RPARPBCYC1 RnB RncCY C2 Y i T 1 i RnBCI RnB RncCY T i T RPCCY C2 Logic Gate Delay Estimation September 23 2009 page 2 of 12 I ECEN 5263 Digital VLSI Design I A B tdY 1 0 R quotA RnCCY RpCCY RnA H RnB i RnCCY RpCCY H O lt gtlt gtq gtlt gtlt lt The logic gates in these examples must be connected to other logic gates to be useful When the logic gates are connected together the output capacitance is increased by the capacitive loading of the other gate inputs and the interconnection wire Just as we did for the simple case of an inverter driving another inverter we can separate the capacitance C Y into output wire and input components but several gates of di erent types might be con nected to node Y as in the drawing below Y new Cam i CW T C wtreT W Cin3 T Let us sum the wire and input capacitances into a single capacitance C load In the follow ing C out is the capacitance of the driving gate with an unconnected output and C load is the additional capacitance from the wires and other logic gate inputs Weste and Harris use C out to mean what we are calling C load Sorry for the confusion but I like my notation better CY Com Cloud C1 C2 and C out are all independent of the load and are determined by the parasitic capaci tances associated with the internal structure of the logic gate All of the delays in the three Logic Gate Delay Estimation September 23 2009 page 3 of 12 I ECEN 5263 Digital VLSI Design I examples and also delays for any CMOS logic gate are proportional to the load capaci tance effort delay tdF parasitic delay tdp i 7 Cloud The parasitic delay tdp is the nonzero delay when there is no load The output resistance Ram is the slope ofthe delay vs load curve rd th tdF tdF RoiCloud The parasitic delay and output resistance are determined the topology of the logic gate Inverter A Y W Rout 2input NAND 11P Rout RnACI i RnA Rmth RnA Rm 4 H Y i 1 T RpACI i RpACom RpA 1 f l RnA Rmth RnA Rm 1 l f RpBCom RpB Logic Gate Delay Estimation September 23 2009 page 4 of 12 I ECEN 5263 Digital VLSI Design I 3input ORNAND A B C Y tap Rout T 0 1 T RnAC1RnARnCC0mC2 RnARnC T 0 1 T RPAC2RPARPBCWC1 RPARPB 0 T 1 i RnBCl i RnB RncCom RnB Rnc 0 T 1 T RPARPBC0mC1 RPARPB 0 1 T i RnB i RnCC0ut C2 RnB Rnc 0 1 T T RPCCom C2 RFC 1 0 T T RnA RnCCom RnA Rnc 1 0 i T RPCCW RFC 1 1 T i RnA H RnB RncCom RnA H RnB Rnc 1 1 i T RPCCW RFC Unit Channel Resistance A major goal of the logic gate delay model is to see the effect of changing transistor widths without having to do detailed layout and simulation Chan nel resistances of individual transistors are inversely proportional to the transistor widths just as they were for the inverter 27 R R nX anX 7 2 RPX 7 RSPWX Rm is the sheet resistance for nFETs and RS is the sheet resistance for pFETs and we have assumed minimum channel length of 27 for all FETs The table below shows that channel sheet resistance has remained remained nearly constant over several process generations C0 line width um Rm K9 R1 K9 AMIS 06 107 188 IBM 05 77 143 IBM 035 99 198 TSMC 035 101 142 IBM 025 111 240 Logic Gate Delay Estimation September 23 2009 page 5 of 12 I ECEN 5263 DigitalVLSl Design I C0 line width um Rm K9 R3 K9 TSMC 025 100 240 IBM 018 105 253 TSMC 018 99 232 IBM 013 89 260 IBM 009 83 205 To simplify our calculations of channel resistance and make them process independent let us define channel resistance as a multiple of R the channel resistance of a minimum size nFET RPX L SPWPX WPX We assume that all FETs have minimum channel length 27 but the width can be anything at least as big as a minimum width ijn We will use Wmin 47 but many fab pro cesses require larger widths to insure high quality FETs In this case R m SKQ Note that we have retained an extra factor of 2 for pFET resistances to account for the signi cant difference between nchannel and pchannel sheet resistance a factor of 2 or greater is significant in our approximations Input Capacitances in General Logic Gates poly pdiff l l lt gt The loading from connecting logic gates together is caused primarily by the capacitance added by each logic gate input when wires are short The stick diagrams for the three Logic Gate Delay Estimation September 23 2009 page 6 of 12 I ECEN 5263 Digital VLSI Design I example logic gates show that the horizontal layout style logic gate inputs each have the same input capacitance as the inverter Cm anCgPCp oly C C W J W C Wquot n WP p m1 where Cm C C d J w W ALquot P 2 lg 30L Cpgd 2 WP A P P C C CW 50x2 1 4671 Putting in numbers for the several processes C0 line width CinWn fFMm Cin W1 fFMm CinWGFHm AMIS 06um SUBM 17 15 16 IBM 05um SUBM 20 18 19 AMIS 035pm SUBM 20 21 21 IBM 035pm SUBM 15 17 16 TSMC 035pm SUBM 19 15 17 IBM 025 DEEP 20 18 19 TSMC 025 DEEP 26 24 25 IBM 018 DEEP 21 19 20 TSMC 018 DEEP 28 23 26 IBM 013 DEEP 21 17 19 IBM 009GDEEP 17 21 19 Even though the difference between C in Wquot and C in W1 is about 20 we can approxi mate them as the same so that C i WW C inf Wn p ml 911 1 Wquot W 2 Logic Gate Delay Estimation September 23 2009 page 7 of 12 I ECEN 5263 Digital VLSI Design I Unit Capacitance Transistor gate capacitance per unit width has stayed relatively con stant over the last 10 to 15 years as expected from constant eld scaling Table 415 p 247 Since constant eld scaling is projected for the immediate future the next 5 years let us de ne capacitance in terms of C in W the gate input capacitance of approximately 2fFum CX cm W Wmi Note that the unit capacitance depends on line width because it is proportional to ijn whereas the unit resistance is independent of line width because it is proportional to Lmjn ijn C should be about 2fFum times the minimum transistor width in microns Actual values are shown below for several different fab processes CX C0 line width CfF AMIS 06th SU39BM 10 IBM 05th SU39BM 16 IBM 035th SU39BM 08 TSMC 035th SU39BM 11 IBM 025 DEEP 09 TSMC 025 DEEP 11 IBM 018 DEEP 068 TSMC 018 DEEP 089 IBM 013 DEEP 049 IBM 009GDEEP 039 Using the unit capacitor C the total input capacitance is 2 WW C W n p in1 in C 139 W W m C C My 50x2 Poly 46x M I A P C Wmin cm W Wmin Logic Gate Delay Estimation September 23 2009 page 8 of 12 Since W and WP both must be greater than Wm interconnect capacitance on each input cannot be neglected as shown below I ECEN 5263 Digital VLSI in C0 line width CmC AMS 06th SUBM 168 IBM 05th SUBM 087 IBM 035m SUBM 101 TSMC 035m SUBM 090 IBM 025 DEEP 074 TSMC 025 DEEP 057 IBM 018 DEEP 067 TSMC 018 DEEP 051 IBM 013 DEEP 065 IBM 009GDEEP 055 Design the rst term is at least 2 The poly The poly interconnect capacitance is about C 2 for each input This can be added to the wire interconnect capacitance which is also independent of Wquot WP Unit Delay When computing RC delays our results will be proportional to AtRCRS which is about 20psecum times the line width in microns As we shall see typical gate delays are about an order of magnitude larger So we can think of At as the resolution time scale for delays We will ignore differences in delay less than At This time scale shows that gate delays decrease linearly with line width in agreement with constant eld scaling table 415 p 247 Actual values are shown below C0 line width Rm K9 CfF Atpsec AMS 06th SUBM 107 10 106 IBM 05th SUBM 77 16 120 IBM 035m SUBM 99 08 83 TSMC 035m SUBM 101 11 94 IBM 025 DEEP 111 09 103 TSMC 025 DEEP 100 11 124 IBM 018 DEEP 105 068 79 TSMC 018 DEEP 99 089 95 IBM 013 DEEP 89 049 52 IBM 009GDEEP 83 039 37 Logic Gate Delay Estimation September 23 2009 page 9 of12 I ECEN 5263 Digital VLSI Design I Interconnect Wire Capacitance When capacitive coupling between metal layers is taken into account modern deep submicron processes have a capacitance of about 02fF pm of wire length For a metal interconnect wire of length Lwire we have Cwire 02fFumL 02fFum L wire C 2fFum ijn wire L 71 w1reC 7 E Wmin lt3W so that we can neglect 1nterc0nnect w1re capac1tance where Lwire min Channel Propagation Delay he parasitic delay tdp is determined by the FET channel resistances and internal parasitic capacitances of the logic gate C 1 and C 2 in our exam ples including the parasitic capacitance on the output node C our Traditionally as Weste and Harris assume the propagation delay through the FET channels has been neglected In modern deep submicron processes the propagation delay through the FET channels can no longer be neglected especially for 01 processes We have already proposed a wire delay model for the propagation delay through the FET channels Using a pimodel for the FET channels is convenient since the propagation delay can be modeled by adding capacitance to the source and drain nodes of the FET J L S D gtS Dgt 13 ED TT What makes applying the model unusual is that the amount of capacitance added to the source and drain depends on the three operation regions of the transistor Logic Gate Delay Estimation September 23 2009 page 10 of 12 I ECEN 5263 Digital VLSI Design I i on I lJL W T 111201 n Similarly for the pchannel sourcedrain capacitances Normalizing to the unit capaci tance 91 P Wquot prop an 2W min C on and putting in numbers for several processes C0 line width CngdoCin CpgtwCin AMIS 061m SUBM 010 016 IBM 05pm SUBM 016 022 AMIS 035m SUBM 014 014 IBM 035m SUBM 025 020 TSMC 035m SUBM 015 023 IBM 025 DEEP 027 029 TSMC 025 DEEP 024 025 IBM 018 DEEP 020 027 TSMC 018 DEEP 026 030 IBM 013 DEEP 020 019 shows that 1 W C m 4 WminC off prop l Wquot C on 2 Wmin Logic Gate Delay Estimation September 23 2009 page 11 of 12 I ECEN 5263 Digital VLSI Design I This makes the node capacitance di erent depending on whether transistors are on or off which greatly complicates analysis without signi cantly improving accuracy A simpler model suitable for hand calculations is 1L prop 2 Wmin which is what we will use C C Logic Gate Delay Estimation September 23 2009 page 12 of 12


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