### Create a StudySoup account

#### Be part of our community, it's free to join!

Already have a StudySoup account? Login here

# DIG ELTRNC CIRC DESIGN ECEN 4303

OK State

GPA 3.58

### View Full Document

## 7

## 0

## Popular in Course

## Popular in ELECTRICAL AND COMPUTER ENGINEERING

This 0 page Class Notes was uploaded by Louisa O'Kon I on Sunday November 1, 2015. The Class Notes belongs to ECEN 4303 at Oklahoma State University taught by Louis Johnson in Fall. Since its upload, it has received 7 views. For similar materials see /class/232907/ecen-4303-oklahoma-state-university in ELECTRICAL AND COMPUTER ENGINEERING at Oklahoma State University.

## Reviews for DIG ELTRNC CIRC DESIGN

### What is Karma?

#### Karma is the currency of StudySoup.

#### You can buy or earn more Karma at anytime and redeem it for class notes, study guides, flashcards, and more!

Date Created: 11/01/15

I ECEN 4303 DigitalVLSl Design I State Machines The most general nite state machine called a Mealy FSM does not force clocked ele ments on the external inputs and outputs g B2a p 913 This can be dangerous if Mealy machines are cascaded combo combo I r log1c r log1c clocks clocks The longest delay path from the register in the rst machine to the register in the second machine goes through both combinational logic blocks Even though the delays of each individual machine are small enough the worst case delay may be too large greater than the clock period when the machines are cascaded This can occur any time that the out puts of one state machine are used as inputs by another Cascading state machines is much less dangerous if registers are inserted on the FSM inputs or outputs called Moore FSM g B2b p 913 The longest delay path is always through a single combinational logic block registered input form clocks clocks registered output form clocks clocks State Machines September 5 2009 page 1 of4 I ECEN 4303 DigitalVLSl Design I The timing of each of these forms is dilTerent depending on the delays of the combina tional logic circuit Suppose the combinational logic circuit has the following delays tin worst case delay from any external input to any external output tin worst case delay from any external input to any next state bit register input tpo worst case delay to any external output from any present state bit register output The following timing assumes positiVie edge sensitive registers are used in the FSM and neglects the register set up and clock to Q delay 4 T gt clock A 39 phil 39 Mealy input I my M I M VV 39 VV AK re g1stered in Moore input I AAAAAA k maxtp0t0 VVVVVV A registered out Moore max t t lnput m 10 J k A registered out Moore output State Machines September 5 2009 page 2 of4 I ECEN 4303 DigitalVLSl Design I The Mealy machine input must stop changing tin before the end of the clock period in order for the next state register inputs to be stable at the clock edge The Mealy output stops changing at time tin after the inputs stop changing or at time tpa after the clock edge whichever is later The timing diagram shows that the Mealy output can still be changing at times which make it unsuitable for an input to another Mealy FSM However the out puts can change more quickly in response to a changing input than the Moore forms which may be an advantage in some applications The timing requirements for the inputs on a Moore machine with registered inputs are the same as for a normal edge sensitive register The inputs must be stable for a short time near the clock edge The outputs of the registered input Moore machine stop changing at time tpa after the clock edge or tin after the inputs stop If we assume that the inputs come from another registered input Moore machine then the outputs stop changing at maxtp0ti0 after the clock edge The delay can be designed to be small enough maxtp0ti0 lt T so that the outputs can be used by another Moore machine with registered inputs The outputs on the Moore machine with registered outputs change right after the clock edge as in a normal edge sensitive register This is the only form that forces the outputs to change at a speci c time For this reason it is the form of FSM that is most frequently used to generate signals used by other circuitry The other circuitry has the full clock period to use the signal without having to take into consideration the delays of the combin altional logic The inputs to the registered output form must stop changing maxtinti0 before the end of the clock period so that the next state and next output also register inputs are stable at the clock edge As can be seen from the timing diagram the outputs of the Moore machine with registered outputs can be designed to change at a time which allows its use as an input to another Moore machine if maxtnt0 lt T State Machines September 5 2009 page 3 of4 I ECEN 4303 DigitalVLSl Design I Another version of the Moore machine that is often used is to split the register into its master and slave latch and then put the combinational logic in the middle A two phase latch combo latch logic inputs outputs 12 4 1 11 A A inputs A outputs implementation is shown with outputs positive edge sensitive with respect to phil The outputs are stable only when phil is low The inputs can change at any time except just before phi2 goes low phil goes high In order for this timing to be met one must have tin lt T2 tin lt T2 and tpo lt T2 State Machines September 5 2009 page 4 of4 I ECEN 4303 DigitalVLSl Design I Clocked Systems A synchronous design style with a system clock is used in the vast majority of digital sys tems Asynchronous designs without a system clock must be carefully designed to guar antee correct operation even though there can be considerable variation in the delay of circuit elements Clocked systems on the other hand can be designed more easily by meeting simple constraints on the minimum and maximum delay Specialized circuit ele ments are used with the clock signal Fig 71 p 384 Latches and FlipFlops Clocked Circuit Elements In the following the circuit implementations of latches and ip ops are grouped accord ing to the number of global clock lines needed The trend in modern design has been to use implementations with the minimum number of global clock lines to save area and to limit the engineering effort needed to insure proper distribution of the clock signal to all parts of the chip True Single Phase Clock Static implementations Full CMOS latches level high sensitive level low sensitive Can synthesize as 2 complex CMOS gates plus inverter gt no of FETs 2X6 2 l4 Clocked Systems September 5 2009 page 1 of9 I ECEN 4303 DigitalVLSl Design I Full CMOS gate implementation of masterslave DFF rising edge sensitive falling edge sensitive Can synthesize as 4 complex CMOS gates plus inverter gt no of FETs 4X6 2 26 Differential Pair masterslave DFF Fig 729a p 413 is faster than full CMOS but has about the same number of transistors if the fast asynchronous slave latch is used in Fig 72 MUX Pass Transistor implementation is not practical for single phase clocking Q Q reduced noise margin here clk As we saw earlier both the nFET and the pFET reduce the noise margin which is not tol erable in modern processes Dynamic implementations Dynamic registers and latches depend on charge storage on internal nodes in the circuit for memory storage If the charge leaks off between clock pulses the memory state is lost This puts a minimum frequency requirement on dynamic registers and latches The increased leakage in deep submicron processes has reduced storage times to a usec or less which means that the minimum operating frequency must be lMHz or higher Since current clock rates are in excess of lGHz this is not a major problem at present However since leakage is anticipated to be worse in the future dynamic techniques could become impractical clocked Systems September 5 2009 page 2 of 9 I ECEN 4303 DigitalVLSl Design I nonfull swing pass transistor Fig 717a p 404 The output is usually buffered as shown below since the output can be oating D fix 6 D fix 6 level high sensitive latch level low sensitive latch The necessity of using the pFET for the level low sensitive latch makes this implementa tion unattractive but it does have the minimum transistor count Only 3 transistors are required for a latch and 6 for a ip op Also power consumption is a problem unless some of the techniques discussed previously are used to make it full swing True Single Phase Clock TSPC Fig 730 p414 These circuits are slower than other alternatives since the latch and ip op implementation require an extra level of logic Also the output usually needs buffering since it is a dynamic node Pulsed Latches Pulsed latches are dif cult to get to work correctly and for this reason have not been used traditionally With the emphasis on single global clock lines pulsed latches have become more popular recently Any latch can be used with clock pulses as in the bottom of Fig 72 p 385 Signals are prevented from going through the latches except for the short period of time when the pulse is high The trick is to keep the pulses short enough so that signals cannot propagate through more than one latch at a time On the other hand the pulse must be long enough to allow propagation of the signals through the latch Note that latches take the place of ip ops Flip ops are not needed Only level high sensitive latches are needed which makes a nonfull swing implementation more attractive since pMOS pass FETs are not required 39 combinational 39 logic T l Special care must be taken when driving the pulsed clock hp over long distances Recall that the wires act like RC transmission lines which not only delays but spreads out any T clocked Systems September 5 2009 page 3 of 9 I ECEN 4303 DigitalVLSl Design I edges Over long clock lines the edges of the clock pulse gradually merge and the whole pulse can disappear j AA clk 1 9 One solution to this problem is to have a normal global clock with a square wave where the edges are much farther apart and do not grow together so easily Then each pulsed latch includes a local pulse generator It is relatively straightforward to design the local pulse generator so that it produces pulses of the desired length triggered by an edge on the global clock Pulse generators Fig 722 p 408 combined pulse generator and latch Fig 723 since Q is a dynamic oating node do not use it without buffering it rst Pseudo Single Phase Clock Use of both clk and E control signals allows the use of transmission gates to make full swing logic tireduce power consumption and improve noise margin To avoid two global clock lines clk is usually generated from clk with a local inverter as shown in Fig 720 p 406 Static implementations MUX transmission gate implementation for latches Fig 7 l7efgh p 404 regis ters Fig 7 19b p 405 clk m e Q mg Q D 6 D 6 J E level high sensitive latch level low sensitive latch Can synthesize as 2 transmission gates plus 2 inverters gt no of FETs 2X2 2X2 8 Note that this is a static implementation since charge storage is not used Clocked CMOS C2MOS Fig 718 p 405 is just a combined inverter and trans mission gate They can be used in static latches also Fig 7l7gh p 404 clocked Systems September 5 2009 page 4 of 9 I ECEN 4303 DigitalVLSl Design I jamb latch Fig 7 l7i p 404 uses a wea feedback inverter fabricated with high impedance FETs small width possibly longer than minimum length Dynamic implementations latches Fig 7l7cd p 404 registers Fig 7l9a Latches synthesized as 1 transmission gate plus 1 inverter gt no of FETs 2 2 4 True Two Phase Clock Two nonoverlapping clock signals can be used to insure that no signals can propagate through more than one latch at atime middle of Fig 72 p 385 tnonoverlap is kept small compared with the clock period to avoid wasting time It is very dif cult to keep the two clock signals precisely aligned when tnonoverlap is short To avoid two global clock lines the two clock signals can be generated from a single global clock The local two phase clocks can be shared between several nearby latches andor registers clk 42 11 Static Implementations 12 4 1 D 6 D 6 11 12 level high 11 sensitive latch level high 12 sensitive latch Use different clock phases on alternate stages as shown in middle of Fig 72 p 385 Dynamic Implementations D l gt0 6 D l gt0 6 T T 11 12 level high 11 sensitive latch level high 12 sensitive latch clocked Systems September 5 2009 page 5 of 9 I ECEN 4303 DigitalVLSl Design I Pseudo Two Phase Clocks Use of both 11 12 and 1 2 control signals allows the use of transmission gates to make full swing logic to reduce power consumption and improve noise margin To avoid four global clock lines the four clock signals can be generated from a single global clock The increased complexity necessary to properly synchronize 4 clock lines makes it necessary to share the local clock signals over several latches and registers clk 42 11 Static Implementations Fig 721 p 407 Dynamic Implementations 1 2 D i H gt0 6 D i H gt0 6 11 12 level high 11 sensitive latch level high 12 sensitive latch Register and Latch Timing with Two Phase Clocks When using the two phase clocks care must be taken to get the correct timing 11 12 1 2 are all distinctly different functions of time and must be connected correctly to the transmission gates 11 12 are nonoverlapping high and therefore should be used to control the nFETs in the transmission gates 1 2 are nonoverlapping low and therefore should be use to control the pFETs in the transmission gates clocked Systems September 5 2009 page 6 of 9 I ECEN 4303 DigitalVLSl Design I 1 gtt 2 pt 1 i i i 1 pt EAL t pos A edge 11 reg t pos edge 12 reg t 472 471 D W Q positive edge 1sensitive 12 4 1 1 472 D W Q positive edge 2sensitive 11 4 2 clocked Systems September 5 2009 page 7 of 9 I ECEN 4303 DigitalVLSl Design I It is also necessary to specify which clock signal is used when classifying latches as high or low level sensitive and when classifying registers as positive or negative edge sensitive Note that a positive edge 11 sensitive register has a different behavior than a positive edge 12 sensitive register and the two should not be mixed Timing Constraints Fig 74 p 387 Table 71 p 386 Timing Diagrams Note that latches have setup and hold requirements relative to the clock edge that turns them off not the clock edge that turns them on We will examine the timing constraints necessary to insure correct operation of the three clocking schemes in Fig 72 p 385 The two phase clocking scheme is the traditional way of using latches The pulse latch scheme has become more popular as a way to reduce the number of clock lines that must be distributed across the chip Flip Flop Timing Constraints The maximum delay of a logic block between two ip ops is constrained as shown in fig 75 and eq 71 72 p 388 The minimum delay of a logic block between two ip ops is constrained as shown in fig 79 and eq 77 p 393 Flip ops are often designed so that the right side ofthe inequality is negative meaning that the ip ops can be connected directly together without any intervening combinational logic Two Phase Latch Timing Constraints A ip op can be regarded as being composed oftwo series latches clocked with complementary signals fig 73 p 386 There is no real need to put combinational logic only between latch pairs combinational logic can be put between all latches fig 77 p 391 with the timing requirements in eq 74 Note that the constraint on the maximum logic delay in eq 74 does not replace the requirement for D1 to stabilize a setup time before the falling edge of 11 and D2 to stabi lize a setup time before the falling edge of 12 In fig 7 7 the D inputs stabilize near the beginning of the clock phase but the circuit will still work correctly if the D inputs are delayed less than half ofa clock period fig7 12 p397 The combinational logic in the first half of the clock period borrows time from the com binational logic in the second half of the clock period The 12 latch can be moved in time to anywhere within the 12 clock phase Borrowing can always take place across the internal half cycle boundary Borrowing is also possible across the clock period boundary if there are no loops in the circuit for example pipelines We will make use of this tech nique next semester to design high performance pipelines Fig 713 p 397 and eq 710 p 396 maximum borrowing clocked Systems September 5 2009 page 8 of 9 I ECEN 4303 DigitalVLSl Design I The minimum delay of a logic block between two latches is constrained as shown in g 710 p 395 and eq 78 p 394 Increasing the tnonoverlap forces the right side ofthe ine quality negative meaning that the latches can be connected directly together without any intervening combinational logic Pulsed Latch Timing Constraints The maximum delay of a logic block between two pulsed latches is constrained as shown in g 78 and eq 75 76 p 392 No borrowing is possible if the pulse width is short The minimum delay of a logic block between two pulsed latches is constrained as shown in g 711 p 395 and eq 79 p 394 clocked Systems September 5 2009 page 9 of 9 I ECEN 4303 DigitalVLSl Design I Parasitic RL and C Resistance p 198 eq 433 434 sheet resistance def Fig 432 p198 calculating resistance I 4 1 R RS R RS1 l l l R4gtltRS I R zXRS I same as 4 same as 4 squares in I 1 squares in paral series lel I Note L de ned parallel to current and W de ned perpendicular to current When cur rent ow lines are parallel gt R N W39 Current ow lines not always parallel lt w gt Corners R 25RS 1 results same as if square on the corner only counts 1 ERS I Table 47 p 200 sheet resistance values 018pm process Parasitic KL and C August 25 2009 page 1 of 19 I ECEN 4303 DigitalVLSl Design I Fig 431 p 197 Metal layers have different sheet resistances because of different thick nesses Example calculation The shape below is fabricated in a layer with RS 159 l2sql lsq I lsq I lsq 4x 8 R 55RS 8259 Channel Resistance Ohmic reSiStance 4 max on resistance lVGsl VDD lIDl 39 lVDSl From the figure it is clear that the average channel resistance Ron is R lt Ron lt R ohmic maxon For small VDS FET will be ohmic 7 EKVGS VTWDS Abulclz 2 D 1V EWL 1 R VDS ohmic l W R0hmic mwhere KI 4 Ohmic 141637 VT W R Parasitic KL and C August 25 2009 page 2 of 19 I ECEN 4303 DigitalVLSl Design I The channel resistance looks like a voltage dependent sheet resistance times the same L W geometric factor as other ordinary conducting layers T W D i I L 1 More conservative estimate of channel resistance obtained from drain current with maxi mum gate and drain bias lVGsl VDD VDsl VDD We approximate ID R 1 VDS at VDS VDD see illustration above maxon R 7 VDD maxoni IDI VGS VDD Since the FET is in saturation 2 7 3 7 3 EsatLUGS VT Ii V V 7V7 D 2 GS T utmkEwwwGswn R 7 VDD maxoni 2 E EsazLVGs VT J 2 AbulkEsatL VGS 7 VT R 7 2VDDAbulEsatL VDD 7 maxoni 2 KEsarLUDD VT W which also looks like a sheet resistance when written in this form However the L depen dence is actually more complicated In the velocity saturation limit VDD VTgtgtEsatL Rmaxon 51 sa DD T 7 2VDD 1 7 WV the L dependence completely cancels out in velocity saturation limit shortening channel does not decrease resistance Parasitic KL and C August 25 2009 page 3 of 19 I ECEN 4303 DigitalVLSl Design I Contact Resistance Metalsemiconductor diff or poly contacts have nonlinear IV curve because of Schott key diode formation I metal 1 I V V n lt breakdown If semiconductor is highly doped nJr or pl then diode breakdown occurs at low voltages giving approximate small resistance 1 lt approximate metal 1 I contact resistance V V n lt breakdown Typically R is 20 100 ohms for minimum size contacts Metal semiconductor contact conductance is not proportional to contact area 4 top View b low resistance metal low resistance metal i lt side View E resistancem high resistance substrate Laterally owing current goes through the sides of the contact in the high resistance layer gt Gcontact N contact perimeter not area Do not make large contacts Break them into smaller contacts to maximize the perimeter and therefore the conductance minimizes contact resistance Parasitic KL and C August 25 2009 page 4 of 19 I ECEN 4303 DigitalVLSl Design I I I I 47 gt I I I T L I I I 2 large contact contact mask T Each contact is made from minimum size contacts Large contacts are really made of parallel combinations of minimum size contacts metal 1 metall conducting layer conducting layer The resistance of multiple contacts can be determined from the parallel combination of minimum contacts R 7 Rmin contact 7 n Rmin resistance ofmin size contact n no Ofmin contacts contact area contact area m1n contact area 67 67 The resistance of the contact structure should be added to the resistance of the conducting layers since they are in series For example N gt Lml Lndiff L 1 R L Rm1i c ndiff s Wml n R Snd1ff Wndiff RTOT le Rcont Rndiff Note When calculating resistance for classwork we will measure lengths L from the center of a contact as shown above Parasitic KL and C August 25 2009 page 5 of 19 I ECEN 4303 DigitalVLSl Design I Capacitance IQI CV 7 814 C d 39 C SOXWL tax 8 C row 0X gt process constant C m Same area gt same capacitance independent of shape gate Fig 22 p 68 MOS capacitor isolated C s a accumulation C E C ox E A M Channel tax 1 Cdep 1 s r 71 b depletlon C 2Cdep C0x substrate c inversion C E Cox All conducting layers over silicon substrate have this dependence not just the gate of a FET Can show depletion layer thickness dN Zdep Vdep voltage across depletion sub Nsub doping of substrate High doping gt small d gt large C dell gt higher VT for inversion Thus everywhere except where we want transistors we put channel stop high doping of substrate to pre vent inversion where we do not want transistors Parasitic KL and C August 25 2009 page 6 of 19 I ECEN 4303 DigitalVLSl Design I conducting layer no channel stop 3 4 with channel stop no inversion for bias below Vdd gt V Therefore can approximate C m C W for all layers except poly over thin oxide where transistors form and except for diffusions which are down inside the silicon instead of above the oxide MOS DeVice Capacitance Fig 214 p 83 Note Csb Cdb are diff cap Table 21 p 78 Note ng drops off at high Vds saturation region because most channel charge is nearer to source in saturation S D Gate Capacitance The total gate capacitance is C C C C ltWL g gs gb gd A Q A t Detailed circuit simulators like SPICE can take into account the nonlinearities of the gate capacitance see Fig 2 11 p 79 For hand calculations the simpler oxide capaci tance is used to approximate the gate capacitance where Parasitic KL and C August 25 2009 page 7 of 19 I ECEN 4303 DigitalVLSl Design I COX Cg E 7 W so that it depends on the size not the shape of the gate just like other layers The gate W and L are determined by the intersection of the poly and dilTusion layers gt thick oxide poly interconnect thin oxide gate fringing cap contributes to C gba contr1butes to C gm and C gdo Contributions of edges to gate The edges of the channel contribute extra capacitance which is much more important in modern deVices than in older processes Fig 210 p 78 The gate to source and gate to drain overlap capacitances C and C are due to the gm gdo undercutting of the poly gate by the di usion layer and fringing capacitance at the edge of the poly gate across the width of the channel There is also a gate to substrate overlap capacitance C gba due to the fringing capacitance at the edge of the poly gate across the length of the channel Parasitic KL and C August 25 2009 page 8 of 19 I ECEN 4303 DigitalVLSl Design I The gate capacitance including edge effects is then Cox C Cd Cb gm g0 g0 Cg W L W 2 L C Note is the same for both nFETs and pFETs in the same process the overlap capacitances for nFETs and pFETS can be different because of di erences between the n di usion and pdiffusion layers For small digital transistors it is important to use the effective W and L to compute capat ictance Recall that Weff Wdrawn ZWINT XW Leff Ldrawn ZLINTJrXL Example gate capacitance calculations for 06um process 7 03um LIN 003pm LINTp 007pm Ldrawn 2 06pm WWquot 02um WIMP 026pm Warm 4 121m Leffn 054pm Lem 046pm XL XW 0 Weffn 08um We p 068pm C C l WL A 24fFum2 12um 06um 173m C C C d C b Cgquot flweffnieff l 0quot Weffn lamlwe l lamina391 24fFum208um054um02fFum208um0 104fF032fF 136fF Cox Cgsop ngop Cng C 7 Wef a Lef a12 lep We pp 2Lef a 24fFum2 068pm 046pm 024fFum 2 068pm 0 075m 033fF 108fF m5 Parasitic KL and C August 25 2009 page 9 of 19 I ECEN 4303 DigitalVLSl Design I It is more important to include overlap capacitance in modern deep submicron processes Example gate capacitance calculation for 018pm process 7 009Hm LIN 0016um LINTP 0028um L 27 018pm WIND 00Hm WINTp 00um W 47 036pm Leffn 0148um Le p 0124um XL O XW 00le Wefn 035pm Weffp 035pm COX Cg 7 W39 L 85in2 036pm 018pm 055fF C C C d C b Cgquot flweffnieff l 0quot Weffn lamlwe l ifquot ZLeffn 85fFum2 035pm 0148um 079fFum 2 035pm 0 044fF056fF 100m Cox Cgsop ngop CgbOP Cgp 7 Wef a39Lele p Wef l p Weff l p ZLef a 85fFum2 035pm 0124um 064fFum 2 035pm 0 037fF 045fF 082fF Diffusion Layer Capacitance C d junction capacitance of reverse biased pn diode 7quot Cd CINE EO8to 09V Ml l m 3 to 2 Parasitic KL and C August 25 2009 page 10 of 19 I ECEN 4303 DigitalVLSl Design I Detailed circuit simulators like SPICE can model this For hand calculations we approx C d V m C as average cap over operating voltage range 0 to Vdd V dd L Cd 7 Vdd j CdVdV 0 Vdd 1 7m C1Z dV Vddg J l KEY I l 7 m J VD D I Fig 213 p 81 diff cap from layout There are two different types of sidewall capacitance side View lt Trench Oxide reduces sidewall cap K Channel Stop top View sidewall capacitance next to gate sidewall capacitance next to trench oxide 21 LD The total capacitance from the ndiffusion on the right is then Parasitic KL and C August 25 2009 page 11 of 19 I ECEN 4303 DigitalVLSl Design I Cnd Cnd Cndg Cdt 7WD2DW P W where Cnd 7 7 7 ndlff cap per unit area Cnd 7 F 7 ndlff cap per unit per1meter next to th1ck ox1de C ndiff cap per unit perimeter next to gate Here the dimensions are clear In the corresponding equation 216 on p80 the dimensions are not clear C quot for polvover thickoxide and metal laVers First consider an interconnection wire that is isolated from other wires but not from the substrate as in left side of Fig 434 p 201 Fig 435 p201 gives Eq 436 Note that C WL L Another approximation is in Eq 437 plate cap fringe cap layers have plate capacitance term linearly dependent on W and a fringe capacitance term independent of W i capunitarea W A plate cap T 1g capunitperimeter lt gt L fr1nge cap CTOT Z WL2W2L This is a good model for capacitive coupling to the substrate when no other layers are nearby Cross Coupling Capacitance Now consider an interconnection wire that has another conducting wire nearby as in the right side off1g 434 p 201 Capacitance calculations are more complex with multiple metal layers Fig 436 p 202 Modern processes have metal and poly layers with high thickness to width ratios This makes fringing capacitance much more important than in older processes The fringing fields are very complex and there is no general closed form solution Parasitic KL and C August 25 2009 page 12 of 19 I ECEN 4303 DigitalVLSl Design I In modern processes each metal layer is densely packed and can be approximated as a plane The resulting coupling capacitances for the Intel 018pm process are in Table 48 p 203 These results except S 00 can be duplicated within 30 with the following simpli ed model LOW side View side View 9391 A Hy 80x3 P 2HijS Cl P 2HijSJ 8 TL Cadji 0XH WARNING At this time circuit extractors do not include spacing effects Remember that the total capacitance must include the wire layers above and below as well as the adjacent wires on each side as shown in fig 436 p 202 Now consider a long metal line in layer 139 that couples to crossing lines in layer il above and layer il below T IIIIII II 11 i C H 39HSi lquot quotWIHiquot i 1 iil T Ti Cii 1 Hun T IllllllillljF T l 314 l WAT side View Parasitic KL and C August 25 2009 page 13 of 19 I ECEN 4303 DigitalVLSl Design I There are nil1 capacitors Cit1 in parallel coupling lines in layer 1 to lines in layer 11 where tit1 SilWilI Similarly there are nil4 capacitors Ci in parallel coupling lines in layer 1 to lines in layer 1 1 where 71 Li 3 H 171 W171 Then the total capacitance coupling to the line in layer 1 is Ci 2CadjiniilCiilniiilC g T L Zm tLl C 1 C 71 S39 S11W11 1 S171W171 1 1 n 1171 Ci Ci ZW1Li 451 where CH1 c1 c 71 071 9 11 2071 j w 2071 A S11W11 S171W171 9801T1Ci11 W11 Cm71 W171 P S1 P SilWil P S171W171 C has the same form as capacitive coupling to the substrate but the capacitances are much larger as shown in g 437 p 205 We can still View the metal capacitance as an area term plus perimeter terms but the area and perimeter terms are determined by the spacings between metal lines in the layers Calculated values for the 018 pm process are in the table below for minimum width and minimum spacing in each layer All capacitances are in attofarads l aF 103918 F and distances in um Layer Ti Hii71 Si W1 CiirlA ClintP CiirlP C1311 CadjiL poly 027 018 ml 035 060 027 027 58 64 64 86 45 m2 035 085 036 027 41 48 61 89 34 m3 035 097 036 027 36 55 55 85 34 m4 04 090 036 027 39 58 58 92 39 m5 04 097 036 027 36 55 55 85 39 m6 07 095 09 09 37 56 113 251 27 Parasitic KL and C August 25 2009 page 14 of 19 I ECEN 4303 DigitalVLSl Design I Layer CiA CiP CL poly ml 89 50 124 m2 71 39 98 m3 68 39 96 m4 68 44 106 m5 64 44 105 m6 34 32 94 C iL is the total capacitance per unit length in layer 139 CiL CiAWi 2CiP The authors report C L as approximately 02 fFum whereas the calculations above are closer to 01 fFum The discrepancy is probably due to the authors assuming a metal plane in the layers above and below while we have included spaces between wires in lay ers above and below Also the widths and spacings used by the authors were smaller than the scalable design rules used above A good number to use is somewhere between 01 and 02 fFum for metal wires in modern processes Capacitance of contacts and vias top view HI CZ 39 T01 l EXT substrate I I I I contact overlap area Overlap area of contact should be included when computing cap of bottom layer but should not be included in cap of top layer Parasitic KL and C August 25 2009 page 15 of 19 I ECEN 4303 DigitalVLSl Design I 4 10 4 4 8 C 1 C2 A 10x24x44x452x2 A4X832 x2 overlap area of contact counts area of contact does not count P 444210444210 48 P 8 4 8 20 L boundary between poly conductor and boundary between poly conductor contact overlap does not count and contact overlap does not count The same arguments can be made for all other layers where the capacitive coupling to the substrate dominates diffusion layers For metal interconnect in modern processes where crosscoupling capacitance dominates the situation is slightly di erent CTOT CiCj7Cij side view All of the capacitance from both lines is still present except the C if which is shorted out by the contact or via Parasitic KL and C August 25 2009 page 16 of 19 I ECEN 4303 DigitalVLSl Design I Inductance L d VL V dt Note In this section L means inductance and 1 means length Typically wires inside a chip have inductance proportional to the wire length 015pHum lt lt l5pHum but this can be misleading because the true inductance depends on the complicated geom etry of the entire current loop including the power and ground lines Taking into account the parasitic J quot an 39 J a wire should be modeled as an RLC transmission line g 4 46b p 214 However when comparing the waveforms in g 446c leaving the inductance out does not change the results signi cantly and the wire can be modeled as an RC transmission line g 4 46a in most practi cal cases The inductance cannot be left out when the wire inductive impedance is greater in magni tude than the wire resistive impedance Leaving out the resistance gives us a lossless transmission line where electromagnetic signals propagate at the speed of light within the material One can show that this speed is l c 4 m where we have used the magnetic permeability offree space 411 X 10397Hm 125pHum because the materials used for wires are nonmagnetic c is the speed of light in vacuum 3 X 108 msec 300 umpsec Unless the wire is superconducting the resistance will cause signi cant losses if the wire is long enough In the next section we show that the propagation delay for an RC transmission line is W EGJGJIZ If we compare with the lossless case where 1 be we nd that the resistance dominates for long lines and the inductance dominates for short lines The boundary between the two regions corresponds equal LC and RC delays at l 2 iLl Rl C l Parasitic KL and C August 25 2009 page 17 of 19 I ECEN 4303 DigitalVLSl Design I which is shown as the horizontal boundary in the example in fig 445 p 213 The rise time of the signal driving the wire also determines the importance of inductance Faster rise times suffer more from inductive effects whereas with slower rise times induc tive effects are minimal One can show that the rise time of the step input response for the lossless transmission line is about 21 GK If the rise time of the input is longer than this inductance can be ignored Solving for l as function of input rise time gives 1 r which is the diagonal boundary line in the example in fig 445 The rise time constraint is easier to apply if we understand that in practical cases the rise time is approximately ltr 2RdriverC ZRmiverl where Rdriver is the output impedance of the transistors driving the wire and C is the total capacitance of the wire we will justify this later If the rise time is longer than trLC then inductance can be ignored This is satisfied by Ll R gt drlver Cl independent ofl Putting in typical values ofLl lpH and Cl 01fF gives 1009 for the minimum driver impedance Since typical sheet resistance for transistor channels is around 1049 it would take a very wide transistor to produce such a low impedance Replotting the constraints versus wire length and driver impedance gives Wire RC Delay Rise Time and length Dom1nates I RC Dominate Inductance Rise Time Matters Dominates driver 7 impedance As we shall see almost all digital design is done in the lower right quadrant with large Parasitic KL and C August 25 2009 page 18 of 19 I ECEN 4303 DigitalVLSl Design I impedances Only special cases with low driver impedance such as clock lines and power ground lines are effected by inductance In these cases routing a ground line with the signal can signi cantly reduce the inductance see g 447 p 215 Inductance is a concern for any IO signals since the offchip inductance of the package leads is much larger than the onchip inductances Just as nearby wires can couple capacitively through the electric elds caused by charges in adjacent wires they can also couple inductively through the magnetic elds caused by the movement of charge current in adjacent wires This is particularly a problem for long parallel lines in a bus Routing ground lines between the signal lines on a bus as in g 447 helps reduce inductive cross talk In extreme cases long busses it may be neces sary to twist the signal and ground wires ground signal DD Parasitic KL and C August 25 2009 page 19 of 19 I ECEN 4303 DigitalVLSl Design I Clocked Systems Cont Clock Skew Ideally every clocked element should see the same clock signals Clock skew occurs when delays in the clock distribution network cause clock edges to arrive at di erent times than they should Clock skew is caused by l delays in a single clock line Circuit Circuit 1 2 clk T T clock edge clock edge sooner later 2 Different delays on di erent clock lines clock edge clock edge sooner later 1 gt Circuit 1 4 2 1 Fig 715 p 400 shows how clock skew can cause incorrect operation of ip ops Only the magnitude of the clock skew tskew is shown It is more conventional to keep track of the direction of the skew by de ning tskew as the delay of the downstream clock clk2 rel ative to the upstream clock clkl in the diagram below FFl gt 010mlquot FF2 0 IC tpcq tccq t gt tpcq tccq T pd cd T lkl clkl clk2 C t t clk2 quot I tskew gt 0 l positive clock skew Clocked Systems Com September 5 2009 page 1 of5 I ECEN 4303 DigitalVLSl Design I clkl I I l I 1 t Clk2 T H itskewl tskew lt 0 I I I negative clock skew With this more general de nition of t the constraint on the maximum combinational logic delay tpd is skewgt combo logic T39pd ted tpcqtpdtsemp s T t tpd S T tskew 7 tpcq 7 tsemp corrected Eq 712 p 399 skew If tskew gt 0 more time for propagation delay tpd Good If tskew lt 0 less time for propagation delay tpd Bad Note that Eq 712 p 399 and Fig 715a p400 are correct if you interpret tskew as the amount of negative clock skew clocked Systems Cont September 5 2009 page 2 of 5 I ECEN 4303 DigitalVLSl Design I With the more general de nition of tskew the constraint on the minimum combinational logic delay ted is combo logic T39pd ted clkl clkz Fig 715b p 400 T l l t I 7 h tskew I l 39 39A t I r I I thomNI gt p tccq Q1 X I t DZT I l tccq tcd Z tskew thold tcd Z thold 7 tpcq tskew Eq 7 13 p 399 Ift Ift Skew gt 0 contamination delay ted must be larger Bad Skew lt 0 contamination delay ted can be smaller Good Note that Eq 713 p 399 and Fig 715b p400 are correct if you interpret tskew as the amount of positive clock skew Observe that the requirements on clock skew are mutually exclusive Positive clock skew is good for propagation delay but bad for contamination delay Negative clock skew is bad for propagation delay but good for contamination delay The solution is to keep clock skew as small as possible Methods to reduce sensitivity of design to clock skew 1 Force clock skew to be negative combo logic T39pd ted clocked Systems Cont September 5 2009 page 3 of 5 I ECEN 4303 DigitalVLSl Design I Negative clock skew causes setup time violations but not hold time violations Nega tive clock skew can be compensated by increasing the clock period T The circuit will work correctly but at a slower clock frequency N Insert minimum delays between ip ops clkl clk2 Positive clock skew causes hold time violations independent of the clock period The only x is to increase the minimum contamination delay of logic blocks between ip ops This may mean that it is not possible to drive the Dinput of a ip op directly from the Qoutput of a ip op without inserting bulTers E Reduce the number of global clock lines This eliminates the extensive design effort needed to synchronize clock edges on multiple clock lines all over the chip A single global clock line can trigger local clock generation circuits which provide local clock lines for any clocking scheme Allowance must be made for extra skew on signals that cross the local clock boundaries global clock clock clock clock gen gen gen local clock local clock lines I I lines local clock local clock local clock domain domain domain I I clock boundary I Simple clock gating can be used as clock generators which produce the local clock sig nals with correct timing Fig 1239 p799 clocked Systems Cont September 5 2009 page 4 of 5 4 UI O gt1 9 I ECEN 4303 DigitalVLSl Design I Phase locked loops PLL may be used to eliminate skew between different clock domains especially for different chips using the same external clock Fig 1230 p 790 PLL s use feedback of the local clock to zero out the phase error forces skew to zero between the external clock and the feedback clock Design of PLL s is beyond the scope ofthis course Use multiphase nonoverlapping local clocks If the clocks are misaligned by less than the nonoverlap period tnonoverlap gt ltskewl as in Fig 716 p 401 and if the constraints in Eq 714 716 apply then the circuit will work correctly If our sign convention for t is used then the sign oft in Eq 716 should be changed and it should read skew skew T tborrow S E tskew 7 tsetup tnonoverlap Use MUX s instead of gated clocks Fig 726 p 410 clock gate adds skew unless the clock gate delay is included in the clock distribution network Fig 1229 p 789 Organize the clock distribution network as tree a structure with equal delays on each branch The Htree Fig 1234 p 794 is an efficient layout ofthis idea In practice the Htrees turn out to be more assymetric as in Fig 1235 p 795 because of variations in the loading at di erent points in the chip Clock spines very wide low resistance glo bal clock lines have been found to be good for low skew clock distribution Fig 1237 p 796 Fig1238 p 797 Except for a short poly line at the end keep clock lines in metal to avoid excessive wire delays in clock signals no diff or poly crossovers clocked Systems Cont September 5 2009 page 5 of5 I ECEN 4303 DigitalVLSl Design I Transistor Sizing in Inverters Maximizing Inverter Speed minimize delay It is important to understand that the DC transfer curve is not of much use in predicting transient behavior ie switching delays because the input Vin must change m slowly for the DC transfer curve to be valid Correct determination of transient behavior during switching reguires including effects of parasitic capacitances These capacitances are a consequence of the IC fab process and cannot be entirely eliminated Recall that earlier we found that the wire delay was T d E ircL2 If we regard the FET as a nonlinear wire this formula holds for the FET also The sim plest thing a designer can do to minimize delay is to use minimum channel length small est possible L for all FET s in the logic gate This is always done when designing CMOS logic gates for both the pchannel and nchannel devices This applies to all types of gates not just in inverters Finding a value for the transistor widths W that minimize delay is more difficult Although the width does not effect the wire delay through the transistor itself W does have an effect on the on channel resistance recall Ron RSL W and therefore also effects inverter delay The inverter delay in our simplified switching model is RC which would seem to imply that the delay can be reduced by increasing Wto make R smaller However we must first take into account how changing transistor widths changes the capacitance Estimating Width Dependence of Load Capacitance Consider an inverter driving circuit node 139 Assume that only another single inverter is driven by this node driver T Ci load The interconnect resistances have been assumed to be negligible and the capacitances have been lumped into a single node capacitance C 1 which includes parasitic capaci tances from the transistors in the driver and transistors in the load as well as the wire con necting the gates together It will be convenient to divide the node capacitance into three C depends on the width of the driver m where C components Ct C C out wire out driver TCUuI TCWire TC load Transistor Sizing in Inverters August 19 2009 page 1 of 11 I ECEN 4303 DigitalVLSl Design I transistors C in depends on the width of the load inverter transistors and Cwire is indepen dent of transistor widths When logic gates are connected with short wires Cwire is negli gible compared with the other two Consider a horizontal style layout for an inverter driving another inverter of the same size l l lt gt the majority of logic gates in the circuit are about the same size to get good packing den sity of gates into the chip The layout clearly shows that the sizes of parts of the node depend on Wquot and WP The three major components of the node capacitance are as fol lows The MOSIS Deep Submicron SCMOS design rules are used Transistor Sizing in Inverters August 19 2009 page 2 of 11 I ECEN 4303 DigitalVLSl Design I inverter output capacitance poly he l llt gt T Cour The contributions from each layer to the inverter output capacitance are 1 Cg Cgquot 1 Cg Cgp Cg 51 WnLn FM391 51 Wpr F WP C C C Cndiff fawn 4x 4x2 gwn 10k 41 Wn C d 2 C d C d deiff 7PWp4x4x TfWp1oxgWp C W 4x W 4x le 7m14x12xquotTxPTx C W 47t W 47t TT1IZAquotT4K 4x The other half of the gate capacitance is not included since it is connected to the ground or power node not the output node Since both transistors are switching one switching on and the other off the Miller effect has been included in the gate contribution The gate overlap capacitance is much more important in modern deep submicron processes and cannot be neglected The metal area over di usion does not contribute to the capacitance since the diffusion screens the metal from the substrate If the parts of the capacitance that depend on W and WP are grouped together the total inverter output capacitance is Transistor Sizing in Inverters August 19 2009 page 3 of 11 I ECEN 4303 DigitalVLSl Design I C Cg Cndtff deiff le C t C t VWn VWPCWH where C 1C C Cd Cd Cd C1 J i n n g m Wn ZALquotPA4LPP 212 Cm we Cg CM CM Cm W E 52Lp74 775 Cnd 2 Cnd Cd 2 Cd C1 2 C1 1 1 m m Com 14 P10LA4L P 107t A 449t P 16 wire capacitance llt gt CW6 Cf sx 4x quot52 52 Transistor Sizing in Inverters August 19 2009 page 4 of 11 I ECEN 4303 DigitalVLSl Design I inverter input capacitance Poly over thick oxide C C I my f 4x4xL12x2L25x C 0 PTV4 4 44 4 12x225xL 25M Poly over thin oxide gate Cgquot WnLquot 221 Wquot CgP Wpr 2Egg WP The gate to source and gate to drain overlap capacitance is the same in modern processes Let s rst group the parts of the capacitance together that depend on the channel length L C1 L which means that the delay is tdf Rmci L L2 n tdr Rspci LL2 P Transistor Sizing in Inverters August 19 2009 page 5 of 11 I ECEN 4303 DigitalVLSl Design I which once again veri es that only minimum channel length should be used in digital designs We will assume from now on that L 27 which is the minimum design rule However the effective lengths Ln and LP can still be different If the parts of the capacitance that depend on W and Wquot are grouped together the total inverter input capacitance is Cm Cgquot Cg Cpoly C C Wquot WP CW Single Stage Inverter Delay The capacitances we have just calculated may be used to estimate the delay of a single inverter driving the capacitive load from another inverter of the same size Putting in the Wquot and W1 dependence of C 1 the rd equations become 2 3 3 Rani Wquot Wn WP WPCI 2L C C WWW WM P P N S n where RSquot R S are the npFET on channel sheet resistances and 3 Cm Wquot Wquot Wquot 3 Cm W WP WP P CI COMII C CinI As W increases the fall time decreases but the rise time increases As WP increases the wire rise time decreases but the fall time increases Transistor Sizing in Inverters August 19 2009 page 6 of 11 I ECEN 4303 DigitalVLSl Design I rd A tdf l dr W Id A l dr I df WI The design criterion that is most frequently used is to minimize the worst case delay The worst case delay is the largest slowest of the two delays Suppose that we start with a small value of Wquot The fall time delay is reduced by increasing W until the fall time and rise time curves cross Any further increase in W will increase the rise time which is now the worst case delay Similarly for WP We can see that the minimum worst case delay is obtained when tdf tdr Setting the rise and fall delays equal gives 12132 Wquot WP VVESEEZ W7 RSV The worst case delay is c c RMCI c 0 RS CI rd R 4 R 4 2x R 4 R 4 L2x Squot Wquot SP Wquot Squot Wquot SP tat diminishing returns gt Wquot W Note that C t C t l The delay cannot be made smaller than RMW RSPW2L n P Transistor Sizing in Inverters August 19 2009 page 7 of 11 I ECEN 4303 DigitalVLSl Design I N The last term RmC 1 Wquot from interconnect can be made negligible by choosing large widths There is a continuing decrease in delay as the transistor widths W and WP are increased but it takes larger and larger increases in Wto get a signi cant improvement in delay typical of the law of diminishing returns E Delay is minimized only for an in nite value of the transistor widths Clearly this is not an acceptable design criterion The area taken up by the inverter must be taken into account From the previous layout the inverter area is approximately Amv 2M Wn127t Wp2x16x The reduction in delay must be traded off against the increased area and power when the widths are increased This is a costperformance tradeoff area N cost 1 delay N perfor mance typically encountered in real world engineering designs Inverter Pair Delay Replacing the transistors in two series inverters by the equivalent switching circuits we have the two possibilities shown below depending on whether the input V0 is rising or Iquot quotP H t L falling The capacitive load on each inverter is the same since we are assuming that all inverters are the same size In either case an edge on V0 causes the transistors in the rst inverter to switch which causes a delayed edge on V1 The delayed edge on V1 causes the transistors in the second Transistor Sizing in Inverters August 19 2009 page 8 of 11 I ECEN 4303 DigitalVLSl Design I inverter to switch which in turn causes a further delayed edge on V2 The inverter pair delay is the sum of the delays of each individual inverter If the rst inverter output is ris ing then the second inverter output will be falling and the total delay is tdpair td tdf This is the same delay one would obtain if the rst inverter output is falling and the second rising To analyze the inverter pair delay it will be convenient to de ne new variables Z and Was ZsWPWn WE WPWn so that Wquot and W1 can be replaced by W W quot Z1 Z W W P Z1 so that the pair delay becomes R C C tdpalr fug x w 4 CI n P tat diminishin returns g W V The delay again decreases with Wbut cannot be made smaller than Rm Rm ZRM2N Transistor Sizing in Inverters August 19 2009 page 9 of 11 I ECEN 4303 DigitalVLSl Design I We will choose Wto satisfy the areadelay tradeoff and adjust Z to give the minimum delay for any choice of W The following plot shows the effects of choosing different Z tdpair I L Z Zopt From the plot Z01 is the value of Z that minimizes delay for a fixed W Z01 can be found from solving 6t quot 0 6Z which gives after some algebra RR S Sn Ci CWC CW W 1 WP I l The value for Z am is process dependent but typical values in modern processes are l I RSPRm m 2 which gives Zoptpair T AE in modern processes This applies to general situations when logic gates are driving another single logic gate of about the same size Recall that the optimum size ratio for minimizing the delay of a single inverter was dilTer ent Z 2 optinv T This applies to situations where a single logic gate has a much larger load than any other logic gate for example a bus line or other node with high capacitive load Transistor Sizing in Inverters August 19 2009 page 10 of 11 I ECEN 4303 DigitalVLSl Design I Note that using the Z aplpajr reduces the pair delay from 2talinv ltdpaiIIZ2 2 C 0 21 51Rm2t 4 Cr 7 P Ci 1 6Rsn27L W CI V V n l 2 2 tdpmzaE 1Rm2x Wquot J WP CI W 3 2J5Rm2x C1 n which is a reduction of 5836 or about a 3 improvement From the previous plot of delay vs Z the delay has a very broad minimum so that any choice lltZlt2 gives similar delay Designers often use a smaller Z to save area 2 E 2 m tdpairlz1 11Rm27tWn 1 WP C1 W Ci 1 6Rm27t W CI V V n Choosing Z 1 gives the same average delay as Z 2 but uses signi cantly less area The authors choose Z 2 to make analysis easier because rise time and fall time delays are the same Most designers choose a smaller Z to get faster and smaller circuits Therefore we will not assume equal rise and fall time delays and we will leave Z as a parameter that the designer can choose to optimize his circuits Transistor Sizing in Inverters August 19 2009 page 11 of 11

### BOOM! Enjoy Your Free Notes!

We've added these Notes to your profile, click here to view them now.

### You're already Subscribed!

Looks like you've already subscribed to StudySoup, you won't need to purchase another subscription to get this material. To access this material simply click 'View Full Document'

## Why people love StudySoup

#### "There's no way I would have passed my Organic Chemistry class this semester without the notes and study guides I got from StudySoup."

#### "I signed up to be an Elite Notetaker with 2 of my sorority sisters this semester. We just posted our notes weekly and were each making over $600 per month. I LOVE StudySoup!"

#### "Knowing I can count on the Elite Notetaker in my class allows me to focus on what the professor is saying instead of just scribbling notes the whole time and falling behind."

#### "It's a great way for students to improve their educational experience and it seemed like a product that everybody wants, so all the people participating are winning."

### Refund Policy

#### STUDYSOUP CANCELLATION POLICY

All subscriptions to StudySoup are paid in full at the time of subscribing. To change your credit card information or to cancel your subscription, go to "Edit Settings". All credit card information will be available there. If you should decide to cancel your subscription, it will continue to be valid until the next payment period, as all payments for the current period were made in advance. For special circumstances, please email support@studysoup.com

#### STUDYSOUP REFUND POLICY

StudySoup has more than 1 million course-specific study resources to help students study smarter. If you’re having trouble finding what you’re looking for, our customer support team can help you find what you need! Feel free to contact them here: support@studysoup.com

Recurring Subscriptions: If you have canceled your recurring subscription on the day of renewal and have not downloaded any documents, you may request a refund by submitting an email to support@studysoup.com

Satisfaction Guarantee: If you’re not satisfied with your subscription, you can contact us for further help. Contact must be made within 3 business days of your subscription purchase and your refund request will be subject for review.

Please Note: Refunds can never be provided more than 30 days after the initial purchase date regardless of your activity on the site.