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by: Louisa O'Kon I


Louisa O'Kon I
OK State
GPA 3.58

Louis Johnson

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Louis Johnson
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This 0 page Class Notes was uploaded by Louisa O'Kon I on Sunday November 1, 2015. The Class Notes belongs to ECEN 5263 at Oklahoma State University taught by Louis Johnson in Fall. Since its upload, it has received 17 views. For similar materials see /class/232904/ecen-5263-oklahoma-state-university in ELECTRICAL AND COMPUTER ENGINEERING at Oklahoma State University.

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Date Created: 11/01/15
I ECEN 5263 Digital VLSI Design I Memory Cont Example Design A very compact layout style for the CMOS static RAM cell is shown in fig 116 p 717 and the inside front cover The layout is somewhat dif cult to understand due to the stacking of the ndiffusion metall and meta12 layers along the bit line The crosssection along the bit line shown below should aid in understanding this very clever layout Design equation 5 with ratios as small as possible to maximize noise margin and equa tion 6 satis ed as nearly as possible to minimize read access delay can now be used to choose sizes for the transistors in the static RAM memory cell The following design pro cedure is recommended Choose the ncell transistor as big as possible without increasing the size of the layout The design equations specify relationships between the transistor sizes but they do not specify the absolute size of any transistor Satisfying equation 5 with small ratios requires a large Gym large WWW N Find Wylpr from equation 6 to minimize read access delay The optimal value of Wnpass is usually too large to make small ratios in equation 5 Choose Wnpass near minimum size as a compromise between high noise margin and low read access delay Choose Gpce so that equation 5 is satisfied Gpce may be small enough so that it is necessary to use a longer than minimum length for the pcell transistor as in fig 116 p 717 and the inside front cover E Step 1 examining the layout we find the biggest ncell transistor is around WWW 87 without increasing the memory cell size Step 2 design equation 5 requires us to estimate the capacitance on the bit line From the layout in fig 116 p 717 and the inside front cover we have Memory Cont November 3 2005 page 1 of5 I ECEN 5263 Digital VLSI Design I C 2quot C C bit dpass m 2quot MMmm 6x C C M3x2x 39quotlA d 4x4x1x3x A Typical numbers for a process give Cbit 066MV 68x2 npass with C in fF and Win um Equation 5 becomes 68 2 7t Wnpass 066ancell m I IOXWncell We can only satisfy 5 with small ratios if Wnpass lt Wnceu which requires Wnceu gt 107 In step 1 there was not sulTicient area to make Wnceu this large Even though the optimum Wnpass for read access delay would be about 97 we choose Wnpass 47 to gain noise margin This produces only a slight increase in read access delay Step 3 From 5 we want Gpcell anass Wnpass 47 l anass Gncell Wncell 8 2 Recall that l W G RD L so that Ggcell hlt WgcellLgcell anass Rap Wnpassanas where Memory Cont November 3 2005 page 2 of5 I ECEN 5263 Digital VLSI Design I RDquot REP Nil I in most processes Therefore 1Wpcellchellj l 2 2 Wnpassanas Wpcellchell Wnpassanass We choose the pcell transistor to be the same size as the npass transistor Wpceu 47 and cheu 27 In this case it was not necessary to choose a longer than minimum length pcell transistor These choices give the following read noise margin V V V V NMR mv dd Tn anass anGncell 7 GncellVTn Gpcell Vddi IVTpl anass V V 7 7 dd T Gncell Gpcell anass anGncell n VTn GpcellGncellXVddi IVTpl 7 anassGncell 1GpcellG G Gm an ncell npass Vdd VTquot Assuming an m 12 G G 12 npass ncell GpcellGncell GpcellG IVTpl m VTn Vdd 5 VTn npassanassGncell 14 gives 157147 12 7 VNMR 114 12125 1lVTquot 042VTn The write noise margin is the same Memory Cont November 3 2005 page 3 of5 I ECEN 5263 Digital VLSI Design I A modi ed layout is shown below The modi ed layout has a slightly smaller height bit E Vdd Will ii II i IIII Il because of a more clever arrangement of the poly contacts A faster circuit results if big ger transistors are used but the increase in speed must be traded off with an increased area The authors have chosen the same sizes in g 116 p 717 and the inside front cover 37 The authors choice makes except for the pcell transistor which has Wpceu cheu Ggcell h WgcellLgcell 137L37L l anass Rap Wnpassanas 2 LUV2 4 which changes the noise margins to Memory Cont November 3 2005 page 4 of 5 I ECEN 5263 Digital VLSI Design I VNMR 009 VTquot VNMW 066 VTquot Note that although the write noise margin is increased the read noise margin is decreased so that the worst case smallest noise margin is worse than using the sizes we found ear lier Memory Cont November 3 2005 page 5 of5


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