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by: Louisa O'Kon I


Louisa O'Kon I
OK State
GPA 3.58

Louis Johnson

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Louis Johnson
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This 0 page Class Notes was uploaded by Louisa O'Kon I on Sunday November 1, 2015. The Class Notes belongs to ECEN 4303 at Oklahoma State University taught by Louis Johnson in Fall. Since its upload, it has received 9 views. For similar materials see /class/232907/ecen-4303-oklahoma-state-university in ELECTRICAL AND COMPUTER ENGINEERING at Oklahoma State University.

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Date Created: 11/01/15
I ECEN 4303 DigitalVLSl Design I Power Dissipation Chip power dissipation budget air cooled packages cheap lt lOWchip heat sinks lt 200Wchip cooling uid expensive lt lOOOWchip Static Power Dissipation CMOS logic gates became popular in the early 1980 s because of low power consumption IDC m 0 3 PDC m 0 The power is not quite zero because of leakage currents As device sizes have decreased leakage currents have come to be a signi cant part of overall power dissipation There is small power dissipation from diffusion layer leakage currents 11er lt l uAcm2 through parasitic reversed bias pn junction diodes Fig 219 p 90 In modern processes with small VT the leakage current through off transistors has become much more important We have assumed that when VGS lt VT that there is no drain current but there is nonzero subthreshold current that increases exponentially as VT is lowered see eq 234 p 88 Many modern processes olTer a high VTtransistor high VT gt low ID gt slow to save power in noncritical delay paths As process dimensions continue to shrink quantum mechanical tunneling of electrons through the thin oxide underneath the gate produces signi cant current Fig 220 p 90 Pseudo nMOS pFETs always on I z i on Ronp Ronn on off two possible states for nFETs 01 off on Power Dissipation September 5 2009 page 1 of 12 l ECEN 4303 Digital VLSI Design I On average 12 of nFETs are on at any given time 1 1 l2 dd gt p V 1 DC 2 on 2 0np onn for each gate and the total static power dissipation is 13 ii DC Ngates 2R R onp onn where Ngam is the number ofpseudo NMOS gates Typical values are 01 10 mWgate Dynamic Power There are two components to the switching transient current 1 load capacitor chargedischarge through one FET 2 short circuit between power ground through both FET s Power Dissipation September 5 2009 page 2 of 12 I ECEN 4303 DigitalVLSl Design I Assume that the input risefall times are very fast so that both transistors are never on at the same time the short circuit current is negligible Fi 3 Cloud T Cloud output low to high output high to low Vm I 0 Tmz Tm Vout t IF g I I R I r Power is dissipated only in the transistors not the capacitor We are approximating zero current and therefore zero power dissipation in the nFET for 0 lt t lt T2 and in the pFET for T2 lt t lt T The average dynamic power dissipation is 1 Tm Pd itvtdt TSWIO 1 TSwZ 1 Tm I V dt I V 611 TSWIO Dp DSp TSWITSWZ Dn DSn where Power Dissipation September 5 2009 page 3 of 12 I ECEN 4303 DigitalVLSl Design I dV IDp icloada OM VDSp 7Vdd7 Vout dV 7 out IDn 7 icloada VDSn Vout Therefore 1 TSwZ dV t 1 Tm dV t Pd T 10 Cigar d10quotVddiV0mdt T 1T 27C0adt V dt SW xw out SW These integrals over time can be converted to integrals over voltage as in the following 2 dV VamOz 139 d1 malt J Vow i i 1 Vdd 1 0 Pd Cload Vdd 7 VoutdV0ut icloadVouthout sw 0 sw Vdd Cloud E E Tm 2 2 Tm is the switching period can be di erent for every gate De ne fm lTSW as switching frequency can be di erent for every gate Define activity factor at fSWf where f is the clock frequency Usually at lt l but can be larger than 1 when glitches occur 3 xC V2 d load ddvf total cap voltage switching with chang swing frequency ing voltage Note Power consumption reduced by reducing l Vdd2 gt reduce voltage swing reduce power supply 2 C load not capacitance on power ground lines gt rearrange circuit topology to reduce load capacitance Power Dissipation September 5 2009 page 4 of 12 I ECEN 4303 DigitalVLSl Design I 3 f gt reduce frequency reduce clock rate 4 or gt reduce activity factor turn clocks off during idle mode The dynamic power dissipation is the dominant mode of power dissipation in full comple mentary CMOS circuits Every logic family has dynamic power dissipation but it is usu ally not the dominant mode for gates with DC power dissipation Let s compare CMOS with pseudo NMOS P NMOS PDC CMOS gt f The load capacitance for NMOS is smaller than CMOS which makes the dynamic power consumption for NMOS smaller than CMOS but the DC power consumption of CMOS is orders of magnitude smaller than NMOS Total CMOS power dissipation is smaller when 1 3CMOS lt 13 DCNMOS 1 3NMOS 1 Vi CloaACMOS ngflt CloadNMOS 2Ronp Ronn l l lt f 2R0npRonnCloadCMOSTCloaANMOS l flt Ntrtf Tgttrtf As long as the switching period is larger than the sum of the rise and fall times CMOS cir cuits have a power dissipation advantage In clocked systems the switching period is close to the clock period which is usually about 10 times typical gate rise and fall times This allows CMOS gates to dissipate about 10 times less average power than pseudo NMOS CMOS Short Circuit Power Dissipation We have been assuming up to this point that the input signals change so fast that the nFETs are never on at the same time the pFETs are on For more slowly changing inputs this is not the case There will be a path from power to ground through the partially turned on FETs for a short time for any input waveform with a finite risefall time Let s assume Power Dissipation September 5 2009 page 5 of 12 I ECEN 4303 DigitalVLSl Design I a very slow risefall time for the input so that almost all current goes through both FET s and not into the load capacitance l IDI Vin ID i iIDn W IDnlIDp VddVTp Vinv VTn I I 39 I I t1 t239 it3 4 51 6 39 4 i T gt l I D sat limits current N A t I I Dquot sat limits current When the input voltage rises there is no current until the input voltage reaches VTquot and the nFET turns on at t1 Since we are assuming capacitive loading effects to be small the out put voltage follows the DC voltage transfer curve into the region where the nFET is in sat uration This situation continues until the input voltage reaches Vim at t2 A similar situation occurs when the input is falling n EsatnLnVint 7 VTn2 IDquot3 t1lttltt2t5lttltt6 Vina 7 VTn Art Eimerl When the input rises to Vim the output falls rapidly so that the pFET saturates The pFET stays on until the voltage rises to Vdd lVTpl where the pFET turns off at t3 and there is no more current A similar situation occurs when the input is falling Power Dissipation September 5 2009 page 6 of 12 I ECEN 4303 DigitalVLSl Design I 2 E V tiV 7V 7 P S IJLP quot 0 dd TP t2lttltt3t4lttltt5 I 7 DP 2 Vmt 7 Vddi VTpl APEWPLP The average short circuit power dissipation is 1 Tm PM T j IDPVDSPIDnVDSndt sw 0 1 Tm TI0 SW I VDsp VDSnldt I P D n but the circuit is constructed so that VDsp VDSn Vdd39 Therefore a Tm PM TSij 1136 611 n Vdd 2 t3 5 t6 EJIIIDndIIIZIIDPIdIIt41DPIdIJ tstndl The time dependence enters into I D and I DP only through Vina during the times needed for the integrals Vina varies linearly with time over these periods assuming a smooth ramp input so that the integrals over time can again be changed to integrals over voltage 1 VW Cum 1 Wm 1 me CUm 5 where V i t1 lttltt3 dVin tr 5 V dd it t4lttltt6 f The rst integral in the expression for 13 SC is Power Dissipation September 5 2009 page 7 of 12 I ECEN 4303 DigitalVLSl Design I m 2 Vdd t2 7 Vdd n EsatnLn Vin 7 VTn dVin J391Dndti J TSW 1 TSWV 2 Vin 7 VTn Art Esatrth Vddtr Tn I T r GnUinvi VTn ng sw where E L Gm AWEMLV AWELngt21n1 3 2Vdd n samL The other integrals can be evaluated in a similar fashion so that t 1 PM rT GnVinv 7 VTn GpUddi V39 7 IVTp ng sw mv where g Esat L V2 2 V GV LLE 7A VA lnl P 2V 2 PEthLP PEthLP APEMIPL If we rewrite the short circuit power in terms of the switching frequency ocf as before 13 trtfGnVi iVTnGPVdd7V ilVTplVdocf quotV quot1 1 we see that it has the same frequency dependence as the dynamic capacitive switching power Pd but it is also proportional to the rise and fall times of the input waveform not the output The short circuit power is completely wasted whereas the dynamic power 13d is consumed while doing useful work driving the output capacitance The input rise and fall times should be kept short enough so that P SCltlt Pd which implies that Cloud 7 VTquot GPVdd7 V 7 lVTpl tt r fltltGnVi quotV an This relation can be written in a more useful form if we replace C load by the rise and fall times at the output the rise and fall times we have been discussing are the rise and fall times at the input ltr01ttfout 2Ronp Rom39tCload which gives mwm R GV 7V GV 7V 7V t I t onp arm n mv Tn p dd inv Tp rm tn Power Dissipation September 5 2009 page 8 of 12 I ECEN 4303 DigitalVLSl Design I Using typical values for a 06m process and WV VddZ we have ltr out t out Z 62x103 253x10 6 088x10 6 X Z n i trin tfin 10 and for a 018pm process ltr01ttfout ltrin lt in 2189gtlt103 z 120x103163x10 6 044x10 6 gtlt Zm1 10 This demonstrates that the input rise and fall times can be as much as an order of magni tude slower than the output rise and fall times before we start worrying about short circuit power PowerPerformance Trade off The power dissipation in CMOS and other logic families too circuits linearly increases as the transistor sizes increase P The power consumption does not vary proportional to the area because the coef cients of Wquot and W are different in the power equations 2 The dynamic power dissipation is also proportional to the switching frequency This means that we can make widths larger for transistors that do not switch very often with out increasing the power very much E Short circuit power is most significant for small widths which produce slow switching 4 Power from leakage currents is insignificant in older processes but has become a big problem in the newest small line width processes Recall that the circuit delay decreases as the transistor sizes increase As we increase tran sistor sizes to improve speed we must pay a price in additional power consumption in addition to the increase in area Conversely if we decrease transistor sizes to try to con serve power then we must pay a price in additional delay Usually a range of widths can Power Dissipation September 5 2009 page 9 of 12 I ECEN 4303 DigitalVLSl Design I be found that meets a maximum allowable delay constraint and a maximum allowable power constraint tat P t W minimum power feasible solutions for W mlnlmum delay Within the feasible range the larger widths give smaller delay and the smaller widths give smaller power The picture above is for a single width the general solution must be obtained in multidimensional Wspace where there is a dimension for each transistor width This is a difficult problem in nonlinear constrained optimization Power Ground Line Sizing Sizing power and ground lines is done with di erent criterion than normal signal wires The power and ground lines carry much higher currents than signal wires because the cur rent passing through every gate in the chip must eventually come through the power and ground nets Also the power and ground lines are supposed to stay at a constant voltage and therefore may have a large capacitance This allows very wide metal lines to be used to handle the large currents The metal lines must be wide enough to handle the metal migration and ohmic drop problems discussed below Metal Migration Aluminum is used almost always to form the metal lines in integrated circuits The metal atoms are bound very loosely in solid aluminum It is possible for the metal atoms to be knocked out of their normal position by the conduction electrons collid ing with the atoms Once an atom is moved from its original position the wire becomes slightly thinner at that point V 1 0 metal atom A This increases the current density at that point which makes it more likely that another atom will be knocked away in the same vicinity An open circuit failure can eventually be produced if enough metal atoms are moved This phenomenon is called metal migration Power Dissipation September 5 2009 page 10 of 12 I ECEN 4303 DigitalVLSl Design I Metal migration occurs above a critical current density of about Jmm lmAum2 in alumi num t metal line thickness a l process constant I t I lt J Wmt mm or I W gt m J mmt Typically 05um lt tlt 10um so that um Wmgt12m A XI The current is usually estimated from the dynamic power dissipation Z 0cgatngme Vddf gates a a where the summation is over the gates that draw current through that section of the power or ground line Ohmic Voltage Drop Vdd I N GND 1 N We want the ohmic voltage drop AV to be a small fraction of the power supply voltage Vdd Let s choose AVlt 01 Vdd Then Power Dissipation September 5 2009 page 11 of 12 I ECEN 4303 DigitalVLSl Design I Lm AV Rsmetal 1lt 01Vdd Wm Rsmetal Lm gt m 01Vdd Typically Rsmetal S 019 Vdd 5V so that L Hm W Z quot39 39 5000mA 1mA Supply Line Width The power and ground line widths must be large enough so that both metal migration and ohmic drops are not a problem Comparing the two inequalities ohmic voltage drops are more of a problem for long lines If Lm gt 1000 um then ohmic drops are a more serious problem than metal migration and below this length metal migra tion is more serious Global power ground lines are most often sized to avoid ohmic drops and local lines are sized to avoid metal migration global ohmic drop Vdd l local metal migration GND Power Dissipation September 5 2009 page 12 of 12


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