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# DIGITAL LOGIC DESIGN ECEN 3233

OK State

GPA 3.58

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This 0 page Class Notes was uploaded by Louisa O'Kon I on Sunday November 1, 2015. The Class Notes belongs to ECEN 3233 at Oklahoma State University taught by Staff in Fall. Since its upload, it has received 14 views. For similar materials see /class/232910/ecen-3233-oklahoma-state-university in ELECTRICAL AND COMPUTER ENGINEERING at Oklahoma State University.

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7 if 7 i i i39 39 7 i 7 1 7 ii swim mi i i 39 739 i I i 1 Digital Logic Design James E Stine Jr Portions of slides taken from Digital Design and Computer Architecture D M Harris and S L Harris Elsevier 2007 OKLAHOMA Copyright 2007 Elsevier lt1 gt NIIERSITY ev quot F Boolean Algebra X s and Z s Oh My Karnaugh Maps Combinational Building Blocks Timing Copyright 2007 Elsevier 3 bk AHoiIITI VERS Y39 a f Set of axioms and theorems to simplify Boolean equations Like regular algebra but in some cases simpler because variables can have only two values 1 or O Axioms and theorems obey the principles of duality ANDs and ORs interchanged 0 s and 1 s interchanged Copyright 2007 Elsevier bK AHDMA jiulv VERS TY39 g 1 l u Ll Ll l l l 7 n quot u 39 x 5 quotfjj 5 5quot quot j I l l l J l l l J l l V l 7 3 v g y 1 J 739 39 39iv a 77 v V 7 V Axiom Dual Name A B 0 if B i 1 Al39 B 1 if B i 0 Binary field A2 U 1 Al39 T 0 NOT A3 0 0 0 0 A339 391 39l 39l ANDOR A4 1011 A439 000 ANDOR A5 001IOOO AS39 100ll ANDOR Theorem I u 31 Name T1 B o 1 B Tl B 0 B Identity T2 B 0 0 0 T239 B 39l 391 Null Element T3 B 0 B B T339 B B B Idempotency T4 B B Involution T5 B 0 B 0 TS39 B B l Complements 0K A 0M7I Copyright 2007 Elsevier lt4gt V gum VERS OKLA HaMA Copyright 2007 Elsevier lt5gt f r J 7 77 739 739 7quot W J 7quot 739 r a 3 V quot1 V 39 B0020 B11 Om II o A OKLAHOMA Copyright 2007 Elsevier lt6gt I J g gnu VERSITY if i 7 f I 1 J u m mm H to mm H to y f 4 OKLAHOMTI Copyright 2007 Elsevier lt7gt Copyright 2007 Elsevier lt8gt 3 runquot VERSITY mm U II CD mm H OKLAHOMA f Theorem Name T6 B 0 C C 0 B T6 B C C B Commutativity T B o C o D B o C o D 1quot B C D B C D Associativity T8 BOCBDB0CD T8 8 C BD BCD Distributivity T9 B 0 B C B T9 B B 0 C B Covering T10 B o C B at B TIO39 B C o B 7 B Combining T11 BOOHBO D COD Tll B C039BD0CD Consensus BoCBD BC39BD T12 3039 3139 32m Tll39 30 31 32quot De Morgan s 33 393 E BEOBTOBE Theorem 3 0K IHDM7I V r Copyright 2007 Elsevier lt1 Ogt i 7 39 9 39 f quot 1 quot l iquot quoty f If 39 V quot J L I 1 1 x 1 1 g H YABAB BZA T8 B1 T5 T1 4 bK 2 Hail7 Copyright 2007 Elsevier lt11gt 7 7 r i 39 39 F1 3 7 Y BAB ABC AAB1 C T8 AAB1 T2 AAB T1 AAB T7 AB T3 Copyright 2007 El ssss er 12 Copyright 2007 Elsevier ungt m3gt OKLAHOMA 2 x Ifquot S aquot F N LRSITY 1 V I A l i i 7 7 a r jg Q 1quot u if Pushing bubbles backward from the output or forward from the inputs changes the body of the gate from AND to OR or Vice versa Pushing a bubble from the output back to the inputs puts bubbles on all gate inputs A A o Pushing bubbles on all gate inputs forward toward the output puts a bubble on the output and changes the gate body A y A B 039 B Copyright 2007 Elsevier 7 7 7 777 7 7 7 7 t i i i N W 7 7 it 7 7 777 H i 7 7 7 7 7 t 7 t 1 3 i c J J J L g i t 7 7 t 7 V 7 i J 7 L 7 7 7 7 7 V 7 7 7 7 i J 7 7 7 7 7 7 7 What is the Boolean expression for this circuit A7 a 8 E bK 2 Han17 Copyright 2007 Elsevier plum VERS Y 7 7 7 777 7 7 7 7 t i i 7 i N W 7 it 7 7 7 777 H i 7 r n 7 7 v 39 r i i t 7 t 7 t i 7 i t i l V 77 i x I 1 1 i g i i t c J J J L x i t 7 7 A A 7 7 7 x t 7 7 7 7 V 7 i 7 V 7 V V 7 7 7 V 7 7 7 7 i 7 r 7 7 7 7 7 7 7 What is the Boolean expression for this circuit DO thgt i J N Y E quot YABCD l w u 3 f l I bKL39AHoMTq w 77 7 77 X r g 39 71 x77 3 t as 7 in lt gt i I ii aquot Iiquot i v 2quot 39 l quot J 1 plum VERSITY Copyright 2007 Elsevier 7 7 7 7 1 7 7 r 7 7 l i 7 7 l 7 r 7 7 7 7 7 7 7 7 Begin at the output of the circuit and work toward the inputs Push any bubbles on the nal output back toward the inputs 39 Working backward draw each gate in a form so that bubbles cancel J K 77 L wv l OKLAHOMA Copyright 2007 Elsevier lt17gt 7 rquot 4 l ll J j 3 gun VERSITY39 7 in 7 quotiquot 7 39 i i 7quot 39 quotiquot t t 7 j 7 r r w w 777 7r 77 W7 77 7 A 7 777 r n V 777 777 f t t t j if V V 7 t I 7 7 quot 2 3 2 t 39 V v Mfrquot i gt t V 39 t quot 39 t 39 v n t t t 39 V I 7 A A a 777 7 m u t r a 777 N V d L 7quot r 7quot W A 7 7 if L 77 t7 7 77 V 7 7 7 7 7 7 7 7 77 7 V 7 7 17 V V 7 if 777 t7 no output DQ bubble bubble on input and output DO WJgt no bubble on A6 input and output B j o o C D Y Copyright 2007 Elsevier Y D l h Twolevel logic ANDs followed by Ors Example 1721 96 A1736 ABC A B C minterm ABC minterm AEC J minterm ABC OK AHDMA Copyright 2007 Elsevier lt19gt l L 1 H U 7 1 if H i I H r w s a l quot771 J Ll Ll Ll l l J m a Inputs are on the left or top side of a schematic Outputs are on the right or bottom side of a schematic Whenever possible gates should ow from left to right Straight Wires are better to use than Wires With multiple comers l J 77 4 139 v bK AHDMA Copyright 2007 Elsevier lt20gt i VERS TY39 39 f n r r I I K quotii i 2 1 139 i quotfi 39 7 if 5 i i i Wires always connect at a T junction A dot Where Wires cross indicates a connection between the Wires Wires crossing without a dot make no connection wires crossing wires connect wires connect without a dot do at a T junction at a dot not connect Copyright 2007 Elsevier lt21gt i r 7 rquot i if J iridium VERS ryr r i 9 l J J quot T J J J i J i J 77 7J 7 7 J 7i 77 J 777 VJ J7 J 71 r 7777 J gt J 7 7 777 7 J 3 r 777 7 7 J 7 777 J 39 J J J J J J J J J J J quot39J J J J J J J j J J J J J J J J 77 I J l Ifquot 1 7 V 7V 739 l 7 y r V 3 gt h 77 7 J 7 7 J 7 7 m7 J J 7 J 7 7 r J 7 7 7 7 J 7 7 7 7 J 7 J 7 J Multiplexers Copyright 2007 Elsevier OKLA Hani7 39 Jigiunu VERSITY i F i 7 7 i w i 77739 7 7 3977 739 7 V 397 7quot l 7 V 739 39 7 y 3 W 39 39w 39 7 397 V V 7quot 39 739 39 7 7quot 39 V 39 V 739 39 1 3 77 7 x f 3 y 2 V a V V w t J K I 7 1 J t v 39 t v V7 quotgt a quot quotV V V quot 39x 39 V V 39 7quot 1 J 7 1 1 x I v V 7 r 7 7 t 7 7 7 7 W 7 Using the mux as a lookup table I I ogt I OI Om I OOOlt Y AB AB 00 O1 10 y bK AHDMA Copyright 2007 Elsevier lt24gt l w 7 L Q l l l l n l 1 Delay between input change and output changing One of the biggest challenges in circuit design making the circuit fast Time gt OKLAHOMA Copyright 2007 Elsevier lt25gt J gunquot VERSITY E n E I u w H l u Propagation delay tpd max delay from input to output Contamination delay tcd min delay from input to output Time 77 DKLAIIDMA Copyright 2007 Elsevier lt26gt frj iUNI VERSITY39 l r 2 l 39 1 T Delay is caused by Capacitance and resistance in a circuit Speed of light limitation Reasons Why tpd and ted may be different Different rising and falling delays Multiple inputs and outputs some of which are faster than others Circuits slow down when hot and speed up When cold Copyright 2007 Elsevier I Iquot l is J 539 UN VERS rvr 1 fquot a yquot 41409 Important Issues Datapath DeSIgn Control Lines Register 0 WalMart Customers had some Issues you writeReg2bits RA2 bits have to be careful about Mem wagons out IWriteRead YOU cannot read and erte lntO same reglster r Imriteirllegngl bit 39 rlte It That is you cannot read from Register 2 and write into Tiwr39lemem IMuxes I Register 2 e mi These control lines are not used all the time For example you would not need WriteMem when adding two values from the RF The Const is 2 bits long for no particular reason Ll39lpwlgm 2W7quot letre r Sllflz u L cuuyrlehi 2009 lamest hIIE ll m Now what Commands or Opcodes FOllOW the methodology We arbitrarily choose to have 2types of instruction formats so input is only 8 bits The user would have to know the format or else 0 DeSIgners resort to not glVlng the user too many inputs they have to deal with n 2 b39t 2 b39t 2 b39t 2 b39t In other words there are many ways to complete 395 395 395 395 tnlS prOblEm What we are trying to do is ForinstructionZoran add instruction minimize the command bits so the user only has quot3 to inputa small number of bits forlcommand I I I I 2 bits 2 bits 2 bits 2 bits 0 We arbltrary choose 8blts for our command HOW many possible combinations lS this For instructions 0 l and 3 or lw addi and sw instructions respectfully I could havejust given a 10bit sequence if I was feeling lazy DJ Wight JUAN arlw E Stink I l IJIQ lamb F irl39m Ir 15 Instruction Opcode RTRD RDCunst HV Cu39rmmd39lnz39szun Example l lw t2 Mem 00 XorO 2 XorO add t2 Stl StO 01 1 o 2 lemlstu addl Stl 5m 2 10 0 l 10 sw Memtl ll XorO l XorO N 7 3 s C ld b 012 3 39 h 4 i 23 g tutuunite r wilifin lfeannu 3 3 l write into some register reading Arbitrarily chose instruction example to be opcode Destination SDUICEZ Source2 Signals Iu uluua ll Chose binary encoding for opcode since only 4 instructions How would I Lprrifhl zoo lamp E Sn ne ll Cayurl h l uu know the be enmdlng I8 i 3 1 i i ii ii ii i i 7 i 39 r 739 i 39 i Digital Logic Design James E Stine Jr Portions of slides taken from Digital Design and Computer Architecture D M Harris and S L Harris Elsevier 2007 bKLIq Hail174 Copyright 2007 Elsevier lt1 gt Synchronous Logic Design Finite State Machines 7 J QOK AHDMA Copyright 2007 Elsevier lt2gt gulv VERS Y ft m i l ti 7 l7 lquot Ll 3 771 m M x quotl g 5 l T l j 1 i ll l 1121 v 211 quot Li fi 7 7 1 l 39 Sequential circuits all circuits that aren t combinational A problematic circuit This circuit has no inputs and 1 3 outputs It is an astable circuit that oscillates Its period depends on the delay of the inverters which depends on the manufacturing process temperature etc The circuit has a cyclic path output fed back to input 7 tquot y A Iquot 4 7 A OKLAHOMA Copyright 2007 Elsevier lt3gt 1 77 L f x u gunquot VERSITY 7 v f 2 11 i g l l l i r r r i Breaks cyclic paths by inserting registers These registers contain the state of the system The state changes at the clock edge so we say the system is synchronized to the clock Rules of synchronous sequential circuit composition Every circuit element is either a register or a combinational circuit At least one circuit element is a register All registers receive the same clock signal Every cyclic path contains at least one register Two common synchronous sequential circuits Finite state machines FSMs Pipelines 7 l f 91 J Copyright 2007 Elsevier lt4gt g l 1 u UNI VERSITYn g t t lquot i I r tirstawzv 39gewi39clti f9 Consists of CLK State register that Store the current state and S 3 Next Current Load the next state at the clock edge State State Next State Logic Combinational logic that N t ex Computes the next state E JV State Computes the outputs Output Logic E j0utputs Copyright 2007 Elsevier V 7 i 1 y J 7 j 3J 5 f UNI VERSITY39 47 W f 7 r39 a pesos Next state is determined by the current state and the inputs Two types of nite state machines differ in the output logic Moore FSM outputs depend only on the current state Mealy FSM outputs depend on the current state and the inputs Moore FSM CLK i k N state output logic outputs M 1 3 next neXt I state inputs Mealy FSM CLK i M Xt next he k state inputs 7 state logic 7 in J 1 i i X39 I r f 3 z iiiOKLAHOMA V v9 7 f f F E r r 5 Copyright 2007 Elsevier Together with Mealy developed automate theory the mathematical underpinnings of state machines at Bell Labs Not to be confused With Intel founder Gordon Moore 0 Published seminal article Gedankenexperimems 0n Sequential Machines in 1956 Copyright 2007 Elsevier A Published A Method OfSyntheSizing Sequential Circuits in 1955 Wrote the rst Bell Labs operating system for the IBM 704 computer l bk AHOM7I Copyright 2007 Elsevier lt8gt VERS Y39 r g f 39 if iii ll r 39 s i i it i 5 quot quot ii quot39 t Iquot Traf c light controller Traf c sensors T A T B TRUE when there s traf c Lights LALB Modified to be familiar to OSU AOJEQW J 7 1i i OKLAHOMA Copyright 2007 Elsevier lt9gt 7 gym VERSITY39 f Inputs CLK Reset T A T B Outputs LALB CLK T Traffic L Light TB Controller LB Reset 4 bK 2 Hail7 Copyright 2007 Elsevier lt10gt frigiulv VERS Y l39aquotzazt39 lr 39 Moore FSM outputs labeled in each state States Circles Reset Trans1t10ns Ares OKLAHOMA Copyright 2007 Elsevier lt11gt if Iquot l is J Y UNI VERSITY n I W ff Copyright 2007 Elsevier 1quot2 quotWNW quot 339 i39 l L 3911 x l H r f y 1 w 39 j f i w 393 1 I w 391 L xi x g I quotquot 2 Current State Inputs Next State SO S1 SO SO S1 S2 S2 S3 S2 S2 S3 gtltgtlt1gtlt1gtlt1HO gtltOgtltgtltgtltt SO W x j 7 1 gt in 139 1 3 lquot r 1quot a A I r t 3 r I I quot quotwk K I J r v 1 r 1 1 1 g I 1 2 s 1 A 1 1 7 1 r 1 1 1 1 1 1 1 1 1 1 1 1 X 1 i kg i SI Current State So Next State S O State Encoding SO 00 S1 01 S2 10 O O O 1 1 1 t OO OO OOt OOH S3 11 Copyright 2007 Elsevier lt13gt 1 If A4 1 J L 1 7 UNI VERSITY a 1 44 Jquot 75 L77 1 W15quot 171 LIDKLAHDMA J 3 S390 8O r Reset state register OKLA Hani7 Copyright 2007 Elsevier lt15gt 7 7 7 7 V 7 r 7 t 7 7777 7 7777 7 7 ti 7 7 gt 7 7 7139 77 77 77 7 J 7 7 7 39 7 39 r 7 7 t J 7 1 39 39 7 7 t h 7 7 7 t t r 7 x7 3 t x j 7 7 t I x 1 x 7 7 7 7 7 7 7 7 r 77 77 7 7 7 7 77 1 7 7 t 7 7 7 77 t 7 u r in 7 7quot r r r 7 77 W 77 w r r i wtw he 7 ix output logic outputs y xquot 4 OKLAHOMTI Copyright 2007 Elsevier lt17gt C e n K x W llllllllllllllllllllllll IIII muIIIIIIIIIIIIIIIII IIII O T 1 b S C y hIw C lill lllllll IMuUIIIII I 5 lllllllllllllllllllll I w m 4 9 m w 1 b O m w nVC S G R C gt vmW W o llllllllllllllllllllllll IIIWIIHIIAQMWII I 4 8 o m m m s 3 m y SI C WK wA 5 llllllllllllllllllllllll 1 inIIIIIIIIII I 3 7 3 b S C y C ml O lllllllllllllllllllllllllllllllllll IHII C IIMuM 3 6 O 1 n 1 d e e 6 ml d a R e y W C MU V n M I 5 llllllllllllllllllllllllllll IUIIHIIWIIV 2 5 2 m w e S mlx m d e y VMS Y C 1 O llllllllllllllllllllllllllll IWIIIIIIIII II I 2 4 1 b S C y C h IWA 5 3 b C y C IIIII IIM IIIIIIIIIIIIIIIIIIIII IIII IIII I O 2 2H 1 O y 0 nU r m C m m m m m I l l l l I I l l I l l I I l l l I I l l l I I l I I I I I I IIKIlllelllllllIllll I 5 e gf 0 O m w B C 1 S G R E I b 1 WA W C O C 7 7 7 7 J 7 7 7 7 0 t IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII III I h K 7 mu 9 A B O 0 0 O W C S L L C f l Binary encoding ie for four states 00 01 10 11 Onehot encoding One state bit per state Only one state bit is HIGH at once le for four states 0001 0010 0100 1000 Requires more ip ops Often next state and output logic is simpler 7 I llquot bKLhHoiIHI LUNI VERSITY39 r Alyssa P Hacker has a snail that crawls down a paper tape with 1 s and 0 s on it The snail smiles whenever the last four digits it has crawled over are 1101 Design Moore and Mealy FSMs of the snail s brain Classic String Detector OK AHDMA Copyright 2007 Elsevier quot lt20gt rquot i if J iquot zunl VERS rvp i W l 139 Moore FSM Mealy FSM arcs indicate inputoutput Mealy FSM J i 7 1v 0 OKLAHOMA Copyright 2007 Elsevier lt21gt J W UNIVERSITY 77 W 7 Digital Luglc Dengn James E sane lr Pamons at shdesiaken ton Distal Design and Computer Atdntteettte o M Hemsenns L HaYVlStEtsevleYt2 7 ctwrnuuann enter I Synchronous Logic Design I Finite State Machines ctwrnuuann entet Sequential circuits all circuits that aren t cornbinational Aproblematic circuit gtlt V Z itttttttt U123A5678ilmems This circuit has no inputs and 13 outputs It is an astable circuit that oscillates Its period depends on the delay ofthe inverters ewhich depends on the manufacturing process ternperature etc The circuit has acyclchath output fed back to input ctwrnuuann enter Breaks cyclic paths by inserting registers These registers contain the state ofthe system The state changes at the clock edge so we say the systern is synchronized to the clock Rules ofsynchronous sequential circuit composition 7 Every eireuit elernent is either aregister or a eornbinahonai eireuit Atleast one circuit elementis a register All registers receive the same clock signal Every cyclic path contains atleast one register Two c rnon synchronous sequential circuits 7 Finite state rnaehines FSMs e Pipelines ctwrnuuann entet Consists of 7 State registerthat Store the current state and 5 S Luadthenextstateatthecluckedge Eggs Next Sh e Logic 7 Combinationallogiethat Ne Curnputes thenext state sme Curnputes the uutputs Output Logic outpms CLK cawwuuzml enter cawwuuzml entet Next state is detennined by the current state and the inputs Two types of nite state machines di er in the output logi 7 Moor e FSM outputs depend only on the eurrent state 7 Mealy FSM outputs depend on the eunent stateandthe inputs MEIan FSM CLK M ne m v nets Ksn tsn N MM Meaty FSM inputs I Together with Mealy developed automata theory I Published A Method of Synthesizin g Sequential the mathematical underpinnings of state machines Circuits in 1955 at B 511 L 3175 I Wrote the rst B ell L abs operating system for the I Not to be confused with Intel founder Gordon IBM 704 computer Moore I Published seminal article Gedankenexperimems on Sequential Machines in 1956 oawnnom sum lt1gt cawrguuzmv Emmy lt5 Traf c light controller Inputs CLK Reset TA TE 7 Tramo sensors TA TB TRUE when there39s traf c Outputs LA LE 7 Lights LB Modi ed to 9 be familiar to OSU TA 7 Traf c LA Light TE 7 Controller LE l Reset anrguusz Elauhr s cawrguuzmv must an L I States Clrc e I TransitionsArcs Moore FSM outputs labeledin each state 1 s cawrguuzmv Enos A cawwuuzmv sum Sf 3 lt9 Sn LE y S u Ei a 5375 LED SSn cawrguuzmv mm A cawrguuzmv mm A gt Reset 513 2 yEmstev mum new 513 2 mum cawrguuzmv mm A cawrguuzmv mm As numunugm mum cawrguuzmv mm m cawrguuzmv mm A Binary encoding i e for four states 00 01 10 11 Onehot encoding 7 One state bitper state 7 Only one state bit is HIGH at once 7 1e for four states 0001 0010 0100 1000 7 Requires more ip op 7 O en next state and output logic is simpler capvngmmum Elseviev Moore FSM Mealy FSM arcs indicate inputoutput Mealy FSM Capvngm 2uu7 Elseviev lt1 9 Alyssa P Hacker has a snail that crawls down a paper tape with 1 s and 0 s on it The snail smiles whenever the last four digits it has crawled over are 1101 Design Moore and Mealy FSMs ofthe snail s brain ma Classic String 2 In 5724 Detector Mtg canwgmmum Elseviev Dlgltal Luglc Design James E suns Jr Pamans at slidestaken quotam Dlgnal Design and Campmev Armenure o M Hsmsanns L HaVHS ElsevleV ZDW cawnjn zml rrrisr I Outputs of sequential logic depend on current and prior input values I Sequential logic thus has memory I Some de nitions 7 State contains all the information about a circuit ecessary to explain its future behavior 7 Latches and ip ops state elements that store one bit of state 7 Synchronous sequential circuits combinational logic followed by abank of ip ops cawnjn zml rrrisr I The state of a circuit determines its future behavior I State elements store state to see more in depth later 7 Bistable circuit 7 SR L atch 7 D Latch 7 D Flip op cawrguuzml any I Introduction I Synchronous Logic Design I Finite State Machines cawnjn zml may I give sequence to events I have memory shortterm I use feedback from output to input to store information cawnjn zml rrrisi Sequential circuits all circuits that aren t combinational Aproblematic circuit 1 utzatselatimsms This circuit has no inputs and 13 outputs I It is an astable circuit that oscillates Its period depends on the delay ofthe inverters7which depends on the manufacturing process temperature etc The circuit has acyclchath output fed back to input cawrguuzml rrrisi Breaks cyclic paths by inseiting registers These registers contain the state ofthe sy t synchronized to the cloc Rules ofsynchronous sequential circuit cornpositi e t east one circuit elernentis aregister 7 All registers receive the sarne clock si nal 7 Every cyclic path contains atleast one register synchronous sequential circuits 7 Finite state rnachines FSMs e Pipelines cowrcucanii ririsr Next state is determined by the current state and the inputs Two types offinite state machines ditfer in the output logic 7 Moore SM outputs depend only on the current state a Mealy FSM outputs depend on the current state andthe inputs MuanFSM CLK M rext W V inputs sate Ksate Dutpms I ingll I MemyFsM cowrcucanii ririsr ern state changes at the clock edge so we say the systern is n 7 Every circuit elernent is either aregister or a cornbinataonal circuit A l Consists of 7 State registert a Stureth current state and XI Load the next state at the clock edge 5m 7 Cornbinational logicthat ccirnputesthenextstate Computes the outputs cowrcucanii ririsi Traf c light controller amp c LK 5 Cu nent State Next Stake Logic Output Logic ompu r Tratfic sensors TA TB TRUE when there39s traffic Z 7 Lights LA LB cowrcucanii ririsi Modi ed to be familiar to Inputs CLK Reset TA TE Outputs LA LE CLK i T 7 Traf c L A Light A T57 Controller LE i Reset cowniicami ririsr Moore FSM outputs labeled in each state States Circles Transitions Arcs cowniicami ririsi s s su S EI 1TAS1 UTE cawrguuzmv mm A cawrguuzmv mm A gt Reset 513 2 vEmstev cawrguuzmv mm A s cawrguum mm uu pu ugic mm mm next slam ugm cawrguuzmv mm m cawrguuzmv my Binary encoding i e forfourstates 00 01 10 11 onenot encoding l o 5 lt7 er state A only one state bit is HIGH at once 4 1e forfour states 0001 0010 0100 1000 A Requiresmore lpr op r O en next state and output logic is simpler cawrgu zml ennui anw im1ilwhr Selects between one ofNinputs to connect to the output logzNbit select inputr control input Example cawrgu zml ennui anw im1ilwhr Ninputs 2N outputs Onehot outputs only one output HIGH at once Minterm v A At A A3 Au V B is g Grey Encoding II cawrguuzml ennui cawrguuzml sum viii i331 1115 U quotiiagLiLJEiU Digital Logic Design Portions of slides taken from Digital Design and Computer Architecture D M Harris and S L Harris Elsevier 2007 Copyright 2007 Elsevier James E Stine Jr Introduction Combinational Logic Structural Modeling Sequential Logic More Combinational Logic Finite State Machines Copyright 2007 Elsevier U with E El if m 0 Hardware description language HDL allows designer to specify logic function only Then a computeraided design CAD tool produces the optimized gates 0 Most commercial designs built using HDLs 0 Two leading HDLs Verilog developed in 1984 by Gateway Design Automation became an IEEE standard 1364 in 1995 VHDL Developed in 1981 by the Department of Defense Became an IEEE standard 1076 in 1987 7 r V 1 L 39 maK AHaA L quotA 5 Copyright 2007 Elsevier lt3gt I 7 u A v 1 I 39 UN VEHS Y 4 fa I 0 Simulation Input values are applied to the circuit Outputs checked for correctness Millions of dollars saved by debugging in simulation instead of hardware 0 Synthesis Transforms HDL code into a netlist describing the hardware ie a list of gates and the wires connecting them IMPORTANT When describing circuits using an HDL it s critical to think of the hardware the code should produce Copyright 2007 Elsevier 3739 75772 777 4777 V v 2 ll l l ll l l H ll l a b Verllog y Module C Two types of Modules Behavioral describe What a module does Structural describe how a module is built from simpler modules JENDKLAHD LA I I Copyright 2007 Elsevier lt5gt 3177 711 Verllog module exampleinput a b c output y assign y a amp b amp c a amp b amp c a amp b amp c endmodule Copyright 2007 Elsevier lt6gt m if 7 7 Verilog module exampleinput a b c output y assign y a amp b amp C a amp b amp c a amp b amp c endmodule Now Ons 160 320 ns 480 640 ns 80C 80039 Illllllllllllllllll lla 0 Mlb 0 lilo 0 an 0 I Copyright 2007 Elsevier Verilog module exampleinput a b c output y assign y a amp b amp c a amp b amp c a amp b amp c endmodule Copyright 2007 Elsevier lt8gt 7 7 W quot Tquot i 1 r r 72 7 ice 2 Verilog is case sensitive So reset and Reset are not the same signal Verilog does not allow you to start signal or module names With numbers So for example 2mux is an invalid name Verilog ignores whitespace Comments come in singleline and multiline varieties single line comment gt lt multiline comment gtquot Copyright 2007 Elsevier lt9gt 39 7 xquot 7 x k u i 7 u WM 7 H module and3input a output y a amp b amp c b assign y endmodule module invinput a output y assign y a endmodule module nand3input a output y wire out b and3 andgatea inv endmodule b inverterout Copyright 2007 Elsevier quot 7 it t Cr C internal signal c out instance of and3 y instance of inverter module gatesinput gates acting assign assign assign assign 30 a b output 30 yl y2 y3 y4 y5 Five different two input logic on 4 bit busses a ampb AND a b OR a A b XOR a amp b NAND a I b NOR assign endmodule Copyright 2007 Elsevier yl y2 y3 y4 y5 single line comment multiline comment module and8input 70 a output y assign y ampa ampa is much easier to write than assign y a7 amp a6 amp a5 amp a4 amp a3 amp a2 amp al amp aO endmodule Copyright 2007 Elsevier J 77 77 7 V 7 quot77 7 l 7 7 gt W 7 r 7 gt quotV i tlwleltltWHHrtMHW module mux2input 30 d0 d1 input 5 output 30 y assign y s d1 d0 endmodule is also called a ternary operator because it operates on 3 inputs 5 all and 010 Copyright 2007 Elsevier x m a i 7mg module fulladderinput a b Cin output s cout wire p g internal nodes assign p a A b assign g a amp b assign s p A cin assign cout g p amp cin endmodule Copyright 2007 Elsevier Highest Lowest Copyright 2007 Elsevier De nes the order of operations NOT mult div mod addsub ltlt gtgt shift ltltlt gtgtgt arithmetic shift lt lt gt gt comparison equal not equal amp amp AND NAND A A XOR XNOR I OR XOR 399 ternary operator u A v 1 I 39 UN VEHS Y 1 9 I 117911m Format N39Bvalue N number of bits B base N39B is optional but recommended default is decimal Number Bits Base Decimal Stored Equivalent 3 b101 3 binary 5 101 b11 unsized binary 3 00 0011 8 b11 8 binary 3 00000011 8 b10101011 8 binary 171 10101011 3 d6 3 decimal 6 110 6042 6 octal 34 100010 8 hAB 8 hexadecimal 171 10101011 42 Unsized decimal 42 00 0101010 Copyright 2007 Elsevier assign y a2l 3b0 aO 3 blOOOlO if y is a 12 bit signal the above statement produces Y a2 Eil b0 bO kDUD a0 l O O O l O underscores are used for formatting only to make it easier to read Verilog ignores them Copyright 2007 Elsevier lt17gt i frUN VEHS Y j H a x i V 7 V 2 739 lt j if if 77 H r 77 H w r C 7 i in l x i 7 V gt Y CM l i all HM 7 m m Verilog dO dl module mux28input 70 input output 70 y 0 s y30 from slide 12 3941 dl74 s y7 from slide 12 mux2 lsbmuxd030 mux2 msbmuxd07 endmodule mux2 SyntheSIs Egt S w d030 y301 3quot 4W W d130 Isbmux mux2 S 4m d030 y30 4 d130 Copyright 2007 Elsevier rnsbmux riff 1 quot LE Verilog module tristateinput 30 a input en output 30 y assign y en a 439bz endmodule Synthesis Copyright 2007 Elsevier module exampleinput a b C output y wire ab bb Cb n1 n2 n3 assign l ab bb Cb a b C assign 2 nl ab amp bb amp Cb assign 2 n2 a amp bb amp Cb assign 2 n3 a amp bb amp C assign 4 y nl n2 n3 endmodule Copyrig module exampleinput a b C output y wire ab bb Cb n1 n2 n3 assign l ab bb Cb a b C assign 2 n1 ab amp bb amp Cb a amp bb amp Cb a amp bb amp C assign 2 n2 assign 2 n3 assign 4 y nl n2 n3 endmodule Copyright 2007 Elsevier 397 D 7 7 39quot i quot391 r F it A 3 I quot 5 quot A t 7 Ju i ll llil H1 7 7 W 7 77 7 i 7 Verilog uses certain idioms to synthesize into latches ip ops and FSMs 0 Other coding styles may simulate correctly but produce incorrect hardware Copyright 2007 Elsevier 77777777 quot7 i 739 w 7 7 V J 7 r 1 7 i i 2 397 39 39u 39 391 39 397 x General Structure always sensitivity list statement Whenever the event in the s en 3 i t ivi t y l i s t occurs the statement is executed Copyright 2007 Elsevier module flopinput elk input 310 d output reg 30 g always posedge elk q lt d pronounced q gets d endmodule Any output assigned in an always statement must be declared reg In this case q is declared as reg Beware A Variable declared reg is not necessarily a registered output We Will show examples of this later Copyright 2007 Elsevier module floprinput input input output reg synchronous reset always posedge olk if reset q lt 439bO else q lt d endmodule Copyright 2007 Elsevier D3O 1301 R module floprinput input input output reg asynchronous reset always posedge elk posedge reset reset 30 d 30 q if reset q lt 439bO else q lt d endmodule Copyright 2007 Elsevier gt D3O 1301 R Q310 lt26gt J f 1 if rUNIIIERSITY v l 39 a we m yam m h Hm module flopreninput elk input reset input en input 30 d output reg 30 q asynchronous reset and enable always posedge elk posedge reset if reset q lt 439bO else if en q lt d endmodule Copyright 2007 Elsevier module latchinput clk input 30 d output reg 30 q always clk d if clk q lt d endmodule lat W 330 Q30 mmmgt CI3I 0 Warning We won t use latches in this course but you might write code that inadvertently implies a latch So if your synthesized hardware has latches in it this indicates an error Copyright 2007 Elsevier lt28gt if r t if f rUNIVE SITY v I 39 2 7 339 v i i 16quot 7 quot 1 l U l l Ll h 139 r is r l b exit dim b i llf il 71H 5 ltll l Eh Ll Copyright 2007 Elsevier Statements that must be inside always statements ifelse casecasez Reminder Variables assigned in an always statement must be declared as reg even if they re not actually registered ECEN 3233 Rule of Thumb When in dm g always implement structurally and not behaviorally lfelse and casecasez are good examples of behavior level code However if coding manuals usually called something like Coding Styles for Verilog for your compiler such as modelsim dictate different behavior ways of coding logic then its best to follow these documents 39UN VEHS TV 1 mt 0 Use always posedge clk andnonblocking assignments to model synchronous sequential logic always posedge clk q lt d nonblocking 0 Use continuous assignments to model simple combinational logic assign y a amp b 0 Use always and blocking assignments to model more complicated combinational logic Where the always statement is helpful 0 Do not make assignments to the same signal in more than one always statement or continuous assignment statement Copyright 2007 Elsevier lt30gt 7 t t 7 7 t D wf g J 7 R r 1 V4 g quot 1 5 Z W U i 1 7 M 5 H H i t t W 7 t t if 7 7L 7 v iii U U U i Three blocks next state logic state register output logic M inputs 0 k next k state state output OUt 113 u p logic Copyright 2007 Elsevier jsz I 7 gig 1 37 135 H The double circle indicates the reset state Copyright 2007 Elsevier Q39bK39LA HonHI i UNI iEns139v f 4 MLM Wary f W W x a Cw m 9 Lajva ugg m gnuufj Jan 0 AM Hi Ju Digital Systems Digital Systems are part of every engineering system They work on groups of ls and Os called bits Each system is a combination of combinational and sequential systems that work together to perform some task How can we take what we learned earlier to help use design a system Q Digital System Methodology Draw block elements of your datapath or computational logic you mightwant to use identifying all inputs and outputs of these blocks gt Before proceeding further make sure each individual block works correctly gt This is usually done through simulation either at the board level orthrough HDL simulation Try connecting all the blocks together Once you connect your computational blocks or datapath together it isusually advisable to simulate your datapath elements so that they behavecorrectly Once you have your datapath elements connected together build thecontrol block of your digital system gt The control block shouldcontrol the datapath design via signals that have been highlighted to becontrollable Simple Design 4bit wide operands Input 9 A Output 9 Z Desjg a 39 gi de e m that does the following Operauon m based off of a Add 4 A ZA01002 or ZA 410 command Output 4 x z01oo2 or z410 Copyright 2009 James E Stine Jr 4 1 Put down parts that you thing will belong to this computation These parts become the datapath Make sure each part works rst though First Step Copyright 2009 James E Stine Jr Notice that I might be wrong with the parts I choose Iamjust trying to think what would elements might be useful U i Its that easy Another Example Design a simple calculator for Wal Mart that they can sell for 1 Each digital device uses 4 bits Let s use several digital devices 3 4 word register le Stores 4 registers and is dual ported Memory storage device Stores or Reads only 1 element writeMem1 write into memory from input of memory writeMemO read from memory from output of memory A carry propagate adder User Needs User requires 4 commands for his customers m 1 ZRD Mem lw Load Word from Memory into RF ie register RD 2 ZRD ARS BRT add Add 2 registers from RF and place result back in RF 3 ZRD ARS 2 bOO Const addi Add Constant 2bits to 1 register from RF and place result back in RF 4 Mem ZRD sw Store Word from RF ie register RD into Memory Used to simplify name calling NaNaNaNa Copyright 2009 James E Stine Jr 12 Important Issues 0 Wal Mart Customers had some issues you have to be careful about You cannot read and write into same register That is you cannot read from Register 2 and write into Register 2 The Const is 2 bits long for no particular reason Datapath Design Control Lines Register writeReg 2 bits RA 2 bits RB 2 bits WriteRead writeMem 1 bit Write 1 bit Muxes 51 1 bit 52 1 bit 2130 Quaimi These control lines are not used all the time For example you would not need WriteMem when adding two values from the RF Copyright 2009 iames Stine Jr 12 Now what Follow the methodology but 0 Designers resort to not giving the user too many inputs they have to deal with In other words there are many ways to complete this problem what we are trying to do is minimize the command bits so the user only has to input a small number of bits for 1 command We arbitrary choose 8 bits for our command How many possible combinations is this Commands or Opcodes We arbitrarily choose to have 2 types of instruction formats so input is only 8 bits The user would have to know the format or else quot35 2 bits 2 bits 2 bits 2 bits For instruction 2 or an add instruction quot5 2 bits 2 bits 2 bits 2 bits For instructions 0 1 and 3 or lw addi and sw instructions respectfully I could have just given a 10bit sequence ifl was feeling lazy Copyright 2009 James E Stine Jr 16 Control Logic Structure Con rnwld39lnsu unun h 5331 Ft RT REIDat Cannot 8103i mam w 15 I39 73 E 239 39r w 339 1 5 gt m if x Sign MS 0 Dsmuam Copyright 2009 Janms E Stine Jr Control Examples Instruction Opcode RT RD RDConst Example 00 lw t2 Mem X or 0 2 X or 0 add t2 tl t0 01 1 O 2 add Stl t0 2 10 0 1 10 sw Memt1 11 X or 0 1 X or 0 Could be 0 1 2 or 3 since we have 4 locations to store in RF remember cannot write into same register reading Arbitrarily chose instruction example to be opcode Destination Sourcel SourceZ Chose binary encoding for opcode since only 4 instructions How would I know the best encoding Copyright 2009 James E Stine Jr 18 Goal The MIPS design is just a system with a whole bunch of digital logic and instructionscommands Our goal for this exercise is to add two instructions as an example similar to what we have to do for our project part I ori bitwise OR immediate or OR a constant with the contents of a register bne branch if not equal Use our methodology in class I have given you the unmodi ed logic you just have to add logic to handle these two new instructions The rst instruction will obvious use the ALU OR function The second instruction will obviously use ALU and if two values are equal or get a zero output when subtracting RTL RTL or Register Transfer Language is just a short form for a description digital designers to help them understand what is happening to the computation ori rt rs 16 b0 imm bne If rs rt then PC PC 4 16imm15 imm ltlt 2 MIPS Digital Logic 0 MIPS is broken into three parts G Register File RF to store data ALU which does basic computation 6 Memory to store data when there is too much of it and it will not t in the RF 0 The current MIPS digital logic also contains memory to store its instructions but this could be supplied by the user when it needs it Instructions from Project mnmmmmmmm 1 1 00 0 5 5 0 0 0 0 0 addi 205 0 20020005 2 0 04 addi 703 0 0 3 3 0 0 0 0 0 20070003 3 0 08 addi 300Xc 0 0 12 12 0 0 0 0 0 20030000 4 0 0C or 4 7 2 0 3 5 7 0 0 5 0 0 00e22025 5 0 10 and 5 3 4 0 c 7 4 0 0 7 0 0 00642824 6 0 14 add 5 5 4 0 4 7 b 0 0 7 0 0 782 7 0 18 3511 5 7 and 1 b 3 8 0 0 3 0 0 10a7000 8 0 1c sIt 6 3 4 0 c 7 0 1 0 7 0 0 0064302a 9 0 20 beq 6 0 around 1 0 0 0 1 1 0 0 0 06000 10 0 28 slt 6 7 2 0 3 5 1 0 0 5 0 0 00e2302a 11 0 20 add 7 6 5 0 1 b c 0 0 b 0 0 00053820 12 0 30 sub 7 7 2 0 c 5 7 0 0 5 0 0 00e23822 13 0 34 j and 1 0 0 0 1 1 0 0 0 0800000f 14 0 3c sw 7 712 0 5 47 4c 0 0 7 1 0 ac470047 Copyright 2009 Jamos E Stine Jr Unmodi ed Digital Logic Only 1 bit Comln l n ma 3U I Jump MemtoReg InstructIo sstored bon rOIMemWrite UnIt Here co Id also have Branch been M6 ALUControlm PCSrc 39 o I Without 50 p ALusrc Funct RegDst BegWrite ZXK CITK WE3 Instr A1 RD1 A RD 3 ALUResult A RD ReadData Instruction 2016 Memory A2 1 RD2 O smB Data A3 1 Memory Register WriteData WD3 File PCJump PCPlus4 4 PCBranch 270 31228 Simple register used by Memory to tell where instructions are stored ie Extends MSB for adding value from RF to a 16bit constant sign extension address can be modi ed to jump to new instruction v 1 r it 0 W I Temporary data stored here Aaddress WDData to Write if RF lls up since its small only has 32 locationsquot Modi ed Digital Logic Instructions come out of memory and go to control and datapath to handle uses zero reSUIt W39th BranCh NEQ operation same as our example The values going to the datapath are values pCSrc supplied by user The control transforms Jump MemtoReg the instruction i to sinals to help the BLLBZEZOI MemWrite datapath work Bram ALUControlZO Op ALUSrcm 50 Funct RegDst RegWrite CLK l CLK l 1 WE3 WE 2521 A1 Rm 0 Result A RD ALUResult A RD ReadData Instruction 2016 A2 R02 Memory A3 M22 Register WriteData y WD3 WD File 2016 C PCJump 1511 1 WriteReg PCPIus4 4390 150 Sign Extend 9 Si 39m Selects OR Zerolmm PCBramh constant 150 Zero Extend 270 I 31 28 250 Added for OR Immediate since constant is 16bits gt since ALU operates on 32bits Co Fun with Boolean Logic James E Stine Associate Professor Electrical and Computer Engineering Department Oklahoma State University Stillwater OK 74078 USA 1 De nitions The following are some de nitions that may be useful for Boolean Algebra Which is the essential underWire for Digital Logic Design Boolean algebra theorems and axioms can be used to simplify Boolean equations As explained in the text these Boolean algebra rules are very similar to those of ordinary algebra but many are simpler This occurs because the number set is signi cantly reduced to only contain 0 and 1 0 An Axiom is a mathematical statement that serves as a starting point from Which other statements are logically derived 0 A Theorem is a type of abstract object Which can be derived from the rules of the formal system that is applied to the formal language usually based off or derived from a xed set of inference rules or axioms Without any additional assumptions 0 A Dual of an expression is computed by replacing every by a every by a every 1 by a 0 and every 0 by a 1 Without changing the order of computation dual f9 19 2awaxma3910fxlax2awaxmu0 1 o A Lemma is a proven proposition Which is used as a stepping stone to a larger result rather than a statement inandof itself 2 Boolean Algebra This section is meant to give the various Boolean algebra axioms and theorems used in the book along With some more advanced and extremely powerful versions The more advanced expressions such as Shannon decomposition are used in programs such as espresso to simplify Boolean logic Table 1 Axioms of Boolean algebra 21 Generalized De Morgan s Theorem z1z2mzn HITm x1x2xn 971T2m Involution 0 1 Table 2 Boolean Theorems of One Variable Table 3 Boolean Theorems of Several Variable 22 Shannon s Theorem fx1x2mxn fmfmuqmw 23 Shannon s Decomposition Theorems Careful extremely powerful f961962w96n 961f1962w96n f0962w96n fx1x2uixn x1f0x2iux f1x2iuxn The decomposition theorems which are usually attributed to Shannon what else isn t can be easily generated by comparing truth tables of both sides of the equations when 951 1 and when 950 0 rom these decomposition theorems a powerful result is formulated that allows many of the synthesis packages including the ones in your Xilinx software to simplify many of your schematics and Hardware Descriptive Language HDL code including espresso xlfx1x2uixn xlf1x2uixn xlfx1x2uixn 71f0x2uixn x1fx1x2uix x1f0x2uixn 971fx1x2uixn 971f1x2iux 4308 Important Issues Datapath Design Control Lines WalIVIart Customers had some issues you RegiSt terzegabits have to be careful about RF m Mem 2853 You cannot read and write into same register 3 WM 4 0 ert frftaedMem 1 bit That is you cannot read from Register 2 and write into riteMem Mux2sNrite 1 bit Register 2 These control lines are not used all the time For example you would not need WriteMem when adding two values from the RF The Const is 2 bits long for no particular reason 14 Copyright James E Stine Jr Copyright James Stine Jr Now what Commands or Opcodes We arbitrarily choose to have 2 types of instruction formats so input is only 8 bits The Follow the methodology but user would have to know the format or else Designers resort to not gIVIng the user too many inputs they have to dea with 2 bits 2 bits 2 bits 2 bits In other words there are many ways to complete this problem what we are trying to do is mm39m39ze the Command 39039 50 the user on39y 35 to Input a small number of bIts for 1 command 2 bits 2 bits 2 bits 2 bits We arbitrary choose 8 bits for our command How many possible combinations is this For instruction 2 or an add instruction For instructions 0 1 and 3 or lw addi and sw instructions respectfully I could have just given a 10bit sequence if I was feeling lazy Copyright James he Jr J a Copyrigi39rt 200 James E he Jr Control Logic Structure Control Examples Instruction Opcode RT RD RDConst Example 00 f Corrmmd39lanUjan g lw St2 Mem X or O 2 X or O 2925 RE RT Routznsz add Stzl Stl Sto 01 1 O 2 CcnlrslBh l Stl StO 2 1 O sw Memt1 11 X or O 1 X or O h x 1 TI T 3 w Could be 0 1 2 or 3 since we have 4 51 395 ii 39 locations to store in RF remember cannot g 3 write into same register reading Arbitrarily chose instruction example to be opcode Destination Sourcel SourceZ S39vqnsls to Datapath s Chose binary encoding for opcode since only 4 instructions How would I know the best encoding Copyright EEJJJEJ James Stine Jr Copyright ZJJJZ JB James E Stir e Jr 17

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