### Create a StudySoup account

#### Be part of our community, it's free to join!

Already have a StudySoup account? Login here

# DIG ELTRNC CIRC DESIGN ECEN 4303

OK State

GPA 3.58

### View Full Document

## 9

## 0

## Popular in Course

## Popular in ELECTRICAL AND COMPUTER ENGINEERING

This 0 page Class Notes was uploaded by Louisa O'Kon I on Sunday November 1, 2015. The Class Notes belongs to ECEN 4303 at Oklahoma State University taught by Staff in Fall. Since its upload, it has received 9 views. For similar materials see /class/232916/ecen-4303-oklahoma-state-university in ELECTRICAL AND COMPUTER ENGINEERING at Oklahoma State University.

## Popular in ELECTRICAL AND COMPUTER ENGINEERING

## Reviews for DIG ELTRNC CIRC DESIGN

### What is Karma?

#### Karma is the currency of StudySoup.

#### You can buy or earn more Karma at anytime and redeem it for class notes, study guides, flashcards, and more!

Date Created: 11/01/15

I ECEN 4303 DigitalVLSl Design I Designing Complex Gates When larger more complicated logic gates are designed we can usually neglect the inter connect resistance as we did for inverters However there may be more than one transis tor turned on at one time and the resistance of each FET channel must be taken into account For example consider the following complex CMOS gate B 0 A o H T C2 Y A T Cour H w All of the parasitic capacitance cannot be lumped into the output capacitance because the two internal nodes are separated from the output node by a FET with a large channel resis tance which cannot be neglected We need to develop a method for estimating delays in circuits with arbitrary parallel and series combinations of FETs The situation is simpli ed if we only consider worst case delays At rst glance one might think there are only 6 delays in the circuit a rising and a falling input on each of the 3 inputs propagates after a delay to the single output However the delays from one input to the output really depend on the DC values of the other two inputs Let us consider a rising edge on the Ainput The output Y starts high and will be pulled low through nFET A and either or both oanETs B and C IfB C 0 then the output does not go low at all and the delay is meaningless since the output does not change The other cases for a rising edge on A are shown below Designing Complex Gates September 6 2009 page 1 of 14 I ECEN 4303 DigitalVLSl Design I When B C 1 both of the nFETs in parallel are on This allows larger current to ow and discharges the capacitances more quickly than the other cases Thus it is not the worst case delay In general when more than one nFET in a parallel combination is on it cannot be the worst case delay I H i quotEU a 31 C2 C1 T Y Tcout RM 1 a w When B 0 and C 1 only nFET C is available to conduct current so that the current must be less than the previous case and the capacitances will discharge more slowly Note however that C2 does not get discharged in this case u quot5 u E Goa H H o G N Qlt Q S N Rnc C1 Designing Complex Gates September 6 2009 page 2 of 14 I ECEN 4303 DigitalVLSl Design I WhenB l and C 0 only nFET B conducts so it is slower than when both nFETs B and C are on Furthermore pFET C is on which makes it necessary to discharge C2 This is usually unless RnB ltlt Rnc the worst case since we have the most capacitance to dis charge with the least amount of current RA A0 gt1 p 31 C2 RC C0 P T Y Tcout RnA RnB T C1 The essential point here is that parallel combinations of nFETs never show up in estimat ing worst case delay A similar result holds for pFETs in parallel For full complementary gates no transmission gates we only need to consider RCtree circuits where each branch in the tree may have several resistors in series but there is never a loop through resistors Elmore delay for RC tree circuits The easiest type of RC circuits to estimate delay are the so called tree circuits They are characterized by a single resistor connected to power or ground and then other branches connected in a tree like fashion with a resistance on each branch and a capacitance to AC ground on each node Note there are no closed loops of resistors in this type circuit Sup TC4 C7T T C8 pose all voltages are initially at some value that may be di erent than the VddGnd node Designing Complex Gates September 6 2009 page 3 of 14 I ECEN 4303 DigitalVLSl Design I When the VddGnd node is Gnd all of the node voltages fall to Gnd as the node capaci tances are discharged When the VddGnd node is Vdd all of the node voltages rise to Vdd as the node capacitances are charged Imagine a loop current starting in each capacitance through a purely resistive path to the VddGnd node and thence to AC ground Because of the tree structure there will always be a single unique path from each capacitor to the VddGnd node The example shows 1398 starting from C8 and going through R8 R7 R5 R2 and R1 Then the voltage at node 6 is Ve ZRekik k where Rek is the resistance of the path to the VddGnd node shared by node 6 and node k and 139 k is the loop current from capacitor k Since the loop currents are the capacitor dis charge currents de 1k Cka then it is possible to nd the Elmore delay at each node 6 When the voltages are falling the fall time delay at node 6 can be estimated as tEfe vetdt Ve0ZkZRekaj g dt fmZkZRekajjkm dvk ZszekC Similarly for nodes with rising voltages the rise time delay can be estimated as Vddivk0 wr Ere 2k e Vddivea When all of the node voltages start at the same voltage this is not always true then the last fraction drops out and we have Designing Complex Gates September 6 2009 page 4 of 14 I ECEN 4303 DigitalVLSl Design I lTie ZRekCc k We will use the Elmore delay to approximate the risefall delays and risefall times in the same manner as for the inverter 7 vkw tdfe tEfe ZRekCc V em k Vddvk0 5 E R kck re re 2k e This is the approximation used in the irsim circuit simulator It is also simple enough to use in hand calculations for estimating the performance of dilTerent circuit topologies Example 1 The fall time delay of the output in the CMOS gate whenA switches from low to high withB 0 and C l A0 gt1 30 C1 Rnc is the only resistor on the path from the output to ground and the path from C1 to ground Both Rnc and RM are on the path from C out to ground The current from C2 does not go to ground and does not contribute to the fall time delay VY0 7 V10 tde RnCC 1m RnA RnCCoutm Before the transistors switch we can see that Designing Complex Gates September 6 2009 page 5 of 14 l ECEN 4303 Digital VLSI Design I VY0 Vdd V10 0 Putting these initial values into the voltage factors in the delay equation gives tde RnA Rudcom Since C1 started at ground it ended up with no net effect on the delay Example 2 The fall time delay of the output in the CMOS gate whenA switches from low to high withB l and C 0 A0 gt1 31 C RnB and Rnc are both on the path from the output to ground and the path from C2 to ground RFC does not contribute to the delay at the output node since RFC is not part of the output to ground path RFC does contribute to the delay at node 2 we are not normally interested in this delay since it is not an output V10 V20 tilY RnBclm RnA RnBCout RnA 1193sz 7 V10 VY0 rm 7 RnBclm RnA RnBComm RnA RnB RPCC2 The effect of RFC is to make the delay at node 2 longer than the delay at the output node Before the switching takes place we see that V10 0 and V20 VY0 Vdd Taking these initial voltages into account the delay estimate is Designing Complex Gates September 6 2009 page 6 of 14 I ECEN 4303 DigitalVLSl Design I td RnA RnBC2 C out Once again there is no contribution from C1 to the delay since it is already discharged but this time there is a contribution from C2 since it discharges through the output node to ground This is the worst case fall time delay fromA to Y Example 3 fall time when B switches from low to high and11 C0 RPB A l B 0 gtl C2 C RFC T Y RnA T Cour RnB Before the transistors switch we can see that VY0 Vdd V10 Vdd VTquot V20 Vdd Recall that our model is only accurate within a factor of 2 At this level of accuracy there is no difference between Vdd and Vdd VTquot V10 m Vdd V20 V10 tde RnBClWO RnA RnBCom RnA 1193sz RnBCl l Rn1 Rn3C C2 out Designing Complex Gates September 6 2009 page 7 of 14 I ECEN 4303 DigitalVLSl Design I In our original derivation of the Elmore fall time delay we assumed that the all the node voltages would be completely discharged to ground eventually This is not the case for node 2 it falls to lVTpl whereupon the pC FET turns off We ignore this nonzero nal voltage since it changes the delay by less than a factor of 2 Series combinations of MOSFETs using our simple Ron model R0711 R0712 R07 3 Vin quot A A quotAquot TC 39 LC lcm Tl T 2 T 3 which has an Elmore delay assuming the left side is the input and the right the output rd R0n1C1R R C2R R0nZR C3 onl onz onl 0 13 Identical Sized FETs If the FETs are all the same size and the interconnect is the same length then Ron C l are all same and Id 1 2 3 R0nC 7 NN 1 7 TRMC gt delay through N FETs in series increases as square ofN This limits the size of CMOS logic gates to a small number of inputs Since the pull up and pull down circuit are duals then one or the other will have a series combination of FETs with large delay see the gate designs in chapt l The N2 delay also limits size ofpass transistor based designs A 4 to l MUX has two pass transistors in series An 8 to 1 has three pass transistors in series etc As the MUX s get larger the delay increases as the square of the number of transistors in series Designing Complex Gates September 6 2009 page 8 of 14 I ECEN 4303 DigitalVLSl Design I ContrastN FETs in series to N inverters in series C C C T T T As was derived earlier the total delay is the sum of the delays of each gate pair N N rd Ead tdf 5RP RNC The total delay is proportional to N not N2 This implies that delay can be reduced by using more small gates than fewer large complex gates Rule of thumb to avoid N2 delay keep the number of transistors in series N S 4 High complexity gates vs low complexity gates The designer has a choice of using a small number of complex gates or a large number of less complex gates to synthesize the desired logic functions Some of the logic forms that we will study later favor using large complex gates Full complementary CMOS favors small simple gates Let us take for example the synthesis of a NAND gate with N inputs The most straight forward way of implementing this is with a single large gate with fin N The layout for this gate shows that the area is proportional to N the total number of inputs I 12 I ll I I I AmnTMNN Our previous analysis shows that the delay of the gate can be approximated as 7 2 rd 7 t0t1Nt2N Designing Complex Gates September 6 2009 page 9 of 14 I ECEN 4303 DigitalVLSl Design I As an alternative to a single large gate let us consider the following tree of NAND and NOR gates where each gate has fin inputs 4 N w w There are a total of N inputs to the circuit and there are a total of ms stages so that a path from one of the inputs to the output goes through 713 small gates It will be necessary to add an extra inverter to achieve the NAND function when 713 is odd but we are neglecting this The area of each individual gate is proportional to fin so that fin WAUV 1403quot The delay of each gate is 2 Id to tlfint2fin Then the delay of the tree is 2 tdtree nst0 t1fm tzfm If we assume that there are no leftover inputs on the tree then 5 lnN nNornS lnfi so that the tree delay is lnfm 2 tdtree lnNt O If 5 2quot Note that the tree delay is proportional to lnN which is much smaller than a single com pleX gate delay whenN is large Thus a tree structure is always preferable if we want to minimize delay but as usual there is an area penalty Designing Complex Gates September 6 2009 page 10 of 14 I ECEN 4303 DigitalVLSl Design I The area of the tree structure is made from two parts the area of the gates and the area of the signal routing between gates To nd the area of the gates we must nd the total num ber of gates ng The top row of the tree has Nfm gates and each row has lfm as many as the previous row until the bottom row which has only one gate which is very close to n 1 g fin1 The area taken up by the gates alone in the tree is Atree igates rig103quot N f lAm 7 fin1N f fin1 Am Since the area of the tree gates is also proportional to N just as the single gate it would appear that there is only a slight area penalty in using the tree However we must also include the routing area needed to connect the gates together One possible scheme when fin 2 is to lay the gates out in a line with the routing as shown below The area below the gates is often called a logarithmic routing channel It is characterized by many odd shaped spaces and gaps that make the layout inef cient in its use of area A careful examination shows that the maximum number of routing wires in parallel is log2N lnNln2 Since there are N l gates across the top the total area taken by Designing Complex Gates September 6 2009 page 11 of 14 I ECEN 4303 DigitalVLSl Design I H H H H H H lvlvlvlvlvlvvlvlvvlvl ll ll W the routing channel is N llnN ln2 In general for arbitrary fan in lnN ln Atreerouting N As N gets very large over 30 the routing will take up more area than the gates them selves complex gate delay area tree I 39 N N4 30 ompleX gate 1 tree always faster for large gates 2 tree is signi cantly bigger for veg large N Optimum value for fan in We have reached the conclusions above without specifying how big the individual gates in the tree should be that is what the optimum value of fin should be If we want to choose fin to minimize area then the above results show that a single complex gate with fin N is best If we want to choose fin to optimize speed then we must nd the value of fin that minimizes the tree delay Recall Designing Complex Gates September 6 2009 I ECEN 4303 DigitalVLSl Design I 2 l 0l lfinl5t2finJ tdtree lnN Inf optimal fin The optimal fin can be found from d dfmtdaree 0 Note that this minimization procedure optimizes the coefficient of lnN it does not change the fact that the tree delay is proportional to lnN Setting the derivative to zero one has the following equation for the optimal fin 2 to t1fm tzfm t1 thfm 2 Mn 23 If 2 fin012t2fin nfin l 0 l lfinl thin 0 This transcendental equation cannot be solved analytically in general but can be solved in the following interesting cases to is the dominant delay term This corresponds to a fixed delay for each gate regard less of size not very realistic The optimal fin is very large A more precise solution in this case shows that the optimal fin N that is a single complex gate N II is the dominant delay term This corresponds to using well designed gates in the tree that do not have any significant delay terms proportional to fin2 final nfin 1 1 in lnfm 1 ft 6 Since we cannot have fractional numbers of inputs the optimal fin 3 We have a small optimal fin in this case because several small well designed gates in series can have a smaller delay than a single large slow gate E t2 is the dominant delay term This corresponds to using not so well designed gates in the tree that have significant delay terms proportional to finz Designing Complex Gates September 6 2009 page 13 of 14 I ECEN 4303 DigitalVLSl Design I momma riff lnfm 12 124 Since we cannot have fractional numbers of inputs the optimal fin 2 We have a smaller optimal fin in this case because there is more of a time penalty associated with high fan in These cases show that any signi cant variation in gate delay vs fin will cause the optimum fan in to be a small number This is in good agreement with our rule of thumb which said to keep the number of series transistors less than four Designing Complex Gates September 6 2009 page 14 of 14 I ECEN 4303 Digital Electronic Design I CMOS Logic Gates Fig 18 p 8 nMOS and pMOS FET Fig 19 p 9 Fig 119 p 15 switch model Fig 110 p 10 inverter Table 11 inverter truth table The inverter has several good characteristics Both FET s are never ON at the same time no static current implies no static power consumption and nMOS passes 0 pMOS passes 1 Fig 121 p 16 noninverting bulTer This has poor performance because nMOS passes 1 pMOS passes 0 Don t use it Fig 120 p 16 transmission gate Note that two gates have complementary inputs and therefore require two different control signals More complex logic gates are based upon the inverter and transmission gate Fig 113 p 11 inverter based gates Table 13 p 11 output states Fig 114 p 12 series parallel switches Fig 111 p 10 CMOS NAND Table 12 p 11 NAND truth table Note that the pchannel FETs in the pull up circuit implement the 1 s in the truth table and the nchannel FETs in the pull down circuit implement the 0 s in the truth table Fig 112 p 11 3input NAND Fig 115 p 14 CMOS NOR Table 14 p 13 NOR truth table Note that the pchannel FETs in the pull up circuit implement the 1 s in the truth table and the nchannel FETs in the pull down circuit implement the 0 s in the truth table Fig 116 p 13 3input NOR Fig 117 p 14 a compound complex gate The function F AB CD is written in such a form so that it is easy to identify the zeroes of F ie whenever AB CD is true F should be 0 We can use this to design the pull down circuit out of nchannel FETs Whenever1 and B are both 1 there should be a path from F to ground The and combination can be implemented by a pair of nchannel FETs in series CMOS Logic Gates August 27 2008 page 1 of 16 I ECEN 4303 Digital Electronic Design I M Bi Similarly there should also be a path from F to ground whenever both C and D are 1 Another pair of nchannel FETs can be added in parallel with the rst pair to accomplish this In general whenever an and combination is required a series combination of FETs Ai Ci Bl Dl can be used to implement it An or combination can be implemented with a parallel combination The same procedure can be used for the pull up circuit to implement the 1 s of F but rst F must be written in a form that makes it clear what the 1 s are Using DeMorgan s laws F AB CD EXC D Z Tax 1 we see that whenever Z E D is true F should be 1 We can regard the pull up circuit as a series combination of two subfunctions Z E and 55 CMOS Logic Gates August 27 2008 page 2 of 16 I ECEN 4303 Digital Electronic Design I Whenever both subfunctions are true there should be a path from power to F Each subfunction can be implemented as a parallel combination of pchannel FETs We can now put the pull up circuit with the pull down circuit to form the complete CMOS logic gate FABCD Al Bi 0 a a a CMOS Logic Gates August 27 2008 page 3 of 16 I ECEN 4303 Digital Electronic Design I Fig 118 p 15 another complex gate F ABCD ATEEE 23539 5 true for 1 s A ABCD trueforO s It is not really necessary to derive both the pull up and pull down circuits Once one has been derived the other can be determined easily The pull up and pull down circuits are duals of each other Whenever there is a series combination in one the other must have a parallel combination Fig 126 p 18 tristate inverter The truth table is The truth table in Table 15 p 17 is for a transmission gate which is the same as a truth table for a NONinverting tristate buffer Beware that the transmission gate is not really a buffer since the output is connected to the input when the transmission gate is on Fig 127 p 19 MUX Table 16 p 19 truth table This design style is significantly di erent than what was done for the inverter In the inverter the output is connected directly to power or ground through the FET switches In the MUX design the output is instead connected to one of the inputs through the FET switches This design style is called pass transistor logic because the input passes directly through the switches to the output CMOS Logic Gates August 27 2008 page 4 of 16 I ECEN 4303 Digital Electronic Design I Pass transistor logic can frequently be used to reduce the transistor count in a circuit implementation Consider a complex CMOS gate that implements the same function as the MUX but with inverted output Y D1SD2S 171 W172 S Fig 128a p 19 CMOS inverting MUX Fig 128b p 19 tristate inverting MUX Fig 12 p 20 tristate inverting 4 to 1 MUX The CMOS gate for the inverting MUX has twice as many transistors as the pass transistor implementation of the noninverting MUX So does the tristate implementation But they both provide buffering that the transmission gate MUX does not Fig 130 p 21 latch Fig 131 p 22 register The above two examples show that pass transistor style design can also be used in clocked systems to reduce transistor count Compare the design for the latch with one made from standard logic gates There are two complex gates with 6 FETs each plus an inverter for a total of 14 FETs The latch on p 21 has 8 FETs CMOS Logic Gates August 27 2008 page 5 of 16 I ECEN 4303 Digital Electronic Design I Stick Diagrams COLOR NAME FUNCTION green ndllT sourcedrain yellow pdilT red poly gate blue metal 1 Violet metal 2 interconnect light blue metal 3 Connections crossing lines in same layer are always connected crossing lines in di erent layers are always Econnected CMOS Logic Gates August 27 2008 page 6 of 16 I ECEN 4303 Digital Electronic Design I nFET pFET exception poly crossing dilT always makes FET even if you don t want one there To get connections between layers use contacts 1 l l I I I Note contacts possible between metal and any other layer but that is all Metal must be one of the layers in the contact For example Impossible one other restriction Impossible pdl and ndl cannot touch Rules of the layer game 1 Keep areas of all interconnect not FET to a minimum 2 Keep interconnect lengths to a minimum in the following prioritized order ndiff pdiff short lengths only poly short or intermediate lengths OK metal 1 metal 2 etc any length OK 3 Use as few contacts as possible 4 One of the layers in the contact must be metal CMOS Logic Gates August 27 2008 page 7 of 16 I ECEN 4303 Digital Electronic Design I Layout Procedure 1 Make transistor circuit diagram Vdd GND 2 Make stick diagram symbolic layout to help plan layout a For each transistor make short diffusions for source and drain and cross with poly to make gate Vdd Note pdiff and ndiff cannot lt touch at output GND b Complete stick diagram by adding interconnect plus power and ground connections Note short interconnect can be poly but long interconnect must be metal Do not use di usion lines for interconnect Vdd short poly m interconnect l D 1 D GND CMOS Logic Gates August 27 2008 page 8 of 16 I ECEN 4303 Digital Electronic Design I 3 Use the layout editor program to make layout by eshing out stick diagram with cor rect spacing and line widths without design rule Violations Symbolic Layout Examples inside front cover Fig l43a p33 inverter The width of the lines has no real signi cance Note that the transistors are rotated so that a straight poly line can be used to make the transistor gates This makes for much more efficient layouts for CMOS gates Fig 172 p 65 NAND gate Layout style from transistor diagram Fig l43b p 33 NAND gate The line of diffusion layout style is more efficient since it allows transistors to be placed end to end sharing contacts and has much simpler gate con nections with parallel poly lines Fig 855a 855b p 557 NOR gate Two versions ofthe line of diffusion layout style The one with the fewest contacts on the output node is faster The line of diffusion layout style can be extended to more complex gates by attempting to layout all of the FETs of each type end to end This is possible if a path through the transistor circuit can be found that includes each transistor once and only once Fig 849 p 552 Finding circuit graph from the transistor circuit diagram Fig 850 p 552 Euler path from graph and corresponding layout CMOS Logic Gates August 27 2008 page 9 of 16 I ECEN 4303 Digital Electronic Design I Simpli ed design process using Euler paths Euler Paths o D Both paths must go through transistors in same order We know immediately that the stick diagram will look like this Blue Vdd GND red CMOS Logic Gates August 27 2008 page 10 of 16 I ECEN 4303 Digital Electronic Design I Then we add the metal interconnect to implement the rest of the circuit topology B1 ue Vdd GND D red There may be several different valid stick diagrams for the same logic gate By inter changing the nMOSFETs controlled by C and D the Euler path can also be chosen as fol lows Euler Path CMOS Logic Gates August 27 2008 page 11 of 16 I ECEN 4303 Digital Electronic Design I This results in an equally good but different stick diagram Blue Vdd GND red Not all circuits have an Euler path By putting the pMOSFET controlled by A at the top there is no Euler path and instead the two paths shown must be used I No Euler Path A i This results in a stick diagram with a gap in the pdiffusion Note the extra contacts com pared with the other designs of the same gate Whenever an Euler path is possible it gives CMOS Logic Gates August 27 2008 page 12 of 16 I ECEN 4303 Digital Electronic Design I a more compact layout than layouts with gaps in the diffusion lines Blue Vdd GND red After the metal lines are routed one can check the stick diagram for obvious errors A few examples are shown below Leaving the end of a di usion line unconnected causes an short m 1 open open circuit fault Strapping a metal line over a single transistor causes a short fault across the transistor Fig 851 p553 Cascaded gates with common inputs For faster gates whenever there is a choice always reduce the loading contacts on nodes closer to the output node For example faster Slower CMOS Logic Gates August 27 2008 page 13 of 16 I ECEN 4303 Digital Electronic Design I Recall transmission gate de nition 2 Transmission gates do not easily t into the line of diffusion layout style because a the vertical poly line must be split for the two complimentary inputs Recall the circuit for the transmission gate multiplexer K l K l S E Euler paths through the pFETs and the nFETS give the following stick diagrams I I l I I B A I l l A B ALI t I IB I I I s Y s s Y s Crossovers are necessary in either metal or poly CMOS Logic Gates August 27 2008 page 14 of 16 I ECEN 4303 Digital Electronic Design I Making Layout from Stick Diagrams Stick diagrams symbolic layout show which layers are used and the relative position of the layers but they do not accurately depict the width of the layers or the spacing between them The line widths and spacings must be chosen carefully when constructing layouts Common mistakes made by naive designers Make channel at least as wide as contacts Use minimum space between series transistors and between con tacts and transis tors This means that real layout can look somewhat di erent from the stick diagrams For example in the NOR gate the poly lines in the layout are not straight even though they are drawn that way in the stick diagram This is necessary to minimize the distance between the series pFETs while accommodating the contact between the nFETs Fig 855a p 557 NOR gate stick diagram CMOS Logic Gates August 27 2008 page 15 of 16 Digital Electronic Design ECEN 4303 NOR gate layout u u ruq u rrvw u u u rru u u u r wJJII1III1IIII1 rLLIIIrrLLIIIrrLLIIIr L LIIIr IIIrL LIIIrLLIII III1IIII LLIIIrLLIIIrLL IIIr Note that the layout looks like a lled out stick diagram but the spatial dimensions are no longer arbitrary Also the exact shapes may be slightly di erent as for example the dog legs in the poly lines page 16 of16 August 27 2008 CMOS Logic Gates

### BOOM! Enjoy Your Free Notes!

We've added these Notes to your profile, click here to view them now.

### You're already Subscribed!

Looks like you've already subscribed to StudySoup, you won't need to purchase another subscription to get this material. To access this material simply click 'View Full Document'

## Why people love StudySoup

#### "I was shooting for a perfect 4.0 GPA this semester. Having StudySoup as a study aid was critical to helping me achieve my goal...and I nailed it!"

#### "Selling my MCAT study guides and notes has been a great source of side revenue while I'm in school. Some months I'm making over $500! Plus, it makes me happy knowing that I'm helping future med students with their MCAT."

#### "Knowing I can count on the Elite Notetaker in my class allows me to focus on what the professor is saying instead of just scribbling notes the whole time and falling behind."

#### "Their 'Elite Notetakers' are making over $1,200/month in sales by creating high quality content that helps their classmates in a time of need."

### Refund Policy

#### STUDYSOUP CANCELLATION POLICY

All subscriptions to StudySoup are paid in full at the time of subscribing. To change your credit card information or to cancel your subscription, go to "Edit Settings". All credit card information will be available there. If you should decide to cancel your subscription, it will continue to be valid until the next payment period, as all payments for the current period were made in advance. For special circumstances, please email support@studysoup.com

#### STUDYSOUP REFUND POLICY

StudySoup has more than 1 million course-specific study resources to help students study smarter. If you’re having trouble finding what you’re looking for, our customer support team can help you find what you need! Feel free to contact them here: support@studysoup.com

Recurring Subscriptions: If you have canceled your recurring subscription on the day of renewal and have not downloaded any documents, you may request a refund by submitting an email to support@studysoup.com

Satisfaction Guarantee: If you’re not satisfied with your subscription, you can contact us for further help. Contact must be made within 3 business days of your subscription purchase and your refund request will be subject for review.

Please Note: Refunds can never be provided more than 30 days after the initial purchase date regardless of your activity on the site.