VLSI & Adv Digital Dsgn
VLSI & Adv Digital Dsgn ECE 3060
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This 0 page Class Notes was uploaded by Cassidy Effertz on Monday November 2, 2015. The Class Notes belongs to ECE 3060 at Georgia Institute of Technology - Main Campus taught by Sung Lim in Fall. Since its upload, it has received 11 views. For similar materials see /class/233855/ece-3060-georgia-institute-of-technology-main-campus in ELECTRICAL AND COMPUTER ENGINEERING at Georgia Institute of Technology - Main Campus.
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Date Created: 11/02/15
ECE 3060 VLSI and Advanced Digital Design Lecture 4 Layout Design amp Tools Cell Design Principles Cell Floorplanning Separate nFETs and pFETs Use One Continuous Well when Possible 0 Set Pitch Using Power and Ground Lines 0 Run Busses with Metal 1 and Metal 2 Perpendicular Route External Signals to Edges of Cell DON T FORGET Substrate and Well Contacts 0 Select Around All Active E CE 3060 Lecture 4 2 Layout Example CMOS Inverter 0 Set Pitch place well and powerground busses 15653060 Lecture 473 Layout Example CMOS Inverter 0 Add Transistors active select and poly 15653060 Lecture 44 Layout Example CMOS Inverter 0 Make Connections poly metal and cuts 15653060 Lecture 475 Layout Example CMOS Inverter 0 Add Substrate and Well Contacts 15653060 Lecture 476 Layout Example CMOS Inverter 0 Add External Wiring and Resize 15653060 Lecture 477 Symbolic Layout Stick diagrams capture spatial relationships but abstract away design rules Vdd Out Gnd What gate is this Note sticks are done slightly differently in text E CE 3060 Lecture 4 8 Design Capture Tools HDL amp Schematic capture 0 Hardware Description Languages such as VHDL amp Verilog capture a textual hierarchical description of design at abstraction ranging from gate or even transistor level up to a behavioral description more later 0 Schematic editors such as Cadence Composer capture a structural hierarchical graphical representation of the design netlist Layout 0 Layout editors such as Cadence Virtuoso capture a hierarchical view Gem of the physical geometric aspect of a cenz Ce2 design The units of hierarchy are Instance1 nstance2 called cells and have physical extent size In general good design requires that only one cell contain the design info for a particular area of the chip E CE 3060 Lecture 4 9 Rules Checking Complex designs invariably suffer design and design entry errors There are a number of tools and method ologies to detect and correct 0 Physical Design Rules Checking DRC checks for design rule violations such as minimum spacing etc DRC checking is complicated by hierarchy and overlap between cells 0 Electrical Rule Checking checks for violations such as shorts between Vdd and GND opens and so on 0 Layout vs Schematic LVS checks for a one to one correspondence between transistor schematic and the layout Formal verification is used to show that the design satisfies a formal description of what it should do Simulation is used to show that the design is func tional on some well selected set of input vectors Timing analysis is used to predict design performance E CE 3060 Lecture 4 10 Verification Two types Simulation based verification test vectors Formal verification mathematical properties boolean logic Trend include formal verification in the design invariants E CE 3060 Lecture 4 1 I Circuit Extraction Circuit extraction extracts a schematic representation of a layout including transistors wires and possibly wire and device resistance and capacitance a Circuit extraction is used for LVS and for spice simu lation of layouts E CE 3060 Lecture 4 12 Cell datapath Generators Custom layout of a chip is very time consuming and is justifiable only in very high volume design with critical requirements or in research A datapath generator is a program designed to para metrically create a data path cell say an ALU cell which can meet size pitch and timing constraints E CE 3060 Lecture 4 13 Standard Cell Approach Use full custom process but design to higher level abstraction SSI NAND NOR lNV XOR Register 0 MSI Decoder Adder Comparator Datapath ALU Shifter Register file 0 Memory RAM ROM CAM Cells are designed at multiples of std pitch Cells may be parameterized for power speed Design target is netlist of cells which are then placed and routed using automated tools E CE 3060 Lecture 4 14 Standard Cell Design 0 Cells are designed to abut horizontally 0 Cells are placed and routed automatically 0 Wiring channels may have variable of tracks 15653060 Lecture 4715