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# Analog Electronics ECE 3050

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This 0 page Class Notes was uploaded by Cassidy Effertz on Monday November 2, 2015. The Class Notes belongs to ECE 3050 at Georgia Institute of Technology - Main Campus taught by William Leach in Fall. Since its upload, it has received 12 views. For similar materials see /class/233860/ece-3050-georgia-institute-of-technology-main-campus in ELECTRICAL AND COMPUTER ENGINEERING at Georgia Institute of Technology - Main Campus.

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Date Created: 11/02/15

The Conunon Base Ampli er Basic Circuit Fig 1 shows the circuit diagram of a single stage commonebase ampli er The object is to solve for the smallesignal voltage gain7 input resistance7 and output resistance Figure 1 Commonebase ampli er DC Solution a Replace the capacitors with open circuits Look out of the 3 BJT terminals and make Th venin equivalent circuits as shown in Fig 2 VR2 V7 R1 R R R R1R2 BB 1H 2 VBB VEE V7 REE RE VCC V R00 RC 10 Make an educated guess for VBE Write the loop equation between the V33 and the VEE nodes To solve for 0 this equation is C I BBB VBE CREE 04 VBB VEE IBRBB VBE EREE c Solve the loop equation for the currents VBB VEE VBE 1 1 1 C 06E B BBB5REE06 d Verify that V03 gt 0 for the active mode VCB V0 VB V00 IcRcc V1313 BRBB VCC VBB C Rec BBB5 CC R CC I V BBB B C BB VBE E REE VEE Figure 2 DC bias circuit SmallSignal or AC Solutions a Redraw the circuit with VJr V 0 and all capacitors replaced with short circuits as shown in Fig 3 Figure 3 Signal circuit 10 Calculate gm7 rm re and m from the DC solution C VT VT VA VCE WV 5 E FT c Replace the circuits looking out of the base and emitter with Thevenin equivalent circuits as shown in Fig 4 RE 111 0 Ru 0 Uteusm Rte RSHRE Figure 4 Signal circuit with Thevenin emitter circuit Exact Solution a Replace the BJT in Fig 4 with the Thevenin emitter circuit and the Norton collector circuit as shown in Fig 5 Figure 5 Emitter and collector equivalent circuits b Solve for iCSC RE R5 RE 7 1 are r rm 8 1 5 Z39csc 7 me39Ute Gmeus Gme c Solve for 110 10 iicscricllRCll RL Gme39us TicllRCll RL RE R5 RE To Tl2llRte 1 7 O Rte 7 l Rte Tic 3 d Solve for the voltage gain 11 RE A 0 G 39 R R 1 Us RS merlcll Cll L e Solve for rm r R Tm R1llellMe We O ta r m th 1 19 f Solve for rum Tout Wall RC Example 1 For the CB ampli er in Fig 1 it is given that RS 100 9 R1 120 k9 R2 100 k9 RC 43M RE 56M R3 1009 EL 201lt ZV4r 15V V 7 715V VBE 065V 8 99 04 099 rm 209 VA 100V and VT 0025V Solve for A1 rm and ram Solution Because the dc bias circuit is the same as for the commoniemitter ampli er example the dc bias values re gm hr and m are the same In the signal circuit the Thevenin voltage and resistance seen looking out of the emitter are given by RE Ute my 09825115 Rte RSHRE 98259 The Thevenin resistances seen looking out of the base and the collector are Rt 0 Ric RollRL 3539 kg I Next we calculate re Gme MC and n5 B brm 1 ar0r 1 1203Q G 5 T5 15 We quot 5 Rt5rgllr0 r0rg 1114 70TlellRte Tic 4423k9 me LR C 12839 1 magma 1115 He Has1 19 The output voltage is given by R 10 Gme Wall Ric Ute Gme Wall Ric RSTE R us Thus the voltage gain is A 3097 The input and output resistances are rm RlllRZHru 1281 9 ram malch 425919 Approximate Solutions These solutions assume that To 00 except in calculating no In this case 2656 2C awe zb Figure 6 Simpli ed T model Circuit Simpli ed T Model Solution a After making the Thevenin equivalent Circuits looking out of the base and emitter7 replace the BJT With the simpli ed T model as shown in Fig 6 b Solve for and MC 2quot 04 0 Ute Z T B e j T Rte gt Z 711mm TV m Hum w 1 7 O Rte 7 l Rte 3 Solve for 110 MellRCllRL RE 04 7 v R R L v R R U0 Zcrlcll Cll L views Rterlcll Cll L USES 748 Rte d Solve for the voltage gain 11 R 04 A quot 5 v R R us R5RE rgRtenCll all L e Solve for me and rm u 39l l 39l 8 07u525r5gt257 7 5 7quot i e 7 7 75 7 7 2 5 5 l mu TellRE f Solve for rum Tout Well RC Example 2 For Example 1 use the simplified Timodel solutions to calculate the values of A rm and ram A 09825 X 8978 X 10 3 X 3511 X 103 3097 rm 129 ram 4259 kg 7T Model Solution a After making the Th venin equivalent Circuits looking out of the base and emitter7 replace the BJT with the 7T model as shown in Fig 7 Figure 7 Hybridi 39 model Circuit b Solve for and MC 39 I I Uie O Utezb7 mu7rze RteE7mE RtegtzcT 1 Rt m I 8 9m 04 TV m Hum w 1 7 aRte we Rte 3 Solve for 110 11 RE Z JicllRCHRL ml eRmTicHRCHRL Wm H 1 Rte CHRCHRL F g a m 0 gm 0 d Solve for the voltage gain 10 A R5RE7A R 1 E 1 RRWCHRCHRL gm 0 e Solve for rum Tout CH RC f Solve for me and rm 2quot 1 Oil52T gj l 7 7r1 7 m7 7rgt2 uer 6 7r 7 7 Us irm l39r rr 7722 15 Tm We HRE Example 3 For Example 1 use the 7T 77L0d6l solutions to calculate the values of A rm and ram A 09825 X 8978 X 10 3 X 3539 X 103 3097 rm 129 ram 4259 kg T Model Solution a After making the Th venin equivalent Circuits looking out of the base and emitter7 replace the BJT with the T model as shown in Fig77 Figure 8 T model Circuit 10 Solve for and MC 2quot 2quot 711 0795 Zbrml ereRte Ecmtrerthe 22 W 04 TV 70T llRte w l 7 Othe We Rte 3 Solve for 110 4 8 A U0 7 ZCTMHRCHRL 7 Ti 7 5 Rte TZCHRCHRL 7 USES RE Ti 7 5 Rte TZCHRCHRL 04 oz CommonBase Amplifier Example X Rpltxygt y xy Function for calculating parallel resistors R11100000 R22120000 RC4300 RE5600 RSI100 RL10000 Vplus 215 Vminus 15 VBE 065 VT 0025 3 2 99 01099 rX 220 r0150000 v 5 1 With v S 1 the voltage gain is equal to v O DC Bias Circuit V R1 R2 V V R V R VBB plus 2 mlnus 1 VBB1I364 R1R2 4 RBB RPltR1R2 RBB 5455010 V V V BB BE mlnus 7 393 IE IE 7 255710 BB RE 13 V rel T re 9777 IE Test for Active Mode VCvplusaIERC vC4115 VB ZijnusIEREVBE VB o031 VCB VC VB VCB 4146 Thus active mode AC Signal Circuit RE V te zv s39 V te 0982 RSRE Rte RPR ER 5 Rte 98246 Rtb20 R r tb X Y equot e re9977 Circuit for v O to W O 15 fr C80 w R 39R R R R 73007103 tc39 P C L to 39 r0RPrYe Rtegt 5 alRte ric 49383910 1quotYe 39Rte v xr r icsc te 0 e icsc 89871o 3 RteRPltr e ro 1F0quot39re v O i CSCRPltR toxic v O 26862 This is the voltage gain CIrCUIt for I out routlRPltROricgt rout 4263103 r r rie10569 rin1RPltrieREgt rm 10549 The following solution is based on the r0 approximations where r0 is neglected in calculating icsc but not neglected in calculating ric X G me r e R te I 3 1 CSC v teGme 1 CSC 89873910 v c i cscRPltR toxic v c 26861 This is the voltage gain v C 26862 3 Percent 100 Percent 302810 This is the percent change from 26862 the exact value R R 74263103 r out 39 Pltr1c C r out T 39 rin1RPltrieREgt rm 10549 Approximate solution 1 using the equation icg mltv b v e and neglecting rX and r0 xI ng E gm0101 VT rie Ire rie 9777 39 RE rie g R R R v 39 39 39 m39 P C L RSRE rieRte AV 27075 riniRPltREriegt rm 976 r out 1R C rout 43103 Copyright 2008 W Marshall Leach7 Jr7 Professor7 Georgia Institute of Technology7 School of Electrical and Computer Engineering The BJ T Differential Ampli er Basic Circuit Figure 1 shows the circuit diagram of a differential ampli er The tail supply is modeled as a current source IQ The object is to solve for the smallisignal output voltages and output resistances It will be assumed that the transistors are identical Figure 1 Circuit diagram of the differential ampli er DC Solution Zero both base inputs For identical transistors7 the current IQ divides equally between the two emitters a The dc currents are given by Q OdIQ IE1IE2 01102T b Verify that V03 gt 0 for the active mode IE 1H9 IE 1H9 RB VCB V0 7 VB VJr 7 aIERC RB VT HERO e Calculate the collectoriemitter voltage VCE VC VE V0 VB VBE VCB VBE SmallSignal AC Solution using the Simpli ed T Model This solution uses the To approximations a Calculate gm7 rm re and Tie 041E 1 5 VT VT RB 790 VA VCE gm hr re re re r0 VT IE IE 1H9 10 Redraw the circuit with VJr V 0 Replace the two BJTs with the simpli ed T model The emitter part of the circuit obtained is shown in Fig 2 why Figure 2 Emitter equivalent circuit using the To approximations c Using Ohm s Law7 solve for 221 and igg 2 7 W1 112 2 7 72 51 2T18 52 51 d The circuit for 1101 1102 rau and Tautg is shown in Fig 3 Figure 3 Circuits for calculating 1101 1102 rau and Tautg 704 R 1101 221MCHRC lm517mlch Hi jg W1 M2 5 704 R 1102 Z griclch Otl lncHRc MHZ 5250112 1M1 5 Tautl ToutZ TicH RC To T Rte RM 7J5 Rte e The resistance seen looking into the 11 m2 input with 1112 0 11 0 is RB Tmrw1 Bte R R3rm1 2REBT Q mm 1 2RB rmm 1 RE 2 R3 Tl where r 1 Q has been used and r rrmr7r13RE B RB 112 Figure 4 Base equivalent circuit for calculating ibl and ibg The differential input resistance rid is the resistance seen between the two inputs when u viii2 and 1112 fwd2 where um is the differential input voltage It can be seen from the gure that it is given by rid 2 R3 The Di 39 Amp with an Active Load Figure 5 shows a BJT diff amp with an active load formed by a current mirror with base current compensation The object is to solve for the openicircuit output voltage 110C the shorticircuit output current isc and the output resistance ram By Thevenin s theorem these are related by the equation 110C iscraut It will be assumed that the current mirror consisting of transistors Q3 7 Q5 is perfect so that its output current is equal to its input current ie ic4 id In addition the To approximations will be used in solving for the currents That is the Early effect will be neglected except in solving for rum For the bias solution it will be assumed that the tail current IQ splits equally between Q1 and Q2 so that IE1 IE2 IQQ Because the tail supply is assumed to be a current source the commonimode gain ofthe circuit is zero when the To approximations are used In this case it can be assumed that the two input signals are pure differential signals that can be written 11 viii2 and 1112 fwd2 For differential input signals it follows by symmetry that the signal voltage is zero at the node above the tail current supply IQ Following the analysis above the smallisignal collector currents in Q1 and Q2 are given by 2 0 2 7 0 C1 rgRE2 C2 rgRE2 where 74 w 748 1 The shorticircuit output current is given by 7 256 7 264 7 262 Figure 5 Diff amp With active currentimirror load With 23924 23923 23921 and 23922 7211 this becomes a a Zsc 22 1 39Uid m1 7 M2 C r RE r RE The output resistance is given by Tout To4llnc2 Where nag is given by I To Te llRte2 R 352 2RE n51 2RE re 0 teZ r RteZ 741122 By Thevenin s theorem7 the smallisignal openicircuit output voltage is given by 06 X To4llnc2v1 7 U r RE l l 106 Zscraut Example 1 For IQ QmA RB 1009 RE 51 Q VJr 15V V 715V VT 0025V Tm 509 3 99 Oz VBE1 VBEZ VE33 VEB4 VEB5 V02 V04 137V and VA 50 V calculate isc ram and 110C Solution 2V R T B 7 r51 r52 3 259 r el r eg 1 m we 2659 R7552 n51 7 13 isc 06 mltui1 7 1112 U 7 1112 I r02 W 65 k9 m2 W 3627M O IQQ amp r Rm 7 7 04 M Tout 7 04H7 l C2 IQ vac Z39scraut W1 7 112 This is a dB gain of 553 dB Di 39 Amp with NonPerfect Tail Supply Fig 6 shows the circuit diagram of a differential ampli er The tail supply is modeled as a current source I Q having a parallel resistance RQ In the case of an ideal current source7 RQ is an open circuit Often a diff amp is designed with a resistive tail supply In this case7 I Q 0 The solutions below are valid for each of these connections The object is to solve for the smallisignal output voltages and output resistances Figure 6 BJT Differential ampli er DC Solutions This solution assumes that is known If IQ is known7 the solutions are the same as above a Zero both inputs Divide the tail supply into two equal parallel current sources having a current I Q 2 in parallel with a resistor QRQ The circuit obtained for Q1 is shown on the left in Fig 7 The circuit for Q2 is identical Now make a Thevenin equivalent as shown in on the right in Fig 7 This is the basic bias circuit Figure 7 DC bias circuits for Q1 b Make an educated guess for VBE Write the loop equation between the ground node to the left of RB and V To solve for IE7 this equation is IE 1H9 c Solve the loop equation for the currents 0 7 V7 7 I RQ RB VBE IE RE QRQ IE IC 18IB 06 7V7 I 2RQ 7 VBE 7 RB17l7 RE2RQ d Verify that V03 gt 0 for the active mode IE 1H9 IE 1H9 VCB V0 7 VB V7 7 OtIERc 7 7 RB V7 7 OtIERC RB e Calculate the collectoriemitter voltage VCE V0 7 VE V0 7 VB 7 VBE V013 VBE f If R 007 it follows that IE1 IE2 I 2 If I 07 the currents are given by Q Q C 7V7 7 VBE I 1 I E 1 H3 3 RB1 RE2RQ SmallSignal or AC Solutions Simpli ed T Model This solution uses the To approximations a Calculate gm7 rm re and Tie 7 VA VCE aIE 15VT j FRBWH r 9quot VT quot IE IE 8 15 5 0 ME V 0 and 1amp2 0 Replace the two BJTs with the b Redraw the circuit with VJr simpli ed T model The emitter part of the circuit obtained is shown in 8 Figure 8 Emitter equivalent circuit for the simpli ed T model c Using superposition Ohm s Law7 and current division7 solve for 221 and 222 R W1 W2 2 7 51 T RERQlW REgt TERERQHWREgtRQT RE 2 m2 7 m1 RQ 52 r eJrRERQllT eJrRE T2RERQllT RERQTl2RE For RQ 007 these become 1M1 1M2 1M2 1111 I 7 39l M WHRE 2ltrgREgt d The circuit for 1101 1102 rang and Tautg is shown in Fig 9 Figure 9 Circuits for calculating 1101 1102 rau and Tautg 7 39 RC R 7 r V R 7 r V R O rzcll V 7 Q U01 chrlcll C Odelrlcll C 713 RE we U11 1 RQ 713 RE farmlch UV 7 UV RQ 12 11 RQ 713 RE 7quot vR7quot vR U02 Zagrlcll C Odelncll C 7 Tautl ToutZ Wall RC r rquot R Bate RE RQH r w 5 7 l Rte e The resistance seen looking into the 2121 m2 input with 2112 0 2121 0 is Mb 33 Tmr7r13B e f Special case for RQ 00 farmlch 2 We farmlch 1101 U21 7 U22 U02 W 1122 1 21 g The equivalent circuit seen looking into the two inputs is similar to that in Fig 4 with the exception that a resistor representing the effect of RQ must be added It is shown in Fig 10 The resistors labeled T have the same value as the ones in Fig 4 They are given by 2rmr7r1 RE B RB quot732 Figure 10 Equivalent circuits for calculating 211 and 212 The differential input resistance rid is de ned the same way that it is de ned for Fig 4 That is7 it is the resistance seen between the two inputs when u viii2 and 2112 fwd2 where uid is the differential input voltage In this case7 the smallisignal voltage at the upper node of the resistor 1 RQ is zero so that no current ows it It follows that rid is given by rid 2 R3 Hybrid7T Model This solution assumes that To 00 Replace the two transistors with the hybridi 39 model as shown in Fig 11 a Write the loop equations for the two input loops Use the relations U7r1 2quot gm and cl U22 i czgm 2 2 1 2 1 2 1 2 2 U21L1RBMLLRE LLRQ 9272 0 0 0 2 2 2 2 2 v22RBrmL2L2RE 22RQ gm 02 02 02 These equations are in the form Tout 7quotout gt C j j CJ U01 39 39 U02 7701 i z 1 RB Tm Tn Trr Ta RB U2 1 79015 lv7r1 Un2 1 025 l 71Oltgt et z a RE ltgt lt RE Figure 11 Hybridi 39 model To W2 Bilcl t AJFBME Where 1 R R E BQ gm a a RBM A 5 b Use determinants to solve the two equations simultaneously for id and 23922 ABU 1BU 2 ABU 1BU 2 2C1 AB27B2 7 AAQB 2 AB UigiB L 1 AB UigiB L 1 62 AB2 732 AA2B Thus the solutions are gm 0 RBTm 1 E 7 iii w a R R Q Uzi QU 2 06 06 9m 0 9m 04 R 1 R R R EQWQm 3917 gm 06 Oz 04 2 i i 9m 0 9m 0 0 After some algelora7 the solutions reduce to those obtained With the simpli ed T model The output voltages are given by 39l 39l 1101 7ch U02 ZCZRC For the case of a nite To the To approximation replaces BC with ricllRC Differential and CommonMode Gains This solution uses the To approximations a De ne the commonimode and differential input voltages as follows 7 7 m1 1112 111d 7 W1 1M2 Uicm 7 T With these de nitions7 u and 1112 can be written 111d 111d m1 39Uicm 3 1M2 39Uicm 3 By linearity7 it follows that superposition of mm and um can be used to solve for the currents and voltages b Redraw the emitter equivalent circuit as shown in Fig 12 Figure 12 Emitter equivalent circuit for calculating the commonimode and differential emitter currents c For 11 viii2 and 1112 fwd2 it follows by superposition that 11a 0 and Uni2 film2 51 rgRE 52 rgRE s 01 MWHRC 7 5 RE 2 713 RE 2 1102 faileZT iCllRC larWlClchu lanCllRC W1 7 mg 7 5 RE 2 713 RE 2 The differential voltage gain is given by A 7 1101 7 1102 7 104mlch d 7 7 7 7 111d Um 2 We RE d For 11 m2 mam it follows by superposition that ia 0 and Him Uicm 7 251 r RE 2RQ 252 r RE QRQ v wi rvHR quotW ch 0 ch quot1 51 C rgRE2RQWm rgRE2RQ 2 10 Copywright 2008 W Marshall Leach Jr Professor Georgia Institute of Technology School of Electrical and Computer Engineering The J FET Device Equations The circuit symbols for the junction FET or JFET are shown in Fig 1 There are two types of devices the nichannel and the pichannel Each device has gate G drain D and source S terminals The drain and source connect through a semiconductor channel A diode junction separates the gate from the channel For proper operation as an amplifying device this junction must be reverse biased This requires 1105 lt 0 for the nichannel device and 1105 gt 0 for the D S 4 in i is G G Is 0 S D a b pichannel device Figure 1 JFET circuit symbols a N channel b P channel The discussion here applies to the nichannel JFET The equations apply to the pichannel device if the subscripts for the voltage between any two of the device terminals are reversed eg 1105 becomes 1150 The JFET must be biased with the gatesource junction reverse biased to prevent the ow of gate current ie 1105 lt 0 for the nichannel device and 1105 gt 0 for the pichannel device The gate current is then equal to the reverse saturation current of the junction This current is very small and is usually neglected in bias and smallisignal calculations However its effect is included in the noise model given here The JFET is biased in the active mode or the saturation region when 11135 2 1105 7 VTO where VTO is the threshold or pinchioff voltage which is negative In the saturation region the drain current is given by iD 50105 VTO2 for 1105 2 VP 0 for 1105 lt VTo 1 where 8 is the transconductance coef cient given by 5 50 1 MDS 2 In this equation 80 is the zeroibias value of ie the value with 11135 0 and A is the channel length modulation parameter which accounts for the change in 8 with drainisource voltage Because 2390 2 0 in the pinchioff region the source current is equal to the drain current ie is iD A second way of writing the JFET current is 2 239D IDSS 1 i for 1105 2 VP 0 for 1105 lt VP 3 where IDSS is the drainisource saturation current7 ie the value of ip with 1105 0 It is given by IDSS 5VT20 50 1 MDS VTZ O 4 Typical device parameters are g 2 X 10 4 A27 VTO 74 V7 and A 001 V71 Figure 2 shows the typical variation of the drain current ip with gateitoisource voltage 1105 for VTO S 1105 S 0 The slope of the curve is the smallisignal transconductance gm For 1105 lt VTO7 the drain current is zero For 1105 gt 07 gate current ows Fig 2 shows the typical variation of drain current ip with drainitoisource voltage ups for eight values of V05 in the range VTO lt V05 3 0 The dashed line separates the linear or triode region from the active or saturation region In the saturation region7 the slope of the curves is the reciprocal of the smallisignal drainisource resistance r0 IDSS Drain Cu rrem VTO Gofe l o Source Voltage 0 Figure 2 Plot of ID versus V03 for constant VDS Triode I Sc rura on O Decreasing l Vcs Drain Current Drohn lo Source Vol rage Figure 3 Plot of ID versus VDS for eight values of V05 Bias Equation Figure 4 shows the JFET with the external circuits represented by Thevenin dc circuits If the JFET is in the pinchioff region7 the following equations for ID hold 113 5 V05 VTO2 5 VGS VGG V55 IDRSS 6 50 1 AVDS 7 VDS VDD IDRDD V55 IDRSS 8 Because this is a set of nonlinear equations7 a closed form solution for ID cannot be easily written unless it is assumed that is not a function of VDS This assumption requires the condition AVDS ltlt 1 In this case7 the equations can be solved for ID to obtain 71f 9 1 ID 451 Figure 4 JFET dc bias circuit Unless AVDS ltlt 17 Eq 9 is only an approximate solution A numerical procedure for obtaining a more accurate solution is to rst calculate ID with e Then calculate VDS and the new value of from which a new value for D can be calculated The procedure can be repeated until the solution for ID converges Alternately7 computer tools can be used to obtain a numerical solution to the set of nonlinear equations SmallSignal Models There are two smallisignal circuit models which are commonly used to analyze JFET circuits These are the hybrid77T model and the T model The two models are equivalent and give identical results They are described below Hybrid7T Model Let the drain current and each voltage be written as the sum of a dc component and a smallisignal ac component as follows if D id V 1105 VGS 1195 11 39UDS VDS 1115 12 If the ac components are suf ciently small7 we can write 81D 81D Zd BVGS 195 l BV DS Uds where the derivatives are evaluated at the dc bias values Let us de ne 8 9m avg 23 V05 VTO 2 51D 7 81D 71 2 17VD51 J lavDsl VOW W l T The drain current can thus be written Ud 2d 21 5 7 0 where Zd 25 gmugs 16 17 The gate current is given by 2399 7 239 0 The smallisignal circuit which models these equations is given in Fig 5a This is called the hybrid77T model The resistor rd is the parasitic resistance in series with the drain contact It has a typical value of 50 to 100 Q Often it is neglected in calculations This is done in the following It is simple to account for rd in any equation by adding it to the external drain load resistance rd d rd 1d AAA AA v v 7 gt7 O O Figure 5 a JFET hybrid77T model b T model T Model The T model of the JFET is shown in Fig 5b The resistor To is given by Eq 15 The resistor TS is given by TS gm where gm is the transconductance de ned in Eq 14 The currents are given by Ud 4 5 2d 2d 7 0 7 1 7 195 7 2d 7 25 i gm39ugs 7 s 74 47 zgizsizdio 18 19 20 21 The currents are the same as for the hybrid77T model Therefore7 the two models are equivalent SmallSignal Equivalent Circuits Several equivalent circuits are derived below which facilitate writing smallisignal lowifrequency equations for the JFET We assume that the circuits external to the device can be represented by Th venin equivalent circuits The Norton eqivalent circuit seen looking into the drain and the Th venin equivalent circuit seen looking into the source are derived Several examples are given which illustrate use of the equivalent circuits Simpli ed T Model Figure 6a shows the JFET T model with a Th venin source in series with the gate We wish to solve for the equivalent circuit in which the source i i connects from the drain node to ground rather than from the drain node to the gate node We call this the simpli ed T model Aside for the subscripts7 the T model in Fig 5b is identical to the T model for the BJT with rm 0 Therefore7 the simpli ed T model for the JFET must be of the same form as the simpli ed T model for the BJT Because 2399 07 the effective current gains of the JFET are 04 1 and 00 The simpli ed T model is shown in Fig 6b7 where i i and Q are given by 212 22 1 r 23 5 gm lt gt Figure 6 a JFET T model with Th venin source connected to the gate b Simpli ed T model Norton Drain Circuit The Norton equivalent circuit seen looking into the drain can be used to solve for the response of the commonisource and commonigate stages Fig 7a shows the JFET with Th venin sources connected to its gate and source The Norton drain circuit follows directly from the BJT Norton collector circuit with appropriate changes in subscripts and the substitutions 04 17 and 007 and rm 0 The circuit is given in Fig 7b7 where idsc and rid are given by idsc Gmgutg 7 Gmsuts 24 To TsHRts Bis r39 r 1 R 25 quot1 liRtsr Rts 0 r 5 The two transconductances Gmg and Gms are given by 1 m G 26 my rsRterorost 5 1 7 Rm Tsllro 1d loLsc rid b Figure 7 a JFET with Thevenin sources connected to the gate and the source b Norton drain circuit For the case To gtgt Bis and To gt m we can write idsc Gm 119 7 115 28 where 1 Gm 29 r Rt l The value of idsc calculated with this approximation is simply the value of calculated with To considered to be an open circuit The term r0 approximations is used in the following when m is neglected in calculating idsc but not neglected in calculating rid Th venin Source Circuit The Thevenin equivalent circuit seen looking into the source is useful in calculating the response of commonidrain stages Fig 8a shows the JFET symbol with a Thevenin source connected to the gate The resistor BM represents the external load resistance in series with the drain The Thevenin source seen looking into the source follows directly from the Thevenin emitter circuit for the BJT with appropriate subscript changes and the substitutions Oz 17 007 and no 0 The circuit is shown in Fig 8b7 where 115OC and n5 are given by To W 30 Ts To Bid 31 5 rs To When BM 07 note that MS rsllm Summary of Models Figure 9 summarizes the four equivalent circuits derived above Figure 8 a JFET With Thevenin source connected to the gate b Thevenin equivalent circuit seen looking into the source lt soc rig ts is S Figure 9 Summary of the smallisignal equivalent circuits Example Ampli er Circuits The CommonSource Ampli er Figure 10a shows the ac signal circuit of a JFET commonisource ampli er We assume that the bias solution and the smallisignal resistances rs and m are known The output voltage and output resistance can be calculated by replacing the circuit seen looking into the drain by the Norton equivalent circuit given in Fig 10b These are given by 110 iid sc WdH R td Gmg TidH thutg 32 Tout Taillde 33 where Gmg and rid respectively7 are given by Eqs 26 and 25 Because the gate current is zero7 the input resistance is in nite Figure 10 a Commonisource ampli er b Commonidrain ampli er c Commonigate ampli er The CommonDrain Ampli er Figure 10b shows the ac signal circuit of a JFET commonidrain ampli er We assume that the bias solution and the smallisignal resistances rs and m are known The output voltage and output resistance can be calculated by replacing the circuit seen looking into the source by the Th venin equivalent circuit given in Fig 8b These are given by UH W i TD in 34 5 quotC ms R25 rs To Us Bis g Tout TiSHRtS where 115UC and n5 respectively7 are given by Eqs 30 and 31 Because the gate current is zero7 the input resistance is in nite The CommonGate Ampli er Figure 10c shows the ac signal circuit of a JFET commonigate ampli er We assume that the bias solution and the smallisignal parameters rs and m are known The output voltage and output resistance can be calculated by replacing the circuit seen looking into the drain by the Norton equivalent circuit given in Fig 7b The input resistance can be calculated by replacing the circuit Copyright 2008 W Marshall Leach Jr Professor Georgia Institute of Technology School of Electrical and Computer Engineering Current Mirrors Basic BJT Current Mirror Current mirrors are basic building blocks of analog design Fig 1 shows the basic npn current mirror For its analysis we assume identical transistors and neglect the Early effect ie we assume VA gt 00 This makes the saturation current 5 and current gain 8 independent of the collector base voltage VCE The input current to the mirror is labeled IREF This current might come from a resistor connected to the positive rail or a current source realized with a transistor or another current mirror The emitters of the two transistors are shown connected to ground These can be connected to a dc voltage eg the negative supply rail 2 l 0 REF 5 0 0 Front Q1 Q m 2 6 6 V Figure 1 Basic current mirror The simplest way to solve for the output current is to sum the currents at the node where REF enters the mirror Because the two transistors have their baseemitter junctions in parallel it follows that both must have the same currents Thus we can write the equation 21 REF 10 70 Solution for 10 yields 0 REF 1 25 Note that this equation predicts that O lt REF unless gt 00 Because the Early effect has been neglected in solving for 0 the output resistance is in nite If we include the Early effect and assume that it has negligible effect in the solution for 0 the output resistance is given by 7 7 VA VCE2 10 For a more accurate analysis we can include the Early effect in calculating the output current Consider the circuit if Fig 2 If the transistors have the same parameters we can write Q 131 50 V0132 VBE 10 I I 1 I 0 50 T VA exp VT B2 501 VCBzVA V 101 150 exp By taking the ratio of O to 01 we obtain V 10 1 532 101 A Note that the voltage V03 is used for the Early effect not the voltage VCE This agrees with the EbersiMoll model for the BJT that is used in SPICE ln deriving the smallisignal 7T and T models the derivations are simpli ed by the use of VCE Thus VCE is used in most contemporary texts for the Early effect The correct value is V03 which is used here I I REF 0 C1 Fraut Q1 Q 2 B1 B2 V Figure 2 Circuit for including the Early effect Summing currents at the node where REF enters the circuit yields 101 Io 21 I I I REF Cl 50 50 1 VCBzVA Cl 50 Thus 01 is given by REF I 01 1250 It follows that O is given by V0132 1 VCBZVA IO 7 1 TA101 WIREF Note that this equation predicts that O can be larger that IREF The output resistance is given above Note that the effect of a nite 8 is to reduce 10 but the effect of the Early effect is to increase it Because of the Early effect the output current can be greater than the input current One way of obtaining a better match between the input and output currents is to use series emitter resistors on the transistors If the current in one transistor increases it causes the voltage across its emitter resistor to increase which causes a decrease in its baseiemitter voltage This causes the current to decrease thus causing the two transistors to have more equal currents A typical value for the emitter resistors might be 100 9 With these resistors R552 is no longer zero so that the output resistance is increased It is given by rout nag which can be much greater than r02 BJT Mirror with Base Current Compensation Figure 3 shows the basic current mirror with a third transistor added The collector of Q3 must be connected to a positive reference voltage eg the positive supply rail which biases it in the active mode If we neglect the Early effect and assume all transistors are identical we can write 210 51 5 REF 10 Solution for 10 yields 7 REF 7 12l515l Io Figure 3 Mirror with base current compensation For a noniin nite Early voltage and V031 VBE3 ltlt VA it can be shown that the output current is given by O REF 1 VCEZVA 1 2 l o 1 53H where 53 50 1 VCEP VA BJT Wilson Mirror A Wilson current mirror is shown in Fig 4 We neglect the Early effect in the analysis and assume the transistors to have identical parameters The emitter current in Q3 is O a This current is the input to a basic current mirror consisting of Q1 and Q2 This current is mirrored into the collector of Q1 by dividing by 1 At the node where REF enters the mirror we can write 10 04 IO 1 10 7 5 IREFil2 7 02 Solution for 10 yields 0 REF 1 5 lt2 5 15 The advantage of the Wilson mirror over the current mirrors examined above is that it has a much higher output resistance This is caused by two positive feedback effects To see how this occurs suppose a test current source is connected between the mirror output and ground If the source delivers current to the output node the voltage increases This causes a current to ow through r03 causing the emitter voltage of Q3 and the base voltage of Q1 to increase The increase in voltage at the emitter of Q3 causes its collector voltage to increase because Q3 is a commonibase stage for an emitter input Because Q1 is a commoniemitter stage for a base input the increase I 7quot REF 0 0 1 out 5 0 3 00 0 120 04 Q1 Q2 V Figure 4 Wilson mirror in voltage at its base causes the collector voltage of Q1 and the base voltage of Q3 to decrease Because Q3 is a commoniemitter stage for a base input the decrease in voltage at its base causes its collector voltage to increase Thus there are two positive feedback effects which cause the collector voltage of Q3 to increase to a larger value Because ram is the ratio of the collector voltage of Q3 to the current in the test source it follows that the output resistance is increased BJT LowLevel Mirror The circuit shown in Fig 5 is a lowilevel current mirror It can be used when it is desired to have a much lower output current than input current For the analysis we neglect the Early effect assume identical transistors and assume that 3 gt 00 We can write V V 71 R REF Sexp 51 10 Sexp By taking ratios we obtain REF ex ORE O p VT This equation cannot be solved for 0 If REF and O are speci ed it can be solved for RE to obtain V I RE i T ln REF IO 10 As an example suppose REF 1mA VT 25 mV and O 50 44A It follows from this equation that RE 1498 9 The effect of this large a value of RE on ram is to make it greater than To To calculate ram we must know the smallisignal Thevenin resistance Rm looking out of the base of Q2 Note that Q1 is a bjt connected as a diode and exhibits a smallisignal resistance mull rml 1 81 VTIEll VTIE1 25 9 This is in parallel with the smallisignal resistance looking up into the REF source Thus an upper bound on Rm is 25 9 Let us assume r02 40 k9 r052 0 042 0995 and 82 199 It follows that n52 Ra 1 aVTIcg 4976 99 Thus ram is given by 40000 4976H1498 1595 kg 1 7 0995 X 1498 4976 1498 Tout 741122 This is larger than mg by a factor of almost 4 V Figure 5 Lowilevel mirror BJT Transconductance Op Amp An example application of the current mirror is the transconductance op amp The circuit is shown in Fig 6 The circuit consists of an input diff amp and four Wilson current mirrors For the analysis we assume 3 gt 00 and VA gt 00 for each bjt so that the output current from each mirror is equal to the input current We assume that ABC splits equally between the emitters of Q1 and Q2 Thus the total currents in Q1 and Q2 respectively are given by ABC 7 ic2 23901 ici icz 1 ABC 1 ABC 2 2 The latter expression for 23902 follows because id 23962 0 It follows from the mirrored currents that the output current is given by 2390 2261 If we neglect base currents and the Early effect id 23951 111 7 m2 2re where he QVTIABC Thus in is given by Z 1 ABC 0 QVT It can be seen that the transconductance gain is set by the current 1430 The gain can be varied by varying L430 Because ABC 2 0 the circuit operates as a twoiquadrant multiplier The circuit symbol for the transconductance op amp is shown in Fig 7 W1 7 112 An example application of the transconductance op amp is a circuit which generates an amplii tude modulated signal The circuit is shown in Fig 8 Let 11 and ABC be given by 11 V1sinwct ABC IQ 1msinwmt where wc is the carrier frequency mm is the modulating frequency and m is the modulation index which must satisfy 71 lt m lt 1 The current in is given by 20 1 ABC W32 QVT R1 R2 If we assume that CF is an open circuit at the operating frequencies the current in must flow through RF Because the second op amp forces the voltage at its inverting input to be zero the output voltage is given by L430 11132 IQRF V132 2VT R1R2 F m R1R2 110 iaRF sin coat 1 msin wmt 5 Figure 6 Transconductance op amp Figure 7 Transconductance opiamp symbol Voh ctge Figure 8 AM modulator Time Figure 9 AM modulated waveform CommonCollector Amplifier Example RPxy X39y F Xy unction for calculating parallel reelstors R11100000 R22120000 RC0 RE5600 RSI5000 RL10000 vplus 15 vminus 15 VBE 065 vT o025 3 99 a1099 rX 20 r0150000 v 5 1 With v S 1 the voltage gain is equal to v O V Vplus39R 2 Vminus39Rl VBB VBB 1364 R1R2 4 RBB RPltR1R2 RBB 5455010 393 IE IE25573910 VT re IE AC Solutions This solution uses the equations involving Rte even though Rto 0 It is based on the Thevenin emitter circuit which has v we in series with rie RPR1R2gt RSRPltR1R2gt vtblv S vtb0916 Rtb R PltR SRPltR1R2gtgt Rtb 458103 7 3 Rte RPR ERLgt Rte 7 35910 R r r39e r39e 55779 1l3 RtCIRC tho r01 3 7 V eoc quotV tb39 R V eoc 0915 r r to e 0 1 r0th rier e R rie 55717 r r to 0 e v v w V 0901 0 eoc R R R o 39 r1e Plt E L AV v 0 AV 0901 This is the voltage gain routlRPltrieREgt rout55168 1 39r0th 1quot0Rteth 5 rib39rx1 39reRte ri133359o1o rinRPltribRPltR1R2gt rm 46930104 The following solution is based on the simplified T model I prefer it when Rto 0 Note that this is an exact solution where r0 is considered to be an external resistor The answers are the same as the ones in the solution above tb rieRPltRE RPltrO RLgt AV v 0 AV 0901 This is the voltage gain v 0 0901 rout RPltrieRPltr0REgt rout 55107 ribrx1 39ltreRPltRE RPltr0 RLgtgtgt rib 3359105 riniRPltribRPltR1R2gt rm 4693104 Note that the CC amplifier has a voltage gain that is just less than unity a low output resistance and a high input resistance Notational Conventions DC Quantity 7 Upper case7letter7 upper7case subscript VBE7 ID Small7Signal Quantity 7 Lower case7letter7 lower7case subscript vbg id Total Quantity 7 Lower case7letter7 upper7case subscript UBE VBE vbg iD ID id Phasor Quantity 7 Upper case7letter7 lower7case subscript ng Id Independent Sources Figure 1a shows the diagram of an independent voltage source The voltage U is independent of the current 239 that ows through the source Fig 1b shows the diagram of an independent current source The current 239 is independent of the voltage 1 across the source 139 a b Figure 1 a Independent voltage source b Independent current source Dependent Sources VCVS Voltage Controlled Voltage Source Figure 2a shows the diagram of a voltage controlled voltage source The output voltage is given by a voltage gain AU multiplied by an input voltage 121 Such a source in SPICE is called an E source 39i 139 gt gt 111 Au39u1 v1 va1 v 1 Aii1 v gt gt b c a 0 Figure 2 a Voltage controlled voltage source b Voltage controlled current source c Current controlled voltage source d Current controlled current source VCCS Voltage Controlled Current Source Figure 2b shows the diagram of a voltage controlled current source The output current is given by a transconductance Gm multiplied by an input voltage 121 Such a source in SPICE is called a G source CCVS Current Controlled Voltage Source Figure 2c shows the diagram of a current controlled voltage source The output voltage is given by a transresistance Rm multiplied by an input current 2391 Such a source in SPICE is called an F source CCCS Current Controlled Current Source Figure 2d shows the diagram of a current controlled current source The output current is given by a current gain Ai multiplied by an input current 2391 Such a source in SPICE is called an H source Passive Elements Resistor Figure 3a shows the diagram of a resistor The voltage across it is given by v iR This relation is known as Ohm s law quot5 i ii 39U U T 0 b C Figure 3 a Resistor b Inductor c Capacitor Inductor Fig 3b shows an inductor The voltage across it is given by In the analysis of circuits having sinusoidal excitations phasor analysis is usually used In this case the voltage across the inductor is given by V LsI where V and I are phasors s jw and w is the radian frequency of the excitation In the phasor domain a multiplication by s is equivalent to a time derivative in the time domain This is because the time domain excitation is assumed to be of the form exp st Capacitor Fig 3c shows a capacitor The current through it is given by C 2 dt For phasor representation of the signals the current through the capacitor is given by ICsV Voltage Division and Current Division Voltage Division Figure 3a shows a twoeresistor voltage divider The voltages v1 and 112 are given by 123 R1 1 2 R R v 1 S 1 R1R2 1 SR1R2 2 15112 R2 1 1 15 711 Figure 4 a Voltage divider b Current divider Current Division Figure 3b shows a twoeresistor current divider The currents i1 and i2 are given by Z 2 iSR1llR2 2 R2 1 R1 R1 SR1R2 Z 3 iSR1llR2 2 R1 2 R2 2 SR1R2 Use of Superposition in Solving Circuits This section illustrates the use of superposition in solving circuits containing dependent sources The correct use of superposition requires the dependent sources to be treated as independent sources in writing equations When a source is zeroed its controlling variable is not zeroed Example 1 For the circuit in Fig 5a it is given that R1 20 k9 R2 le and A 50 Solve for the Th uenin and Norton equivalent circuits seen looking into the output terminals Rout to 7390 o 1 0 1 ac quotsc Rout b c Figure 5 a Circuit for Example 1 b Thevenin equivalent b Norton equivalent Solution The Thevenin voltage is the openecircuit output voltage 1200 The Norton current is the shortecircuit output current isc The output resistance is the ratio of the openecircuit output voltage to the shortecircuit output current First we solve for the openecircuit output voltage By superposition we can write Aii1R1llR2 R2 Next we use superposition to solve for i1 Us A R2 Z 7 2 1 R1 R2 2 1 R1 R2 This can be solved for i1 to obtain vs 1 vs 1 1 R1R21AV R2 1311AR2 ZR1R2 We substitute the solution for i1 into the expression for voc to obtain R2 Av R R v00 USR1R2 21H 2R11AiR2 R2 239 1 7 USR1R21RQ R11AiR21 7 2019 50gtlt20k9gtlt1k9 1k920k9 20k91501k9 US 50gtlt20 1 21 2051 0718113 The Thevenin equivalent circuit is shown in Fig 5b By superposition the shortecircuit output current is given by Us Zsc Aill R1 where i1 is given by 3903 R1 We substitute the expression for i1 into the expression for iSC to obtain 2391 Us 7 HAL 150 ZSC Rl US 7 73 R1 1kg 7255gtlt10 vs 1 AiR i US The output resistance is given by 1200 0718123 0718 R 2829 W 23930 255 X 107353 255 X 103 The Norton equivalent circuit is shown in Fig 5c Example 2 For the circuit in Fig 6a it is given that R1 3kQ R2 QkQ and Gm 01 S Solve for the input resistance to the circuit Figure 6 a Circuit for Example 2 b Equivalent input circuit Solution The input resistance is given by the ratio of the source voltage to the source current By superposition we can write 03 is R1 R2 va1R2 where 111 is given by 121 isRl Substitute the expression for 111 into the expression for US to obtain vs is R1 R2 GmisR1R2 is R1 R2 GleRz Thus the input resistance is given by Rm S R1 R2GmR1R23kQ2kQO1 gtlt 3k9gtlt 2k9605k9 s The equivalent circuit seen looking into the input is shown in Fig 6b Example 3 Solve for the open circuit output voltage and the short circuit output currth for the circuit in Fig 7a gmvl gmv1 Figure 7 Circuit for Example 3 Solution The circuit contains a oating current source To make superposition simpler to apply this source can be broken into two series sources as shown in Fig 7b The node between the sources is shown connected to ground Although no current ows from this node to ground when both sources are active a current does ow when either is zeroed However by superposition the sum of these currents must be zero Because the currents ow into the ground node the voltages or current in the circuit are not affected By superposition the open circuit output voltage is given by 39 m R R R R U00 7 239mv1m 3 va1 1 2 3 R1R3 R2133 ZsRl R2 R3 gmlel R2 R3 The Voltage 121 is given by I 39Ul ZS 9mm El 152 RS 97nle R R El 7 R R R R1132 7 ZS 2 3gmv1R1R2R3 Solution for v1 yields 7 R1HR2R3 U1 7 Zs R 1 1 2 Wmampm When this is used in the equation for 1200 we obtain R3 Rlll R2 R3 R 7 R voc ZSR1R2R3 1 9m 2179 R1132 m R1 R2 R3 By superposition the short circuit output current is given by isc is gmvl L gmvl EL 7 9mini R1R2 R1R2 R1R2 The voltage 111 is given by 111 is gmv1R1HR2 This can be solved for v1 to obtain v i R1HR2 1 31 9mR1HR2 When this is used in the equation for isc we obtain 1 RlllR2 R 7 R Zsc ZsR1R2 1 9m 2ligmR1HR2 Example 4 For the circuit of Fig 8a it is given that is 51nA R1 4kQ R2 QkQ R3 319 and A 3 Solve for the Norton equivalent circuit seen looking into the output terminals and the voltage at the output if a load resistor of value RL GkQ is connected from the output to ground 112 R2 vac i R R A i i R s 1 3 522 Y SC 0 110 L al a b Figure 8 Circuit for Example 4 Solution By superposition the open7circuit output voltage is given by 39 R1 R A39R RHR v Z 7 392 oc SR1 R2 R3 3 z 2 1 2 3 The current i2 is given by R1 R3 i A39Z 2 SR1R2R3 22R1R2R3 Solution yields R1 1 R1 2 i i 2 R1R2R3 17 AiR3 R1R217AR3 R1R2R3 When this equation is used in the equation for voc we obtain R1R3 R1 7 Av R R R v00 ZS R1R2R3 212 1 M 3R1R217AiR3 For the element values given it follows that voc 700 This means that the output resistance of the circuit is 00 ie the circuit looks like a current source to any load By superposition the short7circuit output current is given by R1 A i i 7 392 so SR1 R2 2 2 The current i2 is given by R1 Z Z 2 SR1 R2 When this is used in the equation for iSC we obtain R1 A R1 1 14239 R1 4 i i 7 v i 7 i SC S R1R2 ZR1R2 S R1R2 3 Fig 8b shows the circuit with RL connected to its output The output voltage is given by 1207 gtlt 5mAX6kQ740V Ampli er Representations Figure 9 shows the diagram of an ampli er The source is represented by a Thevenin equivalent circuit In general7 the input resistance Rm is a function of the load resistance RL and the output resistance Rom is a function of the source resistance RS Figure 9 Ampli er model The output circuit of the ampli er can be represented by either a Thevenin equivalent circuit or a Norton equivalent circuit using one of the four dependent sources described above The four equivalent circuits are summarized below VCVS Model Figure 10a shows the ampli er model with the output represented by a voltageecontrolled voltage source The output voltage is given by RL A Rm RL Rout RL U Rs Rm Rout RL U0 Av U1 BS is Rautmo R5 is 3950 39 0 0 s Rm 1 4va EL 1 3 Rm 1 cm Rout RL 0 b Figure 10 a Voltage controlled voltage source ampli er b Voltage controlled current source ampli er VCCS Model Figure 10b shows the ampli er model with the output represented by a voltageecontrolled current source The output voltage is given by R 110 va1RomHRL Gm Wm RoutHRL CCVS Model Figure 11a shows the ampli er model with the output represented by a currentecontrolled voltage source The output voltage is given by RL v0 Rmz39sL Rm 7 Rout RL Rs Rm Rout RL BJT Differential Amplifier Example X Rpltxygt y Xy RC 20000 Vp 20 rX 20 Function for calculating parallel resistors RB 1000 RE 1oo 1Q o001 3 vm 2o VBE 065 vT o025 3499 x 13 r0 soooo There are two ac solutions one for the second input zeroed and one for the first input zeroed By superposition the total solution would the be sum ofthese two To keep Mathcad happy all source voltages are taken to be equal to 1 V so that the output voltage is equal to the voltage gain In general the output voltage is equal to the voltage gain multiplied by the source voltage DC Bias Solution Assume the do value of the sources is zero I Q 394 IE1quot IE1 53910 IE2quot1E1 VCIIVp aIE1RC VCI1005 I E1 7 3 VB1 RB VBI 7 2510 1H VCBl VCl VBl VCBl 100525 Thus active mode Same for Q2 V T 1quote1391 1quote150 1quote239re1 E1 R r i B X i i i r 61 rel r 61 7 551 r e2 r el 13 AC Solutions Circuit for the first output With the input equal to 1 the voltage gain is equal to the v 1 21 v 2 1 1 output voltage RC r0 1H 7 09989 V e200 39V 12 R Ve20c 39 C r 2ro e 1l3 r R 0 C rieZ 769015 1quotie2 1quot e239 r39 r RC 2 0 e thl V11 Rtbl RB Vtel V e200 Rtel 239RErie2 Rtel 2769015 101 R tel a r 0 T 3 G 39 G 2994110 mbl i i mbl r el Rtel r0RPr el Rtelgt r el r0 X x 3 G 39 G 2997510 mel i i mel r el Rtel r0RPr el Rtelgt r R r R rid rid 294161 IR tel r el R tel Voltage gain from first input to first output 7 3 1 also Gmb1vtb1 1 else 7 2994110 Vol 39iclsc39RPltricl RCgt Avl Vol Avl 560705 This is the voltage gain from the first input to the first output The gain from the second input to the second output is the same Voltage gain from the second input to the first output 3 iclsc 39Gme139V tel iclsc 23999423910 Vol 39iclsc39RPricl RCgt Av2vol Av2 560725 This is the voltage gain from the second input to the first output The gain from the first input to the second output is the same v 01 560705vi1 560725v i2 This is the sum ac output from Q1 v 02 560705vi2 560725v n This is the sum ac output from Q2 Differential input resistance 7110 2 RB szf 7quotin RB Tia Wm 2 39Rtel39Rc rim rx1i339ltrelRPRte1aroRcgtgt Rte1r0RC 4 ribl 4953910 ribz rib1 7 5 rid 2RBrib1rib2 rid71013910 CommonMode Rejection Ratio Avl 7 560705 AV2 560725 Let us take the output from the collector ofthe first transistor Because neither 3 nor r0 is infinity the two voltage gains are not equal This causes the CMRR to be non infinite We calculate it below V vidi1 1d 39Vid Vil quotT Vi2 39 Vol Av139vi1Av239Vi2 Advol A d 560715 This is the differential voltage gain vicm 1 1 Vil Vicm Vi2vicm V01 Av139vi1Av239Vi2 A V cm 01 Acm 199380163 This is the common mode voltage gain A CMRR d CMRR 2812339104 A cm CMRRdB 20logCMRR CMRR dB 889811 If R Q the ac resistance of the current source is not infinity the CMRR would be lower CommonCollector Amplifier Example RPxy X39y F Xy unction for calculating parallel reelstors R11100000 R22120000 RC0 RE5600 RSI5000 RL10000 vplus 15 vminus 15 VBE 065 vT o025 3 99 a1099 rX 20 r0150000 v 5 1 With v S 1 the voltage gain is equal to v O V Vplus39R 2 Vminus39Rl VBB VBB 1364 R1R2 4 RBB RPltR1R2 RBB 5455010 393 IE IE25573910 VT re IE AC Solutions This solution uses the equations involving Rte even though Rto 0 It is based on the Thevenin emitter circuit which has v we in series with rie RPR1R2gt RSRPltR1R2gt vtblv S vtb0916 Rtb R PltR SRPltR1R2gtgt Rtb 458103 7 3 Rte RPR ERLgt Rte 7 35910 R r r39e r39e 55779 1l3 RtCIRC tho r01 3 7 V eoc quotV tb39 R V eoc 0915 r r to e 0 1 r0th rier e R rie 55717 r r to 0 e v v w V 0901 0 eoc R R R o 39 r1e Plt E L AV v 0 AV 0901 This is the voltage gain routlRPltrieREgt rout55168 1 39r0th 1quot0Rteth 5 rib39rx1 39reRte ri133359o1o rinRPltribRPltR1R2gt rm 46930104 The following solution is based on the simplified T model I prefer it when Rto 0 Note that this is an exact solution where r0 is considered to be an external resistor The answers are the same as the ones in the solution above tb rieRPltRE RPltrO RLgt AV v 0 AV 0901 This is the voltage gain v 0 0901 rout RPltrieRPltr0REgt rout 55107 ribrx1 39ltreRPltRE RPltr0 RLgtgtgt rib 3359105 riniRPltribRPltR1R2gt rm 4693104 Note that the CC amplifier has a voltage gain that is just less than unity a low output resistance and a high input resistance CommonBase Amplifier Example X Rpltxygt y xy Function for calculating parallel resistors R11100000 R22120000 RC4300 RE5600 RSI100 RL10000 Vplus 215 Vminus 15 VBE 065 VT 0025 3 2 99 01099 rX 220 r0150000 v 5 1 With v S 1 the voltage gain is equal to v O DC Bias Circuit V R1 R2 V V R V R VBB plus 2 mlnus 1 VBB1I364 R1R2 4 RBB RPltR1R2 RBB 5455010 V V V BB BE mlnus 7 393 IE IE 7 255710 BB RE 13 V rel T re 9777 IE Test for Active Mode VCvplusaIERC vC4115 VB ZijnusIEREVBE VB o031 VCB VC VB VCB 4146 Thus active mode AC Signal Circuit RE V te zv s39 V te 0982 RSRE Rte RPR ER 5 Rte 98246 Rtb20 R r tb X Y equot e re9977 Circuit for v O to W O 15 fr C80 w R 39R R R R 73007103 tc39 P C L to 39 r0RPrYe Rtegt 5 alRte ric 49383910 1quotYe 39Rte v xr r icsc te 0 e icsc 89871o 3 RteRPltr e ro 1F0quot39re v O i CSCRPltR toxic v O 26862 This is the voltage gain CIrCUIt for I out routlRPltROricgt rout 4263103 r r rie10569 rin1RPltrieREgt rm 10549 The following solution is based on the r0 approximations where r0 is neglected in calculating icsc but not neglected in calculating ric X G me r e R te I 3 1 CSC v teGme 1 CSC 89873910 v c i cscRPltR toxic v c 26861 This is the voltage gain v C 26862 3 Percent 100 Percent 302810 This is the percent change from 26862 the exact value R R 74263103 r out 39 Pltr1c C r out T 39 rin1RPltrieREgt rm 10549 Approximate solution 1 using the equation icg mltv b v e and neglecting rX and r0 xI ng E gm0101 VT rie Ire rie 9777 39 RE rie g R R R v 39 39 39 m39 P C L RSRE rieRte AV 27075 riniRPltREriegt rm 976 r out 1R C rout 43103 Copyright 2009 W Marshall Leach Jr Professor Georgia Institute of Technology School of Electrical and Computer Engineering The MOSFET Device Equations Whereas the JFET has a diode junction between the gate and the channel the metaleoxide semiconductor FET or MOSFET differs primarily in that it has an oxide insulating layer separating the gate and the channel The circuit symbols are shown in Fig 1 Each device has gate G drain D and source terminals Four of the symbols show an additional terminal called the body B which is not normally used as an input or an output It connects to the drainesource channel through a diode junction ln discrete MOSFETs the body lead is connected internally to the source When this is the case it is omitted on the symbol as shown in four of the MOSFET symbols ln integratedecircuit MOSFETs the body usually connects to a dc power supply rail which reverse biases the bodyechannel junction In the latter case the soecalled body effect must be accounted for when analyzing the circuit Channel Depletion MOSFET Enhancement MOSFET D D D D N GP le G i zDB 647 344 2173 3 S 1 W S S S S S S J J Gl Gl 3 Gl G l B P If D11 11 11 D D Figure l MOSFET symbols The discussion here applies to the nechannel MOSFET The equations apply to the pechannel device if the subscripts for the voltage between any two of the device terminals are reversed eg vgs becomes vsg The nechannel MOSFET is biased in the active mode or saturation region for 12133 2 vgs 7 12TH where 12TH is the threshold voltage This voltage is negative for the depletionemode device and positive for the enhancementemode device It is a function of the bodyesource voltage and is given by UTHVTO YV UBS T 1 where VTO is the value of 12TH with 1233 0 y is the body threshold parameter ab is the surface potential and 1233 is the bodyesource voltage The drain current is given by k W 2 2D 3 f 1 VUDS UGS vTH 2 where W is the channel width L is the channel length A is the channelelength modulation parameter and k is given by e k 00 tax In this equation 0 is the average carrier mobility C is the gate oxide capacitance per unity area 60 is the permittivity of the oxide layer and in is its thickness It is convenient to de ne a transconductance coef cient K given by 1 mm 3 With this de nition the drain current can be written iD K ms 7 um 4 Note that K plays the same role in the MOSFET drain current equation as plays in the JFET drain current equation Figure 2 shows the typical variation of drain current with gateetoesource voltage for a constant draine toesource voltage and zero bodyetoesource voltage In this case the threshold voltage is a constant ie 12TH VTO For vgs S VTO the drain current is zero For vgs gt VTO the drain current increases approximately as the square of the gateetoesource voltage The slope of the curve represents the smallesignal transconductance gm which is de ned in the next section Fig 3 shows the typical variation of drain current with drainetoesource voltage for a several values of gateetoesource voltage vgs and zero bodyetoe source voltage 113 The dashed line divides the triode region from the saturation or active region In the saturation region the slope of the curves represents the reciprocal of the smallesignal drainesource resistance 7 0 which is de ned in the next section Current Drain O VTO Gate to Source Voltage Figure 2 Drain current iD versus gateetoesource voltage vgs for constant drainetqsource voltage Ups Trtode Saturation Current Increasing T CS Drain DraintoSource Voltage Figure 3 Drain current iD versus drainetoesource voltage UDS for constant gateetoesource voltage vGS Bias Equation Figure 4 shows the MOSFET with the external circuits represented by Thevenin dc circuits If the MOSFET is in the pincheo quot region the following equations for ID hold ID K VGS 7 VTH2 5 VGS VGG Vss 131333 6 K K0 1 AVDs 7 VDS VDD DRDD Vss DRSS 8 Because this is a set of nonlinear equations a closed form solution for ID cannot be easily written unless it is assumed that K is not a function of VDS and VTH is not a function of VBS The former assumption requires the condition AVDS ltlt 1 With these assumptions the equations can be solved for ID to obtain 1 2 ID 7 m M1 4KRSS VGG 7 V33 7 VTH 7 1 9 Vac f 11 VBH V E SS Figure 4 MOSFET dc bias circuit Unless AVDS ltlt 1 and the dependence of VTH on VBS is neglected Eq 9 is only an approximate solution A numerical procedure for obtaining a more accurate solution is to rst calculate ID wit and VTH VTO Then calculate VDS and the new values of K and VTH from which a new value for D can be calculated The procedure can be repeated until the solution for ID converges Alternately computer tools can be used to obtain a numerical solution to the set of nonlinear equations SmallSignal Models There are two smallesignal circuit models which are commonly used to analyze MOSFET circuits These are the hybrid7739r model and the T model The two models are equivalent and give identical results They are described below Hybrid7T Model Let the drain current and each voltage be written as the sum of a dc component and a smallesignal ac component as follows z39D D id 10 UGS VGS vgs 11 11133 VBS vbs 12 11133 VDS vds 13 If the ac components are sufficiently small we can write 81D 81D 81D 14 2d BVGS v93 BVBS vbs BVDS vds l where the derivatives are evaluated at the dc bias values Let us de ne 8 9m D K VGS VTH 2 KID 15 BVGS 31D YVKID 16 gmb BVBS W 7 VBS Xgm Y X 17 2W VBS 81D 1 W 2 1 VDS1 x V 7 V 18 T0 BVDS 2 L GS TH D l The smallesignal drain current can thus be written id idg idb 19 7 0 where idg gmvgs 20 idb gmbvbs 21 The smallesignal circuit which models these equations is given in Fig 5 This is called the hybrid7739r model Figure 5 HybrideTr model of the MOSFET T Model The T model of the MOSFET is shown in Fig 6 The resistor 7 0 is given by Eq 18 The resistors 7 s and 73b are given by 1 TS 22 gm 1 1 TS 5 lt23 gmb Xgm X where gm and gmb are the transconductances de ned in Eqs 15 and 16 The currents are given by v 2d 239 Zsb E 24 7 0 v 239 gmvgs 25 7 s v Zsb E gmbvbs 26 st The currents are the same as for the hybrid7739r model Therefore7 the two models are equivalent Note that the gate and body currents are zero because the two controlled sources supply the currents that ow through 73 and 73b Figure 6 T model of the MOSFET SmallSignal Equivalent Circuits Several equivalent circuits are derived below which facilitate writing smallesignal lowefrequency equations for the MOSFET We assume that the circuits external to the device can be represented by Thevenin equivalent circuits The Norton equivalent circuit seen looking into the drain and the Thevenin equivalent circuit seen looking into the source are derived Several examples are given which illustrate use of the equivalent circuits Simpli ed T Model Figure 7 shows the MOSFET T model with a Thevenin source in series with the gate and the body connected to signal ground We wish to solve for the equivalent circuit in which the sources 23939 and isb are replaced by a single source which connects from the drain node to ground having the value i d We call this the simpli ed T model The rst step is to look up into the branch labeled and form a Thevenin equivalent circuit With 07 we can use voltage division to write st TsX vtg v 27 rsrsb ths l TsX 1X Usoa vtg With vtg 07 the resistance T s seen looking up into the branch labeled is I Ts 1 7 28 TS HT 1x 1xgm Figure 7 T model with Thevenin source connected to the gate and the body connected to signal ground The simpli ed T model is shown in Fig8 Compared to the corresponding circuit for the BJT7 the MOSFET circuit replaces vtb with vtg l x and 7 with T 73 l x Because the gate current is zero7 set a l and 00 in converting any BJT formulas to corresponding MOSFET formulas The simpli ed T model is derived with the assumption that the body lead connects to signal ground In the case that the body lead connects to the source lead7 it follows from Fig 7 that isb 0 Connecting the body to the source is equivalent to setting X 0 in the MOSFET equations Figure 8 Simpli ed T model Norton Drain Circuit Figure 9a shows the MOSFET with Thevenin sources connected to its gate and source leads and the body lead connected to signal ground The Norton equivalent circuit seen looking into the drain can be obtained from the Norton equivalent circuit seen looking into the BJT collector by replacing Gmb with Gmg7 Gme with Gms7 and Tia with rid The factor 1 1 X must be incorporated into the equation for Gmg To convert the formulas7 replace Rtb with Rtg Rte with Rte Rm with Rm 7 with 7 set a 17 and set 00 The circuit is given in Fig 9b7 where idsa and rid are given by idsa Gmgvg 7 GmsvtS 29 rid 7 0 1 R 30 The transconductances Gmg and Gms are given by Gm 31 GM 32 The equations for the case where the body is connected to the source are obtained by setting X 0 For the case B 07 the equations for Gmg and Gms reduce to G 33 my 1 X T s gm G 7 i 1 1 34 ms TQHTO X 9m T0 For the case 7 0 gt R and 7 0 gtgt 7 we can write 1 1 G 35 my 1 X T s R and G 7 36 ms 7 T s Rts The value of idsa calculated with these approximations is simply the value of calculated with 7 0 considered to be an open circuit The term To approximations is used in the following when 7 0 is neglected in calculating idsa but not neglected in calculating rid 0 b Figure 9 a MOSFET With Thevenin sources connected to the gate and source b Norton drain circuit Th venin Source Circuit Figure 10a shows the MOSFET With a Thevenin source connected to its gate7 the body lead connected to signal ground7 and the external drain load represented by the resistor Rm The Thevenin equivalent circuit seen looking into the source can be obtained from the Thevenin equivalent circuit seen looking into the BJT emitter by replacing 12900 With 1230 Tie With us vtb With vtg 1 x Rtb With Rtg Rm With Rm 7 With 3 setting a 17 and setting 00 The circuit is given in Fig 10b7 Where 12300 and us are given by my 7 0 1 37 30 1X 7 0 7 7 0 R d Q t 38 USOC Tia lbs US b Figure 10 a MOSFET With Thevenin source connected to gate b Thevenin source circuit The 7 0 Approximations The 7 0 approximations approximate 7 0 as an open circuit in all equations except the one for rid In this case7 the equations for idsa Gmg Gms rid 1130 and us are 1 1 1 39 quot G 7 G G G 39 Zdsc 2d 7719th msvts mg 1X T Rts ms T Rts T0 T HRts or Rm V 1 R 40 quotd 1 7 Bisr 131 TO r 3 l U 12900 13X m T 41 The simpli ed T model the hybrid 7T model and the T model respectively are given Figs 11 7 13 If 7 0 00 then rid is an open circuit in each Because 7 0 no longer connects to the source there is only one source current and is Figure 13 T model With the 7 0 approximations Summary of Models Figure 14 summarizes the four equivalent circuits derived above For the case Where the body is connected to the source set X 0 in the equations Example Ampli er Circuits This section describes several examples Which illustrate the use of the smallesignal equivalent circuits derived above to Write by inspection the voltage gain the input resistance and the output resistance of several ampli er circuits Figure 14 Summary of the smallesignal equivalent circuits Set X 0 if the body is connected to the source CommonSource Ampli er Figure 15a shows a commonesource ampli er The active device is M1 lts load consists of a currentemirror active load consisting of M2 and M3 The current source IQ sets the drain current in M3 Which is mirrored into the drain of M2 Because the sourceetoedrain voltage of M2 is larger than that of M37 the Early effect causes the dc drain current in M2 to be slightly larger than IQ The input voltage can be written 111 VB 157 Where VB is a dc bias voltage Which sets the drain current in M1 It must be equal to the drain current in M2 in order for the dc component of the output voltage to be stable In any application of the circuit7 VB would be set by feedback Looking out of the drain of M17 the resistance to ac signal ground is thl 7 02 Figure 15 a CMOS commonesource ampli er b Commonedrain ampli er The voltage gain of the circuit can be Written voizd1sc v0 7 vi vi Zc11sa Gmgl gtlt Tidl Wm 42 Where Gmgl is given by Eq 317 Tidl is given by Eq 307 and R331 R3 The body effect cancels if RS 0 The output resistance is given by Tout Tidl 11702 43 CommonDrain Ampli er Figure 15b shows a commonedrain ampli er The active device is M1 lts load consists of a currentemirror active load consisting of M2 and M3 The current source IQ sets the drain current in M3 Which is mirrored into the drain of M2 As With the commonesource ampli er the Early effect makes the drain current in M2 slightly larger than that in M3 The input voltage can be written 111 VB 112 Where VB is a dc bias voltage Which sets the dc component of the output voltage Looking out of the source of M1 the resistance to ac signal ground is Rtsl 702 The voltage gain can be Written amp Usloc v0 1 701 702 44 vi 39Ui Usloc 1 X1 T01 7 31 702 7 23931 Where Tislis given by Eq The output resistance is given by Tout TislHTo2 45 CommonGate Ampli er Figure 16a shows a commonegate ampli er The active device is M1 lts load consists of a currentemirror active load consisting of M2 and M3 The current source IQ sets the drain current in M3 Which is mirrored into the drain of M2 As With the commonesource ampli er the Early effect makes the drain current in M2 slightly larger than that in M3 The dc voltage VB is a dc bias voltage Which sets the drain current in M1 Which must be equal to the drain current in M2 in order for the dc component of the output voltage to be stable In any application of the circuit VB would be set by feedback Looking out of the drain of M1 the resistance to ac signal ground is thl 7 02 2 3 4 vooc 4 7 f 030 V a b Figure 16 a CMOS Commonegate ampli er b CMOS differential ampli er The voltage gain of the circuit can be Written E M v 0 Gmsl gtlt TileTOZ 46 vi 39Ui Zc11sa Where Gmsl is given by Eq 32 and Tidl is given by Eq The input and output resistances are given by Tin Ri Tisl 47 Tout 7 z39cl1H7 02 48 Where Tislis given by Eq Differential Ampli er A MOS differential ampli er with an active currentemirror load is shown in Fig 16b The object is to determine the Norton equivalent circuit seen looking into the output To do this the output is connected to ac signal ground which is indicated by the dashed line It will be assumed that the Early effect can be neglected in all devices in calculating iosa but not neglected in calculating Tom ie we use the 7 0 approximations We can write iosc id1sa id3sa id1sa id4sa id1sa id2sa 49 Because the tail supply is a current source the currents idl and Q2 can be calculated by replacing v and 1222 with their differential components In this case the ac signal voltage at the sources of M1 an M2 is zero Let vil vid2 and 1222 7vid2 where vid v 7 1222 It follows by symmetry that id2sa 722mm so that iosa is given by UV 2030 22d1sa2Gmgl Ed 1 l vim 2 v 7 v 50 1X T 2 gm1vz1 v22 where Eq 35 with R 0 is used for Gmg Note that the body effect cancels This is because the sourceetoebody ac signal voltage is zero for the differential input signals The output resistance is given by Tout T01HT03 51 Note that Tidl 701 because Rtsl Rts2 0 for the differential input signals SmallSignal HighFrequency Models Figures 17 and 18 show the hybrideTr and T models for the MOSFET with the gateesource capacitance 093 the sourceebody capacitance csb the drainebody capacitance cdb the drainegate capacitance cdg and the gateebody capacitance cgbadded These capacitors model charge storage in the device which affect its highefrequency performance The rst three capacitors are given by 2 cg EWLCW 52 st C b 53 S 1 VSB 012 Cdb i 54 1 VDB 012 where V33 and VDB are dc bias voltages 0st and cdbo are zeroebias values and 0 is the builtein potential Capacitors CW and cgb model parasitic capacitances For lC devices cgd is typically in the range of l to 10 fF for small devices and cgb is in the range of 004 to 015 fF per square micron of interconnect Figure 17 Highefrequency hybrideTr model Copyright 2008 W Marshall Leach7 Jr7 Professor7 Georgia Institute of Technology7 School of Electrical and Computer Engineering The FET Bias Equation Basic Bias Equation a Look out of the 3 MOSFET terminals and replace the circuits With Thevenin equivalent circuits as showin in ig DD RDD ID V R00 00 VIT39 V08 15 RSS VS S Figure 1 Basic bias circuit b Solve the FET drain current equation for VGS I VGSMDVTO c Write the gate7source loop equation in the gate7source loop and let S ID VGG Vss VGS SRSS VGS DRSS d Solve the loop equation for VGS VGS VGG Vss DRSS e Equate the two expressions for VGS and rearrange the terms to obtain a quadratic equation in ID I DRSS 1 fr VGG Vss VTO 0 f Let a R33 1 lVf and c 7 VGG 7 V33 7 VTO In this case7 the bias equation becomes 11 b c c 0 Use the quadratic equation to solve for V5 then square the result to obtain 2 7bb274ac ID T Note that there is a second solution using the minus sign for the radical This solution results in VGS lt VTO7 Which is a non realizable solution The desired solution is the one Which gives the smaller value of ID e Check for the active mode For the active mode7 VDS gt VGS 7 VTO MIDK VDS VD Vs VDD DRDD Vss 191333 VDD Vss D RDD Rss Example 1 V R D R1 R2 RS V Figure 2 Circuit for Example 1 VR2 V Rl V R R R GG R1 R2 GG 1H 2 Vss V7 Rss Rs VDD V RDD RD Example 2 V R RD 1 ID I R2 S RS Figure 3 Circuit for Example 2 VGG V R2 RD 71 R R R R R RDR1R2 DRDR1R2 2 W 1 D 2 R1 R2 V v R R R R DD RDR1R2 DD D 1 2 V33 0 R33 R3 The gateesource loop equation is R2 RD W J R V 1 R RDR1R2 DRDR1R2 2 GS D S This can be solved for VGS ancl equated to MIDK VTO to obtain RDR2 ID VR2 1 R 1 7 7v 0 D3 RDR1R2 K RDR1R2 To The a b7 and c in the bias equation are given by R RDR2 1 VR2 V a c 7 7 S RDR1R2 RDR1R2 To Example 3 R1 R2 Figure 4 Circuit for Example 3 VR2 V R R R GG R1 R2 GG 1H 2 Vss V S DR RS Rss RsH RD R3 RDR3RS RDR3Rs R R VDD V 3 S RS 1 R R R RR RDR3RS SRDR3RS D DD DH3 S Let 1311 The bias equation for ID is VR2 RS RD ID 7 W J R q V 1 R R R R1R2 RDR3RS DRDR3RS 3 K To DlSlHD 3 Which gives RDRS 1D VR2 VRS 1 R R R 7 M i 7 7v 0 D 5 13 3 RDR3RS K R1R2 RDR3RS To The a b7 and c in the bias equation are given by RDRS 1 R R R 7 1 a SHD 3 RDR3RS K VR2 VRS 07 7 7VTO R1R2 RDR3RS 132 I DZ R1 Q2 I R2 I 31 52 R52 Figure 5 Circuit for Example 4 Example 4 For M1 V Vi R RHR V 0 R R GGl R1 R2 GGl 1 2 331 331 31 VDD1 V RDDl RDl The loop equation for D1 is R2 V V I R R1 R2 GSl D1 9 This and the equation for VGSl can be solved for ID1 VGG2 V DlRDl RGG2 RDl V392 0 R332 R32 VDD2 V RDD2 RD2 The loop equation for Dz is V DlRDl VGsz DZRSZ This and the equation for VGS2 can be solve for 132 Given D1 and 132 it can be determined if the two MOSFETs are in the active mode Example 5 R VGGl VR1T2R2 RGGl R1 HR2 V391 0 R331 R31 VGG2 Slel RGG2 R31 VSSZ 0 RSSZ R32 VDD2 V RDD2 RDZ Let the currents to be solved for be D1 and Dz and let 31 D1 and 32 132 The gateesource loop equation for D1 is R VR1T2R2 VGSl ID1R31 This and the equation for VGSl can be solved for ID1 The gateesource loop equation for Dz is Dlel VGsz ID2RS2 Given D1 and 132 it can be determined if the two MOSFETs are in the active mode Copyright 2008 W Marshall Leach Jr Professor Georgia Institute of Technology School of Electrical an Computer Engineering Frequency Response of the CE Ampli er Midband Voltage Gain The gure shows the signal circuit of the commoneemitter ampli er There are three capacitors in the circuit At the mid frequency band these are considered to be short circuits When 7 0 is neglected except in calculating the collector output impedance no the midband voltage gain from Us to 120 is given by any one of the three equivalent expressions RlHR2 A 739 R R RSR1HR2rgRm quotCH CH L 7 R1HR2 1 mml mww gm a 7 R1HR2 1 RSR1HR2Rmm reRte quot HRCHRL oz Rtb 7 7 0 7 HRt Rtb RsHRlHR2 Rte REHRS T f 72 Tia Wt The The rst expression for AU is derived from the simpli ed T model the second is derived from the 7T model and the third is derived from the T model Effect of 01 At low frequencies Cl is an open circuit and the gain is zero Thus Cl has a high pass effect on the gain ie it affects the lower cutoff frequency of the ampli er To account for Cl AU is multiplied by the highepass transfer function 7391 5 T s 1 1 73915 where 7391 is the time constant for Cl The worst case time constant for the calculation of the lower cutoff frequency is the smallest value ie the value which predicts the highest pole frequency For this to be the case the base input resistance rib must be calculated with Cg a short circuit This makes rib its smallest possible value Imagine C1 being replaced With an ohmmeter With the source zeroed The time constant is given by the resistance measured by the ohmmeter multiplied by C1 7391 RsR1llR2llTibCl TibTzTw15Rte The pole frequency is given by 1 7 27771 f1 Effect of C2 Capacitor C2 also has a high pass effect on the gain To account for C2 AU is multiplied by the highepass transfer function 7392 5 T2 5 7 1 73925 Where 7392 is the time constant for C2 The worst case time constant for the calculation of the lower cutoff frequency is the smallest value ie the value Which predicts the highest pole frequency For this to be the case the collector input resistance Tia must be calculated With C1 and C3 short circuits This makes no its smallest possible value lmagine C2 being replaced With an ohmmeter With the source zeroed The time constant is given by the resistance measured by the ohmmeter multiplied by C2 7 0 7quot R 7392 RollTiaRLC2 Tia OL 3tte e 7 Rte The pole frequency is given by 1 f2 7 27172 Effect of C3 When capacitor C3 is an open circuit or a short circuit the gain is not zero Thus C3 must have the effect of a shelving transfer function The gain is the highest When Rte is has the smallest value This occurs When C3 is a short circuit Thus C3 must have a high pass shelving effect on the gain To account for C3 AU is multiplied by the shelving transfer function 7393p 1 T325 7393Z 1 7393ps T3 5 The gain constant 7393p7393Z is necessary to make the highefrequency asymptotic value of T3 unity lmagine C3 being replaced With an ohmmeter With the source zeroed The pole time constant is given by the resistance measured by the ohmmeter multiplied by C3 7393p TieHRE R3 C3 Tie 72 The zero time constant is given by the resistance measured by the ohmmeter With the emitter of the transistor open circuited 73932 RE R3C3 The pole and zero frequencies are given by 1 1 fap f3 271397393p 271397393Z WorstCase Lower Cutoff Frequency fL The lower cutoff frequency of the ampli er is approximately given by 122 103722 where fpi are the pole frequencies and fzi are the zero frequencies This equation gives the worst case value for fL That is the actual lower cutoff frequency cannot be larger than the value predicted by this equation The frequency that dominates is the highest pole frequency HighFrequency Circuit The gure shows that highefrequency equivalent circuit The internal capacitors c7r and CM cause the high frequency gain to roll off Each has a lowepass effect on the voltage gain Note that both connect to the internal base node the B7 node At high frequencies Cl through Cg are all short circuits The time constant for c7r is calculated with CH an open circuit and the time constant for CM is calculated with c7r an open circuit Because CM connects the collector output back into the base circuit it must be replaced by separate capacitors from base to ground and from collector to ground using the Miller theorem Effect of 0 In applying the Miller theorem a capacitor c b is placed from the B7 node to ground and a capacitor C is placed from collector node to ground These are given by c bliKcH CMCH where K is the voltage gain from the B7 node to the collector node This is given by the equation for AU with Rtb 0 and 75 0 K TiaHROHRL TiaHRCHRL Te Rte am a a Because K is negative 1 7 K is a positive number The equivalent circuit is shown in the gure The pole time constant for CM is given by the sum of the time constants for c b and CH9 Imagine c b being replaced With an ohmmeter The time constant for c b is given by the resistance measured by the ohmmeter multiplied by c b T b Rtb Tr Tibll Cub rib 7 7r 1 5 Rte lmagine CW being replaced With an ohmmeter The time constant for CM is given by the resistance measured by the ohmmeter multiplied by CW We TialchllRL CH0 The time constant for CM is the sum of these two time constants m Rtb Tan H Tib Tall Cub TialchllRL cm The pole frequency caused by CM is given by 1 QWTH fJ Effect of c7r In the 7T model c7r is in parallel With m The collector current is proportional to the voltage 12W across this parallel combination When c7r becomes a short circuit at high frequencies the voltage 12W is zero Thus c7r must have a lowepass lter effect To calculate the time constant it Will be assumed that 7 0 is an open circuit in the smallesignal model Looking out of the emitter in the 7T model the Thevenin voltage and resistance are given by Um gmvate Rm Rte The gure shows the 7T model of the baseeemitter circuit With the Thevenin equivalent emitter circuit gmv R Trte CommonCollector Amplifier Example Summer 2000 R x W P y 39Xy Function for calculating parallel resistors R1 100000 R2120000 RC0 RE5600 RS5000 RL10000 Vp15 Vm15 VBE065 VT0025 B99 a099 rX 20 r 0 50000 v 5 1 With vS 0 the voltage gain is equal to v0 1 out R A s U CZ S U 71 0 7 BL DC Bias Solution v R v R v amp v 1364 BB R R BB 1 2 4 RBB RPltR1R2 RBB 545510 v v v 1Ew 1E 255710 3 RBB RE 1H5 AC Solutions This first solution uses the equations involving Rte even though Rtc 0 It is based on the Thevenin emitter circuit which have veOC in series with rieo RPltR1R2 Sm vtb0916 th V Rtb RPltR SRPltR1R2gt Rtb 458103 3 RteRPRERLgt Rte35910 R r Hem re rie55779 1l5 th 39RC th o r to 0 15 v we vtbv v we 0915 to 1quotle39i39IFO i39 H5 r R rleozrie 0 to rieo55717 tc 1F1equot39r0 H5 R R R v O v 606M v O 0901 This is the voltage gain rieoRPRE RLgt 755168 routzRPltREirieogt 1quotout Copyright 2009 W Marshall Leach Jr Professor Georgia Institute of Technology School of Electrical and Computer Engineering Feedback Ampli ers Collection of Solved Problems A collection of solved feedback ampli er problems can be found at the below link The solutions are based on the use of the Mason Flow Graph described below http usersecegatecheduNmleachece3050notesfeedbackFBExamplespdf Basic Description of Feedback A feedback ampli er is one in which the output signal is sampled and fed back to the input to form an error signal that drives the ampli er The basic block diagrams of noniinverting and inverting feedback ampli ers are shown in Fig 1 Depending on the type of feedback the variables x y and z are voltages or currents The diagram in Fig 1a represents a noniinverting ampli er The summing junction at its input subtracts the feedback signal from the input signal to form the error signal 2 m 7 by which drives the ampli er If the ampli er has an inverting gain the feedback signal must be added to the input signal in order for the feedback to be negative This is illustrated in Fig 1b The summing junction at the input adds the feedback signal to the input signal to form the error signal 2 m by In both diagrams the gain around the loop is negative and equal to ibA where both A and b are positive real constants Because the loopigain is negative the feedback is said to be negative If the gain around the loop is positive the ampli er is said to have positive feedback which causes it to be unstable Figure 1 Feedback ampli er block diagrams a Noniinverting b lnverting In the noniinverting ampli er of Fig 1a the error signal is given by z m 7 by The output signal can be written ymA7m D This can be solved for the gain to obtain yi A E HbA 2 We see that the effect of the feedback is to reduce the gain by the factor 1 bA This factor is called the amount of feedback It is often speci ed in dB by the relation 2010g 1 bAl In the inverting ampli er of Fig 1b the error signal is given by z m by When at goes positive y goes negative so that the error signal represents a difference signal The output signal can be written y7amp7Amgt o This can be solved for the gain to obtain y 7A 4 m 1 bA We see that the amount of feedback for the inverting ampli er is the same as for the noniinverting ampli er If A is large enough so that EA gtgt 1 the gain of the non inverting ampli er given by Eq 2 can be approximated by y A 1 g 5 an EA b The gain of the inverting ampli er given by Eq 4 can be approximated by y 7A 7 1 m 7 EA 7 b 6 These are important results for they show that the gain is set by the feedback network and not by the ampli er In practice this means that an ampli er without feedback can be designed without too much consideration of what its gain will be as long as the gain is high enough When feedback is added the gain can be reduced to any desired value by the feedback network The product bA in Eqs 2 and 4 must be dimensionless Thus if A is a voltage gain voltage inivoltage out or a current gain current inicurrent out then I must be dimensionless If A is a transconductance gain voltage inicurrent out I must have the units of ohms If A is a transresistance gain current inivoltage out I must have the units siemens How these are determined is illustrated below We have assumed so far that the gains A and b are positive real constants In general the gains are phasor functions of frequency This leads to a stability problem in feedback ampli ers As frequency is increased lAl must eventually decrease because no ampli er can have an in nite bandwidth The decrease in lAl is accompanied with a phase shift so that EA can be equal to a negative real number at some frequency Suppose that EA 71 at some frequency Eqs 3 and 4 show that the gain becomes in nite at that frequency An ampli er with an in nite gain at any frequency can put out a signal at that frequency with no input signal In this case the ampli er is said to oscillate It can be shown that an ampli er will oscillate if lel 2 1 at any frequency for which EA is a negative real number ie the phase of EA is i180 In the block diagrams of Fig 1 the input and output variables can be modeled as either a voltage or a current It follows that there are four combinations of inputs and outputs that represent the possible types of feedback These are summarized in Table 1 where the names for each are given These names come from the way that the feedback network connects between the input and output stages This is explained in the following for each type of feedback Table 1 The Four Types of Feedback Name Input Output Error Forward Feedback Variable m Variable y Variable z Gain A Factor I Series7Shunt Voltage 21 Voltage 21 Voltage 21 Voltage Gain Dimensionless Shunt7Shunt Current 239 Voltage 21 Current 239 Transresistance siemens Series7Series Voltage 21 Current 239 Voltage 21 Transconductance ohms Shunt7Series Current 239 Current 239 Current 239 Current Gain Dimensionless The Mason SignalFlow Graph The analysis of feedback ampli ers is facilitated by the use of the Mason signali ow graph A signali ow graph is a graphical representation of a set of linear equations which can be used to write by inspection the solution to the set of equations For example consider the set of equations m2Am1Bm2Cm5 7 1 3 D331 E332 1 4 F333 G335 m5 H734 10 are 1mg 11 where 261 through are are variables and A through I are constants These equations can be rep resented graphically as shown in Fig 2 The graph has a node for each variable with branches connecting the nodes labeled with the constants A through I The node labeled m1 is called a source node because it has only outgoing branches The node labeled are is called a sink node because it has only incoming branches The path from 1 to 2 to 3 to are is called a forward path because it originates at a source node and terminates at a nonisource node and along which no node is encountered twice The path gain for this forward path is AEI The path from 2 to 3 to 4 to 5 is called a feedback path because it originates and terminates on the same node and along which no node is encountered more than once The loop gain for this feedback path is EFHC D B A E I x 5 1 x 3 2 953 C F H 5 274 C Figure 2 Flow graph for the equations Mason s formula can be used to calculate the transmission gain from a source node to any nonisource node in a flow graph The formula is 1 T szjpkAk 12 where Pk is the gain of the kth forward path A is the graph determinant and A is the determinant with the kth forward path erased The determinant is given by A 1 7 sum of all loop gains sum of the gain products of all possible combinations of two nonitouching loops 7 sum of the gain products of all possible combinations of three nonitouching loops sum of the gain products of all possible combinations of four nonitouching loops For the ow graph in Fig 2 the objective is to solve for the gain from node 261 to node are There are two forward paths from 1 to are and three loops Two of the loops do not touch each other Thus the product of these two loop gains appears in the expression for A The path gains and the determinant are given by P1 AEI 14 P2 D1 15 A17BCEFHGHBgtltGH 16 Path P1 touches two loops while path P2 touches one loop The determinants with each path erased are given by A1 1 7 GH 17 A217BGHBgtltGH 18 Thus the overall gain from 1 to are is given by 7AEIgtlt17GHDIgtlt17BGHBgtltGH 17 17BCEFHGHBgtltGH 19 This equation can also be obtained by algebraic solution of the equations in Eqs 7 through 11 Review of Background Theory This section summarizes several BJT smallisignal ac equivalent circuits which are used to write the circuit equations in the following sections Fig 3a shows an npn BJT with Thevenin sources connected to its base and emitter and a load resistor connected to its collector First we de ne the emitter intrinsic resistance re the collectoriemitter resistance To the resistance rig and the transconductance Gm These are given by V 5 i 20 V V 0191 A 21 c I Rib l Tm 22 T5 1 5 T T5 a G 23 m 713 Rte where VT is the thermal voltage IE is the emitter bias current VCE is the quiescent collectoriemitter voltage VA is the Early voltage 10 is the quiescent collector current rm is the base spreading resistance 8 is the basecollector current gain and 04 is the emittericollector current gain The latter two are related by 04 1 and 8 04 1 7 a The smallisignal ac Thevenin equivalent circuit seen looking into the base is shown in Fig 3b where UM and m are given by To Ric W 24 1 R C 7 7x 1 78 Raw To Rte Ric 7 6 rib c E 1 Figure 3 Smallisignal equivalent circuits The smallisignal ac Thevenin equivalent circuit seen looking into the emitter is shown in Fig 3c7 where 115UC and me are given by 118076 7 W T To th 1 F 26 V 7 Lth Heirerie thrthlJVa 27 The smallisignal ac Norton equivalent circuit seen looking into the collector is shown in Fig 3d7 where 456 and MC are given by icsc Gmb39utb Gmevze 28 29 The transconductances Gm and Gme are given by Gm m 31 The re Approximations In some of the examples that follow7 the analysis is simpli ed by making use of the soicalled r0 approximations That is7 we assume that m gt 00 in all equations except in the one for MC This assumption makes Gm Gme rib and n5 independent of To In addition7 it makes Gm Gme so that we can denote Gm Gme Gm In this case7 icsc Gm 11 Ute Oz 7 32 r Rte 11 Ute Ub06 Ute m Tm13TeRte 34 was 11th 35 n5 r 36 37gt 7 Z39csc 25 7 a 38 If Ute 0 and Rm 0 r0 appears as a resistor from the collector to ground If Ric 0 r0 appears as a resistor from emitter to ground In either case m can be easily included in the analysis by treating it as an external resistor from either the emitter or the collector to ground SeriesShunt Feedback A seriesishunt feedback ampli er is a noniinverting ampli er in which the input signal at is a voltage and the output signal y is a voltage If the input source is a current source it must be converted into a Thevenin source for the gain to be in the form of Eq Because the input is a voltage and the output is a voltage the gain A represents a dimensionless voltage gain Because bA must be dimensionless the feedback factor is also dimensionless Two examples are given below The rst is an opiamp example The second is a BJT example Op Amp Example Fig 4a shows an op amp with a feedback network consisting of a voltage divider connected between its output and inverting input The input signal is connected to the noniinverting input Because the feedback does not connect to the same terminal as the input signal the summing is series The feedback network connects in shunt with the output node thus the sampling is shunt To analyze the circuit we replace the circuit seen looking out of the opiamp inverting input with a Thevenin equivalent circuit with respect to 110 and the circuit seen looking into the feedback network from the 110 node with a Thevenin equivalent circuit with respect to 2391 We replace the op amp with a simple controlled source model which models the differential input resistance the openiloop voltage gain and the output resistance A test source it is added at the output in order to calculate the output resistance The circuit is shown in Fig 4b where Rid is the differential input resistance A0 is the openiloop gain R0 is the output resistance of the op amp The feedback factor b is given by R1 5 R1 RF The error signal 2 in Fig 4b is a voltage which we denote by 115 It is the difference between the two voltage sources in the input circuit and is given by 39 115 US 7 bug 40 By voltage division the voltage 11 which controls the op amp output voltage is 41 11139 U Rid BBS Rid RillRF Figure 4 a Seriesishunt opiamp example b Circuit with feedback removed Signal tracing shows that the negative feedback has the effect of making the current 2391 smaller For this reason we will neglect the ilRl source in the output circuit in calculating 110 By superposition it follows that 110 can be written R1 RF HRL A v 0 0 1R0R1RFHRL itRoll 31 RF URL 4 To calculate the input resistance we need the current 2391 It is given by 1 239 43 1 Bid To simplify the equations let us de ne Rid k 44 1 RS l Rid l Rlll RF R1 RF HRL k 45 2 R0R1RFll RL Req Roll 31 RF HRL 46 The circuit equations can be rewritten u klue 47 U0 kgAO UZ39 itReq The flow graph for these equations is shown in Fig 5 The determinant is given by A 1 7 161162140 717 1 7616ng 1 174 49 From the flow graph the voltage gain is given by 110 1 616210 A k k A 50 us A 12 0 1bk1k2A0 1bA It follows that A is given by A k116ng This is the gain from US to 110 with b 0 If bA gtgt 1 the gain approaches 110 A 1 RF 1 52 us a 12A 12 T R1 l 7 Figure 5 Flow graph for the seriesishunt opiamp example This is the familiar formula for the gain of the noniinverting op amp From the flow graph the output resistance is given by Tm Req Roll 3115 llRL 53 Similarly the input resistance is given by 2391 1 1 k1 1 rm Z RM 1bARSRid R1HRF 54 Note that the voltage gain and the output resistance are decreased by the feedback The input resistance is increased by the feedback These are properties of the seriesishunt topology Transistor Example The ac signal circuit of an example BJT seriesishunt feedback ampli er is shown in Fig 6 We assume that the dc solutions to the circuit are known The feedback network is in the form of a voltage divider and consists of resistors RF1 and Rpg Because the input to the feedback network connects to the 110 node the ampli er is said to employ shunt sampling at the output The output of the feedback network connects to the emitter of Q1 Because this is not the node to which US connects the circuit is said to have series summing at the input The following analysis assumes the To approximations for Q1 That is we neglect To in all equations except when calculating rid Figure 6 Seriesishunt ampli er In order for the ampli er to have negative feedback the voltage gain from the emitter of Q1 to the collector of Q2 must be inverting When the feedback signal is applied to its emitter Q1 is a commonibase stage which has a noniinverting voltage gain Q2 is a commoniemitter stage which has an inverting gain Thus the ampli er has an inverting voltage gain from the emitter of Q1 to the collector of Q2 so that the feedback is negative To remove the feedback7 we replace the circuit seen looking out of the emitter of Q1 with a Thevenin equivalent circuit with respect to 110 The circuit seen looking into RF1 from the 110 node is replaced with a Thevenin equivalent circuit with respect to 23951 Fig 7 shows the circuit A a test current source is connected to the 110 node to calculate ram The Thevenin voltage looking out of the emitter of Q1 is given by R 1151 UaRlTlRF bun 55 where b is the feedback factor given by R1 1 56 R1 RF Figure 7 Circuit with feedback removed For the circuit of Fig 77 the error voltage 115 is given by 115 US 7 bug 57 Signal tracing shows that the negative feedback has the effect of making the current 23951 smaller For this reason7 we will neglect it in calculating 110 To circuit equations are inn Gmi Us bug Gmive 58 Um icuscwciHRm 59 Rm TicillRm 60 i62sc Gmbzvm 61 110 lama it gtlt MczHRwH RFi RFZ 62 To solve for rm we need ibl If we use the To approximations it is given by Zlclsc Z11 63 51 To simplify the flow graph let us de ne Reqi MaillRm 64 Rqu Mc2llRC2ll RFi RF2 65 The flow graph for the equations is shown in Fig 8 The determinant is given by A 1 lelReq1Gm2Req2bl 1 M 66 Where A is given by A GmlReq1Gm2R5q2 This is the gain from US to 110 With b 0 From the flow graph the voltage gain is given by u 1 A 11 Zaml RequmZ Rqu m The output resistance is given by U0 1 Rqu R 69 Tout it A eq2 1 b 1 icKsc Qth 10230 Rqu s 15 v2 WrRew MGM R242 vquot 1m 31 Figure 8 Flow graph for the seriesishunt example The input resistance is given by Tin usibl Because US is an independent variable it can be used to solve for ibl us not usibl Thus the input resistance can be written 71 71 1 A 7 1 7 i Uni Us 7 A 51 TAGmi 70 But lGml is given by A G 1 RSTm11 1Tel Rtel 71 5 731 l Riel 1 061 Thus rm is given by Tm 1bA Rsm1 151Tei B eil 72 Summary of the E 39ects of SeriesShunt Feedback From the examples above it can be seen that the voltage gain is divided by the factor 1 114 The input resistance is multiplied by the factor 1 EA And the output resistance is divided by the factor 1 114 ShuntShunt Feedback A shuntishunt feedback ampli er is an inverting ampli er in which the input signal at is a current and the output signal y is a voltage If the input source is a voltage source it must be converted into a Norton source for the gain to be in the form of Eq Because the input is a current and the output is a voltage the gain A represents a transresistance with the units 9 Because bA must be dimensionless the feedback factor has the units of U Two examples are given below The rst is an opiamp example The second is a BJT example Op Amp Example Fig 9a shows an op amp with a feedback network consisting of a resistor connected between its output and its inverting input The input signal is connected through a resistor to the inverting input Because the feedback connects to the same terminal as the input signal the summing is shunt The feedback network connects in shunt with the output node thus the sampling is shunt To analyze the circuit we replace the circuit seen looking out of the 1 node through Rs with a Norton equivalent circuit with respect to US and the circuit seen looking out of the 11 node through RF with a Norton equivalent circuit with respect to 110 This must always be done with the shunt shunt ampli er in order for the gain with feedback to be of the form 7A 1 EA where A and b are positive and the 7 sign is necessary because the circuit has an inverting gain In addition we replace the circuit seen looking out of the 110 node through RF with a Th venin equivalent circuit with respect to 11 The circuit with feedback removed is shown in Fig 9b where r n is the input resistance seen by the source current 2395 The Norton current seen looking out of the 1 node is represented by the bug source where b is the feedback factor The current is and the feedback factor are given by Us is R S 73 1 b 74 RF lt gt The error current is is the total current delivered to the 11 node It is given by is is bug 75 Because 110 is negative when is is positive the current bug subtracts from is to cause is to be decreased Figure 9 a Shuntishunt op amp circuit b Circuit with feedback removed Fig 10 shows the circuit with the op amp replaced with a controlled source model which models the differential input resistance Rid the openiloop voltage gain A0 and the output resistance R0 11 A test source it is added at the output in order to calculate the output resistance The voltage 11 controls the opiamp output voltage It is given by U 39 b Ua ieRsllRFllR d Signal tracing shows that the negative feedback has the effect of making the voltage 11 smaller For this reason we will neglect the 11 source in calculating 110 It follows that 110 is given by RFHRL 7A v R R R 77 U0 0U1R0RFHRL 2 0H PM L T2271 Tout l gt 7 Ra J Av 110 is 125 12 1402 RF RL it 7 r r vi 7 bvo RF Figure 10 Shuntishunt circuit with the op amp replaced with a controlled source model To simplify the equations let us de ne Reqi RSllRFll Rid 78 Req2 RollRFHRL 79 RFHRL so RO l RFll RL The circuit equations can be rewritten 1395 15 11110 81 11 ieReql Ua kAO L QRqu The flow graph for these equations is shown in Fig 11 The determinant is given by A 1 7 Reql 74016 1 bReqlek From the flow graph the transresistance gain is given by 110 1 iReqlek 7A 7 7R Ak 85 15 A 1 0 1bReq1A0k 1bA It follows that A is given by A ReqlAOk 86 If bA gtgt 1 the transresistance gain approaches Edi 17173F 87 2395 bA b qu eq1 A0k U0 Figure 11 Flow graph for the shuntishunt ampli er We note that A is the negative of the gain from is to 110 calculated with b 0 Also 711A is the loop gain in the flow graph From the flow graph the output resistance is given by 110 1 ROHRFHRL R 88 Tout it A eq2 1 Similarly the input resistance is given by I W 1 RsllRFllRid R 89 Tm is A 5111 1 We note that Rqu is the output resistance with the 11 source zeroed at the output Also Reql is the input resistance with the bug source zeroed at the input The voltage gain of the original circuit in Fig 9a is given by U0 2511071 7A Alli17 RF US US i57R51bA7R5 17147 Rs 90 where the approximation holds for EA gtgt 1 This is the familiar gain expression for the inverting op amp ampli er The input resistance is obtained from 7 with the relation 1 1 1 Tm R5 i 91 in Transistor Example Fig 12 shows the ac signal circuit of an example BJT shuntishunt feedback ampli er The feedback network consists of the resistor RF which connects between the output and input nodes Because RF connects to the output node the ampli er is said to have shunt sampling Because the current fed back through RF to the input node combines in parallel with the source current the circuit is said to have shunt summing Thus the ampli er is said to have shuntishunt feedback In order for the feedback to be negative the voltage gain from 11 to 110 must be inverting Q1 is a common emitter stage which has an inverting gain Q2 is a commonicollector stage which has a noniinverting gain Thus the overall voltage gain is inverting so that the feedback is negative Fig 13 shows the equivalent circuit with feedback removed The circuits seen looking out of the 1 node through R3 and through RF respectively are converted into Norton equivalent circuits with respect to US and 110 The source current is and the feedback factor b are given by u 25 R 92 1 b 93 RF lt gt Figure 12 Example BJT shuntishunt ampli er Figure 13 Shuntishunt ampli er with feedback removed The feedback network at the output is modeled by a Thevenin equivalent circuit with respect to 11 The external current source it is added to the circuit so that the output resistance can be calculated Signal tracing shows that the input voltage u is reduced by the feedback Therefore we neglect the effect of the 11 controlled source in the output circuit when calculating 110 The circuit equations are Um ieRsHRF ieReqi 94 2395 is bug 95 vi Zlez FtSVll RFllribl Z39e Req2 iclsc Gmbl39utbl 97 Um icuscwdHRm ic1scReq3 98 702 Ue2ac mum 791112172 99 RE2 RF mue ac 2 gtlt TieleREle RF k2U52ac ZtReq4 100 The ow graph for the equations is shown in Fig 14 The determinant is given by A 1 Reinmbi Reqa k1925 1 bReinmbiReq3k1k2 101 The transresistance gain is given by 110 1 Reql GmblRquklkZ 14 R G 7R kk 102 239 A 1 WM 5 13 1 2 1 bRequmblRquklkg 1 bA It follows that A is given by A Reqi GmbiReqaki k2 103 The input and output resistances are given by 7 7 Req2 7 RillRFllmi rm 7 is 7 7 A 104 7 2 7 Req4 7 T e2HRE2HRF Tout it 7 A 7 A It can be seen from these expressions that the transresistance gain the input resistance and the output resistance are all decreased by a factor equal to the amount of feedback Um quot5m 14512 11e2oc Figure 14 Flow graph for the shuntishunt ampli er The voltage gain of the original circuit in Fig 12 is given by 110 2395 110 1 7A 1 74 RF 7 106 US US is RS RS 15 where the approximation holds for 1124 gtgt 1 This is the familiar gain expression for the inverting op amp ampli er The input resistance is obtained from Tl with the relation 1 1 1 Tm Rs T R S 107 in Summary of the E 39ects of ShuntShunt Feedback Notice from the examples above that the transresistance gain and the voltage gain are divided by the factor 1 114 The input resistance Tl is divided by the factor 1 114 And the output resistance is divided by the factor 1 EA Series Series Feedback A seriesiseries feedback ampli er is a noniinverting ampli er in which the input signal at is a voltage and the output signal y is a current 1f the input source is a current source it must be converted into a Thevenin source for the gain to be in the form of Eq Because the input is a voltage and the output is a current the gain A represents a transconductance with the units U Because bA must be dimensionless the feedback factor has the units of 9 An opiamp example is given below Fig 15a shows an opiamp circuit in which a resistor R1 is in series with the load resistor BL The voltage across R1 is fed back into the inverting opiamp input The voltage across R1 is proportional to the output current 2390 This is said to be series sampling at the output Because the feedback does not connect to the same opiamp input as the source the circuit is said to have series summing Thus the circuit is called a seriesiseries feedback ampli er Figure 15 a Example seriesiseries feedback ampli er b Circuit with feedback removed To remove the feedback the circuit seen looking out of the opiamp inverting input is replaced with a Thevenin equivalent circuit with respect to 2390 The circuit seen looking below BL is replaced with a Thevenin equivalent circuit with respect to 2391 The circuit with feedback removed is shown in Fig 15b where the op amp is replaced with a controlled source model that models its differential input resistance Rid its gain A0 and its output resistance R0 The feedback factor b is given by bR1 A test voltage source 11 is added in series with BL to calculate the output resistance We de ne the resistance ram as the effective series resistance in the output circuit including BL It is given by ram iii2390 The output resistance seen by BL is given by lm ram 7 BL Because BL is oating it is not possible to label rant on the diagram 16 Signal tracing shows that the negative feedback has the effect of reducing 2391 For this reason the ilRl source in the output circuit will be neglected in solving for 2390 We can write the following equations U5 Us 7 big 108 Bid 1139 U 109 l RS l Rid l Rl e AO Ul39 U 2 110 a RoRLR1 R0RLR1 vi 21 111 Rid To simplify the equations let us de ne Rid k 112 Rs Rid R1 Reg R0RLR1 113 The circuit equations can be rewritten U 115 114 A0111 11 2 115 0 Reg Reg The flow graph for these equations is shown in Fig 16 The determinant is given by A0 A0 A17 k 7b 1bk 1bA 116 Reg lt gt Re lt gt From the flow graph the transconductance gain is given by 39 kA R 2 ikA0 7 0 w 7 A 117 us A Reg 7 1bkA0Req 7 1bA It follows that A is given by 40 Reg This is the gain from Us to 2390 with b 0 1f 1124 gtgt 1 the gain approaches 2390 A 1 1 777 119 UsTbA 11 R1 Ak 11s This is the gain obtained by assuming the op amp is ideal Because it has negative feedback there is a virtual short between its two inputs so that the voltage at the upper node of R1 is Us and the current through R1 is UsRl Thus the output current is 2390 UsRl The input resistance rm and the output resistance rout are given by 71 71 V 7 21 7 ii 7 7 rm 7 7 A RM 7 A k 7 11ARSRdR1 120 71 71 Z 7 ii 7 Tout 7 7 Reg 7 1 R0 1 RL 1 R1 Note that the effect of the the feedback is to reduce the gain increase the input resistance and increase the output resistance In the case 114 7gt 00 the output resistance becomes in nite and the load resistor BL is driven by an ideal current source 17 Figure 16 Flow graph for the seriesiseries feedback ampli er ShuntSeries Feedback A shuntiseries feedback ampli er is an inverting ampli er in which the input signal at is a voltage and the output signal y is a current If the input source is a voltage source it must be converted into a Norton source for the gain to be in the form of Eq Because the input is a current and the output is a current the gain A represents a dimensionless current gain Because bA must be dimensionless the feedback factor is dimensionless An opiamp example is given below Fig 17a shows an opiamp circuit in which a resistor R1 connects from the lower node of the load resistor BL to ground The voltage across R1 causes a current to flow through the feedback resistor RF into the inverting opiamp input The current through RF is proportional to the output current 2390 This is said to be series sampling at the output Because the feedback connects to the same opiamp input as the source the circuit is said to have shunt summing at the input Thus the circuit is called a shuntiseries feedback ampli er 7 in l gt RS vi a 1 Figure 17 a Shuntiseries ampli er example b Circuit with feedback removed To analyze the circuit we replace the circuit seen looking out of the 11 node through R5 with a Norton equivalent circuit with respect to US and the circuit seen looking out of the 1 node through RF with a Norton equivalent circuit with respect to 2390 This must always be done with the shunt series ampli er in order for the gain with feedback to be of the form 7A 1 114 where A and b are positive and the 7 sign is necessary because the circuit has an inverting gain In addition we replace the circuit seen looking through RF into the 11 node with a Thevenin equivalent circuit with respect to 11 The circuit with feedback removed is shown in Fig 17b where the op amp is replaced with a controlled source model that models its differential input resistance Rid its gain A0 and its output resistance R0 The feedback factor b is is a current divider ratio given by El b 122 R1RF 18 A test voltage source 11 is added in series with BL to calculate the output resistance We de ne the resistance rout as the effective series resistance in the output circuit including BL It is given by ram iii2390 The output resistance seen by BL is given by rim ram 7 BL Because BL is oating it is not possible to label rout on the diagram Signal tracing shows that the negative feedback has the effect of reducing 11 For this reason the 11 source in the output circuit will be neglected in solving for 2390 The error current is is the sum of the two current sources in the input circuit We can write the following equations 2395 is big 123 11139 ieRsH R1 RF ieReql 7A 7A 20 0111 Ut 0111 Ut R0RLR1HRF RoRL R1llRF Reqz Req2 The ow graph for these equations is shown in Fig 18 The determinant is given by A 1 7 1151 11017 1 bReqli 1 bA 126 R5112 R5112 From the ow graph the current gain is given by 390 7 7115 A Re 7 2 iReq1 AO 0 12 7 A 127 15 A 11qu 1 17115le meg2 1 bA It follows that A is given by A0 A R 128 eql Rqu This is the negative of the gain from is to 2390 with b 0 If 1124 gtgt 1 the gain approaches 2390 74 1 RF 7 7 1 129 15 1 12A 11 T R1 This is the gain obtained by assuming the op amp is ideal In this case there is a virtual ground at its inverting input which causes 2395 is big 0 Solution for in yields in figb b L 1 U t s 19 R2111 A0 10 Iqu Figure 18 Flow graph for the shuntiseries ampli er The input resistance Tl and the output resistance rout are given by 1 7 1117 1 7 Rsll R1 RF ll Rid rm 7 7 ZReql 7 1 2390 1 1 1 1 Tout 11 K Rqu 1 T R0 1 BL 19 Copyright 2008 W Marshall Leach Jr Professor Georgia Institute of Technology School of Electrical and Computer Engineering The BJ T Notation The notations used here for voltages and currents correspond to the following conventions Dc bias values are indicated by an upper case letter with upper case subscripts eg VDS Io lnstantaneous values of smallisignal variables are indicated by a lowericase letter with lowericase subscripts eg Us ic Total values are indicated by a lowericase letter with uppericase subscripts eg UBE iD Circuit symbols for independent sources are circular and symbols for controlled sources have a diamond shape Voltage sources have a i sign within the symbol and current sources have an arrow Device Equations Figure 1 shows the circuit symbols for the npn and pnp BJTs In the active mode the collectoribase junction is reverse biased and the baseiemitter junction is forward biased For the npn device the activemode collector and base currents are given by u 239 2015exp 23 EC 1 where VT is the thermal voltage 5 is the saturation current and 8 is the basetoicollector current gain These are given by CT VT 0025V for T 290K 2586 mV for T 300K 2 q Is 150 1U g E 3 A UCE 1 4 5 M VA lt gt where VA is the Early voltage and so and g respectively are the zero bias values of Is and Because Is ISO50 it follows that 2393 is not a function of 110E The equations apply to the pnp device if the subscripts BE and CE are reversed The emitteritoicollector current gain 04 is de ned as the ratio To solve for this we can write 1 1 ZEZBZC 1ZC ZC 5 8 8 It follows that I 2 0 i 6 2E 1 5 Thus the currents are related by the equations ic i3 OtiE z 1 39LB C 13 E B E iE 1C39 E C Fm Pnp Figure 1 BJT circuit symbols Transfer and Output Characteristics The transfer characteristics are a plot of the collector current 2390 as a function of the basetoiemitter voltage UBE with the collectoritoiemitter voltage 110E held constant From Eqs 1 and 3 we can write i0 ISO 1 exp It follows that 2390 varies exponentially with UBE A plot of this variation is given in Fig 2 It can be seen from the plot that the collector current is essentially zero until the basetoiemitter voltage reaches a threshold value Above this value the collector current increases rapidly The threshold value is typically in the range of 05 to 06 V For high current transistors it is usually smaller The plot shows a single curve lf 110E is increased the current for a given UBE is larger However the displacement between the curves is so small that it can be dif cult to distinguish between them The smallisignal transconductance gm de ned below is the slope of the transfer characteristics curve evaluated at the quiescent or dc operating point for a device l l Collector Current 130 I I Bdse Emilier Vol roge vBE Figure 2 BJT transfer characteristics The output characteristics are a plot of the collector current 2390 as a function of the collector toiemitter voltage 110E with the base current 2393 held constant From Eqs 1 and 47 we can write UCE ZC 50 1 2B 9 A It follows that 2390 varies linearly with 110E A plot of this variation is given in Fig 3 For small 110E such that 0 S 110E lt ung7 Eq 9 does not hold In the region in Fig 3 where this holds7 the BJT is saturated The smallisignal collectoritoiemitter resistance r0 de ned below is the reciprocal of the slope of the transfer characteristics curve evaluated at the quiescent or dc operating point for a device 7J0 f ncreqsing B Collec ror Current I Collector Emitter Voltage vCE Figure 3 BJT output characteristics Hybrid7r Model Let each current and voltage be written as the sum of a dc component and a smallisignal ac component as follows icIcic iBIBib 10 39UBE VBE Ube 39UCE VCE 1165 11 If the ac components are sufficiently small7 we can write 7 810 810 7 813 26 7 BVBE39Ube BVCEUCB 2b 7 BVBE 39Ube 12 where the derivatives are evaluated at the dc bias values Let us de ne the transconductance gm7 the collectoritoiemitter resistance To and the baseitoiemitter resistance r as follows BIC 5 ex E 0 13 gm BVBE VT p VT VT r 7 81C 1 7 ex VBE 1 7 VA VCE 14 0 BVCE VA p VT Io 813V ll VBEll hr ex BVBE oVT p VT The collector and base currents can thus be written 1iVT IB u u ce 7r 26 Zc l Zb 7 0 7 7r where 39l 7 7 26 gm39uw 11w We 15 16 17 The smallisignal circuit which models these equations is given in Fig 4a This is called the hybrid77T model The resistor rm which does not appear in the above equations7 is called the base spreading resistance It represents the resistance of the connection to the base region inside the device Because the base region is very narrow7 the connection exhibits a resistance which often cannot be neglected 73 73 O C lb Tx B c 10 I B AvAvAv C TO ltgt lt lt lt To 7T Te lt quot0 me e i e e E b Figure 4 a Hybridi 39 model b T model The smallisignal basetoicollector ac current gain is de ned as the ratio i Cib It is given by 39 Zc gm39uw 9m7 7r Z1 Z1 ilcVTilc TV TIBTIB Note that ic differs from by the current through r0 Therefore7 iCib 7 unless r0 00 T Model 18 The T model replaces the resistor hr in series with the base with a resistor TB in series with the emitter This resistor is called the emitter intrinsic resistance The current can be written 1 1 5 2 22b2g122 225 where 04 is the smallisignal emitteritoicollector ac current gain given by a i 1 Thus the current can be written 19 20 21 The voltage u7r can be related to as follows 2quot ai an m U Zbr7r r7r er 71 zre 22 It follows that the intrinsic emitter resistance TB is given by u r V V re 7r 7r T T ZEEUTHEE The T model of the BJT is shown in Fig 4b The currents in both models are related by the equations gmu7r ib an 24 Simpli ed T Model Figure 5 shows the T model with a Thevenin source in series with the base We wish to solve for an equivalent circuit in which the source connects from the collector node to ground rather than from the collector node to the B node d OPP 39 e z RwB HB cc AAA AAA vvv quotTvvv 1 U 7 lt ltgt tb re ro d 1e 10 18 U8 E Figure 5 T model with Thevenin source connected to the base The rst step is to replace the source on with two identical series sources with the common node grounded The circuit is shown in Fig 6a The object is to absorb the left 04239 source into the baseemitter circuit For the circuit7 we can write 2quot 1 i mvmi zm mm Us vi 7 Let us de ne the resistance r by amp mgamp i w 1 1 With this de nition7 115 is given by 115 11 7 27 The circuit which models Eq 27 is shown in Fig 6b We will call this the simpli ed T model It predicts the same emitter and collector currents as the circuit in Fig 5 Note that the resistors Ru and rm do not appear in this circuit because they are contained in r13 Rtb B Ta B e e le C AvAvAv AVAV v 39 39 g L 0 e 39 tb 2 Te ltgt 7 0 16 7 e 7 0 be Ue E Figure 6 a Circuit With the source replaced by identical series sources b Simpli ed T model The 7 0 Approximations The re approximations approximate m as an open circuit except When calculating the resistance seen looking into the collector Fig 7 shows the simpli ed T model for calculating Tic utic We assume a Thevenin resistance R connected from the base to ground This resistor is absorbed into r13 Which is given by Eq 26 We can write Rte 11 Rte 17 17 28 26 20 Me 20 was r0rguRte was It follows that MC is given by To TlellRte 29 vi Tic 7 2396 7 liaRteT l Rte Figure 7 Circuit for calculating the resistance MC seen looking into the collector The re approximations for the hybrid 7T model the T model and the simpli ed T model respectively are given Figs 8 and 9 If m 00 then ma is an open circuit in each Because r0 no longer connects to the emitter there is only one emitter current and is 2395 a b Figure 8 a Hybrid 7T and b T models with the To approximations Figure 9 Simpli ed T model with the To approximations The Simpli ed 7T Model When To connected from collector to emitter is replaced with ma connected from collector to ground7 it is possible to simplify the 7T model to obtain a circuit that is similar to the simpli ed T model in Fig 9 Consider the circuit of Fig 10a A Thevenin source Ute and Big is connected from the emitter to ground We can write 111 2391 m M 239ng5 1amp5 2391 m hr 1 5 Riel 1amp5 This equation is of the form 39Ub i177 Ute where rlr is given by r 7 7 7r1 Rte With ib the equivalent circuit that predicts the same base and collector currents is shown in Fig 10b We will refer to this as the simpli ed 7T model It is useful when calculating 2391 and the resistance seen looking into the base node when the To approximations are assumed SmallSignal HighFrequency Models Figure 11 shows the hybrid77T and T models for the BJT with the baseiemitter capacitance c7r and the baseicollector capacitance cu added The capacitor Gas is the collectorisubstrate capacitance which in present in monolithic integratedicircuit devices but is omitted in discrete devices These capacitors model charge storage in the device which affects its highifrequency performance The Figure 10 a To approximation to the 7T model With a Thevenin equivalent circuit connected to the emitter b The simpli ed 7T model With the To approximation capacitors are given by T39 I c 05 FTC 30 cC c 31 H l1 VCB bclmn Cos Cjcs l1 VCS bc lmn Where C is the dc collector current V03 is the dc collectoribase voltage V03 is the dc collectori substrate voltage 015 is the zeroibias junction capacitance of the baseiemitter junction 739 is the forward transit time of the baseemitter junction 01C is the zeroibias junction capacitance of the baseicollector junction Cjcs is the zeroibias collectorisubstrate capacitance be is the builtiin potential and ma is the junction exponential factor For integrated circuit lateral pnp transistors Gas is replaced With a capacitor 015 from base to substrate ie from the B node to ground c C H T 03 7 quot H 39 Iquot b w B315 10 lb Tx 3 77 C 7 c 39M C B c J 3 lt lC Orr v 74e jgtTOI CS T a Q e E E a b Figure 11 Highifrequency smallisignal models of the BJT a Hybridi 39 model b T model Copyright 2008 W Marshall Leach Jr Professor Georgia Institute of Technology School of Electrical and Computer Engineering Current Mirrors Basic BJT Current Mirror Current mirrors are basic building blocks of analog design Fig 1 shows the basic npn current mirror For its analysis we assume identical transistors and neglect the Early effect ie we assume VA gt 00 This makes the saturation current 5 and current gain 8 independent of the collector base voltage VCE The input current to the mirror is labeled IREF This current might come from a resistor connected to the positive rail or a current source realized with a transistor or another current mirror The emitters of the two transistors are shown connected to ground These can be connected to a dc voltage eg the negative supply rail 2 l 0 REF 5 0 0 Front Q1 Q m 2 6 6 V Figure 1 Basic current mirror The simplest way to solve for the output current is to sum the currents at the node where REF enters the mirror Because the two transistors have their baseemitter junctions in parallel it follows that both must have the same currents Thus we can write the equation 21 REF 10 70 Solution for 10 yields 0 REF 1 25 Note that this equation predicts that O lt REF unless gt 00 Because the Early effect has been neglected in solving for 0 the output resistance is in nite If we include the Early effect and assume that it has negligible effect in the solution for 0 the output resistance is given by 7 7 VA VCE2 10 For a more accurate analysis we can include the Early effect in calculating the output current Consider the circuit if Fig 2 If the transistors have the same parameters we can write Q 131 50 V0132 VBE 10 I I 1 I 0 50 T VA exp VT B2 501 VCBzVA V 101 150 exp By taking the ratio of O to 01 we obtain V 10 1 532 101 A Note that the voltage V03 is used for the Early effect not the voltage VCE This agrees with the EbersiMoll model for the BJT that is used in SPICE ln deriving the smallisignal 7T and T models the derivations are simpli ed by the use of VCE Thus VCE is used in most contemporary texts for the Early effect The correct value is V03 which is used here I I REF 0 C1 Fraut Q1 Q 2 B1 B2 V Figure 2 Circuit for including the Early effect Summing currents at the node where REF enters the circuit yields 101 Io 21 I I I REF Cl 50 50 1 VCBzVA Cl 50 Thus 01 is given by REF I 01 1250 It follows that O is given by V0132 1 VCBZVA IO 7 1 TA101 WIREF Note that this equation predicts that O can be larger that IREF The output resistance is given above Note that the effect of a nite 8 is to reduce 10 but the effect of the Early effect is to increase it Because of the Early effect the output current can be greater than the input current One way of obtaining a better match between the input and output currents is to use series emitter resistors on the transistors If the current in one transistor increases it causes the voltage across its emitter resistor to increase which causes a decrease in its baseiemitter voltage This causes the current to decrease thus causing the two transistors to have more equal currents A typical value for the emitter resistors might be 100 9 With these resistors R552 is no longer zero so that the output resistance is increased It is given by rout nag which can be much greater than r02 BJT Mirror with Base Current Compensation Figure 3 shows the basic current mirror with a third transistor added The collector of Q3 must be connected to a positive reference voltage eg the positive supply rail which biases it in the active mode If we neglect the Early effect and assume all transistors are identical we can write 210 51 5 REF 10 Solution for 10 yields 7 REF 7 12l515l Io Figure 3 Mirror with base current compensation For a noniin nite Early voltage and V031 VBE3 ltlt VA it can be shown that the output current is given by O REF 1 VCEZVA 1 2 l o 1 53H where 53 50 1 VCEP VA BJT Wilson Mirror A Wilson current mirror is shown in Fig 4 We neglect the Early effect in the analysis and assume the transistors to have identical parameters The emitter current in Q3 is O a This current is the input to a basic current mirror consisting of Q1 and Q2 This current is mirrored into the collector of Q1 by dividing by 1 At the node where REF enters the mirror we can write 10 04 IO 1 10 7 5 IREFil2 7 02 Solution for 10 yields 0 REF 1 5 lt2 5 15 The advantage of the Wilson mirror over the current mirrors examined above is that it has a much higher output resistance This is caused by two positive feedback effects To see how this occurs suppose a test current source is connected between the mirror output and ground If the source delivers current to the output node the voltage increases This causes a current to ow through r03 causing the emitter voltage of Q3 and the base voltage of Q1 to increase The increase in voltage at the emitter of Q3 causes its collector voltage to increase because Q3 is a commonibase stage for an emitter input Because Q1 is a commoniemitter stage for a base input the increase I 7quot REF 0 0 1 out 5 0 3 00 0 120 04 Q1 Q2 V Figure 4 Wilson mirror in voltage at its base causes the collector voltage of Q1 and the base voltage of Q3 to decrease Because Q3 is a commoniemitter stage for a base input the decrease in voltage at its base causes its collector voltage to increase Thus there are two positive feedback effects which cause the collector voltage of Q3 to increase to a larger value Because ram is the ratio of the collector voltage of Q3 to the current in the test source it follows that the output resistance is increased BJT LowLevel Mirror The circuit shown in Fig 5 is a lowilevel current mirror It can be used when it is desired to have a much lower output current than input current For the analysis we neglect the Early effect assume identical transistors and assume that 3 gt 00 We can write V V 71 R REF Sexp 51 10 Sexp By taking ratios we obtain REF ex ORE O p VT This equation cannot be solved for 0 If REF and O are speci ed it can be solved for RE to obtain V I RE i T ln REF IO 10 As an example suppose REF 1mA VT 25 mV and O 50 44A It follows from this equation that RE 1498 9 The effect of this large a value of RE on ram is to make it greater than To To calculate ram we must know the smallisignal Thevenin resistance Rm looking out of the base of Q2 Note that Q1 is a bjt connected as a diode and exhibits a smallisignal resistance mull rml 1 81 VTIEll VTIE1 25 9 This is in parallel with the smallisignal resistance looking up into the REF source Thus an upper bound on Rm is 25 9 Let us assume r02 40 k9 r052 0 042 0995 and 82 199 It follows that n52 Ra 1 aVTIcg 4976 99 Thus ram is given by 40000 4976H1498 1595 kg 1 7 0995 X 1498 4976 1498 Tout 741122 This is larger than mg by a factor of almost 4 V Figure 5 Lowilevel mirror BJT Transconductance Op Amp An example application of the current mirror is the transconductance op amp The circuit is shown in Fig 6 The circuit consists of an input diff amp and four Wilson current mirrors For the analysis we assume 3 gt 00 and VA gt 00 for each bjt so that the output current from each mirror is equal to the input current We assume that ABC splits equally between the emitters of Q1 and Q2 Thus the total currents in Q1 and Q2 respectively are given by ABC 7 ic2 23901 ici icz 1 ABC 1 ABC 2 2 The latter expression for 23902 follows because id 23962 0 It follows from the mirrored currents that the output current is given by 2390 2261 If we neglect base currents and the Early effect id 23951 111 7 m2 2re where he QVTIABC Thus in is given by Z 1 ABC 0 QVT It can be seen that the transconductance gain is set by the current 1430 The gain can be varied by varying L430 Because ABC 2 0 the circuit operates as a twoiquadrant multiplier The circuit symbol for the transconductance op amp is shown in Fig 7 W1 7 112 An example application of the transconductance op amp is a circuit which generates an amplii tude modulated signal The circuit is shown in Fig 8 Let 11 and ABC be given by 11 V1sinwct ABC IQ 1msinwmt where wc is the carrier frequency mm is the modulating frequency and m is the modulation index which must satisfy 71 lt m lt 1 The current in is given by 20 1 ABC W32 QVT R1 R2 If we assume that CF is an open circuit at the operating frequencies the current in must flow through RF Because the second op amp forces the voltage at its inverting input to be zero the output voltage is given by L430 11132 IQRF V132 2VT R1R2 F m R1R2 110 iaRF sin coat 1 msin wmt 5 Figure 6 Transconductance op amp Figure 7 Transconductance opiamp symbol Voh ctge Figure 8 AM modulator Time Figure 9 AM modulated waveform Copyright 2009 W Marshall Leach Jr Professor Georgia Institute of Technology School of Electrical and Computer Engineering The BJ T Notation The notations used here for voltages and currents correspond to the following conventions Dc bias values are indicated by an upper case letter with upper case subscripts eg VDS IO lnstantaneous values of smallisignal variables are indicated by a lowericase letter with lowericase subscripts eg Us ic Total values are indicated by a lowericase letter with uppericase subscripts eg UBE iD Circuit symbols for independent sources are circular and symbols for controlled sources have a diamond shape Voltage sources have a i sign within the symbol and current sources have an arrow Device Equations Figure 1 shows the circuit symbols for the npn and pnp BJTs In the active mode the collectoribase junction is reverse biased and the baseiemitter junction is forward biased For the npn device the activemode collector and base currents are given by u 239 2015exp 23 EC 1 where VT is the thermal voltage 5 is the saturation current and 8 is the basetoicollector current gain These are given by VTEO025V forT290K2586mV forT300K 2 q IS 150 VA 39UCE 1 4 50 VA where VA is the Early voltage and ISO and g respectively are the zero bias values of Is and Because Is 5050 it follows that 2393 is not a function of 110E The equations apply to the pnp device if the subscripts BE and CE are reversed The emitteritoicollector current gain 04 is de ned as the ratio To solve for this we can write iEiBic1iCiC 5 It follows that I 20 a i 239E 15 Thus the currents are related by the equations 6 i0 MB ME 7 739 1 39LB C 13 E B B iE 1C39 E C rlF l l Pnp Figure 1 BJT circuit symbols Transfer and Output Characteristics The transfer characteristics are a plot of the collector current 2390 as a function of the basetoiemitter voltage UBE with the collectoritoiemitter voltage 110E held constant From Eqs 1 and 3 we can write 39UCE 39UBE I 1 8 20 SOVABXPVT It follows that 2390 varies exponentially with UBE A plot of this variation is given in Fig 2 It can be seen from the plot that the collector current is essentially zero until the basetoiemitter voltage reaches a threshold value Above this value the collector current increases rapidly The threshold value is typically in the range of 05 to 06 V For high current transistors it is usually smaller The plot shows a single curve 1f 110E is increased the current for a given UBE is larger However the displacement between the curves is so small that it can be dif cult to distinguish between them The smallisignal transconductance gm de ned below is the slope of the transfer characteristics curve evaluated at the quiescent or dc operating point for a device l l Collector CurremL LC I I I I I I I Base Emitter Volidge vBE Figure 2 BJT transfer characteristics The output characteristics are a plot of the collector current 2390 as a function of the collector toiemitter voltage 110E with the base current 2393 held constant From Eqs 1 and 47 we can write z39c 50 1 2393 9 A It follows that 2390 varies linearly with 110E A plot of this variation is given in Fig 3 For small 110E such that 0 S 110E lt ung7 Eq 9 does not hold In the region in Fig 3 where this holds7 the BJT is saturated The smallisignal collectoritoiemitter resistance r0 de ned below is the reciprocal of the slope of the transfer characteristics curve evaluated at the quiescent or dc operating point for a device C f ncreosing i3 Colleclor Current I Collec0rEmiler Voltage vCE Figure 3 BJT output characteristics Bias Equation Figure 4a shows the BJT with the external circuits represented by Thevenin dc circuits If the BJT is biased in the active region7 we can write VBB VEE BRBB VBE EREE I I 03133 VBE fREE 10 This equation can be solved for C to obtain I VBB VEE VBE 11 C BBB5REE06 It can be seen from Fig 2 that large changes in C are associated with small changes in VBE This makes it possible to calculate C by assuming typical values of VBE Values in the range from 06V to 07V are commonly used Two sets of values for 04 and are convenient for hand calculations One is 04 099 and 99 The other is 04 0995 and 199 Figure 4 a BJT dc bias circuit b Circuit for Example 1 Example 1 Figure 41 shows a BJT dc bias circuit It is given that VJr 15V R1 20 k9 R2 10kg R3 R4 3kg R5 R6 2kg Solve for I01 and I02 Assume VBE 07V and 100 for each transistor Solution For Ql7 we have V331 VR2R1 R2 R331 R1HR27 VEE1 IBZR4 1023457 VEEl 07 and REEi R4 For Q27 W8 haVe V3132 El R4 101R4067 R3132 R47 VEEZ 07 REEZ R6 Thus the bias equations are R I 2 2 101 101 R R R R R1R2 4 BE 3 1H2 04 4 I I I 234 VBE 34 2R6 04 04 These equations can be solved simultaneously to obtain I01 141 mA and I02 174 mA Hybrid7T Model Let each current and voltage be written as the sum of a dc component and a smallisignal ac component as follows icIcic iBIBib 12 39UBE VBE Ube 39UCE VCE 1165 13 If the ac components are suf ciently small7 we can write BIC BIC BIB 2 u u 2 u c BVBE be BVCE as b BVBE be 14 where the derivatives are evaluated at the dc bias values Let us de ne the transconductance gm7 the collectoritoiemitter resistance To and the baseitoiemitter resistance r as follows BIC 1 5 ex E 0 15 gm BVBE VT VT VT r 7 81C 1 7 ex VBE 1 7 VA VCE 16 0 BVCE VA p VT Io 813V ll hr ex BVBE oVT p The collector and base currents can thus be written VBE VT 1iVT IB l u u ce 7r 25 ZC 2b 7 0 7 7r where 39l 7 7 26 gm39uw 11w We 17 18 19 The smallisignal circuit which models these equations is given in Fig 5a This is called the hybrid77T model The resistor rm which does not appear in the above equations7 is called the base spreading resistance It represents the resistance of the connection to the base region inside the device Because the base region is very narrow7 the connection exhibits a resistance which often cannot be neglected 1 C l 7 a O l E b x c C AAA B C d vvv L gt C lt ltgtTO U ltgtTO me 19 11 719 e E b Figure 5 a Hybridi 39 model b T model The smallisignal basetoicollector ac current gain is de ned as the ratio i Cib It is given by Lc JLC iigm39uwi 7A 39 m VTIB B Z1 5 i1 Note that ic differs from by the current through r0 Therefore7 iCib 7 unless r0 00 T Model 20 The T model replaces the resistor hr in series with the base with a resistor TB in series with the emitter This resistor is called the emitter intrinsic resistance The current can be written l1i15 39 39 ZC 2C Oz 5 5 where 04 is the smallisignal emitteritoicollector ac current gain given by i 1H9 47 47 2872bzci a Thus the current can be written 21 22 23 The voltage u7r can be related to as follows aquot 2quot 2 an m u7r 2hr7r Ear erw 237 231 are 24 It follows that the intrinsic emitter resistance TB is given by u r V V re 7r 7r T T ZWWE The T model of the BJT is shown in Fig 5b The currents in both models are related by the equations I gmu7r ib die 26 Simpli ed T Model Figure 6 shows the T model with a Thevenin source in series with the base We wish to solve for an equivalent circuit in which the source connects from the collector node to ground rather than from the collector node to the B node X7 39 e 1 Rtb B Tx 8 c 3 AAA AAA VVV VVV Utb lb ltgtr ltI 3 gt O me 10 18 118 E Figure 6 T model with Thevenin source connected to the base The rst step is to replace the source on with two identical series sources with the common node grounded The circuit is shown in Fig 7a The object is to absorb the left 04239 source into the baseemitter circuit For the circuit7 we can write 2quot 1 5 3 RH m 7 m 7 239 Rf j we 27 Us vi 7 Let us de ne the resistance r by Rtb l rw orRtb l T m l T W I 28 7 5 1 T T5 1 With this de nition7 115 is given by 39l I 115 11 7 Zara 29 The circuit which models Eq 29 is shown in Fig 7b We will call this the simpli ed T model It predicts the same emitter and collector currents as the circuit in Fig 6 Note that the resistors Ru and no do not appear in this circuit because they are contained in r13 Rtb B Ta B e e le C AVAVAV AVAVAV g L 0 e 39 tb 2 Te 2 To 16 7 e 7 0 be Ue E Figure 7 a Circuit with the source replaced by identical series sources b Simpli ed T model Norton Collector Circuit The Norton equivalent circuit seen looking into the collector can be used to solve for the response of the commoniemitter and commonibase stages It consists of a parallel current source icsc and a resistor Tic from the collector to signal ground Fig 8a shows the BJT with Thevenin sources connected to its base and emitter To solve for the Norton equivalent circuit seen looking into the collector7 we use the simpli ed T model in Fig 8b By superposition of 11C ails 111 and Ute the following equations for ic and can be written 2 39Uc O i17 39Utb Rte C rorgHRze 5 rgRzeHmRtem I Ute Te 7 30 Rzergllrorgro l 2 11th 7 We 5 r RteHTo Rter ll70 116 31 5 7 0 l dell Rte 713 Rte These can be solved to obtain 239 Lai LGHFT g C rgB ellTO B e70 B er ll70 T rro 16 1 7 r0 T llRte r Rze This equation is of the form u 2c 2cm 33 LC where mg and MC are given by icsc Gmb39utb Gmevte 34 I R J T8 8 lt35 1 7 O Rte 7 l Rte 7 Figure 8 a BJT with Thevenin sources connected to the base and the emitter b Simpli ed T model Figure 9 a Circuit for calculating MC b Norton collector circuit and Gm and Gme are given by G a 7 m r Rzellro Rte r0 g 06 7 0 Rte 36 7J5 Rtellro To Rte 1 r G a 5 me Rzer llro rgro E I M 37 7 5 l RtellTO 7 0 Rte The Norton equivalent circuit seen looking into the collector is shown in Fig 9 For the case To gtgt Rte and To gtgt r13 we can write Z39csc Gm vi 7 Ute where a G 39 m 745 Rte 8 a Figure 10 a BJT with Th venin source connected to the base b T model circuit for calculating 115026 39 The value of icsc calculated with this approximation is simply the value of ails where is calf culated with To considered to be an open circuit The term r0 approximations is used in the following when m is neglected in calculating iCSC but not neglected in calculating MC Th venin Emitter Circuit The Th venin equivalent circuit seen looking into the emitter is useful in calculating the response of commonicollector stages It consists of a voltage source 115UC in series with a resistor me from the emitter node to signal ground Fig 10a shows the BJT symbol with a Th venin source connected to the base The resistor Ric represents the external load resistance in series with the collector To solve for the Th venin equivalent circuit seen looking into the emitter7 we use the simpli ed T model in Fig 10b By superposition of 111 2395 and dig the following equations for 115 and can be written To R Us 11th Ze To thl Rtch 7 8 40 Mar TO Ric Utb 7 Us 25 T 41 These can be solved to obtain O th Utb U 1 i r 1 7 04 8 T T0th T 70thl0 BLcl ier ll T0 Rte 42 which simpli es to 1 7 I Us Utb 7 0 l 04 Ric 7 5 70 l Ric rgro1iach Tzergro1iach This equation is of the form 115 1150C 7 25775 Figure 11 a Circuit for calculating iesc b Th venin emitter circuit where 115UC and me are given by U U 701704th 506 tbrm1ath or 7 0 45 vibrgroch1 l 7439 Ti 70th w er ro106th Er 740th 46 7 ergroth1 The Th venin equivalent circuit seen looking into the emitter is shown in Fig 10 Th venin Base Circuit Although the base is not an output terminal7 the Th venin equivalent circuit seen looking into the base is useful in calculating the base current It consists of a voltage source 111mm in series with a resistor m from the base node to signal ground Fig 12a shows the BJT symbol with a Th venin source connected to its emitter Fig 12b shows the Pi model for calculating the base voltage By superposition of 115 ib and ib treating each branch of ib separately in the superposition we can write the following equation for 11 r u waif 2 in r Riel m Rt TORte 2 quot Bis m Bax r UteBmir ffBLC 2b Tm hr Rtell To Ric TORte 47 Rte l 7 0 l Ric This equation is of the form 39Ub 111mm ibm 48 where UM and m are given by 7 0 l Ric 49 WW Ute Rte To Ric 10 R zb Tx E 70 Rte t0 vb LC T 51b 2 39 U b lt o b y lt Le me i 9 Rte lt R ltgt te Q 15 e lt29 a in Figure 12 a BJT With Thevenin source connected to the emitter b T model for calculating Ubac b vboc Figure 13 a Circuit for calculating 11 b Thevenin base circuit Mb Tmr7rRtellToth TORte 5Rroth grm l 1 reRtellTO th TORte 50 5Rroth l The equivalent circuit Which models these equations is shown in Fig 13 The re Approximations The re approximations approximate m as an open circuit in all equations except the one for MC In this case7 the equations for mg Gm MC 11506 n5 ubac and m are 51 Oz 2556 Zlc Gm 1112 Ute Gm m To Tl2llRte 52 T limeMR l 115026 111 We Tl 53 um vie m n r 1 5 B42 g n 1 5 re Rte 54 The simpli ed T model the hybrid 7T model and the T model respectively are given Figs 14 and 15 If m 00 then ma is an open circuit in each Because r0 no longer connects to the emitter there is only one emitter current and is a b Figure 15 a Hybrid 7T and b T models with the To approximations Summary of Models Examples This section describes several examples which illustrate the use ofthe smallisignal equivalent circuits derived above to write by inspection the voltage gain the input resistance and the output resistance of both singlestage and twoistage ampli ers The CommonEmitter Ampli er Figure 17a shows the ac signal circuit of a commoniemitter ampli er We assume that the bias solution and the smallisignal resistances r and m are known The output voltage and output Figure 16 Summary of the smallisignal equivalent circuits resistance can be calculated by replacing the circuit seen looking into the collector by the Norton equivalent circuit of Fig 9b With the aid of this circuit we can write 110 icpec Ticllth Gmb Ticllth 111 55 Tout TicllBtc 56 where Gm and ma respectively are given by Eqs 36 and 35 The input resistance is given by Tm Ru m 57 where m is given by Eq 50 The CommonCollector Ampli er Figure 17b shows the ac signal circuit of a commonicollector ampli er We assume that the bias solution and the smallisignal resistances r and m are known The output voltage and output resistance can be calculated by replacing the circuit seen looking into the emitter by the Thevenin equivalent circuit of Fig 10b With the aid of this circuit we can write U U Rte 70th1Jr3 Rte U 58 0 R r m R 1 5 me Rte Tout Well Rte where we is given by Eq 46 The input resistance is given by Tm Ru m 60 where m is given by Eq 50 Figure 17 a Commoniemitter ampli er b Commonicollector ampli er c Commonibase ampli er The CommonBase Ampli er Figure 17c shows the ac signal circuit of a commonibase ampli er We assume that the bias solution and the smallisignal parameters r and m are known The output voltage and output resistance can be calculated by replacing the circuit seen looking into the collector by the Norton equivalent circuit of Fig 9b The input resistance can be calculated by replacing the circuit seen looking into the emitter by the Thevenin equivalent circuit of Fig 10b with 115OC 0 With the aid of these circuits we can write 110 725W mallec Gme Ticllth Ute 61 Tout Wollth Tm Rte We 63 where Gme MC and mg respectively are given by Eqs 37 35 and 46 VV The CE CC Ampli er Figure 18a shows the ac signal circuit of a twoistage ampli er consisting of a CE stage followed by a CC stage Such a circuit is used to obtain a high voltage gain and a low output resistance The voltage gain can be written U0 7 Zlclsc 1th U82OC 39Ua Um Um iclsc 1112 Ue2ac 7 R7552 Gleir39lRCq X X m l w r22 To n52 352 where rig is calculated with Rm T idHRCL The input and output resistances are given by Tm Rm W1 65 Tout TieleRtBZ Although not a part of the solution the resistance seen looking out of the collector of Q1 is Rm RCi HTM Figure 18 a CECC ampli er 00 Cascode ampli er The Cascode Ampli er Figure 1800 shows the ac signal circuit of a cascode ampli er The voltage gain can be written 10 7 20156 39UteZ 26256 10 Wu Um 51095 1152 Z39c2sc Gmi gtlt incl gtlt GmBZ gtlt TiCle RtCZ where Gmeg and nag are calculated with Rteg Md The input and output resistances are given by Tm Rm m1 Tout RtCleriCZ The resistance seen looking out of the collector of Q1 is Rid n52 A second cascode ampli er is shown in Fig 19a where a pnp transistor is used for the second stage The voltage gain is given by 10 20156 39UteZ 26256 10 i X X X Um 39Utbl Zc1sc U252 Zc2sc Gml gtlt Ticlll Rcl gtlt Gme2 gtlt HallRch The expressions for rm and ram are the same as for the cascode ampli er in Fig 1800 The resistance seen looking out of the collector of Q1 is Rid Relllneg The Differential Ampli er Figure 1900 shows the ac signal circuit of a differential ampli er For the case of an active tail bias supply the resistor RQ represents its smallisignal ac resistance We assume that the transistors are identical biased at the same currents and voltages and have identical smallisignal parameters Figure 19 a Second cascode ampli er b Differential ampli er Looking out of the emitter of Q1 the Thevenin voltage and resistance are given by RQ 1151 7 U52acm roth1 RQ 67 rgroB c1 RQ REne Riel RE l Tie The smallisignal collector voltage of Q1 is given by 1101 7i51sc Mall Ric 7 Gmb39utbl 7 Gmeutel Wall Ric mb TicllthMtbi 1 R TORZC Q G u mer T0th13 VieRERQ Z By symmetry7 1102 is obtained by interchanging the subscripts 1 and 2 in this equation The smalli signal resistance seen looking into either output is Tout thllric Where Tic calculated from Eq 35 With Rte RE RQH RE me Although not labeled on the circuit7 the input resistance seen by both utbl and 11th is rm rib A second solution of the diff amp can be obtained by replacing utbl and 11th With differential and commonimode components as follows 11139 Wu Uicm 1 71 2 72 Um Uicm Where 111w utbl 711th and 11mm utbl um 2 Superposition of via and 11mm can be used to solve for 1101 and 1102 With 11mm 07 the effects of utbl MOD2 and 11th iuid2 are to cause 16 uq 0 Thus the uq node can be grounded and the circuit can be divided into two commoniemitter stages in which Rte RE for each transistor In this case 110101 can be written Zlclsc X 10111 Utb1d Zc1sc 11139 110101 Utb1d Gmd X TicllBLc cm X WCHRR bl 3W 73 By symmetry 110201 7110101 With 1101 0 the effects of utbl 11th 11mm are to cause the emitter currents in Q1 and Q2 to change by the same amounts lf RQ is replaced by two parallel resistors of value QRQ it follows by symmetry that the circuit can be separated into two commoniemitter stages each with Biacm RE QRQ In this case 1101mm can be written Zlclsc U01cm U0 cm X I U cm Gmcm inc Ric Uicm 1 Utb1cm Z5156 tb1 Gmtmwcncmaw 74 By symmetry 1102mm 1101mm Because Rte is different for the differential and commonimode circuits Gm and m are different However the total solution 1101 110101 1101mm is the same as that given by Eq 69 and similarly for 1102 Note that MC is the same for both solutions and is calculated with Rte RE RQH RE We The smallisignal base currents can be written ibl 11mm rvbcm 1101 rvbd and M 11mm rbcm 7Udrvbd lf RQ gt 00 the commonimode gain is very small approaching 0 as To gt 00 In this case the differential solutions can be used for the total solutions If RQ gtgt REne the commonimode solutions are often approximated by zero SmallSignal HighFrequency Models Figure 20 shows the hybrid77T and T models for the BJT with the baseiemitter capacitance c7r and the baseicollector capacitance cu added The capacitor Gas is the collectorisubstrate capacitance which in present in monolithic integratedicircuit devices but is omitted in discrete devices These capacitors model charge storage in the device which affects its highifrequency performance The capacitors are given by T39 I c7r 015 3T0 75 Cu 76 l1 VCB Cl a CCS 77 l1 VCS bc lmn where C is the dc collector current V03 is the dc collectoribase voltage V05 is the dc collectori substrate voltage 015 is the zeroibias junction capacitance of the baseiemitter junction 739 is the forward transit time of the baseemitter junction CjC is the zeroibias junction capacitance of the baseicollector junction Cjcs is the zeroibias collectorisubstrate capacitance be is the builtiin potential and ma is the junction exponential factor For integrated circuit lateral pnp transistors Gas is replaced with a capacitor 015 from base to substrate ie from the B node to ground In these models the currents are related by gmuw wile 78 These relations are the same as those in Eq 26 with 239 replaced with 2392 17 Copyright 2008 W Marshall Leach Jr Professor Georgia Institute of Technology School of Electrical and Computer Engineering Useful Circuit Theorems Impedance of a TwoTerminal RC Network Consider any twoeterminal RC network If the impedance at dc is not in nite the impedance can be written 17 zs ZR da1TpS where Rda is the dc resistance of the circuit To is its openecircuit time constant and 739 is its shortecircuit R C C 01 b time constant 2 R 0 cl Figure 1 Example twoeterminal circuits For example applications of the theorem consider the circuits shown in Fig 1 In order from a to d the impedances are given by 1 ZR 1RCs 1R1HR2CS Z R R 1 2 1R2Cs 1 R1HRg R2 Cs 1 R2 R3 Cs 1 R1HR2 Rg HR4CS 1 R2 R3 HR4Cs Although the theorem is strictly valid for circuits containing only one capacitor it can be applied to circuits containing more than one capacitor if the adjacent poles and zeroes in the transfer function are well removed preferable by a decade or more Consider the circuit shown in Fig 2 Let us assume that C2 and Cg are open circuits in the frequency range in which C1 is active C1 is a short circuit and Cg is an open circuit in the frequency range in which C2 is active and C1 and C2 are short circuits in the frequency range in which Cg becomes active Z R1 R2 Z R1 R2H R3 134 Figure 2 Example circuit containing more than one capaictor With the above information the impedance in the range Where 02 and 03 are open circuits is given by 1 R2 R1 R3 R4 015 1 R2 01 5 1 5 w2 1 5 w1 21 R1R2R3R4 R1 R2R3R4 Where 7 1 7 1 m 2 W At low frequencies Z1 starts at the value R1 R2 R3 R4 and shelves at high frequencies at the value R1 R3 R4 The impedance in the range Where 01 is a short circuit and 03 is an open circuit is given by 1 R3H R1 R4 025 1 R3025 1 5 w4 1 5 w3 W1 Z2 R1R3R4 R1 R3 R4 Where 1 1 414 R302 R311 R1 R4 02 At low frequencies Z2 starts at the value R1 R3 R4 and shelves at high frequencies at the value R1 R4 The impedance in the range Where 01 and 02 are short circuits is given by W3 1R4llR1035 Z R R 3 1 4 1 R4035 15w6 R R 1 4 1 51425 Where 7 1 7 1 Q15 7 R403 we 7 1341113103 At low frequencies Z3 starts at the value R1 R4 and shelves at high frequencies at the value R1 The three impedances can be pieced together to obtain the overall impedance to obtain 1 51422 1 51424 1 51425 Z R R R R l 1 2 3 4 1 544 1 543 1 5425 This expression is strictly if 1 ltltw2 ltltw3 ltltw4 ltltw5 ltltw5 The straighteline approximation to the Bode magnitude plot for the impedance is shown in Fig 3 The impedance theorem can be used to Write by inspection the transfer function of an inverting opeamp circuit Where the input and feedback impedances contain no more than one capacitor each Consider the circuit shown in Figure 4 The voltage gain can be Written by inspection to obtain V2 R3 1R1HR2015 77 R R V1 1R3025 1 2 1R2025 1R2025 R3 7R1 R2 1 R1HR2015 1 R3025 IZI 1Y3911139lt211231124 1131R3R4 21m4 I 601002 603 604 605 606 Figure 3 Bode magnitude plot for the impedance Z Figure 4 Inverting opeamp example Impedance of an RC VoltageDivider Network Case 1 7 Capacitor in Shunt Arm Consider the voltageedivider network shown in Fig 5a Let the impedance Z2 contain one capacitor and satis es the condition for the twoeterminal impedance theorem By voltage division7 the gain of the network is given by V2 7 Z2 7 Z2 1 R1 Z2 Z3 where Z3 R1 Z2 The impedance Z2 can be written 1 739 s 22 32 23 1 T205 where 73920 is the openecircuit time constant for Z2 and 7392S is its shortecircuit time constant The impedance Z3 can be written 1 T335 1 T305 where 73930 is the openecircuit time constant for Z3 and 7393S is its shortecircuit time constant Z3 R1 R2 Figure 5 Voltage divider networks containing only one capacitor But the openecircuit time constants for Z2 and Z3 are the same Let this be denoted by To 73920 73930 thus the two impedances can be written 17 235 Z 3 2 21739os and 1 7 335 Z R R 3 1 21739os It follows that the gain of the voltage divider is given by V2 7 R2 1 739sz 1 R1 R2 1 T335 Notice that the term 1 73905 is canceled Note also that the gain constant is the circuit gain at dc7 the pole time constant 7393S is the time constant calculated with Vi 07 and the zero time constant 7392S is the time constant with V0 0 Case 2 7 Capacitor in Series Arm Now consider the case shown in Fig 5b where Z1 contains one capacitor and satis es the condition for the twoeterminal impedance theorem By voltage division7 the gain of the network is given by V2 R2 R2 71 m 2 3 where Z3 Z1 R2 The impedance Z3 can be written 1 T335 23R1R21T3 s o where 73930 is the openecircuit time constant for Z3 and 73933 is its shortecircuit time constant It follows that the gain of the voltage divider is given by V2 7 R2 1 T305 V1 R1 R2 1 T335 But the openecircuit time constant for Z3 is equal to the openecircuit time constant for Z1 ie 73930 73910 Thus the gain of the circuit can be written V2 7 R2 1 T105 V1 R1 R2 1 T335 Note that the gain constant is the circuit gain at dc the pole time constant 73933 is the time constant calculated with Vi 0 and the zero time constant 73913 is the time constant with the Vi node oating ie open circuited Combined Theorem We seek to combine the two theorems into one which gives the correct answer for both cases In the second case the time constant 73910 is the same as the time constant calculated with V0 0 Thus it follows that the two theorems can be combined to obtain the general solution V2 17392s kda V1 17 15 where kda is the dc gain 7391 is the time constant with V1 0 and 7392 is the time constant with V2 0 As an example consider the circuit shown in Fig 6a By inspection the voltage gain can be written V2 R2R3 1R2HR3R4CS 71 R1R2R31R1R2HR3R4le The Bode magnitude plot is that of a lowepass shelving function b Figure 6 Example circuits for the voltageedivider theorem The voltage gain of the circuit in Fig 6b is given by E R4 1R2R3Cs V1 7 R1R2R41lR1R4HR2R3lCS The Bode magnitude plot is that of a highepass shelving function The voltageedivider theorem can be used to write the voltage gain expression for a noneinverting opeamp circuit Consider the circuit shown in Fig 7 The voltage divider network in Fig 6a is shown connected between the output of the op amp and its inverting input Because the op amp has negative feedback there Copyright 2009 W Marshall Leach Jr Professor Georgia Institute of Technology School of Electrical and Computer Engineering Collection of Solved Feedback Ampli er ProbleIns This document contains a collection of solved feedback ampli er problems involving one or more active devices The solutions make use of a graphical tool for solving simultaneous equations that is called the Mason Flow Graph also called the Signal Flow Graph When set up properly the graph can be used to obtain by inspection the gain of a feedback ampli er its input resistance and its output resistance without solving simultaneous equations Some background on how the equations are written and how the ow graph is used to solve them can be found at httpusersecegatecheduNmleachece3050notesfeedbackfdbkampspdf The gain of a feedback ampli er is usually written in the form A l bA where A is the gain with feedback removed and b is the feedback factor In order for this equation to apply to the four types of feedback ampli ers the input and output variables must be chosen correctly For ampli ers that employ series summing at the input alson called voltage summing the input variable must be a voltage In this case the source is modeled as a Thevenin equivalent circuit For ampli ers that employ shunt summing at the input also called current summing the input variable must be a current In this case the source is modeled as a Norton equivalent circuit When the output sampling is in shunt with the load also called voltage sampling the output variable must be a voltage When the output sampling is in series with the load also called current sampling the output variable must be a current These conventions are followed in the following examples The quantity Ab is called the loop gain For the feedback to be negative the algebraic sign of Ab must be positive lf Ab is negative the feedback is positive and the ampli er is unstable Thus if A is positive b must also be positive If A is negative b must be negative The quantity 1 Ab is called the amount of feedback It is often expressed in dB with the relation 2010g1 Ab For series summing at the input the expression for the input resistance is of the form BIN X l bA where BIN is the input resistance without feedback For shunt summing at the input the expression for the input resistance is of the form BIN l bA For shunt sampling at the output the expression for the output resistance is of the form R0 1 bA where R0 is the output resistance without feedback 0 calculate this in the examples a test current source is added in shunt with the load For series sampling at the output the expression for the output resistance is of the form R0 X l bA To calculate this in the examples a test voltage source is added in series with the load Most texts neglect the feedforward gain through the feedback network in calculating the forward gain A When the ow graph is used for the analysis this feedforward gain can easily be included in the analysis without complicating the solution This is done in all of the examples here The dc bias sources in the examples are not shown It is assumed that the solutions for the dc voltages and currents in the circuits are known In addition it is assumed that any dc coupling capacitors in the circuits are ac short circuits for the smallesignal analysis SeriesShunt Exalnple 1 Figure 1a shows the ac signal circuit of a serieseshunt feedback ampli er The input variable is 111 and the output variable is 122 The input signal is applied to the gate of M1 and the feedback signal is applied to the source of M1 Fig 1b shows the circuit with feedback removed A test current source 239 is added in shunt with the output to calculate the output resistance RE The feedback at the source of M1 is modeled by a Thevenin equivalent circuit The feedback factor or feedback ratio b is the coefficient of 112 in this source ie b R1 R1 R3 The circuit values are gm 0001 S 7 s 91 le 7 0 00 R1 le R2 10 k9 R3 9k9 R4 lkfl and R5 100 k9 The following equations can be written for the circuit with feedback removed 1 R1 idl Gmlva Gml 11a 11 Um Um v2 7 31 R1HR3 R1 R3 id2 vatgz Figure 1 a Ampli er circuit b Circuit With feedback removed 7 R1R4 7 R1 R3 R4 Utgz ile2 112 1ch itRC id1RD RC R4H R1 R3 RD The voltage 12a is the error voltage The negative feedback tends to reduce 12a making lval A 0 as the amount of feedback becomes in nite When this is the case7 setting 12a 0 yields the voltage gain 122121 If1 1 RgRl Although the equations can be solved algebraically the signale ow graph simpli es the solution Figure 2 shows the signale ow graph for the equations The determinant of the graph is given by R1 A17G 7R 7 R R 71 m1xl 2Xgm2x 0 plxR1R3x RD 1 vcu id1 V rgZ id2 V2 v1 r 1Gm1 R2 gm2 RC RC v rsl R1 R1R3 Figure 2 Signale ow graph for the equations The voltage gain 122121 is calculated With it 0 It is given by U2 Gml gtlt l R2 gtlt 9m2 gtlt RC RDl 111 A 1 gtlt R gtlt gtltR R 7 T31R1HR3 2 gm2 C D 7 R1 R R R T31R1HR3M2xym2x 0 DXR1R3 This is of the form 12 2 7 A 111 7 1 Ab where 1 R R R 483 T31R1HR3 gtlt 2gtlt9m2gtlt 0 D R1 1 01 R1 R3 Note that Ab is dimensionless Numerical evaluation yields 122 483 326 121 1 0483 The output resistance R3 is calculated with U1 0 It is given by 122 R0 R0 R 6139 B 239 A 1Ab Note that the feedback tends to decrease RB Because the gate current of M1 is zero7 the input resistance is RA R5 100k9 SeriesShunt Exalnple 2 A serieseshunt feedback BJT ampli er is shown in Fig 3a A test current source is added to the output to solve for the output resistance Solve for the voltage gain 122111 the input resistance RA and the output resistance RB Assume 1007 m 10k 27 a 1 gm T7n Te Ozgm 7 0 07 7 75 07 R1 1 k97 R2 1 k97 R3 2 k97 R4 4k 27 and R5 10k9 The circuit with feedback removed is shown in Fig The circuit seen looking out of the emitter of Q1 is replaced with a Thevenin equivalent circuit made with respect to 122 A test current source 239 is added to the output to solve for the output resistance Figure 3 a Ampli er circuit b Circuit with feedback removed For the circuit with feedback removed7 we can write R3 1 R1 2 G 7 G 39 39 21 1 11a v1 122R3 R4 1 T l R3HR4 T21 1 Te 191 04121 ial 1 R2 Zb1 390th 1 1R2 Z 2 GZUth G2 7 2 r 5 a E rig E 1 3 7 R3135 7 R3 R4 R5 The equations can be solved algebraically or by a ow graph The ow graph for the equations is shown in Fig 4 The determinant is 23992 04222 v2 ia2Ra itRa 1le Ra RSH R3 R4 Rb 7R A 17G1gtltagtlt7R2gtlt7G2gtltagtltRQRblgtlt 7 3 7 1G1gtltOzgtltR2gtltGQXOLXRQRblgtlt R3R4 909 Rb 1 v0 G1 I a ic1 R2 32 or Ra Rd v1 I Ie1 i vth ie2 icZ v2 ibl R3 R3R4 Figure 4 Signale ow graph for the equations The voltage gain is v2 7 G1gtltagtlt7R2gtlt7G2gtltagtltRaRb 12 1 7 f 7 G1gtltagtltR2gtltG2gtltagtltRaRb 1G1XaXR2XG2Xo XRaRbX This is of the form 1227 A Z 1Ab Whe re A G1gtltagtltR2gtltG2gtltagtltRaRb 1 1 RSRS gtltRgtlt gtlt gtltR RR T1R3llR4 a 2 722 a 3 4 R3R4R5 2427 R3 b 0333 R3R4 Notice that the product Ab is positive This must be true for the feedback to be negative Numerical evaluation of the voltage gain yields 112 A 267 A 3901 The resistances RA and R3 are given by 71 71 RA 2 AxAx R1r7r100k 2 3901 R R R R 2 5H 44125 2 R B 2 A SeriesShunt Exalnple 3 A serieseshunt feedback BJT ampli er is shown in Fig 5a Solve for the voltage gain 112111 the input resistance RA and the output resistance RB For J17 assume gml 0003 S7 and 701 00 For Q2 assume 2 1007 7W2 25ku7 042 Q 1 2 9mg 27 7r27 7 92 042ng 7 02 07 752 0 The circuit elements are R1 1M9 R2 10 k97 R3 1k 27 R4 20 k97 and R5 10 k9 The circuit with feedback removed is shown in Fig 5b The circuit seen looking out of the source of J1 is replaced with a Thevenin equivalent circuit made with respect to 122 A test current source 239 is added in shunt with the output to solve for the output resistance Figure 5 a Ampli er circuit b Circuit with feedback removed For the circuit with feedback removed7 we can write R3 1 7 39 G G 11a v1 112R3 R4 M1 1 1 T31 R3HR4 1 R2 739 R 39 G G 390th ldl 2 222 2390th 2 32 792 1 m 722 RSRS R R R R R R R R 292 042122 112 192 a Zn a ldl b a 5H 3 4 b R3 R4 R5 The equations can be solved algebraically or by a ow graph The ow graph for the equations is shown in Fig 6 The determinant is 7R3 A 17G 7R 7G R R 1gtltl 2gtlt 2gtltO gtlt a leR3R4 R3 1 G R G R R 1X 3X Max a blxR3R4 2108 The voltage gain is 2 7 G1gtlt7R2gtlt7G2gtlta2gtltRaRb v1 7 A G1gtlt RnggxangaJer R3 1 G R G R R 1gtlt3gtlt 2gtltagtlt a blxR3R4 This is of the form where 1 va G1 i R2 GZ or R0 R0 1 id1 v rb2 ieZ ic2 V2 R3 R3R4 Figure 6 Signale ow graph for the equations 1227147 A 1Ab 2391 A G1gtltR2gtltG2gtlta2gtltRaRb 1 1 R3R4 R gtlt gtlt gtltR R R T31R3HR4 2 WEI 041 5H 3 4R3R4R5 4218 R3 b 00467 R3R4 Notice that the product Ab is positive This must be true for the feedback to be negative Numerical evaluation of the voltage gain yields The resistances RA and R3 are given by 27 4218 720 v1714218gtlt004767 RAR11M Z v2 Ra R5HR3R4 R 32139 B it A A SeriesShunt Exalnple 4 A serieseshunt feedback BJT ampli er is shown in Fig 7a A test current source is added to the output to solve for the output resistance Solve for the voltage gain 122111 the input resistance RA and the output resistance RB Assume 507 hr 25k97 a l gm TW Te 04 R1 1k l7 R2 10097 R3 99 k97 R4 10 k97 and R5 10 k9 The circuit with feedback removed is shown in Fig 8 The circuit seen looking out of the base of Q2 is a Thevenin equivalent circuit made with respect to the voltage 122 A test current source 239 is added in shunt with the output to solve for the output resistance The emitter eQuivalent circuit for calculating 23991 and 23992 is shown in Fig 7b For this circuit and the circuit with feedback removed7 we can write iel lee ial lbi 13993 0423 I w e R2R3 Telr 2 e2 1 e c e 1 UtbS chR1 293 GZ39Utb3 G2 a 723 1 TE R2R4 R R 7 R R R R R R 02 293 a 2 0 Zb2 b a 4ll 2 3 b R2 133 134 am To 00 Ta 07 VCC VEE a Figure 7 a Ampli er circuit b Emitter equivalent circuit for calculating 23991 and 23992 R1 ie3 03 RE R3 ic3 V2 R2 R4 1 Figure 8 Circuit With feedback removed The equations can be solved algebraically or by a ow graph The ow graph for the equations is shown in Fig 9 The determinant is A 17G1gtltaX7R1X7G2XaXRa7X 2 3 Rb R2 1 G R G R 7 1gtlt agtlt 1gtlt 2gtltagtlt a 1 gtltR2R3 8004 1 1 ib2 Rb ieZ 1 ve 11 aim R1 62 a Ru V2 v1 if G1 ie1 v rb3 1e ic3 Ra Ib1 R2 R2R3 Figure 9 Flow graph for the equations The voltage gain is G gtlt gtlt R gtlt G gtlt gtltR Rb 2 7 1 Oz 1 2 04 a 1 v1 7 A Rb G R G R 7 7 1gtltagtlt 1gtlt 2gtltagtlt a 1 Rb R2 1 G R G R 7 1gtltaX 1gtlt 2gtltagtlt a 1 gtltR2R3 This is of the form 1227 A i171Ab Where A 7 G gtlt gtltR gtltG gtlt gtltR Rb 7 1 Oz 1 2 04 a 1 1 1 R2134 gtltRgtlt gtlt gtltR RR 7 mr2a 1 733 a 4H 3 1 R2R3R4 7004 R2 1 001 R2 R3 Notice that the product Ab is positive This must be true for the feedback to be negative Numerical evaluation of the voltage gain yields 112 A 8751 111 A The resistances RA and R3 are given by ibl 71 Glad 71 I RA 7 R511 a 7 R5H RSH A x 1 5 X m 792 8032 kn A U2 R411 R2 133 239 A A RB 62479 ShuntShunt Example 1 Figure 10a shows the ac signal circuit of a shunteseries feedback ampli er The input variable is 111 and the output variable is 122 The input signal and the feedback signal are applied to the base of Q1 A test current source 239 is added in shunt with the output to calculate the output resistance RB For the analysis to follow convention the input source consisting of 111 in series with R1 must be converted into a Norton equivalent This circuit is the current 2391 vlRl in parallel with the resistor R1 Fig 10b shows the circuit with feedback removed and the source replaced with the Norton equivalent The feedback at the base of Q1 is modeled by a Norton equivalent circuit 112134 in parallel with the resistor R4 The feedback factor or feedback ratio 1 is the negative of the coefficient of 112 in this source ie iRil The circuit values are l 100 gml 0058 751 0 Tibl lgml QkQ 7 01 00 ng 0001 S 732 97 1k9 7 02 00 R1 lkfl R2 lkfl R3 10k9 and R4 10kg Figure 10 a Ampli er circuit b Circuit with feedback removed The following equations can be written for the circuit with feedback removed 3902 vbl zaRb 2a 21 R Rb R1 HR4HTib1 191 gmlvbl 4 R2 R3 ldl Zalm U2 Zlea MR9 11mm Ra R3HR4 The current in is the error current The negative feedback tends to reduce in making A 0 as the amount of feedback becomes in nite When this is the case setting in 0 yields the current gain 1122391 7R4 Although the equations can be solved algebraically the signale ow graph simpli es the solution Figure 11 shows the ow graph for the equations The determinant of the graph is given by 7R2 R3 1 A17Rgtlt gtlt gtltR gtlt b gml TslR2 a R3R4 R4 The transresistance gain is calculated with 239 0 It is given by 7R2 R3 R gtlt gtlt gtltR 2 b 9 r32R2 R3R4 2391 7 A 7R2 R3 R R V R R 7 lt 1H 4Hnmxgm1xmR2Xlt 3 Miami iRa R3 71 1 R R v R R 1H 4H72b1X9m1XT3232X 3 4R3R4 X R4 Rb gm1 R2 RC Rc rsZR2 1 m Figure 11 Signale ow graph for the equations This is of the form 1227 A i171Ab where R ARR v gtlt XXRR 3 77781k 2 lummgm mm u mm 1 b 7 7104 s R4 Note that Ab is dimensionless and positive Numerical evaluation yields 122 77781 X 103 78861k9 2391 1 7781 X 103 X 71041 The voltage gain is given by I 22X 22x i78861 U1 21 U1 21 R1 The resistance Ra is calculated with 239 0 It is given by vbi Rb RlllR lHTibl R 11 Z a 2391 A 1 Ab 7 7 Note that the feedback tends to decrease Ra The resistance RA is calculated as follows RA R1 R1 7 Rf 1 10mm The resistance R3 is calculated with 2391 0 It is given by R3 2amp MR4 239 A 1A 56949 b ShuntShunt Example 2 A shunteshunt feedback JFET ampli er is shown in Fig 12a Solve for the voltage gain 122111 the input resistance RA and the output resistance RB Assume gm 0005 S7 7 s 9 200 9 7 0 07 R1 3ku7 R2 7k l7 R3 1 k97 R4 10 k9 The circuit with feedback removed is shown in Fig 12b In this circuit7 the source is replaced by a Norton equivalent circuit consisting of a current 2391 vlRl in parallel with the resistor R1 This is necessary for the feedback analysis to conform to convention for shunteshunt feedback The circuit seen looking up into R2 is replaced with a Norton equivalent circuit made with respect to 122 A test current source it is added in shunt with the output to solve for the output resistance 10 Figure 12 a Ampli er circuit b Circuit With feedback removed For the circuit With feedback removed7 we can Write 1 3902 R R R R R G G U9 21 b R2 b b 1H 2 2d mvg m TS R3 R4 739 R 39 R R R R 112 2d 92 ang2R4 1 2H 4 The equations can be solved algebraically or by a ow graph The ow graph for the equations is shown in Fig 13 The determinant is R4 1 A 17R G 7R bgtltmx CR2RJgtltR2 1 R4 1beGmeaim XE 18539 L R2R4 1 id Rb Gm Id Rc Rc I1 1 V9 V2 Figure 13 Signale ow graph for the equations The transresistance gain is R RbgtltGmgtlt7Ra 4 2 7 R2R4 2391 7 A R4 7R G R7 7 bgtltmgtlt c R2RJ R4 1 1 R G R bgtltmgtlt CR2R4 gtltR2 This is of the form 12 i171Ab Where R4 A 7R G R7 bgtltmgtlt c R2RJ R4 7R R G R R 7 1112xmx 2H 4 1mm 75971k9 b 7i 701429mS R2 Note that the product Ab is dimensionless and positive The latter must be true for the feedback to be negative Numerical evaluation yields 122 A 7322 k9 2391 A The voltage gain is given by 122 112 2391 A 1 gtlt gtlt 7l074 111 2391 111 A R1 The resistances Ra7 RA7 and R3 are given by 12 Rb R 9 113kn 2391 A 1 1 1 RAR1R 7E 482kn a 112 RC R 222kn B 239 A ShuntShunt Example 3 A shunteshunt feedback BJT ampli er is shown in Fig 14 The input variable is the v1 and the output variable is the voltage 122 The feedback resistor is R2 The summing at the input is shunt because the input through R1 and the feedback through R2 connect in shunt to the same node7 ie the UM node The output sampling is shunt because R2 connects to the output node Solve for the voltage gain 1221117 the input resistance RA7 and the output resistance RB Assume 1007 7W 25 9 gm Tm 04 5 1 Te Ozgm 7 0 07 7 2 07 VT 25 mV The resistor values are R1 lkfl7 R2 QOkQ7 R3 50097 R4 lkfl7 and R5 5k9 The circuit With feedback removed is shown in Fig 15 A test current source 239 is added in shunt With the output to solve for the output resistance RB In the circuit7 the source is replaced by a Norton equivalent circuit consisting of a current U1 R1 2391 12 Figure 15 Circuit With feedback removed in parallel With the resistor R1 This is necessary for the feedback analysis to conform to convention for shunt summing The circuit seen looking into R2 from the collector of Q3 is replaced With a Thevenin equivalent circuit made With respect With vbl For the circuit With feedback removed7 we can Write 39U le Z1 R 2 39Ubl leRb Rb RlllR2HT7r 191 gmvbl Ub2 chRc Ra R3HT7r 2 R5 Uba 292Rd Rd R4HT7r 193 gmvba U2 Zaa R R2 vbl Re R2HR5 R2 R5 The equations can be solved algebraically or by a ow graph The ow graph for the equations is shown in Fig 16 The determinant is R5 1 A 17R 7R 7R 7R bxgmx oxymx ngmx ER2R5XR2 R5 1 1 R R R R7 bxgmx oxymx ngmx 2 R2R5XR2 3547 R2R5 Ie I01 vb2 02 vb3 103 V2 ll It 1 Rb Vbl gm Rc gm Rd gm Re Re 1 R2 Figure 16 Signal7 ow graph for the equations The transresistance gain is v2 Rbgtltgmx7Raxgmx7Rdxgmx7ReJr Z A 7Rbgtlt ngRanmXRngmXRe7i 7 R2R5 R2 1 1 R R R R7 bgtltgmgtlt anmX dgtltgmgtlt e R2R5 gtltR2 R2 7Rbgtlt ngRanmXRngmXRe7 7 R2 R5 R2 71 1 7R R R R 7 bgtlt9mgtlt agtlt9mgtlt dgtlt9mgtlt e R2R5 XR2 This is of the form I 292 A 111 1Ab Where A and b are given by A77Rgtlt gtltRgtlt gtltRgtlt gtltR7i b 9m 0 9m d 9m 2 R2R5 RHRH gtlt gtltRH gtlt gtltRH gtlt gtltRHR R5 7 r r r 7 1 2 7r 9m 3 7r 9m 4 7r 9m 2 5 R2R5 77073M9 b 1750ps Notice that the product Ab is dimensionless and positive The latter must be true for the feedback to be negative Numerical evaluation of the transresistance gain yields 727 12 g 71994k9 The resistances Ba and RA are Ra vi bll 19459 1 1 1 RA R1 7 1002162 The resistance R3 is 7 e 11289 2 A 71 v2 v2 vbl A 1 71991 um i1gtlt2391 AXRA ShuntShunt Example 4 v27R The voltage gain is A shunteshunt feedback BJT ampli er is shown in Fig 17 The input variable is the v1 and the output variable is the voltage 122 The feedback resistor is R2 The summing at the input is shunt because the input through R1 and the feedback through R2 connect in shunt to the same node7 ie the 1291 node The output sampling is shunt because R2 connects to the output node Solve for the voltage gain 1221117 the input resistance RA7 and the output resistance RB For Q1 and Q27 assume 1007 7W 25ku7 gm TW a 1 Te Ozgm 7 0 07 7 2 07 VT 25 mV For J37 assume 9mg 00018 and 703 00 The resistor values are R1 1 k97 R2 100 k97 R3 10 9 R4 30 k97 and R5 10 k9 R2 RB AAA vvv Figure 17 Ampli er circuit The circuit With feedback removed is shown in Fig 18 A test current source 239 is added in shunt With the output to solve for the output resistance RB In the circuit7 the source is replaced by a Norton equivalent circuit consisting of a current 7 v1 7 R1 in parallel With the resistor R1 This is necessary for the feedback analysis to conform to convention for shunt summing The circuit seen looking into R2 from the collector of Q3 is replaced With a Thevenin equivalent circuit made With respect With v91 2391 RE R0 gt I ve1 Q1 I01 Hg R1 R3 7 T E 7 R2 R2 I ll Figure 18 Circuit With feedback removed For the circuit With feedback removed7 we can Write U2 le Z1 F 1121 ZeRb Rb 1311le11721 191 gmlvel Utga ZalRa 2 39 39 R 39 G G 1 1 M3 3113 39Ub2 ld34 Z2 WM 1 T T2 9m tg t e t T 2R2HR5 22 R4 9 R5 122 72922Rav91 R2R5 RCRQHRS The equations can be solved algebraically or by a ow graph The ow graph for the equations is shown in Fig 19 The determinant is R5 1 A 7 17Rbgtltgm1XR3X9m2X7R4X7G1gtlt7RamXE 71Rgtlt gtltRgtlt gtltRgtltGgtltR7i xi 7 b gml 3 9m2 4 1 a R2R5 R2 1130 R5 R2R5 1 Ie Rb 1 9m R3 gm3 R4 31 Rc RC I1 1 l ve1 iol vtg3 id3 vtb2 ie2 V L R2 Figure 19 Signale ow graph for the equations The transresistance gain is R2 R R 7R 7G 7R v2 7 bgtlt9m1gtlt 3gtlt9m2gtlt 4gtlt 1gtlt 0R2R5 h A R2 R5 R 7Rbgtltgm1XR3X9m2XR4XG1XRai 2 R2 1 1 R R R G Ri bgtlt9m1gtlt 3gtlt9m2gtlt 4gtlt 1gtlt a R2R5 gtltR2 7Rbgtltgm1XR3X9m2XR4XG1XRai R2 7 R2R5 7 R2 R2 71 1 7R R R G R 7 7 bgtlt9m1gtlt 3gtlt9m2gtlt 4gtlt 1gtlt a R2R5 R2R5gtltR2 This is of the form I 2927 A 111 7 1Ab Where A and b are given by R A 7Rbgtltgm1gtltR3gtltgm2gtltR4gtltG1gtltRa 2 mamp RlHRZHTel gtlt gml gtlt R3 gtlt 9m2 gtlt R4 gtlt 7112MQ R X R2HR5 7 5 1 7122R211R5 R2R5 bT 710ps 2 Notice that the product Ab is dimensionless and positive The latter must be true for the feedback to be negative Numerical evaluation of the transresistance gain yields A 2 7991116 21 A The resistances Ba and RA are 1121 Rb R 0214 Z 2391 A 1 1 1 R R 7 1k 2 A 1 Ra R1 The resistance R3 is 122 RC R 8049 Z B 239 A The voltage gain is 112 122 1291 71 A 1 gtlt gtlt 79909 A R SeriesSeries Exalnple 1 Figure 20a shows the ac signal circuit of a serieseseries feedback ampli er The input variable is 111 and the output variable is idg The input signal is applied to the gate of M1 and the feedback signal is applied to the source of M1 Fig 20b shows the circuit With feedback removed A test voltage source 1 is added in series With the output to calculate the output resistance Rb The feedback at the source of M1 is modeled by a Thevenin equivalent circuit The feedback factor or feedback ratio 1 is the coef cient of idg in this source7 ie b R5 The circuit values are gm 0001 S7 7 s 9 1 k97 7 0 07 R1 50 k97 R2 10 k97 R3 lkfl7 R4 th39l7 and R5 lkfl Rb vl R5 RB RajB ltJ 2 v2 R2 id2 V R2 0392 M2 RA RA I M2 gt 1011 gt loll idZ d2 v1 1 M1 Vi R1 idll R4 W O R5 R5 R5 CH 1012 R5 1 T O b Figure 20 a Ampli er circuit b Circuit With feedback removed 17 The following equations can be written for the circuit with feedback removed 1 ldl Gmlva Gml 11a 121 Um Um ld2R5 7 31 R5 G G 1 R M2 m2vb m2 39Ub39UtquotUt2 39Ut2 ldl 2 732 R3 9 g The voltage 12a is the error voltage The negative feedback tends to reduce 12a making lval A 0 as the amount of feedback becomes in nite When this is the case7 setting 12a 0 yie ds the transconductance gain idgvl If1 Rgl Although the equations can be solved algebraically the signale ow graph simpli es the solution Figure 21 shows the signale ow graph for the equations The determinant of the graph is given by A 1 7 Gml gtlt 7R2 gtlt 71 gtlt Gmg gtlt R5 gtlt 71 vi 1 Va M1 002 1 Gm2 v1 idZ 4 cm R2 1 vb vfsl R5 Figure 21 Flow graph for the equations The transconductance gain idgvl is calculated with v 0 It is given by W 111 A 1 gtltR gtlt TslR5 2 7 31 R5 1 gtltR gtlt gtltR TslR5 2 731R5 5 This is of the form idg A 01 7 1 Ab where 1 1 AG X 7R X 71 gtltG gtltR gtlt 25gtlt10 3S m1 2 m2 TslR5 2 732R3 b R5 10009 Note that 11A is dimensionless Numerical evaluation yields idg 25 X 10 3 4 124 10 S 121 1 1000 X 25 X 103 7 X The resistance Rb is calculated with 111 0 It is given by 71 71 Rb 1bAr32R37k 2 vi A Note that the feedback tends to increase Rb The resistance R3 is calculated as follows RB Rb 7 R3 le 85719 Because the gate current of M1 is zero7 the input resistance is RA R1 50 k9 18 SeriesSeries Exalnple 2 A serieseseries feedback BJT ampli er is shown in Fig 22 The input variable is the voltage 111 and the output variable is the voltage 122 The feedback is from 23992 to the emitter of Q1 Because the feedback does not connect to the input node the input summing is series The output sampling is series because the feedback is proportional to the current that ows in series With the output rather than the output voltage Solve for the transconductance gain iagUl the voltage gain 112121 the input resistance RA and the output resistance RB Assume 100 01 06mA 02 lmA 03 4mA a 1 gm IcVT re aVTIc 7 0 0 Ti 0 VT 25mV R1 1009 R2 9k9 R3 5k9 R4 6009 R5 6409 and R5 100 9 The circuit With feedback removed is shown in Fig 23 Figure 22 Ampli er circuit The circuit looking out of the emitter of Q1 is a Thevenin equivalent made With respect to the current 23993 The output current is proportional to this current ie 23993 0423993 Because 7 0 00 for Q3 the feedback does not affect the output resistance seen looking down through R4 because it is in nite For a nite 7 0 a test voltage source can be added in series With R4 to solve for this resistance It would be found that a nite 7 0 for Q3 considerably complicates the circuit equations and the ow graph R1IIR5R6 R6 R1 93 R6R5R1 Figure 23 Circuit With feedback removed For the circuit With feedback removed7 we can Write R5 R1 1 v v 7239 239 G v G 239 04239 E 1 E3R5R5 R1 E1 1 E 1 Tel R1H R5R5 01 E1 39 1 R a1 2 7 R G G 7 2b1 390th 191 2 222 2390th 2 T72 722 1 g Te 1 39 39 739 R 39 G 7 k 39 G 192 04222 39UtbS 192 3 123 311 1121 3 T73 R6H R1 R5 1 R6 239 ai v 7239 R R1R5rg311R5 R5r3 3 E3 2 2 4 The equations can be solved algebraically or by a ow graph The ow graph for the equations is shown in Fig 24 The determinant is 761 A 17G1gtlt ax 7R2XG2XOLX7R3XG37 1X 7 R5R1 7 1G1gtltozgtltR2gtltG2gtltagtltRaik1gtlt R6R5R1 2515 k1 1 ve ic1 v1b2 ie2 ic2 v1b3 153 v1 103 G1 ie1 x R2 G2 a R3 G3 a 1 1b1 8 R6R1 R6R5R1 Figure 24 Signale ow graph for the circuit The transconductance gain is 23953 7 G1gtltagtlt7R2gtltG2gtltagtlt7R3gtltG37k1plta 12 1 A 7 G1gtltaXRQXGQXaXR3XG37k1gtltO 1G1gtltangngxaxRaikl x G1gtltaXRQXGQXaXR3XG37k1gtltO RBRl 1 1 G R G R 7k 1gtltagtlt 2gtlt 2gtltagtlt a 1gtltagtltR6R5R1gtlta This is of the form 37 A v171Ab Where A and b are given by A G1gtltaXRQXGQXaXR3XG37k1gtltO 1 1 1 gtlt axRX XaxRX Xa 721R1111R5Rsl i 2 7522 3 T 3R6H1R1Rsl R1 R5 X a R1 R5 7133HR5 R5 7133 20838 7 R5131 7 R6 R5 R1 Notice that the product Ab is dimensionless and positive The latter must be true for the feedback to be negative Numerical evaluation of the transconductance gain yields 23993 A K 0083 X l 12029 a U1 The voltage gain is given by v 239 v A 2 03gtlt 2 gtlt7R47497 v1 v1 203 A The resistances RA and R3 are given by 71 1 RA 2 G1 A Xglm Ax 15 X 791 R1H R5R5 3285Mn 3901 RB R4600 Z SeriesSeries Exalnple 3 A seriesseries feedback BJT ampli er is shown in Fig 25a The input variable is the voltage 111 and the output variable is the voltage 122 The feedback is from 23992 to 23992 to the emitter of Q1 Because the feedback does not connect to the input node the input summing is series Because the feedback does not sample the output voltage the sampling is series That is the feedback network samples the current in series with the outpu Solve for the transconductance gain iegUl the voltage gain 122111 the input resistance RA and the output resistance RB Assume 100 hr 25k9 Oz 51 Te agm 7 0 0 Ti 0 VT 25 mV R1 100 9 R2 lkfl R3 20 k9 and R4 10 k9 Figure 25 a Ampli er circuit b Circuit with feedback removed The circuit with feedback removed is shown in Fig 25b The circuit seen looking out of the emitter of Q1 is replaced with a Thevenin equivalent circuit made with respect with 23992 The output current 23992 is proportional to this current ie 23992 04252 A test voltage source 1 is added in series with the output to solve for the output resistance The resistance seen by the test source is labeled Rb For the circuit with feedback removed we can write Us 11 ic2R2 iel lee G1 m ial Otiel ibl 2 21 1 R3 390th ZalRS 222 G2 111 i Uth G2 T 2 Te 292 04292 7 92 R4 9 1 The equations can be solved algebraically or by a ow graph The ow graph for the equations is shown in Fig 26 The determinant is A 1763an 7R3gtlt 7G2gtltagtlt 7R2 1G1gtltagtltR2gtltG2gtltagtltR2 1181 ib1 1 1 ve ie1 a 5 v rb2 ie2 32 v1 vt G1 ic1 R2 02 X icZ R2 Figure 26 Signale ow graph for the equations The transconductance gain is 22 G1XO gtltR3gtltG2 111 A Glxangng 1G1xaxR3xG2gtltagtltR2 This is of the form I 292 A v1 1 Ab Where A and b are given by A G1gtltagtltR3gtltG2 1 gtlt gtlt R gtlt 1 a mR1R2 3 r2R4 09117mS b OLRQ 19819 Notice that the product Ab is dimensionless and positive The latter must be true for the feedback to be negative Numerical evaluation of the transconductance gain yields 239 A 2 0325 ms 111 A The voltage gain is given by v 239 v A 2i2gtlt 2 gtlt7R47325 v1 v1 292 A The resistances RA and R3 are given by 71 71 RAZUE Ax1 rR1R2602kn 1 v A RB Rb 7 R4 HR4 6513k9 23922 71 Gm2 71 Rb A X R4r22868kn 22 SeriesSeries Exalnple 4 A seriesseries feedback BJT ampli er is shown in Fig 27a The input variable is the voltage 111 and the output variable is the current 23952 The feedback is from 23952 to 23992 to the gate of J1 The input summing is series because the feedback does not connect to the same node that the source connects The output sampling is series because the feedback is proportional to the output current 23952 Solve for the transconductance gain 23952121 the voltage gain 112121 the input resistance RA7 and the output resistance RB For J17 assume that gml 0001 S7 731 9amp1 100097 and 701 00 For Q2 assume 2 1007 7 52 25 k97 a2 Q 1 Q 7 92 042ng 7 02 07 752 07 VT 25mV The resistor values are R1 1k l7 R2 10 k97 R3 1k l7 R4 10 k97 R5 lkfl7 and R5 10 k9 62 R5 R3 39 R3R4R5 39 M Figure 27 a Ampli er circuit b Circuit with feedback removed The circuit with feedback removed is shown in Fig 27b The circuit seen looking out of the emitter of Q1 is replaced with a Thevenin equivalent circuit made with respect with 23992 The output current is proportional to this current7 ie 23952 04223992 Because 7 02 07 the feedback does not affect the output resistance seen looking down through R5 because it is in nite For a nite 7027 a test voltage source can be added in series with R5 to solve for this resistance It would be found that a nite 7 02 considerably complicates the circuit equations and the ow graph For the circuit with feedback removed7 we can write R5R3 ldl gmlve Us 122 i 11 390th Zle2 222 G11th R3 R4 R5 1 R2 G 7quot 7 239 ai 1 732 RSH R3 R4 22 1 g 22 02 2 2 The equations can be solved algebraically or by a ow graph The ow graph for the equations is shown in Fig 28 The determinant is RSRS R3 R4 R5 RSRS R3 R4 R5 A 17gm1X7R2XG1X 1gm1gtltR2gtlt G1gtlt 1801 1 ve 9 R2 G1 ie2 a2 v1 Ic2 d1 Vin R5 R3 R3R4R5 Figure 28 Signale ow graph for the equations The transconductance gain is 23992 7 ilxgmlxiRnglxag v1 9m1gtltR2gtltG1gtlt042 R5R3 R3R4 R5 gml gtlt R2 gtlt G1 X 042 R5R3 1 gtlt gtlt R3R4R5 042 1gm1gtltR2gtltG1gtlt 1gm1XR2XG1Xa2 This is of the form I 22 A v1 1 Ab Where A and b are given by gmlngxGlxag gtlt R gtlt gtlt a 9 2 w R5H R3 34 2 9516 mS R5R3 b gtlt R3 R4 R5 Notice that the product Ab is dimensionless and positive The latter must be true for the feedback to be negative Numerical evaluation of the transconductance gain yields 12 g 5284ms i 84179 a2 U1 The voltage gain is given by v 239 v A 2i2gtlt 2 gtlt 7R575284 v1 v1 292 A The resistances RA and R3 are given by 71 72 1 A RA RlH vlc R1H g1 R1H g 1 6439 m RB R510k 2 SeriesSeries Exalnple 5 A serieseseries feedback BJT ampli er is shown in Fig 29 The input variable is the current 2391 and the output variable is the current 23992 The feedback path is the path from 23992 to 23992 to 23993 to 23903 to the emitter of Q1 The input summing is series because the feedback does not connect to the input node The output 24 sampling is series because the feedback is proportional to the output current 23992 and not the output voltage 122 Solve for the current gain gain 239922391 the transresistance gain 1222391 the input resistance RA and the output resistance RB Assume 100 hr 25k9 gm TW Oz 51 Te 049er7 To 00 7 75 0 VT 25mV The resistor values are R1 1kQ R2 1009 R3 10k9 R4 1009 R5 1kQ and R5 10 k9 Figure 29 Ampli er circuit The circuit With feedback removed is shown in Fig 30 The source is replaced With a Thevenin equivalent circuit consisting of a voltage 11 ilRl in series With the resistor R1 This is necessary for the feedback analysis to conform to convention for series summing at the input The circuit seen looking out of the emitter of Q1 is replaced With a Thevenin equivalent circuit made With respect With 23993 The latter is proportional to the output current 23992 The R3 relation is or X X or R3 R4 Tea Ei x 2 23922 23923 13992 23922 Note that 793 in this equation is the smallesignal resistance seen looking into the emitter of Q3 Figure 30 Circuit With feedback removed 25 For the circuit With feedback removed7 we can Write 1 R i Us v1 Z93132 lei Give G1 m 7121 Te 291 04121 lbi 1 R5 390th chRB 222 G2 U1 UM G2 m 722 1 5 T TE 7 7 R3 7 Z112 04222 123 i 202 R3 R4 Te 203 i 04223 1 ve Tel ic1 V le ieZ G2 v1 v r G1 D i quotR6 GZ R2 01 ib1 ic3 102 or 39e3 R3 R3R4re Figure 31 Signale ow graph for the equations The equations can be solved algebraically or by a ow graph The ow graph for the equations is shown in Fig 31 The determinant is R3 A 17Ggtlt gtltinti gtlt gtlt gtltR 1 a 5 2 a R3R4re a 2 R3 1Ggtlt gtltRgtltGgtlt gtlt gtlt gtltR 1 a 5 2 a R3R4re a 2 7335 The transconductance gain is 23992 7 1gtltG1gtlt01gtlt7R5gtlt7G2 v1 7 GlxaxRBXGg R3 1Ggtlt gtltRgtltGgtlt gtlt gtlt gtltR 1 a 5 2 0 R3R4TE 0 2 This is of the form I 292 A 111 1Ab Where A and b are given by A GlxaxRBXGg 1 gtlt gtltRgtlt 1 a T9121R2 6 T9122R5 6543mS R b 3 ax gtltagtltR 9682 Z R3 R4 r 2 Notice that the product Ab is dimensionless and positive The latter must be true for the feedback to be negative Numerical evaluation of the transconductance gain yields 39 A 22K892ms 3901 26 The current gain is given by 239 239 v A i x xR1s92 21 v1 21 A The transresistance gain is v 239 v A Rm2i2gtlt2 gtltR1gtlt7R57892k9 2391 2391 292 A The resistances Ba and RA 71 1 G Ra A gtlt R1 2 1 R2 1133kn 39Ubl RA Ba 7 R1HR1 99129 21 71 v2 v2 39Ubl A 1 R 7990 vbl Z1gtltZ1 AX 1gtltRA The resistances Rb and R3 are 2 71 G 71 Rb A X 92 R5 1098k9 RB Rb 7 R5 HR5 88959 The voltage gain is ShuntSeries Example 1 Figure 32a shows the ac signal circuit of a shunteseries feedback ampli er The input variable is 211 and the output variable is 239d2 The input signal and the feedback signal are applied to the source of M1 A test voltage source 2 is added in series with the output to calculate the output resistance Rb For the analysis to follow convention7 the input source consisting of 211 in series with R1 must be converted into a Norton equivalent This circuit is the current v1 R1 in parallel with the resistor R1 Fig 32b shows the circuit with feedback removed and the source replaced with the Norton equivalent A test source 2 is added in series with the output to calculate the resistance Rb The feedback at the source of M1 is modeled by a Norton equivalent circuit 2cm in parallel with the resistor R4 The feedback is from the output current 2cm to the source of M1 The circuit values are gm 0001 S7 7 s gLl 1k 27 7 0 00 R1 10k 27 R2 20k 27 R3 1k 27 R4 1k 27 and R5 1k9 The following equations can be written for the circuit with feedback removed 2391 1131 Z39aRc 23922 2391 Z39ct2 Ra R1 HR4HTsl Z39dl gmlvsl 1 239Gv G 22272 v 7239R d2 7722 b 7722 T32 RS b 2 292 292 d1 2 The current in is the error current The negative feedback tends to reduce 2a7 making A 0 as the amount of feedback becomes in nite When this is the case7 setting in 0 yields the current gain 2d221 71 Although the equations can be solved algebraically the signale ow graph simpli es the solution Fig 33 shows the ow graph for the equations The determinant of the graph is given by A 1 7 RC gtlt igm1gtlt 7R2gtlt 71gtlt Gmg gtlt 1 The current gain is calculated with v 0 It is given by 233 Ra gtlt igm1gtlt 7R2 gtlt 71gtlt Gmg 2391 A R HR H gtlt gtlt R gtlt 1 7 7 1 4 73931 gm 2 T32R3 7 1 1 R R 1 agtltgm1gtlt 2gtltT32R3gtlt 27 Rb Rb R2 W R3RB R2 W RERB v2 v2 ud1 idZ R0 i ll M11 1 M2 gtvs1 id1 IdZ v31 Figure 32 a Ampli er circuit b Circuit With feedback removed Figure 33 Flow graph for the equations This is of the form 2392 7 A 2391 7 1 Ab where 1 A BC gtlt igm1gtlt 7R2gtlt 71gtlt Gm2 7 R1HR4Hrsl gtlt gml gtlt R2 gtlt 703333 732 R3 1 71 Note that Ab is dimensionless Numerical evaluation yields id2 25 X 10 3 70 692 2391 1 1000 X 25 X 10 3 7 The voltage gain is given by 1 22x2x22x x7R307692 v1 21 11 2d2 21 R1 The resistance Ra is calculated with 122 0 It is given by R R R 1113 KC 1H W 76929 21 1 1 R R X agtlt9m1gtlt 2gtltT32R3 Note that the feedback tends to decrease Ra The resistance RA is calculated as follows RA R1 R1 7 Rf 1 1083k9 The resistance Rb is calculated with 2391 0 It is given by Rb a U1 Note that the feedback tends to increase Rb The resistance RE is calculated as follows 71 1 Ab 732 R3 8667k9 RB Rb 7 R3 1le 88469 ShuntSeries Example 2 A shunteseries feedback BJT ampli er is shown in Fig 34a The input variable is the voltage 111 and the output variable is the current 23992 The feedback is from 23992 to 23992 to the source of M1 The input summing is shunt because the feedback connects to the same node that the source connects The output sampling is series because the feedback is proportional to the output current 23992 Solve for the voltage gain 112121 the input resistance RA and the output resistance RB For M17 assume that gml 0001 S7 731 9 1000 Q and 701 00 For Q27 assume 2 1007 7W2 25ku7 042 2 1 2 7 92 042gm27 7 02 07 T22 07 VT 25mV The resistor values are R1 10k 27 R2 100k 27 R3 100k 27 R4 10k 27 and R5 1k9 The circuit with feedback removed is shown in Fig 34b The source is replaced with a Norton equivalent circuit The current 2391 is given by 11 7 E The circuit seen looking into R2 from the 1231 node is replaced with a Norton equivalent circuit made with respect with 23902 The output current is proportional to this current7 ie 23902 04223992 A test voltage source 1 is added in series with 23992 to calculate the resistance Rb For the circuit with feedback removed7 we can write 2391 R U31 ZaRa la 21 Willi92 Ra R1R2 R4 11731 ldl gmlvsl 390th llea 29 Figure 34 a Shunteseries ampli er b Ampli er With feedback removed 1h 1 I R3 2 G v 7 G 7 e2 1 tb2 Rd 1 Mg R5 22 1 Z The equations can be solved algebraically or by a ow graph The ow graph for the equations is shown in Fig 35 The determinant is 722 Rd R5 T92 Za2 042122 7R4 A 7 171XRCXgm1XR3XG1Xa2Xm 1R gtlt gtltR gtltG gtlt gtlt R4 c m a 9 1 3 1 2 R2R4 5025 1 1 id vs1 id1 v1b2 ie2 Rd i1 v r RC gm1 R5 G1 a iCZ i R2R4 Figure 35 Signale ow graph for the equations The current gain is 22 RaxgmlngxGl 2391 A 7 RaxgmlngxGl R4 1 R R G axgmlx 3gtlt 1gtlt042gtltR2R4 1 R R R R 7 2 4HTs1gtltgm1gtlt 3gtltT 2R4gt 7 1RHRRH gtlt gtltRgtlt 1 X X R4 1 2 4 7 31 gml 3 Mg R4 0 2 R2 R4 30 This is of the form 2393 7 A 2391 7 1 Ab where A and b are given by A RaxgmlngxGl 1 R111 R2 134 11731 X gml gtlt R3 X m 4475 R4 b 7 042 X m 7 009 Notice that the product Ab is dimensionless and positive The latter must be true for the feedback to be negative Numerical evaluation of the current gain yields 23992 A 890 2391 A The resistances Ra and RA are 1231 RC R 1 939 a 2391 A 7 RA R1 R1 7 Rf 1 1013kn The resistance Rb and R3 are 712 1 1 1 1 Rb ARd1012k9 v XE RB Rb 7 R5 HR5 90139 The voltage gain is given by 122 2392 112 2391 A 1 ligtltlgtlt gtltR2gtlt 890 v1 21 222 11 A B1 ShuntSeries Example 3 A shunteseries feedback BJT ampli er is shown in Fig 36a The input variable is the voltage 111 and the output variable is the current 23902 T e eedback is from 23902 to 23992 to 23903 to the emitter of Q1 The input summing is shunt because the feedback connects to the same node that the source connects The output sampling is series because the feedback is proportional to the output current 23992 Solve for the voltage gain 112111 the input resistance RA7 and the output resistance RB Assume 1007 m 25 k97 a l Te Ozgm 7 0 07 7 75 07 VT 25mV The resistor values are R1 R3 1k 2 and R2 R4 R5 10kg The circuit with feedback removed is shown in Fig 36b The source is replaced with a Norton equivalent circuit consisting of the current 1 1 7 R1 in parallel with the resistor R1 The feedback is modeled by a Norton equivalent circuit consisting of the current 23993 Because 7 03 07 the output resistance of this source is an open circuit The output current is proportional to this current Because 7 02 07 the feedback does not affect the output resistance seen looking down through R5 because it is in nite For a nite 7027 a test voltage source can be added in series with R5 to solve for this resistance It would be found that a nite 7 02 considerably complicates the circuit equations and the ow graph 2391 Figure 36 a Ampli er circuit b Circuit With feedback removed For the circuit With feedback removed7 we can Write 13992 la 21 i 193 1121 ZaRb Rb RlHRzHTel 191 gmlvel 292 52291 222 a 2 1 R4 39Utb3 222134 223 letb3 G1 Teg Tea 193 043123 723 R3 1 g The equations can be solved algebraically or by a ow graph The ow graph for the equations is shown in Fig 37 The determinant is A 17be gmlxi lxixR lelxagxil a2 1Rbgtltgm1gtlt 1gtltigtltR4gtltG1gtltOz3 a2 8587 1 IC ve1 icl CZ n391 Rb gm1 82 1 01 2 06 31 R4 103 ie3 vtbl ieZ Figure 37 Signale ow graph for the equations The transconductance gain is 22 7 1gtltRbgtlt79m1gtlt7 2 Z391 Rb gtlt gml X 52 1Rbgtltgm1gtlt 2gtlt gtltR4gtltG1gtlta3 a2 Rb gtlt gml X 52 1 1begm1x 2gtlt a XR4XG1xa3 2 This is of the form I 292 A 2391 1 Ab where A and b are given by A Rb gtlt gml X 52 RlHRzHTel gtlt gml X 52 9639 1 1 1 b R G R 8899 an 4gtlt 1Xa3 an 4gtltT3R3gtlta3 Notice that the product Ab is dimensionless and positive The latter must be true for the feedback to be negative Numerical evaluation of the transconductance gain yields 23992 A 0112 2391 A The voltage gain is given by 39 39 1 A 22X2X2 X X7R571122 U1 U1 2391 192 B1 A The resistances Ra7 RA7 and R3 are given by R RaXb00289 RAR1R17R1 1111lt 2 RBR510k Z ShuntSeries Example 4 Figure 38a shows the ac signal circuit of a shunteseries feedback ampli er The input variable is 111 and the output variable is idg The input signal and the feedback signal are applied to the gate of M1 For the analysis to follow convention7 the input source consisting of 111 in series with R1 must be converted into a Norton equivalent The feedback is from the output current idg to the source of M2 and to the gate of M1 The circuit values are gm 0001 S7 73 9 1k l7 7 0 07 R1 1k l7 R2 100k 27 R3 10 k97 R4 1k 27 R5 1k 27 and R5 1009 The circuit with feedback removed is shown in Fig 38b The source is replaced with a Norton equivalent circuit consisting of the current 1 1 21 7 R1 in parallel with the resistor R1 The feedback is modeled by a Norton equivalent circuit consisting of the current klidg The output current is proportional to this current Because 7 02 07 the feedback does not affect the output resistance seen looking up from signal ground into the lower terminal of R3 because it is in nite For a nite 7027 a test voltage source can be added in series with R3 to solve for this resistance It would be found that a nite 7 02 considerably complicates the circuit equations and the ow graph 33 Figure 38 a Ampli er circuit b Circuit With feedback removed The following equations can be Written for the circuit With feedback removed R5 in i1 klidg k1 m 1291 iaRa Ra R1 HRb Rb R5 R5 5 6 idl gmlvgl id2 G1 1amp92 UtsZ Utgz ilez UtsZ k21291 R 1 kg 5 G R R R R R5R6 1 TsZ l RtsZ 2 4 5 6 The current in is the error current The negative feedback tends to reduce in making A 0 as the amount of feedback becomes in nite When this is the case7 setting in 0 yields the current gain idgil 71161 Although the equations can be solved algebraically the signale ow graph simpli es the solution Fig 39 shows the ow graph for the equations The determinant of the graph is given by A 17Raxgm1X7R2XG1Xk1 1Ragtltgm1gtltR2gtltG1gtltk1 k1 RC v 1 id1 v192 i1 id2 1 1c gm1 R2 G1 k2 G1 v rsZ Figure 39 Signale ow graph for the equations The current gain is given by z RaxgmlxiRngl 2391 A 7Raxgm1xR2x 1 732 R4 R5HR6 1 1 7 R R 7k Xgml X N mR4R5HR5 M 1 This is of the form zd2 7 A 2391 1Ab 34 where l 732 R4 135 le b 7161 70909 A 7 RC gtlt gml gtlt R2 gtlt 72502 Note that Ab is dimensionless Numerical evaluation yields E 72502 71054 2391 1 72502 gtlt 70909 The voltage gain is given by 1 22X2X2Zf xx73371054 v1 21 v1 M2 21 R1 The resistance Ra is 1131 RC R1 R5 R6 R 2203 Z 2391 A A Note that the feedback tends to decrease Ra The resistance RA is RA R1 R1 7 Rf 1 102am The resistance R3 is RB R3 10 k9 This is not a function of the feedback because 702 has been assumed to be in nite ShuntSeries Example 5 Figure 40a shows the ac signal circuit of a shunteseries feedback ampli er The input variable is 111 and the output variable is idg The input signal and the feedback signal are applied to the base Q1 For the analysis to follow convention7 the input source consisting of 111 in series with R1 must be converted into a Norton equivalent The feedback is from the output current 23992 to the current 23992 to the current 23993 to the current 23993 The resistor values are R1 lkfl7 R2 10 k97 R3 10 k97 and R4 10 k9 Assume 1007 m 25k97 a l Te Ozgm 7 0 gt07 Ti 07 VT 25mV RA R1 vb1 Figure 40 a Ampli er circuit b Circuit with the the source replaced with a Norton equivalent The circuit with feedback removed is shown in Fig 40b The source is replaced with a Norton equivalent circuit consisting of the current 3901 i 1 R1 in parallel with the resistor R1 The feedback is modeled by a Norton equivalent circuit consisting of the current 23993 The output current is proportional to this current Because 7 02 07 the feedback does not affect the output resistance seen looking up from signal ground into the lower terminal of R4 because it is 35 in nite For a nite 7027 a test voltage source can be added in series with R4 to solve for this resistance It would be found that a nite 7 02 considerably complicates the circuit equations and the ow gra The following equations can be written for the circuit with feedback removed la Z1 Za3 vb1 laRb Rb RlllTwl 191 gmlvbl Utb2 ZalRa 122 G11th G 1 R3 1 T 2 T22 192 042122 123 122 193 043123 T 2R2T93 3 1 82 The current in is the error current The negative feedback tends to reduce in making A 0 as the amount of feedback becomes in nite When this is the case7 setting in 0 yields the current gain idgil 71161 Although the equations can be solved algebraically the signale ow graph simpli es the solution Fig 41 shows the ow graph for the equations The determinant of the graph is given by A 17begm1xiR3xG1x1xa3x1 1Rbgtltgm1gtltR3gtltG1gtlta3 2888 1 id vb1 ic1 vtb2 ie2 i1 n39cZ 11 Rb gm1 R3 G1 1 1x2 n39c3 x3 ie5 Figure 41 Signale ow graph for the equations The current gain is given by 2392 1gtltRbgtltgm1gtlt7R3gtltG1gtlta2 Z391 7begm1 XR3gtlt G1 xag a 1 7Rb gtlt gml gtlt R3 gtlt G1 gtlt 042 gtlt 7 3 This is of the form id2 7 A 2391 7 1 Ab where A 7Rb gtlt gml gtlt R3 gtlt G1 gtlt a2 72788 7 7 1 042 Note that Ab is dimensionless and the product is positive The latter is a result of the feedback being negative Numerical evaluation yields idg 72788 70965 2391 1 72788 X 71 The voltage gain is given by U2 idz 2391 U2 idz 1 39gtlt 3939 gtlt gtlt7R49654 v1 21 11 2d2 21 R1 The resistance Ra is a Eamp Mm 2391 A A 24749 Copyright 2008 W Marshall Leach Jr Professor Georgia Institute of Technology School of Electrical and Computer Engineering Oscillators Conditions for Oscillations Figure 1 shows the block diagram of an ampli er 145 with a feedback network 115 that can be connected from its output to its input by ipping the switch from position A to position B In position A the switch connects the feedback network to a test signal source Vt The transfer function from V to V2 is V V b 5 A 5 Let 5 jw Suppose there is some frequency at which WVt 110 1f the test signal source puts out a sine wave at this frequency the ampli er output will be a sine wave of the same amplitude and phase 1f the switch is changed to position B the signal input to the feedback network will not change In this case the output signal from the ampli er drives its input and the circuit is a stable oscillator Figure 1 Block diagram of an oscillator 1f gt 1 at the frequency for which VbV 0 O the circuit will oscillate when the switch is closed and the amplitude of the output voltage will increase with time until the ampli er overloads or clips 1f lt 1 at the frequency for which VaVZ39 0 the amplitude of the output voltage will decrease or damp out with time until the output becomes zero Thus the condition for a stable output sine wave is the loop gain must be unity at the frequency for which its phase is 0 A means for varying the gain so as to maintain a unity gain is usually incorporated into practical oscillator designs A classic example is the vacuum tube Wien Bridge Oscillator that was the founding product of HewlettiPackard Corp A simpli ed version of the circuit is shown in Figure 2 The designers used a small light bulb shown in the gure to regulate the gain The temperature coe icient of the lament in the bulb caused its resistance to change when the current through it changed This resistance change varied the gain of the ampli er to maintain a loop gain of unity Wien Bridge Oscillator Figure 3 shows an opiamp Wien Bridge Oscillator circuit It is based on a network originally developed by Max Wien in 1891 In order to calculate the loopigain transfer function the input to the feedback network is broken at the two slant lines For an ideal op amp A 5 is a constant and is given by Va RF A K 5 V R3 1 Pairquot Frgdbucli imal im 69 EH20 V2 F 1 1 5 iiquot 1 RN 323 M32 gin n2 RE 39H umv ll 1 i no u 1 m i awn INN rumor I39Rl m w e we CD EIDIh In 1 Inquot 6 Figure 2 Simpli ed circuit diagram of the HewlettiPackard vacuum tube oscillator The transfer function 115 for the feedback network is 115 E 2 025 7 1 R2025 7 V0 7 1 1 7 1R1C15 R2 R1 015 Rgllcgs 015 l 1 R2025 Figure 3 Opiamp Wien Bridge Oscillator Simpli cation yields b 5 R2015 3132010252 R101 R202 R201 5 1 Thus the overall loopigain transfer function is Va R2015 Kb K V 5 R1R2010252 R101 R202 R201 5 1 For 5 jw this becomes Va 7 K jWR201 VJ T 1 W231320102 110 3101 R202 R201 It can be seen that the angle ofthis transfer function is 0 o if 17w2R1RgCng 0 or equivalently L R1R20102 At this frequency the transfer function is given by Va 7 K R201 VJ 7 3101 R202 R201 If this is equal to unity the circuit will oscillate with a stable output when the loop is closed The circuit is often designed with R1 R2 R and Cl Cg C In this case the frequency of oscillation is given by 7 1 w 7 E and the loopigain at this frequency is V0 7 K 70 7 3 It follows that K 3 is the condition for stable oscillations at this frequency This requires the condition RF 2R3 A method that is often used to regulate the gain for stable oscillations is to connect a resistor in series with a JFET in parallel with R3 The JFET is operated in the triode or linear mode A diode detector is used to generate a dc voltage that varies with the amplitude of the output oscillations This dc voltage is applied to the gate of the JFET to vary its resistance The varying resistance controls the gain of the circuit Wikipedia Reference httpenwikipediaorgwikiWien7bridgeioscillator Phase Shift Oscillator The phase shift oscillator makes use of an ampli er with an inverting gain ie its gain is negative A negative gain is equivalent to a phase shift of i180 For the circuit to be an oscillator the feedback network must introduce an additional phase of i180O so that the total phase is 00 or i360 A phase shift of 180O can be obtained by cascading two RC highipass lters However at the frequency where the phase shift is exactly 180 0 the gain of the lters is zero By cascading three RC highipass lters there is a frequency at which the phase shift is 180O and the gain is nonizero Such a circuit is shown in Figure 4 The gure shows the feedback loop broken so that the loop transfer function can be written It is given by Ei x 2 VJ W V V where E 7 7 RF 7 7 R05 V1 LR R 1RCs Cs Figure 4 Phaseshift oscillator Admittance voltage division can be used to solve for WVa and These are given by V Cs 1 1 Va CsE 1 R RCs1RCs 1 3305 3052 Va 7 Cs 7 1 1 a Cs 1 1 31 1 E 1 3 05 305 1 3305 3052 1 5305 6 3052 3053 It follows that is given by 2 V0 7 RF ROS ROS 1 ROS 305 1 3305 305 Va 3 1 305 1 3305 3052 1 5305 6 3052 3053 7 3F 3053 if 1 5305 6 3052 3053 For 5 jwo Where we is given by 1 7 630 we the transfer function reduces to V0 RF 7139 lxE 3 3F 16 3F 1 70 R 1j51 717j1 3 R 5U f For the loopigain to be unity7 RF must have the value 3F 293 BJT Differential Amplifier Example X Rpltxygt y Xy RC 20000 Vp 20 rX 20 Function for calculating parallel resistors RB 1000 RE 1oo 1Q o001 3 vm 2o VBE 065 vT o025 3499 x 13 r0 soooo There are two ac solutions one for the second input zeroed and one for the first input zeroed By superposition the total solution would the be sum ofthese two To keep Mathcad happy all source voltages are taken to be equal to 1 V so that the output voltage is equal to the voltage gain In general the output voltage is equal to the voltage gain multiplied by the source voltage DC Bias Solution Assume the do value of the sources is zero I Q 394 IE1quot IE1 53910 IE2quot1E1 VCIIVp aIE1RC VCI1005 I E1 7 3 VB1 RB VBI 7 2510 1H VCBl VCl VBl VCBl 100525 Thus active mode Same for Q2 V T 1quote1391 1quote150 1quote239re1 E1 R r i B X i i i r 61 rel r 61 7 551 r e2 r el 13 AC Solutions Circuit for the first output With the input equal to 1 the voltage gain is equal to the v 1 21 v 2 1 1 output voltage RC r0 1H 7 09989 V e200 39V 12 R Ve20c 39 C r 2ro e 1l3 r R 0 C rieZ 769015 1quotie2 1quot e239 r39 r RC 2 0 e thl V11 Rtbl RB Vtel V e200 Rtel 239RErie2 Rtel 2769015 101 R tel a r 0 T 3 G 39 G 2994110 mbl i i mbl r el Rtel r0RPr el Rtelgt r el r0 X x 3 G 39 G 2997510 mel i i mel r el Rtel r0RPr el Rtelgt r R r R rid rid 294161 IR tel r el R tel Voltage gain from first input to first output 7 3 1 also Gmb1vtb1 1 else 7 2994110 Vol 39iclsc39RPltricl RCgt Avl Vol Avl 560705 This is the voltage gain from the first input to the first output The gain from the second input to the second output is the same Voltage gain from the second input to the first output 3 iclsc 39Gme139V tel iclsc 23999423910 Vol 39iclsc39RPricl RCgt Av2vol Av2 560725 This is the voltage gain from the second input to the first output The gain from the first input to the second output is the same v 01 560705vi1 560725v i2 This is the sum ac output from Q1 v 02 560705vi2 560725v n This is the sum ac output from Q2 Differential input resistance 7110 2 RB szf 7quotin RB Tia Wm 2 39Rtel39Rc rim rx1i339ltrelRPRte1aroRcgtgt Rte1r0RC 4 ribl 4953910 ribz rib1 7 5 rid 2RBrib1rib2 rid71013910 CommonMode Rejection Ratio Avl 7 560705 AV2 560725 Let us take the output from the collector ofthe first transistor Because neither 3 nor r0 is infinity the two voltage gains are not equal This causes the CMRR to be non infinite We calculate it below V vidi1 1d 39Vid Vil quotT Vi2 39 Vol Av139vi1Av239Vi2 Advol A d 560715 This is the differential voltage gain vicm 1 1 Vil Vicm Vi2vicm V01 Av139vi1Av239Vi2 A V cm 01 Acm 199380163 This is the common mode voltage gain A CMRR d CMRR 2812339104 A cm CMRRdB 20logCMRR CMRR dB 889811 If R Q the ac resistance of the current source is not infinity the CMRR would be lower CommonSource Amplifier Example Kprime0002 w1 L1 VTO175 A 0016 Xo vplus 24 vminus 24 R15v106 R21v106 RD10v103 RS3v103 R3 50 RL 20v103 RS 5v103 Rpxy W xy V 9quot out R 1 RD A R Cl 0 S R L U S R3 C V I 3 DC Bias Solution V R 1 RD R2 RS V R V vR 39 plus 2 minus 1 39 V GG 16 V SS V V GG R1 R 2 minus R SS R S V1VGG VSS VTO V1 625 We neglect the Early effect ie set A 0 to solve forthe drain bias current W K Kprimef 2 3 v 1 2vav VR 1 1 165510 2 1 s D 2VKVR S VDVp1uS IDVRD VD7454 VSVmnusIDvRS VS19036 VDSVD VS VDS26491 VGSVGG VS VGS3036 VGS VTO1286 Because VDS gt VGS VTO the MOSFET is in the active or saturated state Here is an exact solution for the drain current Note that MathCad requires numbers for everything except the variable being solved for The drainsource voltage in the equation is 48 1Dv13v103 I 1 D 3 3 2 410 v10016vlt48 1Dv13v10gtv3000 2 4v10393v1 0016vlt48 IDv13v103gtv625v3000 1 390017157743653358533060 This is the exact solution for ID including the Early effect We will use the approximate solution for the ac analysis below ID 0017157743653358533060 v 00 3567 This is the percentage error in neglecting the Early effect in 0017157743653358533060 t solving for the drain curren Now for the ac solution W K quotKpr ne39f39lt1 vaSgt K 2848010 3 gm ZVKID gm 30710 3 1 rs rs 325758 gm rs r S ris 325758 No body effect because the body lead is connected to the 1136 source lead This is equivalent to setting X 0 in the equations 1 l V r0 DS r05378104 Rts39 RPRS R3gt Rts 493918 ID R ridr0v1ts Rts rid6195104 ris v 5 1 This makes the gain equal to v O R R R vtg vva vtg 0994 RSRPltR1R2gt 3 R RPltRSRPltR1R2gtgt Rtg49710 3 th RPltRDRL th666710 The BJ T BJ T Device Equations Figure 1 shows the circuit symbols for the npn and pnp BJTs 1n the active mode the collector7base junction is reverse biased and the baseemitter junction is forward biased Because of recombina7 tions of the minority and majority carriers the equations for the currents can be divided into three regions low mid and high For the npn device the currents are given by Low Level UBE I 7 1 1 23 we 1 ltgt 20 5 exp 7 1 2 T Mid Level I 28 S exp 13 i 1 3 20 5 exp U51 7 1 4 T High Level F 4 1K UBE 20 5 E exp E 7 1 6 Where all leakage currents that are a function of 1203 have been neglected In the current equations 5 is the saturation current and F is the mid7level baseto7collector current gain These are functions of the collector7base voltage and are given by U U 7U 5150 1Vif Iso 1CEV ABE 7 1203 UCE UBE 5F Fo 1V A Fo 1V A 8 C E 119 ic l B lE B B 1E 1C E C P pnp Figure 1 BJT circuit symbols 1n the equations for 3 and i0 VA is the Early voltage and ISO and 310 respectively are the zero bias values of Is and The constant 71 is the emission coef cient or ideality factor of the baseemitter junction 1t accounts for recombinations of holes and electrons in the baseemitter junction at low levels Its value typically in the range 1 S n S 4 is determined by the slope of the plot of ln versus UBE at low levels The default value in SPICE is n 15 The constant 15E is determined by the value of i3 where transition from the lowilevel to the midilevel region occurs The constant 1K is determined by the value of i0 where transition from the midilevel to the highilevel region occurs Note that IS F ISO310 so that i3 is not a function of 1203 in the midilevel region The equations apply to the pnp device if the subscripts BE and CB are reversed Figure 2 shows a typical plot of i0 versus UBE for UcE constant The plot is called the transfer characteristics There is a threshold voltage above which the current appears to increase rapidly This voltage is typically 05 to 06 V In the forward active region the baseitoiemitter voltage is typically 06 to 07 V Figure 3 shows typical plots of i0 versus UCE for if constant The plots are called the output characteristics Note that the slope approaches a constant as UCE is increased 1f the straight line portions of the curves are extended back so that they intersect the UCE axis they would intersect at the voltage UCE iVA UBE iVA For UCE small UBE gt UcE and the BJT is in the saturation region Collector Currenl 720 I I BuseiEmlller Volloge UBE Figure 2 Typical plot of i0 versus UBE for UCE constant 39l Increasing B Colleclor Cu rrenl 020 l l Collec ror Emi r rer Vol rage 39UCE Figure 3 Plots of i0 versus UCE for if constant In the GummeliPoon model of the BJT the current equations are combined to write the general equations for if and i0 as follows UBE I so UBE I 7 1 7 1 9 3 SE leXplan 1 leXplvT 1 W 2 10 If Sq exp 7 1 10 where Kq is given by 1 Is UBE i0 K 71 1 11 1 2 41KexpVT IK Fig 4 illustrates typical plots of ln and ln i3 versus UBE where it is assumed that 1203 is held constant At low levels the i0 curve exhibits a slope m 1 while the i3 curve exhibits a slope m 171 where the value 71 15 has been used At mid levels both curves exhibit a slope m 1 At high levels the i0 curve exhibits a slope m 12 while the i3 curve exhibits a slope m 1 It follows that the ratio of 0 to i3 is approximately constant at mid levels and decreases at low and high levels mac and niB Figure 4 Example plots of ln and ln i3 versus UBE Current Gains Let the collector and base currents be written as the sum of a dc component and a smallisignal ac component as follows i0 C Q 12 i3 B i The dc current gain 8ch is de ned as the ratio of lg to 13 It is straightforward to show that it is given by F 3ch 14 1n C FISE IO 1 1 1IK IO ISISIK 1 Because F and 5 are functions of the collectoribase voltage VCB it follows that 3ch is a function of both IQ and VCB lf 1203 is held constant so that the change in i0 is due to a change in UBE the smallisignal change in base current can be written 4731347 8 C 7 is lb 7 le 7 BIC chl 26 7 Fac 15 3 where pac is the smallisignal ac current gain given by a C 1 late F l 21 I I 12 T1 1 C 1 M 1 C C K 7115 Is ISIK Note that pac is de ned for a constant 1203 In the smallisignal models it is common to de ne the smallisignal ac current gain with UCE constant 1e v05 0 This is de ned in the next section where the symbol 3 is used Typical plots of the two current gains as a function of IQ are shown in Fig 5 where log scales are used At low levels the gains decrease with decreasing Io because the base current decreases at a slower rate than the collector current At high levels the gains decrease with increasing Io because the collector current increases at a slower rate than the base current At mid levels both gains are approximately constant and have the same value In the gure the midilevel range is approximately two decades wide 619cm Fd c lgF39d c 5Fu 0 CurremL Gains I I I I I I I Collector Curren r C Figure 5 Logilog plots of 3ch and pac as functions of IC The emittericollector dc current gain odeC is de ned as the ratio of the dc collector current Io to the dc emitter current IE To solve for this we can write 1 3ch 1 IEIBIC 1ICIC 17 ch It follows that 0 ch IE 1 3ch Thus the dc currents are related by the equations IO FdCIB O chIE 19 O ch Bias Equation Figure 6a shows the BJT with the external circuits represented by Thevenin dc circuits If the BJT is biased in the active region we can write VBB VEE IBRBB VBE EREE C O ch CRBB VBE REE 20 ch 4 This equation can be solved for IC to obtain VBB VEE VBE 21 RBB pdc REE06ch It can be seen from Fig 2 that large changes in IQ are associated with small changes in VBE This makes it possible to calculate Io by assuming typical values of VBE Values in the range from 06 to 07 V are commonly used In addition7 3ch and 04ch are functions of IQ and VCB Midilevel values are commonly assumed for the current gains Typical values are pdc 100 and 06ch IO Figure 6 a BJT dc bias circuit b Circuit for Example 1 Example 1 Figure 61 shows a BJT dc bias circuit It is given that VJr 15 V R1 20 k9 R2 10 k9 R3 R4 3 m R5 R6 2 k9 Solve for 01 and 102 Assume VBE 07 V and 3146 100 for each transistor Solution For Q1 we have V331 VR2 R1 1352 R331 RlllR27 VEEl 71321354 IC2R4 de VEEl 07 and REEl 554 For Q27 W8 haVe V332 IE1R4 101R406de R332 R47 VEEZ 07 REEZ R6 Thus the bias equations are R2 02 Cl 101 V R V R R R R1 R2 3ch 4 BE 3ch lll 2 06ch 4 I I I Cl R4 VBE 02 R4 02 Re 06ch pdc 06ch These equations can be solved simultaneously to obtain 01 141 mA and 02 174 mA SmallSignal Models There are two smallisignal circuit models which are commonly used to analyze BJT circuits These are the hybrid77T model and the T model The two models are equivalent and give identical results They are described below Hybrid7r Model Let each current and voltage be written as the sum of a dc component and a smallisignal ac component The currents are given by Eqs 12 and 13 The voltages can be written UBE VBE U175 22 vCB VCB Web 23 1f the ac components are su iciently small i0 can be written BI C BI a BI C BI 4 7 7 C 7 lo 8VBE U175 8VCB Ucb 8VBE U175 8VCB Use U175 7 BIC BIC BIC 7 Use BVBE m U175 mike 7 gmvbe K 24 This equation de nes the smallisignal transconductance gm and the collectoriemitter resistance To From Eqs 8 and 10 it follows that To is given by BIC 1 KqISO 1 T0 7 BVCB 7 V A leXPUBEVT 1 M IO 25 To solve for gm we rst solve for BICBVBE Eqs 10 and 11 can be combined to write 12 VBE I CI 71 26 0IK s XPVT It follows from this equation that BICBVBE is given by BIC 7 IseXpVBEVT 7 7 7 27 The transconductance is given by BI BI I 1 I I I 1 gm C C 7 C C K s 7 28 BVBE 7 BVCB 7 VT 1 7 0 It is clear from Eq 9 that i3 is a function of UBE only We wish to solve for the smallisignal ac base current given by ib BIBBVBE 1255 This equation de nes the smallisignal ac baseiemitter resistance rquot vbib BIBBVBE71 Although Eq 9 can be used to solve for this we use a different approach The smallisignal ac collector current can be written 4 v 1 v v 20 9m i 9m l i m2 i 29 T0 T0 T0 To It follows from this equation that 1 9m vbe Faclb 30 T0 Thus hr is given by U2 Fac ib 9m 1740 The smallisignal ac current gain I is de ned as the ratio of i0 to ib with UCE constant ie v05 0 To solve for this we can write for i0 4 U U 4 U 20 gmvbe l i gmlbr lr l i ll l i 7 0 7 0 7 0 It follows from this that 3 is given by gm Fac gmr7rgm1TO Thus far7 we have neglected the base spreading resistance rm This is the ohmic resistance of the base contact in the BJT When it is included in the model7 it appears in series With the base lead Because the base region is very narrow7 the connection exhibits a resistance Which often cannot be neglected Fig 7a shows the hybrid77T smallisignal model With rm included The currents are given by U is Ti 34 i gmw t 35 U175 36 lb Tquot Where To gm7 and Tr are given above E E a b Figure 7 a Hybridi 39 model b T model The equations derived above are based on the GummeliPoon model of the BJT in the for ward active region The equations are often approximated by assuming that the midilevel current equations hold In this case7 3ch pac To gm7 rm and 3 are given by ch Fac F 37 V V CB A 38 C IcIs 1 C 7 z 39 gm VT T0 VT Fac VT z 40 Tquot 5 10 13 l I gmr lr E IC ch 41 B The three approximations in these equations are commonly used for hand calculations T Model The T model replaces the resistor rquot in series with the base with a resistor T5 in series with the emitter This resistor is called the emitter intrinsic resistance To solve for re we rst solve for the smallisignal ac emitteritoicollector current gain 04 In Fig 77 the current can be written 1 1 zquot Zb 1zg zgj 42 where 04 is given by l a i 43 25 1 3 Thus the current can be written 04239 44 The voltage Uquot can be related to as follows i ai r Ur Z1773K Eonr Farr 22 It follows that the intrinsic emitter resistance is given by V V Te1quotrquot TT 46 25 1 1 chIB IE where the approximation is based on Eqs 40 and 41 It is often used for hand calculations The T model of the BJT is shown in Fig 7b The currents in both the 7T and T models are related by the equations gmvr ib xi 47 SmallSignal Equivalent Circuits Several equivalent circuits are derived below which facilitate writing smallisignal lowifrequency equations for the BJT We assume that the circuits external to the device can be represented by Th venin equivalent circuits The Norton equivalent circuit seen looking into the collector and the Th venin equivalent circuits seen looking into the base and the emitter are derived Although the T model is used for the derivation7 identical results are obtained with the hybrid77T model Several examples are given which illustrate use of the equivalent circuits Simpli ed T Model Figure 8 shows the T model with a Th venin source in series with the base We wish to solve for an equivalent circuit in which the source connects from the collector node to ground rather than from the collector node to the B node The rst step is to replace the source with two identical series sources with the common node grounded The circuit is shown in Fig 9a For the circuit in Fig 9a7 we can write i R r 1251 7 1 Rtbmizrevtbiz fT m 713 48 Let us de ne the resistance r by iRtb me iRtb i Tm i T39lr I 51 49 r 1 r 1 ltgt Figure 9 a Circuit with the source replaced by identical series sources b Simpli ed T model With this de nition we is given by 4 I vs Utb 7 25745 50 The circuit which models this equation is shown in Fig 9b This will be called the simpli ed T model It predicts the same emitter and collector currents as the circuit in Fig 8 Note that the resistors R and m do not appear in this circuit They are part of the resistor rg Norton Collector Circuit The Norton equivalent circuit seen looking into the collector can be used to solve for the response of the commoniemitter and commonibase stages It consists of a parallel current source id and resistor no from the collector to signal ground Fig 10a shows the BJT with Thevenin sources connected to its base and emitter With the collector grounded the collector current is the short circuit or Norton collector current To solve for this we use the simpli ed T model in Fig 10b We use superposition of v and Ute to solve for 240090 With Ute 0 it follows from Fig 10b that We m i0 m 7 i ei TO Rte W Rte 04 7 51 TgRtellT0 T0Rte Figure 10 a BJT with Thevenin sources connected to the base and the emitter b Simpli ed T model With U 07 we have i mquot i m TO T5 0 5 5 el 5 TO T To r 7 We 06m Tl 52 Rte T llro TO r These equations can be combined to obtain ampa i 3 4 m mae memmm This equation is of the form icsc Gmwtb Gmevte 54 where Gmb aii LW 55 TgRtellT0 T0Rte Tg thellTO T0Rte 1 I I Gme om T5 04 TO rea 56 7 Rte T llro TO r F r Rtellro TO Rte The next step is to solve for the resistance seen looking into the collector with v Ute 0 Figure 11a shows the simpli ed T model with a test source connected to the collector The resistance seen looking into the collector is given by no vtic To solve for no we can write 7 7 e 20 7 0425 20 MO T Rte 20 L 1 7 i 57 T0TgllRte TgRte It follows that no is given by I R m U 7 T0 reH 5 58 Z liwmmmau The Norton equivalent circuit seen looking into the collector is shown in Fig 11b 10 Q csc Tic b Figure 11 a Circuit for calculating no b Norton collector circuit For the case 7 0 gtgt Rte and 7 0 gtgt r we can write ZC50 Gm UN 7 Ute where a G 60 m 7 l Rte The value of id calculated with this approximation is simply the value of ails where is calf culated with T0 considered to be an open circuit The term r0 approximations is used in the following when m is neglected in calculating MSG but not neglected in calculating no Th venin Emitter Circuit The Th venin equivalent circuit seen looking into the emitter is useful in calculating the response of commonicollector stages It consists of a voltage source 12500 in series with a resistor me from the emitter node to signal ground Fig 12a shows the BJT symbol with a Th venin source connected to the base The resistor Rte represents the external load resistance in series with the collector With the emitter open circuited7 we denote the emitter voltage by 12500 The voltage source in the Th venin emitter circuit has this value To solve for it7 we use the simpli ed T model in Fig 12b Rtb II 0900 a Figure 12 a BJT with Th venin source connected to the base b Simpli ed T model circuit for calculating 12500 The current can be solved for by superposition of the sources 1m and ails It is given by W Rte 0424 61 TgT0thT eTgT0th l 257 11 This can be solved for to obtain i Utb W 62 e TgT0106th T T0th1 The openicircuit emitter voltage is given by TO th 1 Threats1 63 Ueoc W i W We next solve for the resistance seen looking into the emitter node It can be solved for as the ratio of the openicircuit emitter voltage 12500 to the shorticircuit emitter current The circuit for calculating the shorticircuit current is shown in Fig 13a By superposition of and ails we can write Rte if TO T 1 7 04 Rte 4 4 Z550 ZeTO Ze e TO Rte TO Rte ETO thcl t 64 we 7O l Rte The resistance seen looking into the emitter is given by U R m do 7 TO t 65 Z4550 T Te rle T 70 T th 1 T The Th venin equivalent circuit seen looking into the emitter is shown in Fig 13b to Figure 13 a Circuit for calculating iesc b Th venin emitter circuit Th venin Base Circuit Although the base is not an output terminal7 the Th venin equivalent circuit seen looking into the base is useful in calculating the base current It consists of a voltage source 12500 in series with a resistor m from the base node to signal ground Fig 14a shows the BJT symbol with a Th venin source connected to its emitter Fig 14b shows the T model for calculating the openicircuit base voltage Because ib 07 it follows that 0 Thus there is no drop across rm and r5 so that 12500 is given by TO Rte Rte TO Rte The next step is to solve for the resistance seen looking into the base It can be calculated 66 Woe v5 Ute by setting Ute 0 and connecting a test current source it to the base It is given by m vbit Fig 15a shows the T circuit for calculating 125 where the current source it has been divided 12 vboc Rte Ute a Figure 14 a BJT with Thevenin source connected to the emitter b T model for calculating Uboc 39 into identical series sources with their common node grounded to simplify use of superposition By superposition of it and the two it sources we can write 4 Rt Rt vb mm 2 u m T5 Rtell To Rtel 7 lt 67 Rte l 7 0 This can be solved for m to obtain thRte 7 68 thT0Rte v m m 1 re lel m RM The Thevenin base circuit is shown in Fig 15b i t 39 vb39r 3t 55101 Figure 15 a Circuit for calculating 125 b Thevenin base circuit Summary of Models Figure 16 summarizes the four equivalent circuits derived above Example Ampli er Circuits This section describes several examples which illustrate the use ofthe smallisignal equivalent circuits derived above to write by inspection the voltage gain the input resistance and the output resistance of both singlestage and twoistage ampli ers Figure 16 Summary of the smallisignal equivalent circuits The CommonEmitter Ampli er Figure 17a shows the ac signal circuit of a commoniemitter ampli er We assume that the bias solution and the smallisignal resistances rig and T0 are known The output voltage and output resistance can be calculated by replacing the circuit seen looking into the collector by the Norton equivalent circuit of Fig 11b With the aid of this circuit7 we can write 120 7 mum fem mllth m 69 Tout Ticllth where Gmb and no respectively7 are given by Eqs 55 and 58 The input resistance is given by Tin Ru Mb 71 where m is given by Eq 68 Figure 17 a Commoniemitter ampli er b Commonicollector ampli er c Commonibase ampli er The CommonCollector Ampli er Figure 17b shows the ac signal circuit of a commonicollector ampli er We assume that the bias solution and the smallisignal resistances T13 and 7 0 are known The output voltage and output resistance can be calculated by replacing the circuit seen looking into the emitter by the Th venin equivalent circuit of Fig 13b With the aid of this circuit we can write U U Rte TO th 1 3 Rte U 72 0 50mm Rte T TO th 1 He Rte tb Tout TieHRte where we is given by Eq 65 The input resistance is given by Tin Ru Mb 74 where m is given by Eq 68 The CommonBase Ampli er Figure 17c shows the ac signal circuit of a commonibase ampli er We assume that the bias solution and the smallisignal parameters rig and T0 are known The output voltage and output resistance can be calculated by replacing the circuit seen looking into the collector by the Norton equivalent circuit of Fig 11b The input resistance can be calculated by replacing the circuit seen looking into the emitter by the Th venin equivalent circuit of Fig 13 with 12500 0 With the aid of these circuits we can write U0 724050 TicHth Gme TicHth Ute Tout 0 th Tin Rte We 77 where Gme no and mg respectively are given by Eqs 56 58 and 65 The CE CC Ampli er Figure 18a shows the ac signal circuit of a twoistage ampli er consisting of a CE stage followed by a CC stage Such a circuit is used to obtain a high voltage gain and a low output resistance The voltage gain can be written 2 X X X L W21 W21 25150 W22 Ue2oc Rt 2 Gmbl b TiclHRClN m m 78 where n22 is calculated with Rm ricl RCq The input and output resistances are given by Tin Rm W1 79 Ton Tie2HRte2 80 Although not a part of the solution the resistance seen looking out of the collector of Q1 is Rm RC1HT139b2 Figure 18 a CECC ampli er 00 Cascode ampli er The Cascode Ampli er Figure 1800 shows the ac signal circuit of a cascode ampli er The voltage gain can be written U0 Z0150 UteZ Z0250 U0 X 4 X X 4 W21 W21 20155 UteZ Zc2sc GmiTic1Gme2Tic2llth2 where Gmeg and n02 are calculated with Rteg n01 The input and output resistances are given by Tin Rm Tm Tout 17340le7102 The resistance seen looking out of the collector of Q1 is Riel n52 A second cascode ampli er is shown in Fig 19a where a pnp transistor is used for the second stage The voltage gain is given by i Z40150 X UteZ X Z40250 X U0 W21 W21 iclsc Utez ic2sc Gml Ticllchl Gme2 hwllthz The expressions for Tin and rout are the same as for the cascode ampli er in Fig 1800 The resistance seen looking out of the collector of Q1 is Riel Ralllneg The Differential Ampli er Figure 1900 shows the ac signal circuit of a differential ampli er For the case of an active tail bias supply the resistor RQ represents its smallisignal ac resistance We assume that the transistors are identical biased at the same currents and voltages and have identical smallisignal parameters Looking out of the emitter of Q1 the Thevenin voltage and resistance are given by RQ Utei U52ocm TO th 10 RQ 81 rgroth1 RQ REne 16 Figure 19 a Second cascode ampli er b Differential ampli er Riel RE Tie The smallisignal collector voltage of Q1 is given by vol 722150 Ticllth 7 Gmbvtbl 7 Gmevtel Ticllth Gmb Ticllth W21 R 1 R Gm TO tc 5 Q 33 eTgT0th1 TieRERQUm By symmetry7 1202 is obtained by interchanging the subscripts 1 and 2 in this equation The smalli signal resistance seen looking into either output is Tout thll ric where no calculated from Eq 58 with Rte RE RQH RE me Although not labeled on the circuit7 the input resistance seen by both vim and 12th is Tin rib A second solution of the diff amp can be obtained by replacing vim and 12th with differential and commonimode components as follows Wild Um Uicm 2 85 12 d W22 Uicm l l 86 where 12101 vim 712th and 12mm owl Um 2 Superposition of 12101 and 12mm can be used to solve for 1201 and 1202 With 12mm 07 the effects of vim own2 and 12th fol1 are to cause vq 0 Thus the vq node can be grounded and the circuit can be divided into two commoniemitter stages in which Riga RE for each transistor In this case7 120101 can be written iclsc 0101 Wm M gtlt v Gm inc R c 1d Um 201W tb1d d dH t 2 U i U GM 41001 Rte 87 By symmetry 120201 710101 With 12101 07 the effects of vim 12th 12mm are to cause the emitter currents in Q1 and Q2 to change by the same amounts lf RQ is replaced by two parallel resistors of value QRQ it 17 follows by symmetry that the circuit can be separated into two commoniemitter stages each with BMW RE QRQ In this case voucm can be written Z40150 X U01cm CmGmcm ficcm RC icm Utbucm 20150 Um T tU U01cm W21 W22 T 88 iriccmllRtC By Symmetry U02cm U0 Because Rte is different for the differential and commonimode circuits Gm no and m are different However the total solution v01 120101 voucm is the same as that given by Eq 83 and similarly for 1202 The smallisignal base currents can be written ibl vicmnbcm vidnbd and ibg vicmnbcm 7vidnbd lf RQ gt 00 the commonimode solutions are zero In this case the differential solutions can be used for the total solutions If RQ gtgt RE Tie the commonimode solutions are often approximated by zero SmallSignal HighFrequency Models Figure 20 shows the hybrid77T and T models for the BJT with the baseiemitter capacitance cr and the baseicollector capacitance 0 added The capacitor 005 is the collectorisubstrate capacitance which in present in monolithic integratedicircuit devices but is omitted in discrete devices These capacitors model charge storage in the device which affects its highifrequency performance The capacitors are given by TFIC C1r Cje VT 89 030 0 90 1 VegMW l 005 A 91 l1 VCS i clmu where IQ is the dc collector current VCB is the dc collectoribase voltage VCS is the dc collectori substrate voltage 035 is the zeroibias junction capacitance of the baseiemitter junction 739 is the forward transit time of the baseemitter junction 030 is the zeroibias junction capacitance of the baseicollector junction 0305 is the zeroibias collectorisubstrate capacitance 170 is the builtiin potential and me is the junction exponential factor For integrated circuit lateral pnp transistors 005 is replaced with a capacitor obs from base to substrate ie from the B node to ground M 7 Z 73950 Bab 0 LC AJ C gt gt i lt lt C on Err 79 jgtTOI es y T me e E Figure 20 Highifrequency smallisignal models of the BJT a Hybridi 39 model b T model 18 Copyright 2008 W Marshall Leach Jr Professor Georgia Institute of Technology School of Electrical and Computer Engineering The CommonGate Ampli er Basic Circuit Fig 1 shows the circuit diagram of a single stage commonigate ampli er The object is to solve for the smallisignal voltage gain input resistance and output resistance V R 7quotout 1 RD A C v0 I C1 2 RL L3 R2 RS Ri m V 1 7 Figure 1 Commonigate ampli er DC Solution a Replace the capacitors with open circuits Look out of the 3 MOSFET terminals and make Thevenin equivalent circuits as shown in Fig 2 VR2 ViRl V R R R CO R1R2 00 ill 2 V55 V7 Rss Rs VDD Vl RDD RD lo Write the loop equation between the V00 and the V55 nodes VGG Vss VGS ISRSS VGS IDRSS c Use the equation for the drain current to solve for V05 I VGSFDVTO DD RDD R ID V 00 Ga 39 VIT39 V03 15 RSS VSS Figure 2 Bias circuit d Solve the equations simultaneously IDRSS ng VGG V55 VTol 0 e Let V1 V00 7 V55 7 VTO Solve the quadratic for ID ID m 7 1f QRSSW d Verify that VDS gt V03 7 VTO m for the active mode VDS VD 7 VS VDD 7 IDRDD V7 IDRSS VDD 7 V55 7 IDRDD SmallSignal or AC Solutions a Redraw the circuit with VJr V 0 and all capacitors replaced with short circuits as shown in Fig 3 b Calculate gm7 rs and m from the DC solution 1 x1 V gm2xKID r5 r0 DS gm ID c Replace the circuit looking out of the source with a Thevenin equivalent circuit as shown in Fig 4 R755 Rsll RS Rs 11 1139 1R Rs Exact Solution a Replace the circuit seen looking into the drain with its Norton equivalent circuit as shown in Fig 5 Solve for idsc R Zdsc Gmsuts GmsUiWSRS S Figure 5 Norton collector Circuit 1 G m5 Bis Tsll70 b Solve for 110 U0 iidsc7didllRDllRL Gm MdllRDllRL Rs U S ZRS 35 To TsllRts Bis TV r 1 R 1d 1 7 Rts Ts l Rte 0 7 s S b Solve for the voltage gain 11 B5 A 0 G 39 R R 11 vi RSRS msxridll Dll L c Solve for rm r R R TmRiHRans MsTl3 O Dll L rer0 d Solve for rum Tout TidllRD Example 1 For the CS ampli er of Fig 7 it is given that R 50 9 R1 5M9 R2 1M9 RD 10kQ R5 3kQ R3 509 RL 20M V 24V V 724V K0 0001 AVg VTO 175V A 0016V 1 Solve for the gain A 11011 the input resistance rm and the output resistance ram The capacitors can be assumed to be ac short circuits at the operating frequency Solution For the dc bias solution replace all capacitors with open circuits The Thevenin voltage and resistance seen looking out of the gate are VR2 V7 R1 V 716V R R R 8333k 2 CG R1 R2 BB Ill 2 The Thevenin voltage and resistance seen looking out of the source are V55 V and R55 R5 To calculate ID we neglect the Early effect by setting K K0 The bias equation for ID is I 7 M1 4KV1RSS 1 D WEB To test for the active mode we calculate the drain7source voltage 2 gt 1655mA VD5 VD 7 V5 VJr 7 IDRD 7 V7 IDR55 26491V This must be greater than V05 7 VTO MID K 1286 It follows that the MOSFET is biased in its active mode For the small7signal ac analysis we need gm rs and r0 When the Early effect is accounted for the new value of K is given by K K0 1 AVD5 1424 X 10 3AV2 Note that this is an approximation because the Early effect was neglected in calculating VD5 However the approximation should be close to the true value It follows that gm rs and r0 are given by gm 2xKID 307 X 10 3AV r5 i 3257589 gm 4 71 L0 5373142 ID For the smallisignal analysis7 VJr and V are zeroed and the three capacitors are replaced with ac short circuits The Thevenin voltage and resistance seen looking out of the gate are given by Rs my MEL Rs 098411139 Rm RiHRS 4918 9 The Thevenin resistances seen looking out of the gate and the drain are Rig 09 Bid RDHRL 6667k9 Next7 we calculate Gms and rid 1 1 G S m5 Bis 791 372978 T l39d 7 0 1 1 its 1 R755 S The output voltage is given by 110 Gms gtlt ridHBLd utg Gmg gtlt ridHBLd gtlt 098411139 1587311139 Thus the voltage gain is A U 15373 U l The input and output resistances are given by 7 15 7 5 LR 363932 9 rm LL4le 324569 TO rs Tout TidHRD Approximate Solutions These solutions assume that To 00 except in calculating rid In this case7 idsc i i Simpli ed T Model Solution a After making the Thevenin equivalent circuit looking out of the source7 replace the MOSFET with the simpli ed T model as shown in Fig 6 b Solve for 6 1 0 7 115 2 5 M ELL 2105 ELL gt 21 711mm c Solve for 110 1 RS 1 7quotVRR VRRv VRR UL WM DH L ULLMRELLLH DH L ULR RSmREnLH DH L d Solve for the voltage gain R5 1 A 7 7 Vivi TRLRSTLRL5 WHRDHRL 5 Figure 6 Simpli ed T model Circuit e Solve for as and rm 1 39l 39l 5 0 7115 zsrs gt 25 7 7 5 Us Tls Ts 725 Tm Tell RS f Solve for rum Tout TtdllRD Example 2 Use the simplified Timodel solutions to calculate the values of A1 rm and ram for Example 1 A 0984 X 2667 X 10 3 X 5931 X 103 1556 rm 325659 rid 6195 kg rm 861m 7T Model Solution a After making the Thevenin equivalent Circuit looking out of the source7 replace the MOSFET With the 7T model as shown in Fig 7 b Solve for iii 7 1amp5 39l Z O Utsuwzlths dzliRiSgtle gm Rts 9m 3 Solve for 110 U R 7quot R R is TldllRDllRL ill RS R ldll Dll L 110 il indHRDHRL 1 Rts S Rts 9m 1 gm Figure 7 Hybrid 7T model Circuit d Solve for the voltage gain A 2 Rs TldllRDllRL U 11139 RsRs LRts gm e Solve for rum Tout TldllRD f Solve for ms and rm Z39l 07u5uW dgti1igmus gm 1 ms 725 gm Tm Tlslle Example 3 Use the Wimodel solutions to calculate the values of A1 rm and ram for Example 1 A 0984 X 2667 X 10 3 X 5931 X 103 1556 rm 325659 rid 6195 kg rm 861142 T Model Solution a After making the Thevenin equivalent Circuit looking out of the source7 replace the MOSFET With the T model as shown in Fig8 b Solve for iii Copyright 2008 W Marshall Leach Jr Professor Georgia Institute of Technology School of Electrical and Computer Engineering Complementary CC Ampli er Figure 1 shows a complementary commonecollector stage This is commonly used as the nal output stage in op amps and audio power ampli ers Compared to a nonecomplementary CC ampli er it can supply large positive and negative load currents with low power dissipation in the absence of a signal The npn BJT supplies positive load current while the pnp BJT supplies negative load current V Figure l Complementary commonecollector ampli er Let us rst examine the performance of the circuit with VB 0 For 111 0 both transistors are cut off In order to obtain a positive output voltage 111 must be increased until Q1 turns on Denote the turneon voltage for Q1 by V7 Similarly denote the turneon voltage for Q2 by 7V7 When 7V7 lt 111 lt V7 both transistors are off and there is very little output voltage For 111 gt V7 Q1 turns on and 120 goes positive For 111 lt 7V Q2 turns on and 110 goes negative The plot of 120 versus 111 would resemble curve a in Fig 2 A sine wave applied to the circuit would exhibit distortion in the crossover range for 7V7 lt 111 lt V as is illustrated by curve a in Fig 3 The distortion in the waveform is called crossover distortion or center clipping For VB gt 0 a positive bias voltage is applied to the base of Q1 and a negative bias voltage is applied to the base of Q2 As VB is increased both transistors turn on and emitter currents ow that are given by 2V3 VBE1 VBE2 1 1 E1 E2 REl RE2 The bias voltage causes the portion of curve a in Fig 2 for 111 gt 0 to be shifted to the left and the portion for 111 lt 0 to be shifted to the right The effective sum curve changes into approximately a straight line as shown in curve I in Fig 2 This eliminates the crossover distortion in the output waveform in shown by curve I in Fig 3 Once the transistors are turned on the emitter currents are extremely sensitive to the value of V3 To reduce this sensitivity resistors are often used in series with the emitters as shown in Fig 1 If an excessive emitter current ows the voltage drops across RE1 and Egg cause VBE1 and VE32 to decrease causing the current to decrease For minimum power dissipation in these resistors their value must be much smaller than that of RL In the design of op amps the emitter resistors are usually omitted In this case the value 71 Figure 2 Plots of 120 versus 121 Curve 3 7 VB 0 Curve b 7 VB adjusted to eliminate the deadband region Figure 3 Sine wave a With and 1 Without crossover distortion Cascode Amplifier Example Spring 2002 X39y Xy Function for calculating parallel resistors R FURY 1 R1 390000 R 2 I 200000 R 3 56000 R 4 100 RC20000 RE14300 RS1000 RLI10000 Vplus 35 meus 30 VBE1065 VT 0025 5199 110995 rX 20 r0 50000 vS 1 V th vS 1 the voltage gain is equal to v0 that is Av v0 71 First the dc bias solution Solve forthe Thevenin equivalent circuit looking out of the base of Q1 v me R3memltR1R2gt IE1 R1 R 15151 39 3 R1R2R3 15 R1R2R3 RMHFRP1R2RQ The bias loop equation is m VBB1mem 1BRBB1VBEIETRE It follows that the solution for IE1 is Vplus39R3vminus39RlR2 v R R R minus BE 1 2 3 IE1 R R R I 1055210 3 Bm a 1393 m RE 39 1B 1BR1R2R3 VT r 1 rel 236922 IE1 1 quot011 1 71049910 3 E2quot E1 E2quot VT r62 r62 238113 IE2 Now check to see that Q1 and Q2 are in the active mode VB11VBEIE1RE Vminus VBI 248126 Vplus39ltR2R3gtvminus39Rl IE2 VB2 R1R2R3 1 vaPltR1R2R3gt VB2 50528 vCl vBZ vBE vCl 57028 VCBl VCl VBl VCBl 191098 Thus active mode for Q1 VC21Vplus vaE2vRC VC2141065 VCB2 VC2 VB2 VCB2 191594 Thus active mode for Q2 Now for the ac solution Make a Thevenin equivalent circuit looking out of the base of Q1 R R R vth ivsv vth 09777 RSRPltR2R3gt Rtb1 RPR SRPltR2R3gtgt Rtb19776536 Rtel RPR ER4gt Rtel 977273 R r tbl X y r 61 rel r 61 286805 1B 1 V X Y 7 r e2 r62 r e27239113 1B Next make a Thevenin equivalent circuit looking out of the emitter of Q2 roRPltr39e1 Rte1 r 5 101 IR tel rid 2167810 r e1Rte1 r Rtel G 0 0 B mbl 39 39 r e1Rte1r0RPltr el Rte1gt i v G i e 7 69210 3 0150 tbl mbl clsc 39 7 3 Vte2 39quotlclsc39ricl Vte2 1667410 7 5 Rtez ric1 Rtez 7 2167810 Now make a Norton equivalent circuit looking into the collector of Q1 It follows that the circuit for the output voltage and output resistance is 7 3 th2 RPltRCRLgt Rm 6666710 r 02 r0 0t 0t me2 quot 39 r 02Rt02 r0RPr eZ Rt02gt 3 1 0250 3939Gm0239V teZ 1 0250 7652710 rot39PmPQ39ez Rtez 6 r M ric2 9789910 1R teZ r 02 R teZ V o 39i 025039R Pltr i02 R t02gt AV v 0 AV 509832 This is the voltage gain r out R PR C ric2gt r out 19959104 The circuit for the input resistance is r R r M ir 62v 0 m2 rieZ 270685 r r R t02 2 o e 1 Rtcl rie2 Rtcl 270685 BR tel 39R tcl riblrx1B39ltre1RPRte1 r0th1gtgtR R tclr0 tel ribl 24255104 rmzRPriblRPR2R3gt rin1560439104 Copyright 2008 W Marshall Leach Jr Professor Georgia Institute of Technology School of Electrical and Computer Engineering The MOSFET Device Symbols Whereas the JFET has a diode junction between the gate and the channel the metaleoXide semiconductor FET or MOSFET differs primarily in that it has an oxide insulating layer separating the gate and the channel The circuit symbols are shown in Fig 1 Each device has gate G drain D and source terminals Four of the symbols show an additional terminal called the body B which is not normally used as an input or an output It connects to the drainesource channel through a diode junction ln discrete MOSFETs the body lead is connected internally to the source When this is the case it is omitted on the symbol as shown in four of the MOSFET symbols ln integratedecircuit MOSFETs the body usually connects to a dc power supply rail which reverse biases the bodyechannel junction In the latter case the soecalled body effect must be accounted for when analyzing the circuit Channel Depletion MOSFET Enhancement MOSFET D D D D N G dID G gDB s Finb G IJ zDB s s 1 1 S S S S s s J J G 39G 39B G I G gt B P gt D1 m m D D Figure l MOSFET symbols Device Equations The discussion here applies to the nechannel MOSFET The equations apply to the pechannel device if the subscripts for the voltage between any two of the device terminals are reversed eg vgs becomes vsg The nechannel MOSFET is biased in the active mode or saturation region for 12133 2 vgs 7 12TH where 12TH is the threshold voltage This voltage is negative for the depletionemode device and positive for the enhancementemode device It is a function of the bodyesource voltage and is given by UTHVT0 YV UBS a 1 where VTO is the value of 12TH with 1233 0 y is the body threshold parameter ab is the surface potential and 1233 is the bodyesource voltage The drain current is given by k W 2D 3 f 1 Mpg ms 7 um 2 where W is the channel width L is the channel length A is the channelelength modulation parameter and k is given by k 00an 2 tax In this equation 0 is the average carrier mobility C is the gate oxide capacitance per unity area 60 is the permittivity of the oxide layer and in is its thickness It is convenient to de ne a transconductance coefficient K given by K l AvDS K0 1 AvDS El 2 L where K0 is given by kl K0 5 h 4 With these de nitions the drain current can be written iD K UGS vTH2 5 Note that K plays the same role in the MOSFET drain current equation as plays in the JFET drain current equation Transfer and Output Characteristics The transfer characteristics are a plot of the drain current iD as a function of the gateetoesource voltage vgs with the drainetoesource voltage vDS held constant Fig 2 shows the typical transfer characteristics for a zero bodyetoesource voltage In this case the threshold voltage is a constant ie 12TH VTO For vgs S VTO the drain current is zero For vgs gt VTO Eq 5 shows that the drain current increases as the square of the gateetoesource voltage The slope of the curve represents the smallesignal transconductance gm which is de ned in the following Drain Current O V70 Gote l o Source Voltage Figure 2 Drain current iD versus gateetoesource voltage vgs for constant drainetqsource voltage Ups The output characteristics are a plot the drain current iD as a function of the drainetoesource voltage vDS with the gateetoesource voltage vGS and the bodyetoesource voltage 1233 held constant Fig 3 shows the typical output characteristics for several values of gateetqsource voltage vgs The dashed line divides the triode region from the saturation or active region In the saturation region the slope of the curves represents the reciprocal of the smallesignal drainesource resistance 7 0 which is de ned in the next section SmallSignal Models There are two smallesignal circuit models which are commonly used to analyze MOSFET circuits These are the hybrid7739r model and the T model The two models are equivalent and give identical results They are described below In addition a simpli cation to the T model is derived which is called the simpli ed T model The models are rst developed for the case of no body effect and then with the body effect The former case assumes that the bodyesource voltage is zero ie v33 0 This is the case with discrete MOSFETs in which the source is connected physically to the body It also applies to smallesignal ac analyses for which the body and source leads are connected to the same or different dc voltages In this case the smallesignal bodyesource voltage is zero ie vbs 0 and there is no body effect Triode Saturation Drain Current Increasing 1 Vcs Druiln fo Source Voltage Figure 3 Drain current iD versus drainetoesource voltage 12133 for constant gateetoesource voltage vgs No Body Effect The smallesignal models in this section assume that the body lead is connected to the source lead The models also apply when the body and source leads are connected to different dc voltages so that the ac or signal voltage from body to source is zero Hybrid7T Model Consider the case where the bodyesource voltage is zero7 ie v33 0 In this case7 the threshold voltage in Eq 1 is a constant and given by 12TH VTO Let the drain current and each voltage be written as the sum of a dc component and a smallesignal ac component as follows iD D id UGS VGS vgs 11133 VDS vds If the ac components are suf ciently small7 we can write 7 81 7 81 2d 7 8VGS vgs where the derivatives are evaluated at the dc bias values Let us de ne 7 81 7 BVGS 9m 2 L 1 TO BID KAVGS7VTH2 BVDS It follows that the smallesignal drain current can be written Ud I S Zcl 2d T0 where 39 Zct 97nng 71 K VGS 7 VTH 2K1D D 7 1 VDS 12 13 The smallesignal circuit which models these equations is given in Fig 4 This is called the hybrideTr model Figure 4 7T model of the MOSFET T Model The T model of the MOSFET is shown in Fig 5 The resistor 7 0 is given by Eq 11 The resistor 73 is given by 1 T 14 s gm where gm is the transconductance de ned in Eq 10 The currents are given by id 239 15 7 0 1 1 3 E gmvgs 16 Ts The currents in the T model are the same as for the hybrid7739r model Therefore7 the two models are equivalent Note that the gate and body currents in Fig 5 are zero because the controlled source supplies the current that ows through 7 s Figure 5 Simpli ed T Model Figure 6 shows the MOSFET T model described above with a Thevenin source in series with the gate We wish to solve for the equivalent circuit in which the source id is replaced by a single source which connects from the drain node to ground having the value i d We call this the simpli ed T model Looking up into the branch labeled 2quot we can write vs vtg 7 i srs With vtg 07 the resistance 73 seen looking up into the branch labeled is given by 1 73 gm 17 The simpli ed T model is shown in Fig7 Note that there is no Big in the circuit because there is no current through Rtg in the original circuit Compared to the corresponding circuit for the BJT7 the MOSFET circuit replaces vtb with vtg and 7 with TS Because the gate current is zero7 set a 1 and 00 in converting any BJT formulas to corresponding MOSFET formulas Figure 7 With Body Effect The smallesignal models in this section assume that the body lead is connected to ac signal ground In integrated circuit design7 this ac signal ground is typically a dc power supply rail In this case7 any ac signal voltage on the source lead causes an ac signal voltage between the body and source The effect of this voltage is called the body effect Hybrid7T Model Let the drain current and each voltage be written as the sum of a dc component and a smallesignal ac component as follows z39D D id 18 vGS VGS 1193 19 11133 VBS vbs 20 11133 VDS vds 21 If the ac components are suf ciently small7 we can write 81D 81 31D 22 2d BVGSvgs BVBS vbs BVDS39Uds l where the derivatives are evaluated at the dc bias values Let us de ne 8 gm D K VGS 7 VTH 2xKID 23 BVGS 81D 39yKID 24 gmb BVBS W 7 VBS Xgm Y X 25 2W VBS 7 81 17 W giliVDerlA 7 0 7 BVDS 7 TA VGS VTH 7 ID 26 The smallesignal drain current can thus be written 390 2d ng Zdb E 27 7 0 where idg gmvgs 28 Z39ch gmbvbs 29 The smallesignal circuit which models these equations is given in Fig 8 This is called the hybride739r model If the body B lead is connected to the source7 then vbs 0 and the circuit becomes that given in Fig 4 d Figure 8 HybrideTr model of the MOSFET T Model The T model of the MOSFET is shown in Fig 9 The resistor 7 0 is given by Eq 26 The resistors 7 s and 73b are given by 1 TS 30 gm 1 1 TS 5 lt31 gmb Xgm X where gm and gmb are the transconductances de ned in Eqs 23 and 24 The currents are given by v 2d 239 Zsb E 32 7 0 v 139 g gmvgs 33 7 s v Zsb E gmbvbs 34 st The currents are the same as for the hybride739r model Therefore7 the two models are equivalent Note that the gate and body currents are zero because the two controlled sources supply the currents that ow through 73 and 73b Simpli ed T Model Figure 10 shows the MOSFET T model with a Thevenin source in series with the gate and the body connected to signal ground We wish to solve for the equivalent circuit in which the sources 23939 and isb are replaced by a single source which connects from the drain node to ground having the value i d We call this the Figure 9 T model of the MOSFET simpli ed T model The rst step is to look up into the branch labeled and form a Thevenin equivalent circuit With 2 07 we can use voltage division to write 9 35 v v M v TsX 30 tars rsb tars rsX 1 X With vtg 07 the resistance T s seen looking up into the branch labeled is 7 s 1 7 36 TS HT 1x 1xgm Figure 10 T model with Thevenin source connected to the gate and the body connected to signal ground The simpli ed T model is shown in Fig11 Compared to the corresponding circuit without the body effect7 the circuit replaces vtg with vtg 1 x and 7 3 with T 73 1 x To convert the simpli ed T model with the body effect to one without the body effect7 simply set X 0 The re Approximations No Body Effect The 7 0 approximations approximate 7 0 as an open circuit except when calculating the resistance seen looking into the drain Fig 7 shows the simpli ed T model for calculating rid vtz39d The resistor TS is given by TS 1gm We can write Rm 39Ut Rts 1 7 1 7 37 2d 20 ZS 20 7 s Rm 7 0 TSHRts Te Rm Figure 11 Simpli ed T model It follows that rid is given by 39Ut 7 07 sHRts Rts V 39 1 R 38 quotd 2 1 7 R r was T0 3 l Figure 12 Circuit for calculating the resistance rid seen looking into the drain The 7 0 approximations for the simpli ed T model the hybrid 7T model and the T model respectively are given Figs 13 through 15 Because 7 0 no longer connects to the source there is only one source current and is lf 7 0 00 then Tia is an open circuit in each Figure 13 Simpli ed T model With 7 0 approximations With Body Effect The 7 0 approximations approximate 7 0 as an open circuit except When calculating the resistance seen looking into the drain Fig 16 shows the simpli ed T model for calculating rid vtz39d The resistor T is given by Eq We can Write Rts 39Ut Rts 1 7 1 7 39 2d 2 23 2 r R m TISHR r R l l Figure 15 T model With the 7 0 approximations It follows that rid is given by 39Ut 7 0 TgHRts Rts 1 R 40 quotd id 1 7 Rm r R T r 3 Figure 16 Circuit for calculating the resistance rid seen looking into the collector The 7 0 approximations for the simpli ed T model the hybrid 7T model and the T model respectively are given Figs 17 through 19 Because 7 0 no longer connects to the source there is only one source current and is lf 7 0 00 then Tia is an open circuit in each SmallSignal HighFrequency Models Figures 20 and 21 show the hybrideTr and T models for the MOSFET With the gateesource capacitance 093 the sourceebody capacitance csb the drainebody capacitance cdb the drainegate capacitance cdg and the gateebody capacitance cgbadded These capacitors model charge storage in the device Which affect its highefrequency performance The rst three capacitors are given y 2 cg EWLCW 41 st csb 42 1 VSB 012 Figure 17 Simpli ed T model With 7 0 approximations Figure 18 Hybrid 7T model With the 7 0 approximations Figure 19 T model With the 7 0 approximations Copyright 2008 W Marshall Leach Jr Professor Georgia Institute of Technology School of Electrical and Computer Engineering Transfer Functions and Bode Plots These notes are not compete Transfer Functions For sinusoidal time variations the input voltage to a lter can be written v1t Re Viejw where Vi is the phasor input voltage ie it has an amplitude and a phase and 67 coswt j sinwt A sinusoidal signal is the only signal in nature that is preserved by a linear system Therefore if the lter is linear its output voltage can be written 120 t Re Voejw where V0 is the phasor output voltage The ratio of V0 to Vi is called the voltageegain transfer function It is a function of frequency Let us denote T W SIlt We can write T as follows T m A w em where A w and go to are real functions of w A w is called the gain function and go to is called the phase function As an example consider the lter input voltage 121t V1 cos wt 9 Re Wei957W The corresponding phasor input and output voltages are V V149 V0 VlejeA w 6 It follows that the time domain output voltage is 110 t Re V1579Awej pwejw A to V1 cos wt 9 go This equation illustrates why A w is called the gain function and go to is called the phase function e comp ex frequency 5 is usually used in place of jw in writing transfer functions In general most transfer functions can be written in the form where K is a gain constant and N s and D s are polynomials in 5 containing no reciprocal powers of s The roots of D s are called the poles of the transfer function The roots of N s are called the zeros s an example consider the function 4 1 4 1 T 5 45 45 5265561 521s31 The function has a zero at s 74 and poles at s 72 and s 73 Note that T 0 Because of this some texts would say that T s has a zero at s 00 However this is not correct because N 7E 0 Note that the constant terms in the numerator and denominator of Ts are both unity This is one of two standard ways for writing transfer functions Another way is to make the coefficient of the highest powers of s unity In this case the above transfer function would be written 54 54 TS6525566s2s3 Because it is usually easier to construct Bode plots with the rst form that form is used here Because the complex frequency 5 is the operator which represents ddt in the differential equation for a system the transfer function contains the differential equation Let the transfer function above represent the voltage gain of a circuit ie Ts VoVi where V0 and Vi respectively are the phasor output and input voltages It follows that 52 55 s 1 V 4 1Vv 6 6 o 4 2 When the operator 5 is replaced with ddt the following differential equation is obtained 1d2vo Ede dUI 4 6dt2 6d J0 dtvI where 110 and 121 respectively are the time domain output and input voltages Note that the poles are related to the derivatives of the output and the zeros are related to the derivatives of the input How to Construct Bode Plots A Bode plot is a plot of either the magnitude or the phase of a transfer function T as a function of w The magnitude plot is the more common plot because it represents the gain of the system Therefore the term Bode plot usually refers to the magnitude plot The rules for making Bode plots can be derived from the following transfer function in T s K 1 W0 where n is a positive integer For n as the exponent the function has n zeros at s 0 For in it has n poles at s 0 With 5 jw it follows that Tjw Kji ww0in lTjw Kww0in and AT in X 90 lf w is increased by a factor of 10 lT changes by a factor of 10 Thus a plot of lT versus w on logilog scales has a slope of log 10in in decadesdecade There are 20 st in a decade so the slope can also be expressed as i20n dBdecade As a rst example consider the lowepass transfer function 7 K 7 1sw1 T S This function has a pole at s iwl and no zeros For 5 jw and wwl ltlt 1we have T 2 K lT 2 K and Mom 2 0 X 90 0 For wwl gtgt 1 Tom 2 Kymml lTjwl g Kww171and T 2 71X 90 790 On log 7 log scales the magnitude plot for the lowefrequency approximation has a slope of 0 while that for the highefrequency approximation has a slope of 71 The low and highefrequency approximations intersect when K Kw1w or when w am For w wl lT K 1 jl and AT 7 arctan 1 745 Note that this is the average value of the phase on the two adjoining asymptotes The Bode magnitude and phase plots are shown in Fig 1 Note that the slope of the asymptotic magnitude plot rotates by 71 at w wl Because an is the magnitude of the pole frequency we say that the slope rotates by 71 at a pole A straight line segment that is tangent to the phase plot at w wl would intersect the 0 level at ml481 and the 790 level at 481w1 As a second example consider the transfer function T s K 1 1 W1 This function has a zero at s iwl For 5 jw and wwl ltlt 1we have Tjw 2 K 2 K and 1Tjw 2 0 X 90 0 For wwl gtgt 1 Tjw 2 Kjww11 2 Kww1 and AT 2 ITUm mom 0 b Figure 1 Bode plots a Magnitude b Phase 1 gtlt 90 90 On logilog scales the magnitude plot for the lowefrequency approximation has a slope of 0 while that for the highefrequency approximation has a slope of 1 The low and highefrequency approximations intersect when K Kww1 or when w wl For w wl K and ATjw arctan1 45 Note that this is the average of the phase on the two adjoining asymptotes The Bode magnitude and phase plots are shown in Fig 2 Note that the slope of the asymptotic magnitude plot rotates by 1 at w wl Because an is the magnitude of the zero frequency we say that the slope rotates by 1 at a zero A straight line segment that is tangent to the phase plot at w on would intersect the 0 level at ml481 and the 90 level at 481w1 Tjwl Alma K 1 i I 39 I a b Figure 2 Bode plots a Magnitude b Phase From the above examples we can summarize the basic rules for making Bode plots as follows 1 In any frequency band where a transfer function can be approximated by K jww0in the slope of the Bode magnitude plot is in decdec The phase is in X 90 N Poles cause the asymptotic slope of the magnitude plot to rotate clockwise by one unit at the pole frequency 03 Zeros cause the asymptotic slope of the magnitude plot to rotate countereclockwise by one unit at the zero frequency As a third example consider the transfer function swl T 1 S swl 1 This function has a pole at s iwl and a zero at s 0 For 5 jw and wwl ltlt 1we have 1T 2 Kww1 and ZTjw 2 90 For wwl gtgt 1 2 K and ZTjw 2 0 On logilog scales the magnitude plot for the lowefrequency approximation has a slope of 1 while that for the highefrequency approximation has a slope of 0 The low and highefrequency approximations intersect when K LUM1 K or when w on For w wl 1T and AT 90 7 arctan 1 45 The Bode magnitude and phase plots are shown in Fig 3 Note that the slope of the asymptotic magnitude plot rotates by 71 at the pole The transfer function is called a highepass function because its gain approaches zero at low frequencies Tjwl Alma 90 1 45 1 A a 39 a a b Figure 3 Bode plots a Magnitude b Phase A shelving transfer function has the form 1 T S Km 1 s w1 The function has a pole at s iwl and a zero at s 71122 We will consider the lowepass shelving function for which an lt mg For 5 jw and wwl ltlt 1 we have 2 K and AT 2 0 As w is increased the pole causes the asymptotic slope to rotate from 0 to 71 at an The zero causes the asymptotic slope to rotate from 71 back to 0 at mg For wwg gtgt 1 2 Kw1w2 The Bode magnitude plot is shown in Fig 4a If the transfer function did not have the zero the actual gain at an would be The zero causes the gain to be between and K Similarly the pole causes the actual gain at A12 to be between Kw1w2 and K mlmg The actual plot intersects the asymptotic plot at the geometric mean frequency w1w2 The phase plot has a slope that approaches 0 at very low frequencies and at very high frequencies At the geometric mean frequency W the phase is approaching 790 If the function only had a pole the phase at wl woul e 745 approaching 790 at higher frequencies However the zero causes the highefrequency phase to approach 0 Thus the phase at an is more positive than 745 0 At the geometric mean frequency 1mxlwg the slope of the phase function is zero The Bode phase plot is shown in Fig 4b TJ39w ZITUw 1 02 K o w K091 1 45 T72 w 90 1 2 a b Figure 4 Bode plots a Magnitude b Phase Impedance Transfer Functions RC Network The impedance transfer function for a twoeterminal RC network which contains only one capacitor and is not an open circuit at dc can be written 1 73925 1 TPS zRda where Rda is the dc resistance of the network Tp is the pole time constant and 739 is the zero time constant The pole time constant is the time constant of the network with the terminals open circuited The zero time constant is the time constant of the network with the terminals short circuited Figure 5a shows the circuit diagram of an example twoeterminal RC network The impedance transfer function can be written by inspection to obtain 1 R205 1 R1 R2 Cs CR2 L R2 R R I 1 a b ZR1 Figure 5 Example RC and RL impedance networks RL Network The impedance transfer function for a twoeterminal RL network which contains only one inductor and is not a short circuit at dc can be written 1 73925 1 TF5 ZRda where Rda is the dc resistance of the network Tp is the pole time constant and TZ is the zero time constant The pole time constant is the time constant of the network with the terminals open circuited The zero time constant is the time constant of the network with the terminals short circuited Figure 5b shows the circuit diagram of an example twoeterminal RL network The impedance transfer function can be written by inspection to obtain ZR1HR21 1 LR2s L R1 132 5 Voltage Divider Transfer Functions RC Network The voltageegain transfer function of a BC voltageedivider network containing only one capacitor and having a nonzero gain at dc can be written V0 K 1 73925 Vi da1TpS where Kda is the dc gain C an open circuit Tp is the pole time constant and 739 is the zero time constant The pole time constant is the time constant of the network with Vi 0 and V0 open circuited The zero time constant is the time constant of the network with V0 0 and Vi open circuited Figure 6a shows the circuit diagram of an example RC network The voltageegain transfer function can be written by inspection to obtain V0 R2R3 1R2HR3CS X W R1 R2 R3 1 R1 R2 HR3l Cs Figure 6b shows the circuit diagram of a second example RC network The voltageegain transfer function can be written by inspection to obtain E7 R3 X 1R1R2Cs V R1 R3 1 R1HR3 132le b c Figure 6 Example RC voltage divider networks HighPass RC Network The voltageegain transfer function of a highepass RC voltageedivider network containing only one capacitor can be written V0 TF5 Vi 0 1 TPS where Koo is the in nite frequency gain C a short circuit and Tp is the pole time constant The pole time constant is calculated with Vi 0 and V0 open circuited Figure 6c shows the circuit diagram of a third example RC network The voltageegain transfer function can be written by inspection to obtain E 7 R2 X R1 R2 Cs Vi R1R2 1R1R2CS RL Network The voltageegain transfer function of a BL voltageedivider network containing only one inductor and having a nonzero gain at dc can be written V0 1 73925 Vi 7 do 1 TPS where Koo is the zero frequency gain L a short circuit7 Tp is the pole time constant7 and 739 is the zero time constant The pole time constant is the time constant of the network with Vi 0 and V0 open circuited The zero time constant is the time constant of the network with V0 0 and Vi open circuited Figure 7a shows the circuit diagram of an example RL network The voltageegain transfer function can be written by inspection to obtain E R2 X 1LR2HR35 Vi R1R2 1LlR1R2HR3lS Figure 7b shows the circuit diagram of a second example RL network The voltageegain transfer function can be written by inspection to obtain E 7 R3 X 1 L R1 5 Vi R1 R3 1 L R111 R2 Ram 5 HighPass RL Network The voltageegain transfer function of a highepass RL voltageedivider network containing only one inductor can be written V0 TPS Vi 7 0 1 TPS where Koo is the in nite frequency gain L an open circuit and Tp is the pole time constant The pole time constant is calculated with Vi 0 and V0 open circuited Figure 7c shows the circuit diagram of a third example RL network The voltageegain transfer function can be written by inspection to obtain E R2 X lL RlllR2l 5 Vi R1 R2 1lL R111R2l5 Copyright 2008 W Marshall Leach Jr Professor Georgia Institute of Technology School of Electrical and Computer Engineering The Diode Basic Operation The diode is fabricated of a semiconductor material usually silicon which is doped with two impurities One side is doped with a donor or nitype impurity which releases electrons into the semiconductor lattice These electrons are not bound and are free to move about Because there is no net charge in the donor impurity the nitype semiconductor is electrically neutral The other side is doped with an acceptor or pitype impurity which imparts free holes into the lattice A hole is the absence of an electron which acts as a positive charge The ptype semiconductor is also electrically neutral because the acceptor material adds no net charge Figure 1a illustrates the cross section of the diode The junction is the dividing line between the nitype and pitype sides Thermal energy causes the electrons and holes to move randomly Electrons diffuse across the junction into the pitype side and holes diffuse across the junction into the nitype side This causes a net positive charge to develop in the nitype side and a net negative charge to develop in the pitype side These charges set up an electric eld across the junction which is directed from the nitype side to the pitype side The electric eld opposes further diffusion of the electrons and holes The region in which the electric eld exists is called the depletion region There are no free electrons or holes in this region because the electric eld sweeps them out E Depletion Regon I39l El a Figure 1 a Diode cross section b Reverse biased diode c Forward biased diode Figure 1b shows the diode with a battery connected across it The polarity of the battery is such that it reinforces the electric eld across the junction causing the depletion region to widen The positive terminal pulls electrons in the nitype side away from the junction The negative terminal pulls holes in the pitype side away from the junction No current can flow The diode is said to be reverse biased Figure 1c shows the diode with the battery polarity reversed The battery now tends to cancel out the electric eld in the depletion region causing its width to decrease The positive terminal forces holes toward the junction The negative terminal forces electrons toward the junction A current flows which increases rapidly if the applied voltage is increased The diode is said to be forward biased i 7 1 Characteristics Figure 2a shows the circuit symbol for the diode The arrow part of the symbol points in the direction of current flow when the diode is forward biased The upper terminal is called the anode The lower terminal is called the cathode These names come from vacuum tube diodes 100 I I I I 71D 3 E U 0 O I I I O 02 04 06 08 up volts b Figure 2 a Diode symbol b Typical current versus voltage The theoretical equation for the diode current is if 5 exp 7 1 Where Is is the saturation current n is the emission coef cient and VT is the thermal voltage The emission coefficient accounts for recombinations of electrons and holes in the depletion region Which tend to decrease the current For discrete diodes it has the value n z 2 For integrated circuit diodes it has the value n z 1 The reason it is different for the two cases is because an integrated circuit diode is fabricated as a bipolar transistor With the collector connected to the base The impurity doping in transistors is done so as to minimize recombinations Thus n z 1 When recombinations can be neglected A typical plot of iD versus Up is given in Fig 2b For 11D 3 06V the current is very small For up gt 06V the current increases rapidly With up The voltage at Which the diode appears to begin conducting is called the cutin voltage This is approximately 06V for the plot in Fig 2b The thermal voltage is given by 7 kT q Where k is Boltzmann s constant T is the Kelvin temperature and q is the electronic charge At T 290 K the thermal voltage has the value VT 0025V The default value for T in SPICE is T 300 K In this case the thermal voltage has the value VT 002585 V This value should be used in any hand calculations that are to be compared to SPICE simulations Because VT increases With T the equation for iD seems to imply that increasing T decreases iD However 5 increases rapidly With temperature Which causes if to increase With T A rule of thumb that is often quoted for silicon diodes is that if ip is held constant 11D decreases by about 2 mV for each degree C as T increases VT Example 1 Calculate the amount by which 11D would have to be increased to double the diode current Assume exp 11 nVT gtgt 1 and VT 0025V Solution We have 27 IslexpuD2nVT7 1 11132711131 7 2 exp Is expuD1nVT 7 1 nVT Solution for Au 11132 7 11131 yields Au nVTln2 173mV for n 1 347mV for n 2 This example illustrates how fast the diode current increases with increasing diode voltage Linear Model The linear model of the diode approximates the i 7 1 characteristics by a straight line that is tangent to the actual curve at the dc bias point Fig 3a shows the curve with the tangent line at the point VD7 ID The curve intersects the horizontal axis at the voltage VDO For small changes in 11D and ip about the tangent point7 the tangent line gives a good approximation to the actual curve The slope of the tangent line is given by diD 1 I VD D S 1 m 5exp duD VD ID nVT nVT nVT rd where the units of rd are ohms The equation of the tangent line is VD VDO rd 239D The equivalent circuit which models this equation is shown in Fig 3b Because 11D VD when iD ID7 it follows that the voltage VDO is given by VDO VD IDTd 11 angenf 7 Point V JD 1 d 10 VDU b I I D Vzw lt1 Figure 3 a i 7 1 characteristics with tangent line at VD7 ID b Linear diode model Example 2 A diode is biased at D 1mA It is given that Is 36 X 1079A n 2 and VT 259mV Solve for rd and VDO in the linear model Solution VD nVT ln T d nVTID Q7 VDO VD 7 IDTd SmallSignal Model Because the diode equation for iD as a function of Up is nonlinear the tools of linear circuit analysis cannot be applied in general to circuits containing diodes However if the diode current is known for a particular voltage linear circuit analysis can be used to predict the change in current for a given change in voltage provided the change is not very large Such an approach is called a smallesignal analysis Let the diode voltage and current be written UDVDUd iDIDid where VD and ID are dc bias values and 11d and id are smallesignal changes about the bias values Let the diode equation be denoted by if f Up and its derivative denoted by diD duD f Up We can write ID 211 fVD Ud E fVDf VDUd where the approximation is a firsteorder Taylor series expansion about the point VD ID Because ID f VD we can solve for id to obtain idf VDudi 5 exp E 71 XudI Sexp E Xudmxu dVD nVT VT nVT nVT The smallesignal resistance is de ned as the ratio of W to id and is given by nVT nVT m This is the same rd as in the linear model of the diode in Fig 3b Thus the smallesignal model of the diode is a resistor of value rd The value of rd is inversely proportional to the current through it Each time the current is doubled the resistance is halved It follows from the linear diode model that rd can be interpreted graphically as the reciprocal of the slope of the ip versus 11D curve at the point VDJD Example 3 Figure 4a shows a diode attenuator circuit The input voltage 11 is a smallisignal differential voltage represented by two series sources with the common terminal grounded The current IQ is a dc control current Solve for the smallisignal gain 110111 Assume the diodes are identical n 2 and VT 0025V Figure 4 a Diode attenuator circuit b Smallesignal circuit for calculating 110 Solution For the dc solution we set 11 0 In this case 110 0 For identical diodes the current IQ splits equally between the two It follows the dc voltages across the diodes cancel in calculating The Junction Diode Basic Operation The diode is fabricated of a semiconductor material usually silicon which is doped with two impurities One side is doped with a donor or netype impurity which releases electrons into the semiconductor lattice These electrons are not bound and are free to move about Because there is no net charge in the donor impurity the netype semiconductor is electrically neutral The other side is doped with an acceptor or ptype impurity which imparts free holes into the lattice A hole is the absence of an electron which acts as a positive charge The ptype semiconductor is also electrically neutral because the acceptor material adds no net charge Figure 1a illustrates the cross section of the diode The junction is the dividing line between the netype and petype sides Thermal energy causes the electrons and holes to move randomly Electrons diffuse across the junction into the ptype side and holes diffuse across the junction into the netype side This causes a net positive charge to develop in the netype side and a net negative charge to develop in the petype side These charges set up an electric eld across the junction which is directed from the netype side to the petype side The electric eld opposes further diffusion of the electrons and holes The region in which the electric eld exists is called the depletion region There are no free electrons or holes in this region because the electric eld sweeps them out n Depletion ET lRegion a Figure 1 a Diode cross section b Reverse biased diode c Forward biased diode Figure 1b shows the diode with a battery connected across it The polarity of the battery is such that it reinforces the electric eld across the junction causing the depletion region to widen The positive terminal pulls electrons in the netype side away from the junction The negative terminal pulls holes in the ptype side away from the junction No current can ow The diode is said to be reverse biased Figure 1c shows the diode with the battery polarity reversed The battery now tends to cancel out the electric eld in the depletion region causing its width to decrease The positive terminal forces holes toward the junction The negative terminal forces electrons toward the junction A current ows which increases rapidly if the applied voltage is increased The diode is said to be forward biased i 7 1 Characteristics Figure 2a shows the circuit symbol for the diode The arrow part of the symbol points in the direction of current ow when the diode is forward biased The upper terminal is called the anode The lower terminal is called the cathode These names come from vacuum tube diodes The theoretical equation for the diode current is iD 13 exp 712quot 7 1 where 13 is the saturation current n is the emission coef cient and VT is the thermal voltage The emission coefficient accounts for recombinations of electrons and holes in the depletion region which tend to decrease the current For discrete diodes it has the value n 2 2 For integrated circuit diodes it has the value n 2 1 The reason it is different for the two cases is because an integrated circuit diode is fabricated as a bipolar transistor with the collector connected to the base The impurity doping in transistors is done so as to minimize recombinations Thus n 2 1 when recombinations can be neglected A typical plot of iD versus 12 is given in Fig 2b For 12D 3 06V the current is very small For 12 gt 06V the current increases rapidly with 12 The voltage at which the diode appears to begin conducting is called the cutin voltage This is approximately 06V for the plot in Fig 2b 100 I I I I in 2 E 1 v 50 I a 0 I I I 0 02 04 06 08 1 volts 0 Figure 2 a Diode symbol b Typical current versus voltage The thermal voltage is given by 7 kT q where k is Boltzmann s constant T is the Kelvin temperature and q is the electronic charge At T 290 K the thermal voltage has the value VT 0025V The default value for T in SPICE is T 300 K In this case the thermal voltage has the value VT 002585 V This value should be used in any hand calculations that are to be compared to SPICE simulations Because VT increases with T the equation for iD seems to imply that increasing T decreases iD However 13 increases rapidly with temperature which causes iD to increase with T A rule of thumb that is often quoted for silicon diodes is that if ip is held constant 12 decreases by about 2mV for each degree C as T increases VT Example 1 Calculate the amount by which 12 would have to be increased to double the diode current Assume exp vDnVT gtgt 1 and VT 0025V Solution We have 2 IS expvD2nVT 7 1 N exp 12132 7 12131 13 exp vD1nVT 7 1 T nVT Solution for Au 12132 7 le yields Av nVTln2 173 mV for n 1 347mV for n 2 This example illustrates how fast the diode current increases with increasing diode voltage Reverse Breakdown If the diode is reverse biased and the voltage is increased a point will be reached when the diode enters reverse breakdown and a current will ow The voltage at which this occurs is called the zener voltage Fig 3 illustrates the variation of diode current with voltage The reverse breakdown voltage is labeled 7VZ and the cutin voltage is labeled V7 ln diode applications the reverse breakdown voltage must be greater than the maximum applied reverse voltage to prevent diode failure As an example diodes used to rectify 120V rms ac line voltage must have a reverse breakdown voltage greater than 120 170 V Diodes which are fabricated to have a speci c value of V2 are called zener diodes These diodes are used as voltage reference iodes The zener or reverse breakdown voltage is a function of the n and 17 type doping levels in the Clio e The higher the doping the lower the value of VZ For VZ less than approximately 4V the breakdown is due to zener breakdown For VZ greater than approximately 5V the breakdown is due to avalanche breakdown 7V V 1 Figure 3 Diode characteristics showing the zener voltage V2 and the cutin voltage V7 An example application of a zener diode is shown in Fig 4 The circuit shows a dc source having a voltage V1 connected to a zener diode and a load through a resistor R1 lf V1 changes7 VL remains approximately constant Thus the diode acts as a constant voltage reference The diode current is V1 Vz I 7 I Z R1 L The power dissipated in the diode is given by VZIZ The power dissipated in the resistor R1 is V1 7 V2 12 IL The power dissipated in the diode decreases as IL increases and the power dissipated in R1 increases as IL increases The power ratings of the diode and R1 must be high enough to prevent thermal failure under worst case conditions for each This means that the power rating of the diode must be chosen for the minimum anticipated value of IL and the power rating of R1 must be chosen for the maximum anticipated value of IL Figure 4 Example zener diode regulator Example 2 For V1 24V VZ 12V and 2 mA 3 IL 3 10 mA calculate the value of R1 such that IZ 2 2mA and determine the minimum power ratings of R1 and the zener diode in Fig 4 Solution The value of R1 is calculated for the maximum value of IL Thus the maximum current through R1 is 2 mA 10 mA 12 mA Thus R1 24V 7 12 V 12 mA 1 k9 The minimum power rating for R1 is 12V X 12 mA 144 mW The minimum power rating for the zener diode is 12V X 12 mA 7 2 mA 100 mW Linear Model The linear model of the diode approximates the i 7 1 characteristics by a straight line that is tangent to the actual curve at the dc bias point Fig 5a shows the curve with the tangent line at the point VD7 ID The curve intersects the horizontal axis at the voltage VDO For small changes in 12 and ip about the tangent point7 the tangent line gives a good approximation to the actual curve The slope of the tangent line is given by 7 Lfsexpamp Mi dvD VD ID nVT nVT nVT rd where the units of rd are ohms The equation of the tangent line is VD VDO Td ZD Tangent Poin r V1 n Vpo a Figure 5 a i 7 1 characteristics with tangent line at VD ID b Linear diode model The equivalent circuit which models this equation is shown in Fig 5b Because 12 VD when iD ID it follows that the voltage VDO is given by VDO VD IDTd Example 3 A diode is biased at ID 1 mA It is given that IS 36 X 10 9 A n 2 and VT 259mV Solve for rd and VDO in the linear model Solution VD nVTlnIDIS 0649V rd nVTID 518 9 VDO VD 7 IBM 0598V SmallSignal Model Because the diode equation for iD as a function of Up is nonlinear the tools of linear circuit analysis cannot be applied in general to circuits containing diodes However if the diode current is known for a particular voltage linear circuit analysis can be used to predict the change in current for a given change in voltage provided the change is not very large Such an approach is called a smallesignal analysis Let the diode voltage and current be written vDVDvd iDIDid where VD and ID are dc bias values and 12d and id are smallesignal changes about the bias values Let the diode equation be denoted by iD f Up We can write ID z39d f VD vd 2 f VD f VDW where the approximation is a rsteorder Taylor series expansion about the point VD ID Because ID f VD we can solve for id to obtain d VD Is VD IDIS V I 71 2d fDvd dDSexpnT gtltvd TexpnTgtltvd nT gtltvd The smallesignal resistance is de ned as the ratio of vd to id and is given by nVT nVT 7 2 d ID 13 ID This is the same rd as in the linear model of the diode in Fig 5b This equation says that the diode smallesignal resistance is inversely proportional to the current through it Each time the current is doubled the resistance is halved It follows from the linear diode model that rd can be interpreted graphically as the reciprocal of the slope of the ip versus 1 curve at the point VDJD Current Mirrors Basic Current Mirror Current mirrors are basic building blocks of analog design Fig 1a shows the basic npn current mirror For its analysis we assume identical transistors and neglect the Early effect ie we assume VA gt 00 This makes the saturation current 5 and current gain 5 independent of the collector base voltage VCB The input current to the mirror is labeled IREF This current might come from a resistor connected to the positive rail or a current source realized with a transistor or another current mirror The emitters of the two transistors are shown connected to ground These can be connected to a dc voltage eg the negative supply rail 210 1m 5 0 MW 0 From Q1 ii Q2 l9 is a Figure 1 a Basic mirror b Mirror with base current compensation The simplest way to solve for the output current is to sum the currents at the node where REF enters the mirror Because the two transistors have their baseemitter junctions in parallel it follows that both must have the same currents Thus we can write the equation 2 REF 10 0 Solution for 0 yields IRE F 1 2 3 Because the Early effect has been neglected in solving for 0 the output resistance is in nite If we include the Early effect and assume that it has negligible effect in the solution for 0 the output resistance is given by O V032 VA 0 Tout 7 02 For a more accurate analysis we can include the Early effect in calculating the output current If the transistors have the same parameters we can write V I 01 so exp TEE Bi V032 VBE O I I 1 I O SOlt T VA gtexplt VT B2 501 VCBzVA By taking the ratio of O to 01 we obtain 7 V032 107lt1 VA gt101 Summing currents at the node where REF enters the circuit yields I REF 01 g O i I 2 50 50 1 VCBzVA Cl 50 Thus 01 is given by Cl REF 1 230 It follows that O is given by V032 REF 1 VCBZVA I 1 I o lt VA gt 01 1 2WD The output resistance is given above Note that the effect of a nite 5 is to reduce 0 but the effect of the Early effect is to increase it Because of the Early effect the output current is commonly greater than the input current One way of obtaining a better match between the input and output currents is to use series emitter resistors on the transistors If the current in one transistor increases it causes the voltage across its emitter resistor to increase which causes a decrease in its baseiemitter voltage This causes the current to decrease thus causing the two transistors to have more equal currents A typical value for the emitter resistors is 100 9 With these resistors Rteg is no longer zero so that the output resistance is increased It is given by rant 7702 which can be much greater than r02 Current Mirror with Base Current Compensation Figure 1b shows the basic current mirror with a third transistor added The collector of Q3 must be connected to a positive reference voltage eg the positive supply rail which biases it in the active mode If we neglect the Early effect and assume all transistors are identical we can write 210 REF 10 5 1 5 Solution for 0 yields REF 1 2 39lt1 agt1 For a noniin nite Early voltage and V031 VBE3 ltlt VA it can be shown that the output current is given by 10 I REF 1 VCB2VA O 1 2 50 1 733 where 3 o1gt VA The Wilson Current Mirror A Wilson current mirror is shown in Fig 2a We neglect the Early effect in the analysis and assume the transistors to have identical parameters The emitter current in Q3 is 004 This current is the input to a basic current mirror consisting of Q1 and Q2 It is mirrored into the collector of Q1 by dividing by 1 At the node where REF enters the mirror we can write 004 Io 1 5 O I I REF 1 Q 02 g 3 Solution for 0 yields REF 0 1 1 m E I I I I I I I I Fro I T REF IREF 10 II om Q3 IOa i Q1 92 12pz olt QT Q2 7 RE a ltbgt 39 Figure 2 a Wilson mirror b Lowilevel mirror The advantage of the Wilson mirror over the current mirrors examined above is that it has a much higher output resistance This is caused by two positive feedback effects To see how this occurs suppose a test current source is connected between the mirror output and ground If the source delivers current to the output node the voltage increases This causes a current to flow through 7 03 causing the emitter voltage of Q3 and the base voltage of Q1 to increase The increase in voltage at the emitter of Q3 causes its collector voltage to increase because Q3 is a commonibase stage for an emitter input The increase in voltage at the base of Q1 causes the collector voltage of Q1 and the base voltage of Q3 to decrease because Q1 is a commoniemitter stage for a base input The decrease in voltage at the base of Q3 causes its collector voltage to increase because Q3 is a commoniemitter stage for a base input Thus there are two positive feedback effects which cause the collector voltage of Q3 to increase to a larger value Because rout is the ratio of the collector voltage of Q3 to the current in the test source it follows that the output resistance is increased LowLevel Current Mirror The circuit shown in Fig 2b is a lowilevel current mirror It can be used when it is desired to have a much lower output current than input current For the analysis we neglect the Early effect assume identical transistors and assume that 5 gt 00 We can write V V 7 R m Is exp 31 0 Imp By taking ratios we obtain REF ex ORE O p VT This equation cannot be solved for 0 However if REF and O are speci ed it can be solved for RE to obtain VT REF R 1 E O nlt O gt As an example suppose REF 1 mA VT 25 mV and O 50 MA It follows from this equation that RE 1498 Q The effect of this large a value of RE on rout is to make it greater than 7 02 To calculate rout we must know the smallisignal Thevenin resistance Rm looking out of the base of Q2 Q1 is a bjt connected as a diode and exhibits a smallisignal resistance 7 01 751 1 31 VTIEll VTIE1 25 9 This is in parallel with the smallisignal resistance looking up into the REF source Thus an upper bound on Rm is 25 9 Let us assume 7 02 40 k9 T932 0 a2 0995 and 5 2 199 It follows that neg RtbgT 5 aVTIcg 4976 9 Thus rent is given by 40k 4976H 1498 1595 kg 1 7 0995 X 1498 4976 1498 Tout 3902 This is larger than 7 02 by a factor of almost 4 The Transconductance Op Amp An example application of the current mirror is the transconductance op amp The circuit is shown in Fig 3 The circuit consists of an input diff amp and four Wilson current mirrors For the analysis we assume 5 gt 00 and VA gt 00 for each bjt so that the output current from each mirror is equal to the input current We assume that ABC splits equally between the emitters of Q1 and Q2 Thus the total currents in Q1 and Q2 respectively are given by ABC ABC 7 ABC 7 4 2 2 2401 221 2402 icz lei The latter expression for icg follows because icl icg 0 It follows from the mirrored currents that the output current is given by i0 2i01 If we neglect base currents and the Early effect icl iel vi1 7 1112 27 5 where r5 2VTIABC Thus i0 is given by Z ABC 0 2VT W1 W2 Thus the transconductance gain is set by the current L430 The gain can be varied by varying L430 Because ABC 2 0 the circuit operates as a twoiquadrant multiplier The circuit symbol for the transconductance opamp is shown in Fig 4 An example application of the transconductance op amp is a circuit which generates an amplii tude modulated signal The circuit is shown in Fig 5 Let Ul39 and ABC be given by 39Ui 1inwct ABCIQ1msinwmt Figure 3 Transconductance op amp Figure 4 Circuit symbol for the transconductance op amp Effects of Op Amp Finite Gain and Bandwidth OpenLoop Transfer Function In our analysis of opiamp circuits this far7 we have considered the opamps to have an in nite gain and an in nite bandwidth This is not true for physical opiamps In this section7 we examine the effects of a noniin nite gain and noniin nite bandwidth on the inverting and the noniinverting ampli er circuits Fig 1 shows the circuit symbol of an opiamp having an openiloop voltagegain transfer function A The output voltage is given by vAltsgtltVevgt 1 where complex variable notation is used We assume here that A s can be modeled by a singlepole lowipass transfer function of the form A0 148 1sw0 2 where A0 is the dc gain constant and we is the pole frequency Most general purpose opiamps have a voltagegain transfer function of this form for frequencies such that lA 2 1 V V Figure 1 Opiamp symbol GainBandwidth Product Figure 2 shows the Bode magnitude plot for A The radian gainibandwidth product is de ned as the frequency mm for which lA 1 It is given by mm LamAg 7 1 Aowo 3 where we assume that A0 gtgt 1 This equation illustrates why mm is called a gainibandwidth product It is given by the product of the dc gain constant A0 and the radian bandwidth me It is commonly speci ed in Hz with the symbol f1 where f1 tux27139 Many general purpose opiamps have a gainibandwidth product f1 1MHZ and a dc gain constant A0 2 2 X 105 It follows from Eq 3 that the corresponding pole frequency in the voltageigain transfer function for the general purpose opiamp is f0 2 1 X 106 2 X 105 5H2 NonInverting Ampli er Figure 3 shows the circuit diagram of a noniinverting ampli er For this circuit7 we can write by inspection V0ASV VJ 4 R1 ViV 5 quotR1RF We 711 decdec Figure 2 Bode plot of Simultaneous solution for the voltageigain transfer function yields E 1RFR1 Vi 1ASR1R1RF 11RFR1As For 3 jw and l1 RFR1 A ltlt 17 this reduces to z 1 RFR1 This is the gain which would be predicted if the opiamp is assumed to be ideal Figure 3 Noniinverting ampli er When Eq 2 is used for A s7 it is straightforward to show that Eq 6 can be written V A f Of 7 W 1 swof where Aof is the gain constant with feedback and wof is the radian pole frequency with feedback These are given by A A0 1RFR1 8 0f 1AOR1R1RF 11RFR1Ao A R wof UJO lt1 gt 9 It follows from these two equations that the radian gainibandwidth product of the noniinverting ampli er with feedback is given by Aofwof Aowo mm This is the same as for the opiamp without feedback Fig 4 shows the Bode magnitude plots for both and A The gure shows that the break frequency on the plot for VLVi lies on the negativeslope asymptote of the plot for Ajw A0 71 decdec Aof 1 a we of a Figure 4 Bode plot for Example 1 At very low frequencies an opeamp has the frequency independent openeloop gain A s A0 2 X 105 The opeamp is to be used in a noneinuerting ampli er The theoretical gain is calculated assuming that the opeamp is ideal What is the highest theoretical gain that gives an error between the theoretical gain and the actual gain that is less than 1 Solution The theoretical gain is given by 1 RF R1 The actual gain is always less than the theoretical gain For an error less than 17 we can use Eq 6 to write 1 17001 lt 11RFR12 X 105 This can be solved for the upper bound on the theoretical gain to obtain RF 5 1 1 2 10 7 1 2020 T R1 lt X 099 gt Example 2 An opeamp has a gainebandwidth product of 1MHz The opeamp is to be used in a noneinuerting ampli er circuit Calculate the highest gain that the ampli er can have if the half power or 73 dB bandwidth is to be 20 kHz or more Solution The minimum bandwidth occurs at the highest gain For a bandwidth of 20 kHz7 we can write Aof X 20 X 103 106 Solution for Aof yields Aof 50 Example 3 Two noneinuerting opeamp ampli ers are operated in cascade Each ampli er has a gain of 10 If each opeamp has a gainebandwidth product of 1MHz calculate the halfepower or 73 dB bandwidth of the cascade ampli er Solution Each ampli er by itself has a pole frequency of 10610 100 kHz7 corresponding to a radian frequency wof 27139 X 1007 000 The cascade combination has the voltageegain transfer function given by 2 E W 1 swof The halfepower frequency is obtained by setting 3 jw and solving for the frequency for which 027ng 10022 If we let CU wwof the resulting equation is 1002lt 1 gt21002 12 2 3 This equation reduces to 13 Solution for 33 yields 33 0644 It follows that the halfipower frequency is 0644 X 100 kHz 644 kHz Inverting Ampli er Figure 5a shows the circuit diagram of an inverting ampli er Fig 5b shows an equivalent circuit which can be used to solve for V By inspection7 we can write V0 7143 V 10 Vi V0 V7 R R 11 R1RFlt 1H F lt gt These equations can be solved for the voltagegain transfer function to obtain E 1R1ASR1llRF RFRl 12 w 1 lt1RFgtAltsgtltR1HRFgt 1lt1RFR1gtAltsgt For 3 jw and l1 RFRl A ltlt 17 the voltagegain transfer function reduces to RFRl This is the gain which would be predicted if the opiamp is assumed to be ideal Figure 5 a lnverting ampli er b Equivalent circuit for calculating V2 When Eq 2 is used for 143 it is straightforward to show that the voltagegain transfer function reduces to E A0f 13 W 1 s wo f where Aof is the gain constant with feedback and wof is the radian pole frequency with feedback These are given by 1R1AOR1HRF 7 RFRl 14 0 1 lt1RFgtA0ltR1HRFgt 1 1 RFRn A0 W we 1 AO RZQEF we 1 Ao R1 311 15 Note that Aof is de ned here as a positive quantity so that the negative sign for the inverting gain is retained in the transfer function for Let the radian gainibandwidth product of the inverting ampli er with feedback be denoted by mgr It follows from Eqs 14 and 15 that this is given by a Aofwof waFRF R1 This is less than the gainibandwidth product of the opiamp without feedback by the factor RF RF R1 Fig 6 shows the Bode magnitude plots for VLVi and for Ajw The frequency labeled wa is the break frequency for the noniinverting ampli er with the same gain magnitude as the inverting ampli er The noniinverting ampli er with the same gain has a bandwidth that is greater by the factor 1 R1 RF The bandwidth of the inverting and the noniinverting ampli ers is approximately the same if R1 RF ltlt 1 This is equivalent to the condition that Aof gtgt 1 39 rsls 71 decdee CO def wof com 602 Figure 6 Bode plot for Example 4 An opeamp has a gainebandwidth product of 1MHz Compare the bandwidths of an inverting and a noneiniei ting ampli er which use the opeamp for Aof 1 2 5 and 10 Solution The noneinverting ampli er has a bandwidth of f1 A0f The inverting ampli er has a bandwidth of fxAof gtlt RF R1 RF If we approximate Aof of the inverting ampli er by Aof RFRl7 its bandwidth reduces to 1 Aof The calculated bandwidths of the two ampli ers are summarized in the following table Aof Nonelnverting lnverting 1 1MHz 500kHz 2 500 kHz 333 kHz 5 200 kHz 1 6 7 kHz 10 100 kHz 9 1 kHz For the case of the ideal opeamp7 the V input to the inverting ampli er is a virtual ground so that the input impedance Zm is resistive and equal to R1 For the opeamp with nite gain and bandwidth7 the V terminal is not a virtual ground so that the input impedance differs from R1 We use the circuit in Fig 5a to solve for the input impedance as follows 7 Vi 7 Vi 7 R1 11 Vi V R1 1 ViVa VaVi To put this into the desired form7 we let 1216 7114 s and use Eq 12 for The equation for Zm reduces to Zm 16 71 iltRF RF s 17 RF A O AOUJO RF Z R R in 1 where Eq 2 has been used It follows from this equation that Zm consists of the resistor R1 in series with an impedance that consists of the resistor RF in parallel with the series combination of a resistor R2 and an inductor L given by RF R 18 2 A0 7 RF 7 AOUJO 5 The equivalent circuit for Zm is shown in Fig 7a lf A0 gt 007 it follows that R2 gt 0 and L2 gt 0 so that Zm gt R1 The impedance transfer function for Zn is of the form of a highipass shelving transfer function given by 1swz 1 30p 20 Zm S RDC where BBC is the dc resistance7 up is the pole frequency7 and LUZ is the zero frequency These are given by R RDC R1 TFAO 21 R R up we 1 AU 22 7 R2 RFHR1 7 AURl wzi L 7140 1R1RF 23 The Bode magnitude plot for Zm is shown in Fig 7b R IZmI 1 Vi 9 R2 131 RF Zm RF R RF 1 decdeo L 1 1AO w Cquotz WP a b Figure 7 a Equivalent input impedance b Bode plot for Example 5 At very low frequencies an opiamp has the frequency independent openiloop gain As A0 2 X 105 The opiamp is to be used in an inverting ampli er with a gain of 71000 What is the required ratio RFRl For the value ofRF R1 how much larger is the input resistance than R1 Solution By Eq 127 we have 7 RFR1 1 1 RFR1 2 X 105 This can be solved for RF R1 to obtain 71000 RF 2 X 105 1 1005 R1 2 X 1051000 7 1 By Eq 177 the input resistance can be written RF R1 gt 1005 R 1 1005R 1ltT12gtlt105gt 1 RVR 1 in 1lt1A0 The Junction Diode Basic Operation The diode is fabricated of a semiconductor material usually silicon which is doped with two impurities One side is doped with a donor or netype impurity which releases electrons into the semiconductor lattice These electrons are not bound and are free to move about Because there is no net charge in the donor impurity the netype semiconductor is electrically neutral The other side is doped with an acceptor or ptype impurity which imparts free holes into the lattice A hole is the absence of an electron which acts as a positive charge The ptype semiconductor is also electrically neutral because the acceptor material adds no net charge Figure 1a illustrates the cross section of the diode The junction is the dividing line between the netype and petype sides Thermal energy causes the electrons and holes to move randomly Electrons diffuse across the junction into the ptype side and holes diffuse across the junction into the netype side This causes a net positive charge to develop in the netype side and a net negative charge to develop in the petype side These charges set up an electric eld across the junction which is directed from the netype side to the petype side The electric eld opposes further diffusion of the electrons and holes The region in which the electric eld exists is called the depletion region There are no free electrons or holes in this region because the electric eld sweeps them out n Depletion ET lRegion a Figure 1 a Diode cross section b Reverse biased diode c Forward biased diode Figure 1b shows the diode with a battery connected across it The polarity of the battery is such that it reinforces the electric eld across the junction causing the depletion region to widen The positive terminal pulls electrons in the netype side away from the junction The negative terminal pulls holes in the ptype side away from the junction No current can ow The diode is said to be reverse biased Figure 1c shows the diode with the battery polarity reversed The battery now tends to cancel out the electric eld in the depletion region causing its width to decrease The positive terminal forces holes toward the junction The negative terminal forces electrons toward the junction A current ows which increases rapidly if the applied voltage is increased The diode is said to be forward biased i 7 1 Characteristics Figure 2a shows the circuit symbol for the diode The arrow part of the symbol points in the direction of current ow when the diode is forward biased The upper terminal is called the anode The lower terminal is called the cathode These names come from vacuum tube diodes The theoretical equation for the diode current is iD IS exp 712quot 7 l where 13 is the saturation current n is the emission coef cient and VT is the thermal voltage The emission coef cient accounts for recombinations of electrons and holes in the depletion region which tend to decrease the current For discrete diodes it has the value n 2 2 For integrated circuit diodes it has the value n 2 1 The reason it is different for the two cases is because an integrated circuit diode is fabricated as a bipolar transistor with the collector connected to the base The impurity doping in transistors is done so as to minimize recombinations Thus n 2 1 when recombinations can be neglected A typical plot of iD versus 12 is given in Fig 2b For 12D 3 06V the current is very small For 12 gt 06V the current increases rapidly with 12 The voltage at which the diode appears to begin conducting is called the cutin voltage This is approximately 06V for the plot in Fig 2b 100 I I I I in 2 E 1 v 50 I a 0 I I I 0 02 04 06 08 1 volts 0 Figure 2 a Diode symbol b Typical current versus voltage The thermal voltage is given by 7 kT q where k is Boltzmann s constant T is the Kelvin temperature and q is the electronic charge At T 290 K the thermal voltage has the value VT 0025V The default value for T in SPICE is T 300 K In this case the thermal voltage has the value VT 002585 V This value should be used in any hand calculations that are to be compared to SPICE simulations Because VT increases with T the equation for iD seems to imply that increasing T decreases iD However 13 increases rapidly with temperature which causes iD to increase with T A rule of thumb that is often quoted for silicon diodes is that if ip is held constant 12 decreases by about 2mV for each degree C as T increases VT Example 1 Calculate the amount by which 12 would have to be increased to double the diode current Assume exp vDnVT gtgt 1 and VT 0025V Solution We have 2 7 Is leXPUD2TLVT 1l N 11132 i 11131 7 7 exp IS exp vD1nVT 7 1 nVT Solution for Au 12132 7 le yields Av nVT ln2 173 mV for n 1 347mV for n 2 This example illustrates how fast the diode current increases with increasing diode voltage Reverse Breakdown If the diode is reverse biased and the voltage is increased a point will be reached when the diode enters reverse breakdown and a current will ow The voltage at which this occurs is called the zener voltage Fig 3 illustrates the variation of diode current with voltage The reverse breakdown voltage is labeled 7V2 and the cutin voltage is labeled V7 ln diode applications the reverse breakdown voltage must be greater than the maximum applied reverse voltage to prevent diode failure As an example diodes used to rectify 120V rms ac line voltage must have a reverse breakdown voltage greater than 120 170 V Diodes which are fabricated to have a speci c value of V2 are called zener diodes These diodes are used as voltage reference iodes The zener or reverse breakdown voltage is a function of the n and 17 type doping levels in the Clio e The higher the doping the lower the value of VZ For VZ less than approximately 4V the breakdown is due to zener breakdown For VZ greater than approximately 5V the breakdown is due to avalanche breakdown 7V V 1 Figure 3 Diode characteristics showing the zener voltage V2 and the cutin voltage V7 An example application of a zener diode is shown in Fig 4 The circuit shows a dc source having a voltage V1 connected to a zener diode and a load through a resistor R1 If V1 changes7 VL remains approximately constant Thus the diode acts as a constant voltage reference The diode current is V1 Vz I 7 I Z R1 L The power dissipated in the diode is given by VZIZ The power dissipated in the resistor R1 is V1 7 Vz IZ IL The power dissipated in the diode decreases as IL increases and the power dissipated in R1 increases as IL increases The power ratings of the diode and R1 must be high enough to prevent thermal failure under worst case conditions for each This means that the power rating of the diode must be chosen for the minimum anticipated value of IL and the power rating of R1 must be chosen for the maximum anticipated value of IL Figure 4 Example zener diode regulator Example 2 For V1 24V VZ 12V and 2 mA S 1 S 10 mA calculate the value of R1 such that IZ 2 2mA and determine the minimum power ratings of R1 and the zener diode in Fig 4 Solution The value of R1 is calculated for the maximum value of IL Thus the maximum current through R1 is 2mA 10 mA 12 mA Thus R1 24V 7 12 V 12 mA 1 k9 The minimum power rating for R1 is 12V X 12 mA 144 mW The minimum power rating for the zener diode is 12V X 12 mA 7 2 mA 100 mW Linear Model The linear model of the diode approximates the i 7 1 characteristics by a straight line that is tangent to the actual curve at the dc bias point Fig 5a shows the curve with the tangent line at the point VD7 ID The curve intersects the horizontal axis at the voltage VDO For small changes in 12 and ip about the tangent point7 the tangent line gives a good approximation to the actual curve The slope of the tangent line is given by 7 Lfsexpamp Mi dvD VD ID nVT nVT nVT rd where the units of rd are ohms The equation of the tangent line is VD VDO Td ZD Tangent Poin r V1 n Vpo a Figure 5 a i7 1 characteristics with tangent line at VD ID b Linear diode model The equivalent circuit which models this equation is shown in Fig 5b Because 12 VD when iD ID it follows that the voltage VDO is given by VDO VD IDTd Example 3 A diode is biased at ID 1 mA It is given that IS 36 X 10 9 A n 2 and VT 259mV Solve for rd and VDO in the linear model Solution VD nVT ln IDIS 0649V rd nVTID 518 9 VDO VD 7 IBM 0598V SmallSignal Model Because the diode equation for iD as a function of Up is nonlinear the tools of linear circuit analysis cannot be applied in general to circuits containing diodes However if the diode current is known for a particular voltage linear circuit analysis can be used to predict the change in current for a given change in voltage provided the change is not very large Such an approach is called a smallesignal analysis Let the diode voltage and current be written UDVDvd iDIDid where VD and ID are dc bias values and vd and id are smallesignal changes about the bias values Let the diode equation be denoted by iD f Up We can write ID z39d f VD vd 2 f VD f VDW where the approximation is a rsteorder Taylor series expansion about the point VD ID Because ID f VD we can solve for id to obtain idf VDvdi 13 exp E 71 de exp E deMde dVD nVT VT nVT TLVT The smallesignal resistance is de ned as the ratio of vd to id and is given by nVT nVT r 2 d IDIS ID This is the same rd as in the linear model of the diode in Fig 5b This equation says that the diode smallesignal resistance is inversely proportional to the current through it Each time the current is doubled the resistance is halved It follows from the linear diode model that rd can be interpreted graphically as the reciprocal of the slope of the ip versus 1 curve at the point VDJD Copyright 2008 W Marshall Leach Jr Professor Georgia Institute of Technology School of Electrical and Computer Engineering The BJ T Notation The notations used here for voltages and currents correspond to the following conventions Dc bias values are indicated by an upper case letter with upper case subscripts eg VDS Io lnstantaneous values of smallisignal variables are indicated by a lowericase letter with lowericase subscripts eg Us ic Total values are indicated by a lowericase letter with uppericase subscripts eg UBE iD Circuit symbols for independent sources are circular and symbols for controlled sources have a diamond shape Voltage sources have a i sign within the symbol and current sources have an arrow Device Equations Figure 1 shows the circuit symbols for the npn and pnp BJTs In the active mode the collectoribase junction is reverse biased and the baseiemitter junction is forward biased For the npn device the activemode collector and base currents are given by u 239 2015exp 23 EC 1 where VT is the thermal voltage 5 is the saturation current and 8 is the basetoicollector current gain These are given by CT VT 0025V for T 290K 2586 mV for T 300K 2 q Is 150 1U g E 3 A UCE 1 4 5 M VA lt gt where VA is the Early voltage and so and g respectively are the zero bias values of Is and Because Is ISO50 it follows that 2393 is not a function of 110E The equations apply to the pnp device if the subscripts BE and CE are reversed The emitteritoicollector current gain 04 is de ned as the ratio To solve for this we can write 1 1 ZEZBZC 1ZC ZC 5 8 8 It follows that I 2 0 i 6 2E 1 5 Thus the currents are related by the equations ic i3 OtiE z 1 39LB C 13 E B E iE 1C39 E C Fm Pnp Figure 1 BJT circuit symbols Transfer and Output Characteristics The transfer characteristics are a plot of the collector current 2390 as a function of the basetoiemitter voltage UBE with the collectoritoiemitter voltage 110E held constant From Eqs 1 and 3 we can write i0 ISO 1 exp It follows that 2390 varies exponentially with UBE A plot of this variation is given in Fig 2 It can be seen from the plot that the collector current is essentially zero until the basetoiemitter voltage reaches a threshold value Above this value the collector current increases rapidly The threshold value is typically in the range of 05 to 06 V For high current transistors it is usually smaller The plot shows a single curve lf 110E is increased the current for a given UBE is larger However the displacement between the curves is so small that it can be dif cult to distinguish between them The smallisignal transconductance gm de ned below is the slope of the transfer characteristics curve evaluated at the quiescent or dc operating point for a device l l Collector Current 130 I I Bdse Emilier Vol roge vBE Figure 2 BJT transfer characteristics The output characteristics are a plot of the collector current 2390 as a function of the collector toiemitter voltage 110E with the base current 2393 held constant From Eqs 1 and 47 we can write UCE ZC 50 1 2B 9 A It follows that 2390 varies linearly with 110E A plot of this variation is given in Fig 3 For small 110E such that 0 S 110E lt ung7 Eq 9 does not hold In the region in Fig 3 where this holds7 the BJT is saturated The smallisignal collectoritoiemitter resistance r0 de ned below is the reciprocal of the slope of the transfer characteristics curve evaluated at the quiescent or dc operating point for a device 7J0 f ncreqsing B Collec ror Current I Collector Emitter Voltage vCE Figure 3 BJT output characteristics Hybrid7r Model Let each current and voltage be written as the sum of a dc component and a smallisignal ac component as follows icIcic iBIBib 10 39UBE VBE Ube 39UCE VCE 1165 11 If the ac components are sufficiently small7 we can write 7 810 810 7 813 26 7 BVBE39Ube BVCEUCB 2b 7 BVBE 39Ube 12 where the derivatives are evaluated at the dc bias values Let us de ne the transconductance gm7 the collectoritoiemitter resistance To and the baseitoiemitter resistance r as follows BIC 5 ex E 0 13 gm BVBE VT p VT VT r 7 81C 1 7 ex VBE 1 7 VA VCE 14 0 BVCE VA p VT Io 813V ll VBEll hr ex BVBE oVT p VT The collector and base currents can thus be written 1iVT IB u u ce 7r 26 Zc l Zb 7 0 7 7r where 39l 7 7 26 gm39uw 11w We 15 16 17 The smallisignal circuit which models these equations is given in Fig 4a This is called the hybrid77T model The resistor rm which does not appear in the above equations7 is called the base spreading resistance It represents the resistance of the connection to the base region inside the device Because the base region is very narrow7 the connection exhibits a resistance which often cannot be neglected 73 73 O C lb Tx B c 10 I B AvAvAv C TO ltgt lt lt lt To 7T Te lt quot0 me e i e e E b Figure 4 a Hybridi 39 model b T model The smallisignal basetoicollector ac current gain is de ned as the ratio i Cib It is given by 39 Zc gm39uw 9m7 7r Z1 Z1 ilcVTilc TV TIBTIB Note that ic differs from by the current through r0 Therefore7 iCib 7 unless r0 00 T Model 18 The T model replaces the resistor hr in series with the base with a resistor TB in series with the emitter This resistor is called the emitter intrinsic resistance The current can be written 1 1 5 2 22b2g122 225 where 04 is the smallisignal emitteritoicollector ac current gain given by a i 1 Thus the current can be written 19 20 21 The voltage u7r can be related to as follows 2quot ai an m U Zbr7r r7r er 71 zre 22 It follows that the intrinsic emitter resistance TB is given by u r V V re 7r 7r T T ZEEUTHEE The T model of the BJT is shown in Fig 4b The currents in both models are related by the equations gmu7r ib an 24 Simpli ed T Model Figure 5 shows the T model with a Thevenin source in series with the base We wish to solve for an equivalent circuit in which the source connects from the collector node to ground rather than from the collector node to the B node d OPP 39 e z RwB HB cc AAA AAA vvv quotTvvv 1 U 7 lt ltgt tb re ro d 1e 10 18 U8 E Figure 5 T model with Thevenin source connected to the base The rst step is to replace the source on with two identical series sources with the common node grounded The circuit is shown in Fig 6a The object is to absorb the left 04239 source into the baseemitter circuit For the circuit7 we can write 2quot 1 i mvmi zm mm Us vi 7 Let us de ne the resistance r by amp mgamp i w 1 1 With this de nition7 115 is given by 115 11 7 27 The circuit which models Eq 27 is shown in Fig 6b We will call this the simpli ed T model It predicts the same emitter and collector currents as the circuit in Fig 5 Note that the resistors Ru and rm do not appear in this circuit because they are contained in r13 Rtb B Ta B e e le C AvAvAv AVAV v 39 39 g L 0 e 39 tb 2 Te ltgt 7 0 16 7 e 7 0 be Ue E Figure 6 a Circuit With the source replaced by identical series sources b Simpli ed T model The 7 0 Approximations The re approximations approximate m as an open circuit except When calculating the resistance seen looking into the collector Fig 7 shows the simpli ed T model for calculating Tic utic We assume a Thevenin resistance R connected from the base to ground This resistor is absorbed into r13 Which is given by Eq 26 We can write Rte 11 Rte 17 17 28 26 20 Me 20 was r0rguRte was It follows that MC is given by To TlellRte 29 vi Tic 7 2396 7 liaRteT l Rte Figure 7 Circuit for calculating the resistance MC seen looking into the collector The re approximations for the hybrid 7T model the T model and the simpli ed T model respectively are given Figs 8 and 9 If m 00 then ma is an open circuit in each Because r0 no longer connects to the emitter there is only one emitter current and is 2395 a b Figure 8 a Hybrid 7T and b T models with the To approximations Figure 9 Simpli ed T model with the To approximations The Simpli ed 7T Model When To connected from collector to emitter is replaced with ma connected from collector to ground7 it is possible to simplify the 7T model to obtain a circuit that is similar to the simpli ed T model in Fig 9 Consider the circuit of Fig 10a A Thevenin source Ute and Big is connected from the emitter to ground We can write 111 2391 m M 239ng5 1amp5 2391 m hr 1 5 Riel 1amp5 This equation is of the form 39Ub i177 Ute where rlr is given by r 7 7 7r1 Rte With ib the equivalent circuit that predicts the same base and collector currents is shown in Fig 10b We will refer to this as the simpli ed 7T model It is useful when calculating 2391 and the resistance seen looking into the base node when the To approximations are assumed SmallSignal HighFrequency Models Figure 11 shows the hybrid77T and T models for the BJT with the baseiemitter capacitance c7r and the baseicollector capacitance cu added The capacitor Gas is the collectorisubstrate capacitance which in present in monolithic integratedicircuit devices but is omitted in discrete devices These capacitors model charge storage in the device which affects its highifrequency performance The Figure 10 a To approximation to the 7T model With a Thevenin equivalent circuit connected to the emitter b The simpli ed 7T model With the To approximation capacitors are given by T39 I c 05 FTC 30 cC c 31 H l1 VCB bclmn Cos Cjcs l1 VCS bc lmn Where C is the dc collector current V03 is the dc collectoribase voltage V03 is the dc collectori substrate voltage 015 is the zeroibias junction capacitance of the baseiemitter junction 739 is the forward transit time of the baseemitter junction 01C is the zeroibias junction capacitance of the baseicollector junction Cjcs is the zeroibias collectorisubstrate capacitance be is the builtiin potential and ma is the junction exponential factor For integrated circuit lateral pnp transistors Gas is replaced With a capacitor 015 from base to substrate ie from the B node to ground c C H T 03 7 quot H 39 Iquot b w B315 10 lb Tx 3 77 C 7 c 39M C B c J 3 lt lC Orr v 74e jgtTOI CS T a Q e E E a b Figure 11 Highifrequency smallisignal models of the BJT a Hybridi 39 model b T model Copyright 2009 W Marshall Leach Jr Professor Georgia Institute of Technology School of Electrical and Computer Engineering The MOSFET Device Equations Whereas the JFET has a diode junction between the gate and the channel the metaleoxide semiconductor FET or MOSFET differs primarily in that it has an oxide insulating layer separating the gate and the channel The circuit symbols are shown in Fig 1 Each device has gate G drain D and source terminals Four of the symbols show an additional terminal called the body B which is not normally used as an input or an output It connects to the drainesource channel through a diode junction ln discrete MOSFETs the body lead is connected internally to the source When this is the case it is omitted on the symbol as shown in four of the MOSFET symbols ln integratedecircuit MOSFETs the body usually connects to a dc power supply rail which reverse biases the bodyechannel junction In the latter case the soecalled body effect must be accounted for when analyzing the circuit Channel Depletion MOSFET Enhancement MOSFET D D D D N GP le G i zDB 647 344 2173 3 S 1 W S S S S S S J J Gl Gl 3 Gl G l B P If D11 11 11 D D Figure l MOSFET symbols The discussion here applies to the nechannel MOSFET The equations apply to the pechannel device if the subscripts for the voltage between any two of the device terminals are reversed eg vgs becomes vsg The nechannel MOSFET is biased in the active mode or saturation region for 12133 2 vgs 7 12TH where 12TH is the threshold voltage This voltage is negative for the depletionemode device and positive for the enhancementemode device It is a function of the bodyesource voltage and is given by UTHVTO YV UBS T 1 where VTO is the value of 12TH with 1233 0 y is the body threshold parameter ab is the surface potential and 1233 is the bodyesource voltage The drain current is given by k W 2 2D 3 f 1 VUDS UGS vTH 2 where W is the channel width L is the channel length A is the channelelength modulation parameter and k is given by e k 00 tax In this equation 0 is the average carrier mobility C is the gate oxide capacitance per unity area 60 is the permittivity of the oxide layer and in is its thickness It is convenient to de ne a transconductance coef cient K given by 1 mm 3 With this de nition the drain current can be written iD K ms 7 um 4 Note that K plays the same role in the MOSFET drain current equation as plays in the JFET drain current equation Figure 2 shows the typical variation of drain current with gateetoesource voltage for a constant draine toesource voltage and zero bodyetoesource voltage In this case the threshold voltage is a constant ie 12TH VTO For vgs S VTO the drain current is zero For vgs gt VTO the drain current increases approximately as the square of the gateetoesource voltage The slope of the curve represents the smallesignal transconductance gm which is de ned in the next section Fig 3 shows the typical variation of drain current with drainetoesource voltage for a several values of gateetoesource voltage vgs and zero bodyetoe source voltage 113 The dashed line divides the triode region from the saturation or active region In the saturation region the slope of the curves represents the reciprocal of the smallesignal drainesource resistance 7 0 which is de ned in the next section Current Drain O VTO Gate to Source Voltage Figure 2 Drain current iD versus gateetoesource voltage vgs for constant drainetqsource voltage Ups Trtode Saturation Current Increasing T CS Drain DraintoSource Voltage Figure 3 Drain current iD versus drainetoesource voltage UDS for constant gateetoesource voltage vGS Bias Equation Figure 4 shows the MOSFET with the external circuits represented by Thevenin dc circuits If the MOSFET is in the pincheo quot region the following equations for ID hold ID K VGS 7 VTH2 5 VGS VGG Vss 131333 6 K K0 1 AVDs 7 VDS VDD DRDD Vss DRSS 8 Because this is a set of nonlinear equations a closed form solution for ID cannot be easily written unless it is assumed that K is not a function of VDS and VTH is not a function of VBS The former assumption requires the condition AVDS ltlt 1 With these assumptions the equations can be solved for ID to obtain 1 2 ID 7 m M1 4KRSS VGG 7 V33 7 VTH 7 1 9 Vac f 11 VBH V E SS Figure 4 MOSFET dc bias circuit Unless AVDS ltlt 1 and the dependence of VTH on VBS is neglected Eq 9 is only an approximate solution A numerical procedure for obtaining a more accurate solution is to rst calculate ID wit and VTH VTO Then calculate VDS and the new values of K and VTH from which a new value for D can be calculated The procedure can be repeated until the solution for ID converges Alternately computer tools can be used to obtain a numerical solution to the set of nonlinear equations SmallSignal Models There are two smallesignal circuit models which are commonly used to analyze MOSFET circuits These are the hybrid7739r model and the T model The two models are equivalent and give identical results They are described below Hybrid7T Model Let the drain current and each voltage be written as the sum of a dc component and a smallesignal ac component as follows z39D D id 10 UGS VGS vgs 11 11133 VBS vbs 12 11133 VDS vds 13 If the ac components are sufficiently small we can write 81D 81D 81D 14 2d BVGS v93 BVBS vbs BVDS vds l where the derivatives are evaluated at the dc bias values Let us de ne 8 9m D K VGS VTH 2 KID 15 BVGS 31D YVKID 16 gmb BVBS W 7 VBS Xgm Y X 17 2W VBS 81D 1 W 2 1 VDS1 x V 7 V 18 T0 BVDS 2 L GS TH D l The smallesignal drain current can thus be written id idg idb 19 7 0 where idg gmvgs 20 idb gmbvbs 21 The smallesignal circuit which models these equations is given in Fig 5 This is called the hybrid7739r model Figure 5 HybrideTr model of the MOSFET T Model The T model of the MOSFET is shown in Fig 6 The resistor 7 0 is given by Eq 18 The resistors 7 s and 73b are given by 1 TS 22 gm 1 1 TS 5 lt23 gmb Xgm X where gm and gmb are the transconductances de ned in Eqs 15 and 16 The currents are given by v 2d 239 Zsb E 24 7 0 v 239 gmvgs 25 7 s v Zsb E gmbvbs 26 st The currents are the same as for the hybrid7739r model Therefore7 the two models are equivalent Note that the gate and body currents are zero because the two controlled sources supply the currents that ow through 73 and 73b Figure 6 T model of the MOSFET SmallSignal Equivalent Circuits Several equivalent circuits are derived below which facilitate writing smallesignal lowefrequency equations for the MOSFET We assume that the circuits external to the device can be represented by Thevenin equivalent circuits The Norton equivalent circuit seen looking into the drain and the Thevenin equivalent circuit seen looking into the source are derived Several examples are given which illustrate use of the equivalent circuits Simpli ed T Model Figure 7 shows the MOSFET T model with a Thevenin source in series with the gate and the body connected to signal ground We wish to solve for the equivalent circuit in which the sources 23939 and isb are replaced by a single source which connects from the drain node to ground having the value i d We call this the simpli ed T model The rst step is to look up into the branch labeled and form a Thevenin equivalent circuit With 07 we can use voltage division to write st TsX vtg v 27 rsrsb ths l TsX 1X Usoa vtg With vtg 07 the resistance T s seen looking up into the branch labeled is I Ts 1 7 28 TS HT 1x 1xgm Figure 7 T model with Thevenin source connected to the gate and the body connected to signal ground The simpli ed T model is shown in Fig8 Compared to the corresponding circuit for the BJT7 the MOSFET circuit replaces vtb with vtg l x and 7 with T 73 l x Because the gate current is zero7 set a l and 00 in converting any BJT formulas to corresponding MOSFET formulas The simpli ed T model is derived with the assumption that the body lead connects to signal ground In the case that the body lead connects to the source lead7 it follows from Fig 7 that isb 0 Connecting the body to the source is equivalent to setting X 0 in the MOSFET equations Figure 8 Simpli ed T model Norton Drain Circuit Figure 9a shows the MOSFET with Thevenin sources connected to its gate and source leads and the body lead connected to signal ground The Norton equivalent circuit seen looking into the drain can be obtained from the Norton equivalent circuit seen looking into the BJT collector by replacing Gmb with Gmg7 Gme with Gms7 and Tia with rid The factor 1 1 X must be incorporated into the equation for Gmg To convert the formulas7 replace Rtb with Rtg Rte with Rte Rm with Rm 7 with 7 set a 17 and set 00 The circuit is given in Fig 9b7 where idsa and rid are given by idsa Gmgvg 7 GmsvtS 29 rid 7 0 1 R 30 The transconductances Gmg and Gms are given by Gm 31 GM 32 The equations for the case where the body is connected to the source are obtained by setting X 0 For the case B 07 the equations for Gmg and Gms reduce to G 33 my 1 X T s gm G 7 i 1 1 34 ms TQHTO X 9m T0 For the case 7 0 gt R and 7 0 gtgt 7 we can write 1 1 G 35 my 1 X T s R and G 7 36 ms 7 T s Rts The value of idsa calculated with these approximations is simply the value of calculated with 7 0 considered to be an open circuit The term To approximations is used in the following when 7 0 is neglected in calculating idsa but not neglected in calculating rid 0 b Figure 9 a MOSFET With Thevenin sources connected to the gate and source b Norton drain circuit Th venin Source Circuit Figure 10a shows the MOSFET With a Thevenin source connected to its gate7 the body lead connected to signal ground7 and the external drain load represented by the resistor Rm The Thevenin equivalent circuit seen looking into the source can be obtained from the Thevenin equivalent circuit seen looking into the BJT emitter by replacing 12900 With 1230 Tie With us vtb With vtg 1 x Rtb With Rtg Rm With Rm 7 With 3 setting a 17 and setting 00 The circuit is given in Fig 10b7 Where 12300 and us are given by my 7 0 1 37 30 1X 7 0 7 7 0 R d Q t 38 USOC Tia lbs US b Figure 10 a MOSFET With Thevenin source connected to gate b Thevenin source circuit The 7 0 Approximations The 7 0 approximations approximate 7 0 as an open circuit in all equations except the one for rid In this case7 the equations for idsa Gmg Gms rid 1130 and us are 1 1 1 39 quot G 7 G G G 39 Zdsc 2d 7719th msvts mg 1X T Rts ms T Rts T0 T HRts or Rm V 1 R 40 quotd 1 7 Bisr 131 TO r 3 l U 12900 13X m T 41 The simpli ed T model the hybrid 7T model and the T model respectively are given Figs 11 7 13 If 7 0 00 then rid is an open circuit in each Because 7 0 no longer connects to the source there is only one source current and is Figure 13 T model With the 7 0 approximations Summary of Models Figure 14 summarizes the four equivalent circuits derived above For the case Where the body is connected to the source set X 0 in the equations Example Ampli er Circuits This section describes several examples Which illustrate the use of the smallesignal equivalent circuits derived above to Write by inspection the voltage gain the input resistance and the output resistance of several ampli er circuits Figure 14 Summary of the smallesignal equivalent circuits Set X 0 if the body is connected to the source CommonSource Ampli er Figure 15a shows a commonesource ampli er The active device is M1 lts load consists of a currentemirror active load consisting of M2 and M3 The current source IQ sets the drain current in M3 Which is mirrored into the drain of M2 Because the sourceetoedrain voltage of M2 is larger than that of M37 the Early effect causes the dc drain current in M2 to be slightly larger than IQ The input voltage can be written 111 VB 157 Where VB is a dc bias voltage Which sets the drain current in M1 It must be equal to the drain current in M2 in order for the dc component of the output voltage to be stable In any application of the circuit7 VB would be set by feedback Looking out of the drain of M17 the resistance to ac signal ground is thl 7 02 Figure 15 a CMOS commonesource ampli er b Commonedrain ampli er The voltage gain of the circuit can be Written voizd1sc v0 7 vi vi Zc11sa Gmgl gtlt Tidl Wm 42 Where Gmgl is given by Eq 317 Tidl is given by Eq 307 and R331 R3 The body effect cancels if RS 0 The output resistance is given by Tout Tidl 11702 43 CommonDrain Ampli er Figure 15b shows a commonedrain ampli er The active device is M1 lts load consists of a currentemirror active load consisting of M2 and M3 The current source IQ sets the drain current in M3 Which is mirrored into the drain of M2 As With the commonesource ampli er the Early effect makes the drain current in M2 slightly larger than that in M3 The input voltage can be written 111 VB 112 Where VB is a dc bias voltage Which sets the dc component of the output voltage Looking out of the source of M1 the resistance to ac signal ground is Rtsl 702 The voltage gain can be Written amp Usloc v0 1 701 702 44 vi 39Ui Usloc 1 X1 T01 7 31 702 7 23931 Where Tislis given by Eq The output resistance is given by Tout TislHTo2 45 CommonGate Ampli er Figure 16a shows a commonegate ampli er The active device is M1 lts load consists of a currentemirror active load consisting of M2 and M3 The current source IQ sets the drain current in M3 Which is mirrored into the drain of M2 As With the commonesource ampli er the Early effect makes the drain current in M2 slightly larger than that in M3 The dc voltage VB is a dc bias voltage Which sets the drain current in M1 Which must be equal to the drain current in M2 in order for the dc component of the output voltage to be stable In any application of the circuit VB would be set by feedback Looking out of the drain of M1 the resistance to ac signal ground is thl 7 02 2 3 4 vooc 4 7 f 030 V a b Figure 16 a CMOS Commonegate ampli er b CMOS differential ampli er The voltage gain of the circuit can be Written E M v 0 Gmsl gtlt TileTOZ 46 vi 39Ui Zc11sa Where Gmsl is given by Eq 32 and Tidl is given by Eq The input and output resistances are given by Tin Ri Tisl 47 Tout 7 z39cl1H7 02 48 Where Tislis given by Eq Differential Ampli er A MOS differential ampli er with an active currentemirror load is shown in Fig 16b The object is to determine the Norton equivalent circuit seen looking into the output To do this the output is connected to ac signal ground which is indicated by the dashed line It will be assumed that the Early effect can be neglected in all devices in calculating iosa but not neglected in calculating Tom ie we use the 7 0 approximations We can write iosc id1sa id3sa id1sa id4sa id1sa id2sa 49 Because the tail supply is a current source the currents idl and Q2 can be calculated by replacing v and 1222 with their differential components In this case the ac signal voltage at the sources of M1 an M2 is zero Let vil vid2 and 1222 7vid2 where vid v 7 1222 It follows by symmetry that id2sa 722mm so that iosa is given by UV 2030 22d1sa2Gmgl Ed 1 l vim 2 v 7 v 50 1X T 2 gm1vz1 v22 where Eq 35 with R 0 is used for Gmg Note that the body effect cancels This is because the sourceetoebody ac signal voltage is zero for the differential input signals The output resistance is given by Tout T01HT03 51 Note that Tidl 701 because Rtsl Rts2 0 for the differential input signals SmallSignal HighFrequency Models Figures 17 and 18 show the hybrideTr and T models for the MOSFET with the gateesource capacitance 093 the sourceebody capacitance csb the drainebody capacitance cdb the drainegate capacitance cdg and the gateebody capacitance cgbadded These capacitors model charge storage in the device which affect its highefrequency performance The rst three capacitors are given by 2 cg EWLCW 52 st C b 53 S 1 VSB 012 Cdb i 54 1 VDB 012 where V33 and VDB are dc bias voltages 0st and cdbo are zeroebias values and 0 is the builtein potential Capacitors CW and cgb model parasitic capacitances For lC devices cgd is typically in the range of l to 10 fF for small devices and cgb is in the range of 004 to 015 fF per square micron of interconnect Figure 17 Highefrequency hybrideTr model

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