### Create a StudySoup account

#### Be part of our community, it's free to join!

Already have a StudySoup account? Login here

# Analog Electronics ECE 3050

GPA 3.64

### View Full Document

## 14

## 0

## Popular in Course

## Popular in ELECTRICAL AND COMPUTER ENGINEERING

This 0 page Class Notes was uploaded by Cassidy Effertz on Monday November 2, 2015. The Class Notes belongs to ECE 3050 at Georgia Institute of Technology - Main Campus taught by William Leach in Fall. Since its upload, it has received 14 views. For similar materials see /class/233860/ece-3050-georgia-institute-of-technology-main-campus in ELECTRICAL AND COMPUTER ENGINEERING at Georgia Institute of Technology - Main Campus.

## Reviews for Analog Electronics

### What is Karma?

#### Karma is the currency of StudySoup.

#### You can buy or earn more Karma at anytime and redeem it for class notes, study guides, flashcards, and more!

Date Created: 11/02/15

Ideal Op Amp Circuits The operational ampli er or op amp as it is commonly called is a fundamental active element of analog circuit design It is most commonly used in ampli er and analog signal processing circuits in the frequency band from 0 to 100 kHz Highefrequency op amps are used in applications that require a bandwidth into the MHZ range The rst op amps were vacuumetube circuits which were developed for use in analog computers Modern op amps are fabricated as integrated circuits that bare little resemblance to the early circuits This chapter covers some of the basic applications of the op amp It is treated as an ideal circuit element without regard to its internal circuitry Some of the limitations imposed by noneideal characteristics are covered in the following chapter e notation used here is as follows Total quantities are indicated by lowercase letters with upper case subscripts eg 121 2390 TIN Smallesignal quantities are indicated by lowercase letters with lowerecase subscripts eg 11 2390 Tom Transfer function variables and phasors are indicated by upper case letters and lowercase subscripts eg Vi Io Zin 11 The Ideal Op Amp The ideal op amp is a three terminal circuit element that is modeled as a voltageecontrolled voltage source That is its output voltage is a gain multiplied by its input voltage The circuit symbol for the ideal op amp is given in Fig 11a The input voltage is the difference voltage between the two input terminals The output voltage is measured with respect to the circuit ground node The model equation for the output voltage is 120 A 12 7 11 11 where A is the voltage gain 12 is the voltage at the noneinverting input and v is the voltage at the inverting input The controlled source model of the ideal op amp is shown in Fig 11b i t i u a 39u gt gt 11 0gt 1 11 o v 0 U Av v T gt 74 739 a b Figure 11 a Opamp symbol b Controlledesource model The terminal characteristics of the ideal op amp satisfy four conditions These are as follows 1 The current in each input lead is zero 2 The output voltage is independent of the output current ii IDEAL OP AMP CIRCUITS 3 The voltage gain A is independent of frequency 4 The voltage gain A is very large approaching in nity in the limit The rst condition implies that the resistance seen looking into both input terminals is in nite The second implies that the voltage gain is independent of the output current This is equivalent to the condition that the output resistance is zero The third implies that the bandwidth is in nite The fourth implies that the difference voltage between the two input terminals must approach zero if the output voltage is nite For it to act as an ampli er the op amp must have feedback applied from its output to its inverting input That is part of the output voltage must be sampled by a network and fed back into the inverting input This makes it possible to design an ampli er so that its gain is controlled by the feedback network To illustrate how feedback affects the op amp consider the circuits shown in Fig 12 The networks labeled N1 and NF respectively are the input and feedback networks The op amp of Fig 12a has positive feedback whereas the op amp of Fig 12b has negative feedback Let a unit step of voltage be applied to the input of each circuit at t 0 The arrows in the gures indicate the directions in which the input voltages change ie each input voltage increases For the circuit of Fig 12a the voltage increase at vi is fed through the N1 network to cause the voltage to increase at the 12 terminal This is ampli ed by a positive gain A and causes the output voltage to increase This is fed back through the NF network to further increase the voltage at the 11 terminal The arrow for the feedback voltage is enclosed in parentheses to distinguish it from the arrow for the initial increase in voltage This causes the output voltage to increase further causing 12 to increase further etc It follows that the circuit is not stable with positive feedback Figure 12 a Op amp with positive feedback b Op amp with negative feedback For the circuit of Fig 12b the voltage increase at the input is fed through the N1 network to cause the voltage to increase at the 1 terminal This is ampli ed by a negative gain 7A and causes the output voltage to decrease This is fed back through the NF network to cause the voltage at the 1 input to decrease thus tending to cancel the initial increase caused by the input voltage Because the v voltage is decreased by the feedback it follows that 110 is decreased also Thus the circuit is stable When negative feedback is used in an op amp circuit the feedback tends to force the voltage at the 1 input to be equal to the voltage at the 12 input It is said that a virtual short circuit exists between the two inputs A virtual short circuit between two nodes means that the voltage difference between the nodes is zero but there is no branch for a current to ow between the nodes There is no virtual short circuit between the v and 11 inputs to an op amp which has positive feedback If it has both negative and positive feedback the virtual short circuit exists if the negative feedback is greater than the positive feedback We have used the concept of signal tracing in the circuits of Fig 12 to illustrate the effects of feedback Signal tracing is a simple concept which can be applied to any circuit to check for positive and negative feedback Circuits which have positive feedback are unstable in general and are not used for ampli er circuits With few exceptions the circuits covered in this chapter have only negative feedbac 12 IN VERTING AMPLIFIERS iii 1 2 Inverting Ampli ers 121 The Inverting Ampli er Figure 13a shows the circuit diagram of an inverting ampli er The input signal is applied through resistor R1 to the inverting op amp input Resistor RF is the feedback resistor which connects from the the output to the inverting input The circuit is called an inverting ampli er because its voltage gain is negative This means that if the input voltage is increasing or going positive7 the output voltage will be decreasing or going negative7 and vice versa The noneinverting input to the op amp is not used in the inverting ampli er circuit The gure shows this input grounded so that v 0 i i lt5 RF 0 1gt R1 11 v0 1 R r we R1 1quotin 7 lt1 1 Tout 39 a b Figure 13 a lnverting ampli er b Controlledesource model For the circuit of Fig 13a7 the voltage at the inverting input is given by v 7 ivoA For vo nite and A a 07 it follows that v a 0 Even though the v input is not grounded7 it is said to be a virtual ground because the voltage is zero7 ie at ground potential Because i 07 the sum of the currents into the v node through resistors R1 and RF must be zero7 ie i1 iF 07 where i1 vIRl and ip vORF Thus we can write i1ip0 0 12 This relation can be solved for the voltage gain to obtain v R v f eR j 13 The input resistance is calculated from the relation rm v1 i1 Because v 07 it follows that Tm R1 14 The output resistance is equal to the output resistance of the op amp so that Tout 0 15 The controlled source model of the inverting ampli er is shown in Fig 13b Example 1 Design an inverting ampli er with an input resistance of QkQ an output resistance of 100 Q and an openecircuit voltage gain of 730 an inverting decibel gain of 295dB Solution The circuit diagram for the ampli er is given in Fig 14a For an input resistance of QkQ Eq 14 gives R1 QkQ For a voltage gain of 730 it follows from Eq that RF 60 k9 For an output resistance of 100 Q the resistor R0 100 9 must be used in series with the output as shown in the gure Example 2 Calculate the voltage gain of the circuit of Fig 14a if a 1 k9 load resistor is connected from the output to ground The circuit with the load resistor is shown in Fig 41 iv IDEAL OP AMP CIRCUITS Figure 14 a Circuit for Example 1 b Circuit for Example 2 c Circuit for Example 3 Solution The voltage gain decreases when BL is added because of the voltage drop across R0 By voltage division the gain decreases by the factor RL 7 1000 g RORL 1000100 11 It follows that the loaded voltage gain is IO11 X 730 7273 an inverting decibel gain of 287 dB Example 3 For the inverting ampli er circuit of Fig 14 b investigate the e ect of connecting the feedback resistor RF to the load resistor RL rather than to the op amp output terminal The modi ed circuit is shown in Fig 14c Solution Because i1 iF 0 it follows that v1R1 voRF 0 This gives the voltage gain 120121 7 FRl Because this is independent of RL it follows that the output resistance of the circuit is zero Thus the circuit looks like the original circuit of Fig 14b with R0 0 With R0 7E 0 the op amp must put out a larger voltage in order to maintain a load voltage that is independent of R0 Let v o be the voltage at the op amp output terminal in Fig 14c By voltage division the output voltage is given by 11 0 RLHRF v o RLHRFR0 It follows that do is larger than 110 by the factor 1 RO RLHRF Because this is greater than unity R0 causes the op amp to work harder to put out a larger output voltage We conclude that a resistor should not be connected in series between the op amp output terminal and the connection for the feedback resistor 122 The Inverting Ampli er with T Feedback Network If a high voltage gain is required from an inverting ampli er Eq shows that either RF must be large R1 must be small or both If R1 is small the input resistance given by Eq 14 may be too low to meet speci cations The inverting ampli er with a T feedback network shown in Fig 15a can be used to obtain a high voltage gain without a small value for R1 or very large values for the feedback resistors t N IN VERTIN G AMPLIFIERS V R2 R4 R2R3R4 v1 1 0 a Figure 15 a lnverting ampli er with a T feedback network b Equivalent circuit for calculating v0 The solution for the voltage gain is simpli ed by making a Thevenin equivalent circuit at the v terminal looking to the right through R2 The circuit is given in Fig 15b Because i1 iF 0 it follows that v1 vOR3 1 gtlt 0 16 R1 R3R4 R2R3HR4 This equation can be solved for the voltage gain to obtain v0 7 R2 R4 R2 v I lR1Rl1Rsl 1397 The output resistance of the circuit is zero The input resistance is R1 Example 4 For the inverting ampli er with a Tfeedback network in Fig 15a specify the resistor values which give an input resistance of 10 k9 and a gain of 7100 The maximum resistor value in the circuit is limited to 100 k9 Solution To meet the input resistance speci cation we have R1 10 k9 Let R2 R4 100 k9 It follows from Eq 17 that R3 is given by R 7 R2R4 3 7ivoU1R1 Ra R4 This equation gives R3 125k9 123 The Currentto Voltage Converter The circuit diagram of a currentetoevoltage converter is shown in Fig 16a The circuit is a special case of an inverting ampli er where the input resistor is replaced with a short circuit Because the v terminal is a virtual ground the input resistance is zero The output resistance is also zero Because i1 iF 0 and v0 iFRF it follows that the transresistance gain is given y 7 0 iRp 18 21 Figure 16b shows the currentetqvoltage converter with a current source connected to its input Because RS connects from a virtual ground to ground the current through R3 is zero It follows that i1 is and v0 RFZ39S Thus the output voltage is independent of S vi IDEAL OP AMP CIRCUITS i i F F lt RF lt RF 1 quot 1 gt gt v v 0 15 RS 0 T a 7 T b Figure 16 a Currentetoevoltage converter b Curcuit with an input current source 13 NonInverting Ampli ers 131 The NonInverting Ampli er Figure 17a shows the circuit diagram of a noneinverting ampli er The input voltage 111 is applied to the noneinverting op amp input A voltage divider consisting of resistors RF and R1 connects from the output node to the inverting input The circuit is called a noneinverting ampli er because its voltage gain is positive This means that if the input voltage is increasing or going positive7 the output voltage will also be increasing or going positive If the circuit diagrams of the inverting and the noneinverting ampli ers are compared7 it can be seen that the circuits are the same if 111 0 Thus the only difference between the two circuits is the node at which the input voltage is applied 1 0 b Figure 17 a Noneinverting ampli er b Controlledesource model For the circuit of Fig 17a7 the voltage difference between the two op amp input terminals is given by 11 7 v voA For 120 nite and A a 07 it follows that 12 a 12 It is said that a virtual short circuit exists between the two inputs because there is no voltage difference between the two terminals For 239 07 the condition that 12 1 requires v1 and 110 to satisfy the equation R1 1 v7 gt 1 1 19 I 0 RF R1 lt gt where voltage division has been used for 12 This can be solved for the voltage gain to obtain v0 RF 1 110 111 R1 The input and output resistances are given by Tm 00 111 13 N ONJN VERTIN G AMPLIFIERS vii Tout 0 112 The controlled source model for the noneinverting ampli er is shown in Fig 17b Example 5 Design a noneinuerting ampli er which has an input resistance of 10 k9 an openecircuit voltage gain of 20 a decibel voltage gain of 26 dB and an output resistance of 600 Q The feedback network is speci ed to draw no more than 01mA from the output of the op amp when the openecircuit output voltage is in the range 710V 3 110 3 10V Solution The circuit diagram for the ampli er is shown in Fig 18 To meet the input resistance speci cation we have Ri 10 k9 For the speci ed current in the feedback network we must have 01 mA 3 10 RF R1 If the equality is used we obtain RF R1 100 k9 For the speci ed openecircuit voltage gain Eq 110 gives 1 RFR1 20 or RF 19R1 It follows that R1 5kQ and RF 95 k9 To meet the output resistance speci cation we must have R0 600 Q Figure 18 Circuit for Example 5 Example 6 Examine the e ect of a connecting a resistor between the 11 node and the 1 node in the noneinuerting ampli er of the circuit for Example 5 Solution For an ideal op amp the voltage difference between the 11 and 1 terminals is zero It follows that a resistor connected between these nodes has no current owing through it Therefore the resistor has no apparent effect on the circuit This conclusion applies also for the inverting ampli er circuit of Fig 3 With physical op amps however a resistor connected between the 11 and the 1 terminals can affect the performance of the circuit by reducing the effective openeloop gain 132 The Voltage Follower The voltage follower or unityegain buffer is a unityegain noneinverting ampli er The circuit diagram is shown in Fig 19a Compared to the noneinverting ampli er of Fig 17a the feedback resistor RF is replaced by a short circuit and resistor R1 is omitted Because the output node is connected directly to the inverting input instead of through a voltage divider the circuit is said to have 100 feedback Because 11 12 it follows that 110 121 Therefore the circuit has unity voltage gain The voltage follower is often used to isolate a low resistance load from a high output resistance source That is the voltage follower supplies the current to drive the load while drawing no current from the input circuit Example 7 Figure 19b shows a source connected to a load with a voltage follower It is given that RS 10 k9 and RL 100 Q a Calculate 120 b Calculate 110 if the voltage follower is removed and the source connected to the load Solution a With the voltage follower there is no current through RS so that the voltage at the op amp input is 03 It follows that 110 03 b If the voltage follower is removed and the source is connected directly to the load 120 is given by 110 vsRLRs RL 123101 This is a decrease in output of 20 log 101 401 dB This example illustrates how a unity gain ampli er can increase the gain of a circuit IDEAL OP AMP CIRCUITS viii 1 1 v0 a Figure 19 a Voltage follower b Circuit for Example 7 133 Ampli er with Voltage and Current Feedback Figure 110a shows the circuit diagram of a noneinverting ampli er in which the voltage fed back to the inverting input of the op amp is a function of both the load voltage and the load current To solve for the output voltage it is convenient to rst form the Thevenin equivalent circuit seen by the load resistor RL The circuit is shown in Fig 110b It consists of a voltage source in series with a resistor The voltage source has a value equal to the openecircuit load voltage ie the output voltage with RL a 00 The resistor has a value equal to the ratio of the openecircuit load voltage to the shortecircuit load current ie the output current with RL 0 1 1 T 739 Av v v 7 4 1 1 R o a R quot F R quot v R quot 1 Lj 1 0 0ac L5 0 8 R21 a b Figure 110 a Noneinverting ampli er with voltage and current feedback b Thevenin equivalent circuit seen by the load With RL 00 the openecircuit load voltage is given by 120OC 2391 RF R1 Because there is a virtual short circuit between the 12 and the 1 terminals it follows that 2391 121 R1 R2 It follows that 12mm can be written R1 RF Uooa mm With RL 0 there can be no current through RF or R1 so that 111 v iOSCR2 Thus iosa is given by 113 1 20M R 114 The output resistance of the circuit is given by Uooa R1 RF R 115 Tom iOsa 2 R1 R2 By voltage division it follows from Fig 110b and Eq 113 that the output voltage can be written R1 RF RL RL X 116 v0 Umoa Tout RL W R1 R2 Tom RL 14 SUMMING AMPLIFIERS ix 134 The Negative Impedance Converter Although it is not an ampli er7 the negative impedance converter is an application of the noneinverting con guration For the circuit in Fig 111a7 the resistor R bridges the input and output terminals of a noneinverting ampli er We can write rm 117 2391 118 110 1 111 119 Solution for Tm yields 712423 120 Thus the circuit has a negative input resistance Tin R Figure 111 Negative impedance converters a Negative input resistance b Negative input capacitance A resistor in parallel with another resistor equal to its negative is an open circuit It follows that the output resistance of a noneideal current source ie one having a nonein nite output resistance7 can be made in nite by adding a negative resistance in parallel with the current source Negative resistors do not absorb power from a circuit lnstead7 they supply power For example7 if a capacitor with an initial voltage on it is connected in parallel with a negative resistor7 the voltage on the capacitor will increase with time Relaxation oscillators are waveform generator circuits which use a negative resistance in parallel with a capacitor to generate ac waveforms The resistor is replaced with a capacitor in Fig 111b In this case7 the input impedance is R11 Z1 L 121 m RF ij waZRFC J W It follows that the input impedance is that of a frequency dependent inductor given by R1 LEquot wZRFC 122 1 4 SumIning Ampli ers 141 The Inverting Summer The inverting summer is the basic op amp circuit that is used to sum two or more signal voltages7 to sum a dc voltage with a signal voltage7 etc An inverting summer with four inputs is shown in Fig 112a If all x IDEAL OP AMP CIRCUITS inputs are grounded except the v input where j 1 2 3 or 4 Eq for the inverting ampli er can be used to write vo 7 RFRjv1j It follows by superposition that the total output voltage is given by RF RF RF RF 7 7 7 7 123 U0 R1 111 R2 112 R3 U13 R4 U14 l The input resistance to the jth input is Rj The output resistance of the circuit is zero R 1 R R R M F 1 F v11 R2 15v 012 R5 ulshlyew m Ww o w Figure 112 a Four input inverting summer b Circuit for Example8 Example 8 Design an inverting summer which has an output voltage given by vo 3 7 2v1 Assume that 15V and 715V supply voltages are available Solution The output contains a dc term of 3 V This can be realized by using the 715V supply as one input The circuit is shown in Fig 112b For the speci ed output we can write 715gtlt7RFR1 3 and iRFRQ 72 If RF is chosen to be 3kQ it follows that R1 15kQ and R2 15kQ 142 The NonInverting Summer A noneinverting summer can be realized by connecting the inputs through resistors to the input terminal of a noneinverting ampli er Unlike the inverting ampli er however the input resistors do not connect to a virtual ground Thus a current ows in each input resistor that is a function of the voltage at all inputs This makes it impossible to de ne the input resistance for any one input unless all other inputs are grounded The circuit diagram for a foureinput noneinverting summer is shown in Fig 113a To solve for the output voltage it is convenient to rst make Norton equivalent circuits at the v terminal for each of the inputs The circuit is shown in Fig 113b Eq 110 can be used to write the equation for v0 as follows v0 v 1 121 1 U12 U13 1214 RF R R R R l 124 ampng ampw2H ampHaRJ lt gt The output resistance of the circuit is zero If the vm through v14 inputs are grounded the input resistance to the v11 node is given by Tim R1 R2HR3HR4HR5 125 The input resistance to the other inputs can be written similarly 14 SUMMING AMPLIFIERS xi 4 U14w Figure 113 a Four input noneinverting summer b Equivalent circuit for calculating 120 Example 9 Design a twoeinput noneinuerting summer which has an output voltage given by U0 8U11 U12 With either input grounded the input resistance to the other input terminal is speci ed to be 10kQ In addition the current which flows in the grounded input lead is to be 110 the current that flows in the ungrounded lead Solution The circuit is shown in Fig 114 By symmetry it follows that R2 R1 For the input resistance speci cation we must have R1 R1HR3 10 k9 lf 1112 is grounded i2 is given by current division i2 7i1R3 R3 R1 For i2 7i110 we have R3 R3 R1 110 It follows from these two equations that R3 1099k9 101 k9 and R1 R2 9R3 1011 k9 909 k9 Figure 114 Circuit for Example 9 If v11 v12 121 it follows that 120121 16 Thus we can write the design equation 12 120 R3 RF 16 gtlt 1 v1 12 R3R12 R4 It follows from this equation that 1 RFR4 88 This can be achieved with R4 270 Q and RF 235 k9 Xii IDEAL OP AMP CIRCUITS 15 Differential Ampli ers 151 The Single Op Amp Diff Amp A di erential ampli er or di amp is an ampli er which has two inputs and one output When a signal is applied to one input7 the diff amp operates as a noneinverting ampli er When a signal is applied to the other input7 it acts as an inverting ampli er The circuit diagram of a single op amp diff amp is shown in Fig 115a Superposition can be used to write the equation for 110 as follows RF RF R2 RF RF 7 1 7 7 1 7 126 v0 Ult R3 1112 R3 1111 R1 RQlt RS Um R3 where Eqs and 110 have been used 1132 R1RZ U R a Fv v R 11 12 3 Figure 115 a Diff amp circuit b Equivalent circuit for the special case of a true diff amp b The output resistance of the diff amp is zero The input resistance to the 1111 node is given by Tinl R1 Ra 127 The current 22 which ows in the 1112 input lead is a function of the voltage at the 1111 input It is given by v12 7 v 1 R2 22 1112 i 111 13928 R3 R3 R1 R2 where v 12 has been used The input resistance to the 1112 input is given by 7322 111222 It can be seen that 7322 is a function of 1211 For example7 v11 0 gives Tm2 R37 1111 71212 gives Tm2 R3 R1 R2 R1 2R2 111 1112 giVeS Tinz R3 1 RzR17 etc 152 The True Diff Amp The output voltage of a true di amp is zero if 1111 1212 It follows from Eq 126 that the condition for a true diff amp is R2 7 RF R1 7 R3 To achieve this condition7 it is common to make R1 R3 and R2 RF In this case7 the output voltage can be written 129 U0 F U11 U12 13930 The controlledesource equivalent circuit of the single op amp true diff amp is shown in Fig 115b 15 DIFFERENTIAL AMPLIFIERS xiii Example 10 For the di amp circuit of Fig 115a it is given that R1 R3 10kQ and R2 RF 20 k9 Solve for the output voltage the input resistance to the v11 terminal and the input resistance to the vm terminal for the three cases v11 0 v11 7v and v11 v12 Solution Because RFR3 RgRl the output voltage is given by Eq 130 It follows that vo 2 v11 7 v12 The input resistance to the v11 node is 30 k9 As described above the input resistance to the vm terminal is a function of v11 For v11 0 it is 10 k9 For v11 7v it is 6kQ For v11 v12 it is 40 k9 153 Differential and CommonMode Voltage Gains Figure 116 shows a single op amp diff amp circuit with three sources at its input The two input voltages are given by v11 voM 7 131 39U v12 UCM 7 3D 132 The voltage voM is called the commonimode input voltage because it appears equally at both inputs The voltage vD is called the di erential input voltage because oneihalf of its value appears at each input with opposite polarities i i115 1 o Figure 116 Diff amp with differential and commonimode input sources It is often convenient to analyze diff amp circuits by expressing the input voltages as commonimode and differential components The voltages vCM and vD can be expressed in terms of v11 and v12 as follows 39UD 1211 i 1212 v v UCM M 134 2 These two equations can be used to resolve any two arbitrary input voltages into differential and common mode components For example v12 0 gives vD v11 and vCM v112 v12 ivn gives vD 2v11 and vCM v12 v11 gives vD 0 an voM v11 etc By Eq 126 the output voltage of the diff amp in Fig 116 can be written UD R2 RF UD RF v v 1 v 7 0 CM 2 R1R2 R3 CM 2 R3 RFR1 12 RF R2 R3 RF 1 35 R2 17 UCMR1R2 132133 2 R3 RFR1R2 xiv IDEAL OP AMP CIRCUITS This equation can be used to de ne the differential and commonemode voltage gains respectively as follows Ad 1 R2R3RF 136 Up 2R3 RF R1 R2 I 110 R2 RFRl A 1 7 13 cm voM R1 R2 R2133 7 If RFR2 RgRl these equations give Ad RFR3 and Adm 0 154 The CommonMode Rejection Ratio For a true diff amp the commonemode voltage gain is zero In practice it is difficult to achieve a common mode gain that is exactly zero because of resistor tolerances A gure of merit for the true diff amp is the ratio of its differential voltage gain to its commonemode voltage gain This is called the commonemode rejection ratio or CMRR Ideally it is in nite The CMRR of the circuit in Fig 116 is given by R R R 3 2 Ad is 1 R 1R CMRR 138 Adm R 1 7 RER RiRz 13st This is often expressed in decibels by the relation 20 log CMRR Example 11 For the di amp in Fig 117 solve for no the current i the resistance seen by the generator 1211 1212 and the commonemode input voltage Figure 117 Circuit for Example 11 Solution By Eq 130 no is given by RF 1 v 0 R3 D Because there is a virtual short circuit between the inverting and the noneinverting op amp inputs it follows that i is given by 39UD Z 2R3 Thus the generator sees the resistance 2R3 To solve for 1211 and 1212 we can write v v R v11ZR3RF2 l 3R3RFD hl 39UD RF 39UI239UI1quotUD3 R 31 15 DIFFERENTIAL AMPLIFIERS xv The common7mode component of 1111 and 1112 is given by v vnwu 22 CM 2 R3 2 2 Thus the op amp forces a common7mode voltage at the two diff amp inputs that is equal to one7half the output voltage 155 The Switch Hitter The single op amp diff amp circuit of Fig 118a is known as a switch hitter The signal applied to the non7inverting op amp input is taken from the wiper of a potentiometer To solve for the output voltage as a function of the position of the wiper we denote the potentiometer resistance from wiper to ground by xRp where 0 S at S 1 By voltage division it follows that the voltage at the non7inverting op amp input is 12 111 The circuit is redrawn in Fig 118b with separate sources driving the inverting and the non7inverting inputs By superposition of the two sources the output voltage can be writ en v0 212 7 v1 21 7 1 111 139 where Eqs and 110 have been used It follows that the voltage gain of the circuit is 235 7 1 This has the values 71 for ac 0 0 for ac 05 and 1 for ac 1 Thus the circuit gain can be varied from 71 through 0 to 1 as the position of the potentiometer wiper is varied RF RF 1 0 an xRP1 xRP b Figure 118 a Switch hitter b Equivalent circuit 156 The Two Op Amp Diff Amp A two op amp diff amp is shown in Fig 119 By superposition the output voltage of this circuit is given by RF2 RF2 2 v 7 1 7 v v 140 0 R3 01 R2 12 R1R3 R2 12 where Eq has been used The circuit operates as a true diff amp if either of two conditions is satis ed These are R1 RF1 and R3 R2 or R1 R2 and RF1 R3 Under either condition the expression for the output voltage reduces to RFlRF2 RF v 1 RF 1211 7 1212 141 The input resistance to the 1211 input is R1 The input resistance to the 1112 input is R2 The output resistance is zero The two op amp diff amp has two advantages over the single op amp diff amp First the input resistance to either input is not a function of the voltage at the other input Thus the common7mode voltage at the inputs cannot be a function of the output voltage as it is with the single op amp diff amp Second when the circuit is used as a true diff amp the differential voltage gain can be varied by varying a single resistor without simultaneously changing the common7mode voltage gain This resistor is Rm The single op amp diff amp does not have this feature 00 IDEAL OP AMP CIRCUITS Figure 119 Two op amp diff amp Example 12 Design a two op amp di amp which has a di erential voltage gain of 20 a commonemode voltage gain of U and an input resistance to each input of 10 k9 Solution For the circuit of Fig 119 the input resistance speci cations can be met with R1 R2 10 k9 For the differential gain speci cation it follows from Eq 141 that RFQRQ 20 Thus we must have RF2 20019 For a commonemode gain of zero we must have either R1 RF1 and R3 R2 or R1 R2 and RF1 R3 Because we have already speci ed that R1 R2 we must have RF1 R3 The value for these resistors is arbitrary We specify RF1 R3 20019 157 The Instrumentation Ampli er The diff amp circuit of Fig 120 is known as an instrumentation ampli er In some applications it is called an active transformer To solve for 120 we use superposition of the inputs 1111 and 1212 With 1112 0 the 1 terminal of op amp 2 is at virtual ground and op amp 1 operates as a noneinverting ampli er By Eq 110 its output voltage is given by R 01 1 F1 142 R1 Because there is a virtual short circuit between the 12 and 1 inputs of op amp 1 the voltage at the lower node of R1 is 1211 It follows that op amp 2 operates as an inverting ampli er By Eq 13 its output voltage is given by RFl 7 143 U02 R1 U11 Op amp 3 operates as a true diff amp By Eq 130 its output voltage is given by Rm RM RM 7 1 2 144 110 R2 U01 1102 R2 R1 v11 Similarly for 1211 0 110 is given by RF2 RFl 7 1 2 145 110 R2 R1 1212 By superposition the total output voltage is RF2 RFl 1 2 7 146 110 R2 R1 U11 U12 This is the voltage output of a true diff amp The input resistance to each input of the ampli er is in nite The output resistance is zero 15 DIFFERENTIAL AMPLIFIERS xvii Figure 120 Instrumentation ampli er The instrumentation ampli er can be thought of as the cascade connection of two ampli ers The rst stage consists of op amps 1 and 2 Let its voltage gain be denoted by A1 The second stage consists of op amp 3 Let its voltage gain be denoted by A2 The two gains are given by v01 v02 RFi A 1 2 147 1 1211 i 1212 R1 R A2 7 v 0 148 1101 i 1102 R2 It can be seen that A1 represents the ratio of a differential output voltage to a differential input voltage The instrumentation ampli er is used in applications where a true diff amp is required with a very high commonemode rejection ratio A potentiometer connected as a variable resistor in series with R1 can be used to adjust the voltage gain without simultaneously changing the commonemode rejection ratio A potentiometer connected as a variable resistor in series with R3 can be used to optimize the CMRR To do this experimentally the two inputs are connected together and a commonemode signal voltage applied The potentiometer in series with R3 is adjusted for minimum output voltage Example 13 Design an instrumentation ampli er which has a di erential voltage gain of 100 a decibel gain of 40 dB and a commonemode voltage gain of zero Solution The gain of 100 must be divided between the two stages of the circuit It is convenient to give the input stage consisting of op amps 1 and 2 a gain of 10 and the second stage consisting of op amp 3 a gain of 10 Using Eqs 147 and 148 we can write the two design equations RFi R 12R 110 and R2 With two equations and four unknowns it is necessary to assign values to two of the resistors Let RF1 Rm 10 k9 It follows that R2 1 k9 and R1 1045 k9 222 k9 10 158 The Differential Output Ampli er Figure 121 shows the circuit diagram of a di erential output ampli er This circuit has two output voltages which have opposite polarities That is if 1201 is positive 1102 will be negative and vice versa Because the lower node of resistor R1 is at virtual ground Eq 110 can be used to write for 1101 R 1201 1 f 121 149 1 xviii IDEAL OP AMP CIRCUITS Because there is a virtual short between the inverting and noneinverting inputs to op amp 1 the upper node of R1 sees the input voltage v1 Thus Eq can be use to write for v02 R 1102 RFfm 150 1 1 1 01 gt Rm R1 R F2 02 Figure 121 Differential output ampli er In most applications of the differential output ampli er the condition v02 7v01 is desired When this is satis ed the ampli er is said to be a balanced differential output ampli er This requires the condition 1 RFlR1 RFQRl which reduces to RM RF2 R1 151 In this case the output voltages can be written RF2 v01 1102 R1 121 152 The differential output voltage is given by 2R v01 vo2 Rm 11 L53 1 Example 14 Design a balanced di erential output ampli er with an openecircuit voltage gain of 4 an input resistance of 10 k9 and a balanced output resistance of 600 Q The ampli er is to drive a 6009 load If the maximum peak output voltage from each op amp is i12V calculate the maximum peak load voltage and the output level in dBm for a sine wave input signal The dBm is the decibel output power referenced to the power me 1 mW Solution The circuit is shown in Fig 122 For the input resistance speci cation we have R 10 k9 For an openecircuit voltage gain of 4 it follows from Eq 153 that 2RF2R1 4 This can be satis ed by choosing RF2 20 k9 and R1 10 k9 Eq 151 gives RF1 10 k9 To achieve a 6009 balanced output resistance we must have R01 R02 and R01 R02 600 It follows that R01 R02 300 Q If the voltage output of op amp 1 peaks at 12 V the voltage output from op amp 2 peaks at 712V and the peak load voltage is vp 24 X 600 600 600 12V where voltage division has been used The output level in dBm is given by 2 2 Output Level 1010g g 10log 208 dBm ref 16 OP AMP DIFFERENTIATORS xix Figure 122 Circuit for Example 14 16 Op Amp Di 39erentiators 161 The Ideal Differentiator A di erentiator is a circuit which has an output voltage that is proportional to the time derivative of its input voltage Fig 123 gives the circuit diagram of an op amp differentiator The circuit is similar to the inverting ampli er in Fig 13 with the exception that resistor R1 is replaced by a capacitor It follows that Eq can be used to solve for the voltage gain transfer function of the differentiator by replacing R1 with the complex impedance of the capacitor The voltage gain transfer function is given b Vo RF Vi 7 1015 7 RFCls 154 RF Figure 123 ldeal differentiator Because a multiplication by s in the complex frequency domain is equivalent to a differentiation in the time domain7 it follows from the above equation that the time domain output voltage is given y d t 120 t iRFq m 155 dt Thus the circuit has the transfer function of an inverting differentiator with the gain constant RF Cl Because the gain constant has the units of seconds7 it is called the dz erentiator time constant The output resistance of the circuit is zero The input impedance transfer function is that of the capacitor Cl to virtual ground given y 1 015 With 5 jw it follows that a 0 as w becomes large This is a disadvantage because a low input impedance can cause large currents to ow in the input circuit gm 156 xx IDEAL OP AMP CIRCUITS 162 The Modi ed Differentiator With 5 jw it follows from Eq 154 that the magnitude of the voltage gain of the differentiator is wRFCl For large w the gain can get very high This is a disadvantage in circuits where outeofeband highefrequency noise can be a problem To limit the highefrequency gain7 a resistor can be used in series with Cl as shown in Fig 124a This also has the advantage that the highefrequency input impedance does not approach zero At high frequencies where Cl is a short7 the gain magnitude is limited to the value RFR1 and the input impedance approaches R1 The voltage gain transfer function of the circuit with R1 is given by Vo RF 1 7 7R C 15 Vi R11Cls F 15X 1R1C1s 7 This is of the form of the transfer function of a differentiator multiplied by the transfer function of a lowepass lter which has a pole time constant R101 E Vi 6 RF RF V R1 1 RI i V0 1 decdec 39 RFC1 1 a 1 R101 0 b Figure 124 a Modi ed differentiator b Bode plot for The Bode magnitude plot for the transfer function of Eq 157 is given in Fig 124b For to ltlt 1R1 Cl the asymptotic plot exhibits a slope of 1 decdec which is the proper slope for a differentiator In this band7 the voltage gain is given by VoVi E iijFCl At no 17 the magnitude of the gain is RFCl For to gtgt 1131017 the asymptotic slope is 0 and the magnitude of the gain shelves at the value RFRl It follows that the circuit with R1 acts as a differentiator only for frequencies such that to ltlt 1R101 The input impedance transfer function of the circuit with R1 is given by ZinR1LSR1XM 1 158 C R1015 This is of the form of a constant multiplied by the reciprocal of a highepass transfer function For 5 jw it follows that a R1 as w becomes large Example 15 Design a modi ed di erentiator which has a time constant of 10 ms and a pole frequency of 1 kHz For a 1V peak sineewaue input signal at 100 Hz calculate the peak sine wave output voltage and the relative phase of the output voltage Solution The circuit is shown in Fig 124a For the gain constant speci cation7 we must have RFCl 001 If we let Cl 01 uF7 it follows that RF 10019 For the pole frequency of 1000 Hz7 we must have R101 12771000 This gives R1 1000027139 159 k9 From Eq 1577 the voltage gain magnitude at f 100 Hz is given by V0 7 7 RFClj271100 7 001 X 277100 7 6 25 W 1j271100R1C1 7 1012 7 39 17 THE IN TEGRATOR xxi For a 1V peak input sine wave at 100 Hz it follows that the peak output voltage is 625V It follows from Eq 157 that the phase of the output signal with respect to the input signal is given by so 900 7 tan 1 27710013101 843 A perfect differentiator would have a phase of 900 Thus there is a phase error of 7570 Note that the negative sign in Eq 157 does not affect the phase This is because a negative sign indicates an inversion whereas a phase shift is associated with a shift in time If a sine wave is observed on the screen of an oscilloscope an inversion would ip the sine wave about the time axis A phase shift would shift the position of the zero crossings along the time axis 17 The Integrator 171 The Ideal Inverting Integrator An integrator is a circuit which has an output voltage that is proportional to the time integral of its input voltage The circuit for the integrator can be obtained by interchanging the resistor and the capacitor in the differentiator of Fig 123 The circuit is shown in Fig 125 The voltage gain transfer function is obtained from Eq by replacing RF with the complex impedance of the capacitor CF to obtain 271CF5 7 1 159 V R1 RlCFs 39 CF R Vi 1 V0 Figure 125 lnverting integrator Because a division by s in the complex frequency domain is equivalent to an integration in the time domain it follows from this equation that the time domain output voltage is given by 1 t 110 t 7 v1 739 dT 160 lt gt R1 CF 700 lt gt lt gt Thus the circuit has the transfer function of an inverting integrator with the gain constant 1R1 CF Because R101 has the units of seconds it is called the integrator time constant The input resistance to the circuit is R1 The output resistance is zero 172 The Modi ed Inverting Integrator At zero frequency CF is an open circuit and the op amp in the integrator circuit loses feedback For noneideal op amps this can cause undesirable dc offset voltages at the output To provide feedback at dc a resistor can be used in parallel with Up as shown in Fig 126a At low frequencies where CF is an open circuit the magnitude of the voltage gain is limited to the value RFRl The transfer function for the voltage gain of the integrator with RF is given by E iRFH 1CF5 1 RFCFS 1 7 161 RiCFS X 1RFCFS i xxii IDEAL OP AMP CIRCUITS where Eq has been used This is of the form of the transfer function of an ideal integrator multiplied by the transfer function of a highepass lter which has the pole time constant RF CF The Bode magnitude plot for the transfer function is given in Fig 126b For w ltlt 1RFCF the plot exhibits a slope of 0 For w gtgt 1RFCF the slope is 71 decdec which is the proper slope for an integrator It follows that the circuit with RF acts as an integrator only for frequencies such that w gtgt 1RFCF 5 Vi RF E R1 1 decdsc R1 V7 Va 0 L RFCF a b Figure 126 a Modi ed inverting integrator b Bode magnitude plot for Example 16 Design a modi ed integrator which has a time constant of 01 s and a pole frequency of 1 Hz For a 1V peak sineewaue input signal at 10 Hz calculate the peak sineewaue output voltage and the relative phase of the output voltage Solution The circuit is shown in Fig 126a For the time constant speci cation we have R101 01 If we take CF 01 uF it follows that R1 1 M9 For the pole frequency of 1 Hz we must have RFCF 1277 This gives RF 1 27139 X 01 X 10 6 159MB From Eq 161 the gain magnitude at f 10HZ is given by E 7 7 1 X j27110RFCF 7 159 70158 V j27r10R10F 1j27110RFCF r m 39 For a 1V peak input sine wave at 100 Hz it follows that the peak output voltage is 0158 V It follows from Eq 161 that the phase of the output signal with respect to the input signal is given by so 7 tan 1 27110RFCF 7843quot A perfect integrator would have a phase of 790 Thus there is a phase error of 570 As is discussed in Example 15 the negative sign in Eq 161 indicates that the output signal is inverted with respect to the input signal and does not represent a phase shift 173 The NonInverting Integrator The circuit diagram of a noneinuerting integrator is shown in Fig 127a The voltage output from the op amp is fed back to both its inverting input and to its noneinverting input Thus the circuit has both positive and negative feedback To solve for the voltage gain transfer function it is convenient to make two Norton equivalent circuits at the V node one looking toward the input through the left R and the other looking toward the output through the right R The circuit obtained is shown in Fig 127b where the two parallel 17 THE IN TEGRATOR xxiii resistors are combined into a single resistor of value RZ Because there is a virtual short between the V and the V inputs7 we can write Vo Vi Vo R 1 1 V V 162 2 R 2105 2 1RCs2 1 This equation can be solved for the voltage gain transfer function of the circuit to obtain V0 2 163 Vi ROS This is the transfer function of a noneinverting integrator with the gain constant QRC The time constant of the integrator is RCQ R1 R1 c Figure 127 a Noneinverting integrator b Equivalent circuit for calculating V0 c Equivalent circuit or m The input current in the circuit of Fig 127a can be solved for as follows goingruin 1 I R 7 R 7 R 1 ROS 13964 where V Vo2 has been used This equation can be solved for the input impedance transfer function to obtain Vi R 713205 Ii 7 R R205 The equivalent circuit which has this impedance is a resistor R in parallel with a negative inductor 71320 The equivalent circuit is given in Fig 127c Because the inductor is a short circuit at zero frequency7 it follows that the input impedance to the circuit is zero for a dc source gm 165 Example 17 The noneinverting integrator of Fig 127a has the circuit element values R 1kQ and C 1 uF For a sine wave input signal calculate the voltage gain of the circuit at the frequency f 100Hz In addition calculate numerical values for the circuit elements in the equivalent circuit for the input impedance Solution The voltage gain at f 100Hz is calculated from Eq 163 as follows V 2 7 W gtlt j27139100 71317 i xxiv IDEAL OP AMP CIRCUITS From Eq 1657 it follows that the input impedance circuit consists ofa 1000 Q resistor to ground in parallel with a negative inductor to ground having the value 71000 X 10 6 7 1 8 LowPass Ampli ers 181 The Inverting LowPass Ampli er This section covers several of the many op amp circuits which have a voltage gain transfer function that is of the form of singleepole lowepass and lowepass shelving transfer functions Fig 128a shows the circuit of an inverting lowepass ampli er The voltage gain is obtained from Eq by replacing RF with RFH 101 s It is given by E RFH 1CFS 7 X V 7 R1 7 R1 1RFCFS This is of the form of a gain constant RFRl multiplied by a lowepass transfer function having a pole time constant RFCF The Bode magnitude plot for the transfer function is given in Fig 128b The input resistance of the circuit is R1 The output resistance is zero 166 V RF A Vi R E V 1 R1 1 decdec i V0 CO 1 RF CF 0 b Figure 128 a lnverting lowepass ampli er b Bode magnitude plot for Example 18 Design an inverting lowepass ampli er circuit which has an input resistance of 10 k9 a low frequency voltage gain of 710 and a pole frequency of 10 kHz Solution The circuit diagram of the ampli er is shown in Fig 128a For an input resistance of 10 k9 we have R1 10 k9 The voltage gain transfer function is given by Eq 166 For a lowefrequency gain of 710 we have RF 10R1 100 k9 For a pole frequency of 10 kHz7 we have CF 1277104RF 159 pF A second inverting lowepass ampli er circuit is shown in Fig 129a The currents I17 I27 and IF are given by Vi I 167 1 R11CSHR2 10 1 I I I 168 2 11321Cs 11RzCs V I O 169 F RF where it is assumed that the V op amp input is at virtual ground and current division has been used for I2 The voltage gain of the circuit can be obtained from the relation I2 IF 0 to obtain Vo RF 1 7 x 170 Vi R1 R2 1R1HR2Cs 18 LOW7PASS AMPLIFIERS XXV This is of the form of a gain constant RF R1 R2 multiplied by a lowepass transfer function having a pole time constant R1HR2 C The Bode magnitude plot for the transfer function is given in Fig 129b I F R I1 12 lt F V gt 2 gt 1 V C a 5 0 Vi IZTI39II RF R1R2 R R 1 decdec 1 2 1 decdec R1 RliR 0 1I I1 1 2 R20 R1 ch b c Figure 129 a lnverting lowepass ampli er b Bode magnitude plot for c Bode magnitude plot for lZml The output resistance of the circuit is zero The input impedance is given by 1 R1HR2 Cs 11 1R2Cs 7 1 2m R1 EHRQ R1 R2 This transfer function is in the form of a lowepass shelving function having a pole time constant R20 and a zero time constant R1HR2 C The Bode magnitude plot of the impedance is given in Fig 129c The lowefrequency impedance is R1 R2 As frequency is increased7 the impedance decreases and shelves at the value R1 Example 19 Specify the circuit element values for the circuit of Fig 129a for an inverting voltage gain of unity and a pole time constant of 75 us What is the pole frequency in the voltageegain transfer function Solution Let C 001 uF and R2 R1 It follows from Eq 131 that RlllRQ C Bl2 C 75 X 10 6 Solution for R1 and R2 yields R1 R2 15kQ For an inverting voltage gain of unity7 we must have RF R1 R2 30 k9 The pole frequency in the transfer function has the frequency f 1 27775 X 10 6 212kHz 182 The NonInverting LowPass Ampli er Figure 130a shows a noneinverting lowepass ampli er consisting of a noneinverting ampli er With a RC lowepass lter at its input The voltage gain transfer function of the circuit is given by V0 V1 V0 1Cs RF RF 1 1 1 1 2 V ViXV R1Cs 131 R1 X1RCS 7 Where voltage division and Eq 110 have been used This is of the form of a gain constant 1 RFR1 multiplied by the transfer function of a lowepass lter having a pole time constant RC The Bode magnitude xxvi IDEAL OP AMP CIRCUITS plot for the transfer function is given in Fig 130b The output resistance of the circuit is zero The input impedance is given by 1 1 RCs Z v R R X m Cs ROS This is of the form of a resistor R multiplied by the reciprocal of a highepass transfer function 173 1 decdsc RC b Figure 130 a Noneinverting lowepass ampli er b Bode magnitude plot for Example 20 The noneinverting ampli er of Fig 130a is to be designed for a voltage gain of 12 The input lowepass lter is to have a cuto frequency of 100 kHz Specify the element values for the circuit Solution To meet the cutoff frequency speci cation7 it follows from Eq 172 that RC 1 277105 Either a value for R or a value for C must be speci ed before the other can be calculated Let C 510 pF It follows that R 31219 For a gain of 127 we must have 1 RFR1 12 If we choose R1 1k 27 it follows that RF 11 k9 183 The NonInverting LowPass Shelving Ampli er The circuit diagram of a noneinverting lowepass shelving ampli er is shown in Fig 131a The voltage gain is obtained from Eq 18 by replacing RF with RFH 1CFs It is given by V R 1 C R 1 R R C 01 Fll F5 1F F 1 F5 174 239 R1 R1 1 RFCFs This is of the form of a gain constant 1 RFR1 multiplied by a lowepass shelving transfer function having a pole time constant RFCF and a zero time constant RFHR1CF The Bode magnitude plot for the voltage gain is shown in Fig 131b The lowefrequency gain is 1 RFRl As frequency is increased7 the gain decreases and shelves at unity Example 21 The circuit of Fig 131a is to be designed for a lowefrequency gain of a 6dB boost The zero frequency in the transfer function is to be 100 Hz Specify the circuit element values and calculate the frequency at which the voltage gain is 3dB Solution For a lowefrequency gain of 2 it follows from Eq 174 that 1 RFR1 2 which gives RF R1 For the zero in the transfer function to be at 100 Hz7 it follows that RF HRl CF 1 277100 If we choose CF 01 F it follows that R1 RF 318k9 With 5 j2739rf7 the voltage gain transfer function can be written V0 1jf100 Vi 1jf50 19 HI GHiPASS AMPLIFIERS xxvii 1 decdec C0 1 1 F F RFR1CF 1W b Figure 131 a Noneinverting lowepass shelving ampli er b Bode magnitude plot for At the 3dB boost frequency we have 12 This condition gives 1 f1002 7 1 Home 2 This can be solved for f to obtain f 100 707Hz 1 9 HighPass Ampli ers 191 The Inverting HighPass Ampli er This section covers several of the many op amp circuits which have a voltage gain that is of the form of highepass and highepass shelving transfer functions Fig 132a shows an inverting highepass ampli er circuit The voltage gain is obtained from Eq by replacing R1 with R1 1015 It is given by V R R R C o F FX 71 15 175 Vi R11C1s R1 1RiCis This is of the form of a gain constant RFRl multiplied by a highepass transfer function having a pole time constant R101 The Bode magnitude plot for the voltage gain is given in Fig 132b The output resistance of the circuit is zero The input impedance transfer function is given by 1 1R1015 Z R R 1 6 m 1 015 1 X R1015 7 This is of the form of a resistance R1 multiplied by the reciprocal of a highepass transfer function Example 22 Design an inverting highepass ampli er circuit which has a gain of 710 and a pole time constant of 500 us The input impedance to the circuit is to be 10 k9 or higher Calculate the lower half power cuto frequency of the ampli er Solution The circuit is shown in Fig 132a The voltageegain transfer function is given by Eq 175 For the gain speci cation we must have RFR1 10 For the pole time constant speci cation we must have R101 500 X 10 6 Because there are three unknowns and only two equations one of the circuit elements must be speci ed before the others can be calculated Eq 176 shows that the lowest value of the input impedance is R1 Thus we must have R1 2 10 k9 lf R1 2 10 k9 it follows that Cl 3 005uF Let us choose Cl 0033 uF It follows that R1 152k9 and R2 15219 The lower halfepower cutoff frequency is f 1 27139 X 500 X 10 6 318 Hz IDEAL OP AMP CIRCUITS XXViii E Vi RF RF R1 C1 3 1 V39th V 1 decdac 0 C0 1 R161 0 b Figure 132 a lnverting highepass ampli er b Bode magnitude plot for 192 The NonInverting HighPass Ampli er Figure 133a shows a noneinverting highepass ampli er circuit The voltage gain transfer function is given V0 V V0 R RF RF RCs 1 1 1 V ViXV R1Cs R1 R1 X1RCS 77 where voltage division and Eq 110 have been used This is of the form of a gain constant 1 RFRl multiplied by a singleepole highepass transfer function having a pole time constant BC The Bode magnitude The output resistance of the circuit is zero The input by plot for the voltage gain is given in Fig 133b impedance transfer function is given by 1 1 RCs ZiniR FEiRXW 178 This is of the form of a resistance R multiplied by the reciprocal of a highepass transfer function 515 1 decdec b Figure 133 a Noneinverting highepass ampli er b Bode magnitude plot for Example 23 Design a noneinverting highepass ampli er which has a gain of 15 and a lower cuto frequency of QOHZ The input resistance to the ampli er is to be 10 k9 in its passband Solution The circuit is shown in Fig 133a In the ampli er passband7 C is a short circuit To meet the input resistance speci cation7 we must have R 10 k9 The voltageegain transfer function is given by Eq 177 For a lower halfepower cutoff frequency of 20 Hz7 we must have RC 1 27720 Solution for C yields C 0796 pF For the gain speci cation7 we must have 1 RFR1 15 or R1 RF14 lf RF 56 k9 it follows that R1 4m 110 THE OP AMP AS A COMPARATOR xxix 193 The NonInverting HighPass Shelving Ampli er The circuit diagram of a noneinuerting highepass shelving ampli er is shown in Fig 134a The voltage gain is given by Eq 110 with R1 replaced by R1 1 015 It follows that the gain can be written 2 1 RF 1RFR1015 179 Vi R11C1s 1R1C1s This is of the form of a highepass shelving transfer function having a pole time constant R101 and a zero time constant RF R1 Cl The Bode magnitude plot for the voltage gain is shown in Fig 134b It can be seen from the gure that the gain at low frequencies is unity At high frequencies7 the gain shelves at 1 R F R1 5 Vi Vi Va RF 11T1 R1 RF 1 a c 1 L 1T RFR1C R101 0 b Figure 134 a Noneinverting highepass shelving ampli er b Bode magnitude plot for Example 24 Design a highepass shelving ampli er which has unity gain at low frequencies a pole in its transfer function with a time constant of 75 us and a zero with a time constant of 75Ls What are the pole and zero frequencies and what is the gain at high frequencies Solution The circuit is shown in Fig 134a The voltageegain transfer function is given by Eq 179 For the pole time constant speci cation7 we must have R101 5 us For the zero time constant speci cation7 we must have R1 RF Cl 75 us Because there are three circuit elements and only two equations7 we must specify one element in order to calculate the other two Let Cl 0001 uF It follows that R1 75kQ and R2 75 k9 7 R1 675 k9 The zero frequency is fZ 1 27139 X 75 X 10 6 212 kHz The pole frequency is fp 1 27139 X 75 X 10 6 212 kHz The gain at high frequencies is 1 RFR1 1 67575 10 110 The Op Amp as a Comparator 1101 The Inverting Comparator A comparator is an active circuit element which has two input terminals and one output terminal The output voltage exhibits two stable states The output state depends on the relative value of one input voltage compared to the other input voltage The op amp is often used as a comparator Fig 135a shows the circuit diagram of an op amp used as an inverting comparator The voltage applied to the noneinverting input is the dc reference voltage VREF The output voltage is given by U0 A VREF 1 1 180 xm IDEAL OP AMP CIRCUITS where A is the voltage gain of the op amp For an ideal op amp we assume that A a 00 This implies that no a 00 for 111 lt VREF and no a 700 for 111 gt VREF However a physical op amp cannot have an in nite output voltage Let us denote the maximum value of the magnitude of the output voltage by VsAT We call VsAT the saturation voltage of the op amp 0 I U VSAT a 7 v VREF I VSAT 39 VREF o b Figure 135 a lnverting comparator b Plot of 110 versus 121 For an ideal op amp that exhibits saturation of its output voltage the output voltage of the inverting comparator circuit in Fig 135a can be written 110 VSAT Sgn VREF 121 181 where sgnac is the signum or sign function de ned by sgn 1 for at gt 0 and sgn 71 for at lt 0 The plot of 120 versus 111 for the circuit is given in Fig 135b 1102 The NonInverting Comparator Fig 136a shows the circuit diagram of an op amp used as a noniinverting comparator The output voltage of the circuit is given by 110 VSAT Sgn 111 VREF 182 The graph of 110 versus 111 is given in Fig 136b o 1 I U VSAT quot a v VREF I I VSAT REF 0 b Figure 136 a Noneinverting comparator b Plot of 120 versus 121 1103 The Comparator with Positive Feedback Positive feedback is often used with comparator circuits The feedback is applied from the output to the noneinverting input of the op amp This is in contrast to the circuits covered in the preceding sections of this chapter where feedback is applied to the inverting input The noneinverting integrator is an exception This circuit uses feedback to both op amp inputs Fig 137a gives the circuit diagram of an inverting op amp comparator with positive feedback The circuit is also called a Schmidt trigger The capacitor CF in the gure is assumed to be an open circuit in the following This capacitor is often used to improve the The BJT Differential Ampli er ECE 3050 Analog Electronics The differential ampli er or diff amp is used in applications where it is desired to have an output voltage that is proportional to the difference between two input voltages Fig 1a shows the basic circuit diagram The tail supply is modeled as a current source having an output resistance RQ In the case of an ideal current source7 RQ is an open circuit Often a diff amp is designed with a resistive tail supply In this case7 I Q 0 There are two outputs shown Either or both can be used Often the difference voltage between the two outputs is used V a Figure l a Circuit diagram of the differential ampli er b First equivalent bias circuit for Q1 b Second equivalent bias circuit for Q1 The dc bias circuit is obtained by setting U mg 0 The tail supply can be divided into two parallel current sources of value lg 27 each having an output resistance QRQ By symmetry7 no dc current flows between the two sides of the circuit so that the two sides can be separated The circuit obtained for Q1 is shown in Fig 1b The circuit for Q2 is identical The circuit shown in Fig 1c is obtained by making a Thevenin equivalent of the tail supply in Fig 1b The bias equation for IE is IE 07 V 7I RQ 16RB VBE IERE 2RQ This can be solved IE to obtain 7V7 7 VBE RB1 RE2RQ The dc collectoretoebase voltage is given by E VCB V0 7 VB W 7 aIERC 7 lt E R3 V 7 aIERC E R3 16 16 This must be greater than zero for the two BJTS to be biased in the active mode The collector to emitter voltage is given by VCE VC VE V0 VB VBE VCBVBE It follows that 7 5 71 and 7 0 for each transistor are given by VT RB Tx VAVCE re r0 TBIE Te 15 aIE To solve for the smallisignal value of U01 we zero VJV7 V 7 and lg to form the ac signal circuit Then the circuit seen looking out of the emitter of Q1 is replaced by a Thevenin equivalent circuit To obtain this7 we rst replace the circuit seen looking into the emitter of Q2 with a Thevenin equivalent circuit This circuit is shown in Fig 2a7 where T0RC13 T0RC U U39 7 7 5205 12r r0RC1 152 ergr0RC1 The Thevenin voltage and resistance seen looking out of the emitter of Q1 are given by U 7 U A R R R R 7quot tel 5206 RQ RE n82 e E Q E 152 The new circuit is shown in Fig 2b c Figure 2 a Ac signal circuit for Q1b Circuit for calculating U01 and ram The circuit for calculating U01 and ram is shown in Fig 2c We can write U01 461cm gtlt Helch Gmbvn Gmevtei gtlt Helch Tout Helch where a TO Rte 1 0W0T rotr ll w G G TV mb T RteHT0 T0Rte me Rte l rlellro r0T e w liaRterngRte When the above results are combined7 we obtain 14112 U01 Amvn Au2vz392 Avl W1 A W2 111 where A and Avg are the voltage gains given by RQ HBO15 A G 39R A G 39R 111 mbxrlcll C 112 mexrlcll CXRQREri82 rgr0RC1 By symmetry7 U02 is given by A 2 U02 Ual 14 W2 A EW1 11 We see that the gains for U and U12 differ by the ratio AvgAm This is given by 14112 Gme RQ TO l RC Am 7 Gm RQREM52 TgT0Rc15 If this ratio is unity7 U01 and U02 are proportional to the difference between the two input voltages It can be seen that the ratio is exactly unity only if RQ gt 00 and 7 0 gt 00 Let U0 be the differential output voltage This is given by Av U0 U01 U02 Am Aw W1 W2 Avl 1 j A gt W1 W2 1 This is proportional to the difference between the two input voltages even if RQ lt 00 and 7 0 lt 00 The 7 0 approximations to the gains are obtained by letting 7 0 gt 00 except in the expression for MC We obtain R A111 2 Gm gtlt Malch A112 Gm gtlt Malch X W where G L R RER HREr m 7 l Rte 8 Q 8 The expression for ram is the same except HE is calculated with Rte RE RQH RE The equivalent circuit seen looking into the base of Q1 consists of the resistor 7 in series with the voltage 121106 These are given by 15T0Rc T0RteRc 7 r0RC 7 T0RC15 r0RC Ub1ac 7 Utei w RteT0Rc T5T0Rc15 RteT0RC The equivalent circuit is shown in Fig 3a The circuit for Q2 is shown in Fig 3b7 where Ub2ac is given by Mbrx13T5R e r0RC iUVl T0RC1 T0RC 7 l U U 3 t5 Rte l TO l RC rgroRc1 Rte l TO l RC The two base equivalent circuits can be used to calculate the base currents ibl and ibg RA in Ta Ta in Rs n viz vhloc vb2oa a b Figure 3 a Equivalent circuit for ibl b Equivalent circuit for ibg

### BOOM! Enjoy Your Free Notes!

We've added these Notes to your profile, click here to view them now.

### You're already Subscribed!

Looks like you've already subscribed to StudySoup, you won't need to purchase another subscription to get this material. To access this material simply click 'View Full Document'

## Why people love StudySoup

#### "There's no way I would have passed my Organic Chemistry class this semester without the notes and study guides I got from StudySoup."

#### "I bought an awesome study guide, which helped me get an A in my Math 34B class this quarter!"

#### "There's no way I would have passed my Organic Chemistry class this semester without the notes and study guides I got from StudySoup."

#### "It's a great way for students to improve their educational experience and it seemed like a product that everybody wants, so all the people participating are winning."

### Refund Policy

#### STUDYSOUP CANCELLATION POLICY

All subscriptions to StudySoup are paid in full at the time of subscribing. To change your credit card information or to cancel your subscription, go to "Edit Settings". All credit card information will be available there. If you should decide to cancel your subscription, it will continue to be valid until the next payment period, as all payments for the current period were made in advance. For special circumstances, please email support@studysoup.com

#### STUDYSOUP REFUND POLICY

StudySoup has more than 1 million course-specific study resources to help students study smarter. If you’re having trouble finding what you’re looking for, our customer support team can help you find what you need! Feel free to contact them here: support@studysoup.com

Recurring Subscriptions: If you have canceled your recurring subscription on the day of renewal and have not downloaded any documents, you may request a refund by submitting an email to support@studysoup.com

Satisfaction Guarantee: If you’re not satisfied with your subscription, you can contact us for further help. Contact must be made within 3 business days of your subscription purchase and your refund request will be subject for review.

Please Note: Refunds can never be provided more than 30 days after the initial purchase date regardless of your activity on the site.