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# Microelectronic Circuits ECE 3040

GPA 3.64

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This 0 page Class Notes was uploaded by Cassidy Effertz on Monday November 2, 2015. The Class Notes belongs to ECE 3040 at Georgia Institute of Technology - Main Campus taught by Jeffrey Davis in Fall. Since its upload, it has received 73 views. For similar materials see /class/233867/ece-3040-georgia-institute-of-technology-main-campus in ELECTRICAL AND COMPUTER ENGINEERING at Georgia Institute of Technology - Main Campus.

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Date Created: 11/02/15

Pierret Chapter 17 MOS Essentials Jeff Davis ECE304O Spring 2006 References Prof Alan Doolittle s Notes usersecegatecheduaanindexfilesECE3040indexhtm Prof Farrokh Ayazi s Notes usersecegatecheduayaziece3040 Figures for Require Textbooks Pierret and Jaeger MetalSemiconductor MS Co ntact Ohmic or Rectifying Contact Metal Semiconductor MS Junction Right After Contact ntype semiconductor ntype semiconductor quotquotquotquotquotquotquotquot 7 a c RCIIICIIIUCI llllb lb NUI Ill chIIIUIIUIll 4 MS Junction in Equilibrium PM gt IDS i i i 0 X cps cpM EC EFS EFM 7 V T DB EC Forward and Reverse Bias Operation VAgtO Lowers metal Fermi energy level VAltO Raises metal Fermi energy level Ohmic Contact See notes from class MOSFET Source Drain Junction We need this to always be conducting How do we do this Semiconductor Doping Wwi Low doping Moderate doping High doping b Heavy Doped Junction produces Ohmic Contact zig HIGH DOPING Quantum Mechanical Tunneling allows current to flow both ways with low resistance MOS Transistor Qualitative Description Flow of current from Source to Drain is controlled by the Gate voltage 3 Control by the Gate voltage is achieved by modulating the conductivity of the semiconductor region just below the gate This region is known as the chan el MOS Transistor Qualitative Description nchannel MOS pchannel MOS Transistor Transistor D D VDs G G B VBs VGs VSG S Note All voltages are shown in their positive direction Obviously VYXVXY for any voltage GGate DDrain SSource BBody substrate but to avoid confusion with substrate B is used Nchannel MOS Transistor Qualitative Description Assume an n channel receives it s name from the type of channel present when current is owing device with its source and substrate grounded i e VSVBO V For ANY value of VDS VGS lt0 accumulation the source to drain path consists of two back to back diodes One of these diodes is always reverse biased regardless of the drain voltage polarity holes won t ow S G D VG VD V1320 lib I A SiOz mm m d Ptype N channel MOS Transistor Qualitative Description For ANY value of VDS 0ltVGS ltVT depletion CUTOFF There is a de cit of electrons and holes making the channel very highly resistive gt No Drain current can ow N High p due M to Depletion i3 N channel MOS Transistor Qualitative Description VDS 0 VGS gt VT An induced n type region an inversion layer forms in the channel and electrically connects the source and drain Inversion layer ntype N channel MOS Transistor Qualitative Description Small positive VDS VGS gt VTcontinuedI The induced n type region allows current to ow between the source and drain The induced channel acts like a simple resistor Thus this current ID depends linearly on the Drain voltage VD This mode of operation is called the linear or triode region Nchannel MOS Transistor Qualitative Description Inversion case VGS gt VTcontinuedC Drain current verses drain voltage when in the linear or triode region D Linear region V 0 VDsat D Nchannel MOS Transistor Qualitative Description When VDS increases a few tenths of a volt gt0 VGs gt VT Potentia1 drop across the channel This drop reduces the number of carriers especially around the drain region Channel conductance decreases resulting in a drop in the slope of the IDVD curve Reduced electron concentration in the Inversion layer near the drain N channel MOS Transistor Qualitative Description When VDS increases a few tenths of a volt gt0 VGs gt VT Drain current verses drain voltage for increasing VDS still in the linear or triode region VD VDsat Nchannel MOS Transistor Qualitative Description Inversion case VGS gt VTc0ntinuedI oThe inversion layer eventually vanishes near the drain end of the channel This occurs at VGS VT because the gate to channel potential at the drain side is at the threshold voltage oThis is called PinchOff and results in a Flat IDVDS curve 5 D I I I I I i I 20 Nchannel MOS Transistor Qualitative Description Inversion case VGS gt VTcontinuedI lDVDS curve for the Saturation Region The drainsource voltage VDS at which this occurs is called the saturation voltage Vsalt While the current is called the saturation current IDsat D Saturation region Linear Region B IDsat A VD 0 VDsat VDsat saturation voltage VGS VT 21 Nchannel MOS Transistor Qualitative Description Inversion case VGS gt VTcontinuedI For VDSgtV value AL the channel length L effectively changes by a sat The region of the channel AL is depleted and thus is high resistivity Accordingly almost all voltage increases in VDSgtV are dropped across this portion of the channel sat VDsat VD I l MOS Transistor Qualitative Description Inversion case VGS gt VTcontinuedC If ALltltL the voltage at the end of the channel will be constant Vsat for all VDSgtVsat ID will be constant If ALL the voltage dropped across the the channel VSAT varies greatly with VDS due to large modulations in the electric eld across the pinched off region EVDS VSATAL In this case ID increases slightly with VDS b ALL ALltltL VDsat MOS Transistor Qualitative Description Finally IDVDS curves for various VGS I D VG increasing gtw ltm I r l l VD VDsat depends on VG 24 MOS Transistor IV Derivation With our expression relating the Gate voltage to the surface potential and the fact that S2 F we can determine the value of the threshold voltage 2 VT 2 8 S q NA 21 F for n channel dev1ces ox S VT 2 5 8 ii 2 for p channel devices ox S Where 8 C ox 0 1s the ox1de capac1tance per un1t area x ox Where we have made use of the use of the expression 85 KS80 25 Quantitative Description of MOSFET Current 26 Different Current Models for Enhanced Understanding ZEROTH ORDER CAPACITOR CURRENT MODEL FIRST ORDER SQUARE LAW CURRENT MODEL SECOND ORDER BULK CHARGE CURRENT MODEL 27 MOS Transistor IV Derivation Coordinate Definitions for our NMOS Transistor xdepth into the semiconductor from the oxide interface ylength along the channel from the source contact zwvidth of the channel Xcy channel depth varies along the length of the channel nXy electron concentration at point Xy unXythe mobility of the carriers at point Xy G Device Width is Z Channel Length is L Assume a Long Channel device for now do not worry about the channel 28 length modulation effect Effective Mobility Source W Drain N 7Inxersilt213yer N nX y 71x y PX y Ixo n x nXydx n 2 HO J 0 quot36 ydx Since the electron concentration also varies with position the average mobility of electrons in the channel known as the effective mobility can be calculated by a weighted average ZEROTH ORDER CAPACITOR CURRENT MODEL 30 Zeroth Order Capacitor Current Model M Surface S n AxUE Ay SOUI CG n VDSgtO Z Width of the transistor device drain I Charge Passing Through Surface S Given time interval 31 Zeroth Order Capacitor Current Model Volume V Surface S M n MA lt E n 7 source VDS gt 0 dram Q inversion charge per unit area total charge in volume V QIAyZ I time to move total charge OUT of V At 32 Zeroth Order Capacitor Current Model total charge in volume V QIAyZ I time to move total charge OUT of V At lt vd gt average drift velocity ME Ay ltv gt E d N M AtzA X LLE A Z a a I Q1 y HE Q1HZE Ay 33 Zeroth Order Capacitor Current Model I QIpZE What is the inversion charge in the channel This model assumes that it is ALWAYS uniform along the channel Q1 Cox VGS VT Below threshold applied voltage produces BULK charge NOT free chargg Zeroth Order Capacitor Current Model I COXVGS VT uZE E dV dV dy ICOX VGS VT dy Idy COX VGS VT uZdVH Ingegr39ate both SI es IL 2 Cox VGS VT ILLZVDS Z I z COXIUZVGS VT VDS 35 Zeroth Order Capacitor Current Model IDS A Saturation re ion Linear region Z 2 I z COXILLZVGS VT Z I z COXIuZOGS VT VDS 36 FIRST ORDER SQUARE LAW CURRENT MODEL 37 First Order Square Law Model Derivation Drain CurrentVoltage Relationship In the Linear Region VGSgtVT and OltVDSltVOIsat JN qynnE qDNVn Neglecting the diffusion current and recognizing the current is only in the ydirection 03905 JN JNy Ill 38 First Order Square Law Model Derivation Drain CurrentVoltage Relationship In the Linear Region VGSgtVT and OltVDSltVdsat xxcy ID JJJNydxdy Z 0 JNydx X xxcy 2a P d 39 First Order Square Law Model Derivation Drain CurrentVoltage Relationship In the Linear Region VGSgtVT and OltVDSltVdsat dy YZL VDS L20 DdyZlLth 0 QNd ID Zlu nQN VDS IDL Zun L 0 QNd Z LL n VDS I D L L 0 QNd We need an expression relating q and QN 4O CapacitorLike Model for QN Neglect all but the mobile inversion charge Since CM 2 7 Q dV MOS Capacitor MOS Transistor QN 2 Cm VGS VT for VGS 2 VT QN E CmVGs VT for VGS Z VT Neglect the depletion region charge First Order Square Law Model Derivation Z lTn VDS ID L L 0 WM Z VDS ID J O COXVG VT d Z C V2 Mquot m VG VTVDS i 0 S VDs S VDW and Vcs 2 VT D L This is known as the square law describing the CurrentVoltage characteristics in the Linear or Triode region 42 First Order Square Law Model Derivation But what about the saturation region For VDSgtVDsat ZILL nCOX stat I D om VGS VT VDsat D VDsat S VDS L 2 But QN E Cox VGS VT VDsat O 01quot VGS VT VDsat Thus Z EC 2 ID IDsat 7VGS VT VDsat S VDS 43 MOS Transistor IV Derivation 2Ech v2 D TVGS VTVDS S ZILL nCmC 2 0 s VDS s VDW and V05 2 VT 10 1W 2L Vos VT 1 VW S VDS I F J g VG increasing gtw ltm r vb VGS VT VDsal 44 Deviations From Ideal Channel Length Modulation Effect Above pinchoff when VDSgtVDsatVGsVT the channel length reduces by a value AL VDs t VD s b L 1 gt D quot Thus the expression for drain current Z ILTHCOX I D IDsat TVGS VT 2 VDsat S VDS J Becomes ZILLHCOX ID 1mm mVGs VT 2 VDsat S VDS l 1 AL or since ALL E l L AL L Z C AL ID IDsat VGS VT2 1 VDsat S VDS 45 MOS Transistor Deviations From Ideal Channel Length Modulation Effect But the fraction of the channel that is pinched off depends hnearly on VDS so Channel Length Modulation causes the dependence of drain A V ID current on the drain voltage in DS saturation AL L B Where 9 is known as the ChannelLength Modulation parameter and is typically 0001 V391lttlt01V 1 ALltltL r VDsat ID IDsat 0xVGS VT 2 1 A VDS VDsat S VDS 46 MOS Transistor Deviations From Ideal Body Effect Substrate Biasing Until now we have only considered but the substrate Body is often the case where the substrate Body intentionally biased such that the has been grounded SourceBody and DrainBody junctions are reversed biased D S G D VG VD V1320 VG vD V020 11D l1 Sio2 39 m H a H D pSi The body bias VBS is known as the backgate bias and can be used to modify the threshold voltage Note that now our channel potential has an offset equal to V35 47 MOS Transistor Deviations From Ideal Body Effect Substrate Biasing Thus our threshold potential With the body groun lair for nichannel devices Becomes Surface Potential s S Vcalmnm 2 r VAS t Ci 2a 7 V for nichannel devices But We Would like to have this in terms ofVGS instead ofVGB Since VGS VGBVBS VT vm mw 2g Ci 24 m 7 v for nychannel devices or 5 MOS Transistor Deviations From Ideal Body Effect Substrate Biasing This can be rewritten in the following form more convenient to reference the threshold voltage to the VBSO case VT Pierret VTN Jaeger VTO 9 Q2 F VBS 42 for n channel devices VT Pierret VTP Jaeger VTO 9 Q2 F VBS 2 F for p channel devices where JZqNAes 7 C 1s known as the body e ect parameter 0x 49 nMOS Transistor Enhancement Mode verses Depletion Mode MOSFET We have been studying the enhancement mode MOSFET MetalOxideSemiconductor Field Effect Transistor It is called enhancement because conduction occurs only after the channel conductance is improved or enhanced In this case VTNgt0 Transistors can be fabricated such that VTN s 0 These transistors have conduction for VGSO due to a channel already existing Without the need to invert the near surface region To modulate currents a field must applied to the gate that depletes the channel Thus transistors of this nature are called Depletion mode MOSFETs 50 MOS Transistor Enhancement Mode verses Depletion Mode MO SFET nunme MOSFEI 1 n s c n D E J 5 6 MW gt l 5 Va Dcp Ion mm SWIM 5mm Cruxmmxucs MOSFEI mm mm Va 2 o chum gm cam symbol and 1er chunmenmu u nltlnmn nhmuzmzmmud m dwlmiulrnwd Mos er MOS Transistor Summary 4Terminal 3Terminal Enhancement Depletion Enhancement Depletion is rtchannel S S PMOS 2415 LI a TD gI D D D D D NMOS B 54 Ha g T 3H 3 pchannel 3915 s 3913 S Jaeger uses the notation W03 K K g E c gwhere w is the Gate Width Zin Pierret PMOS K Kpftiw CafwhereWISthe Gatewldthamnmet 52 MOS Transistor Summary NMOS PMOS Regardless of MOde Kn K gaLTnCm Note W Zin Pierrot KP K39P gauinCm Note W Zin Pierrot Cutoff IDS 0 for VGS S VTN ZSD 0 for vs S VTP Linear 2 2 Zv nch V Zv nch V has L VGS VTNVDS S lSD L VSG VTPVSD VGS TNZVDSZO VSGVTPZVSDZO Saturation Z C lDs vss VTN2 1 3 V05 for vDS 2 vGS V77V 20 Z C lSD 2VSGVTPIZ1A V50 for vSD 2 V VTP 2 0 Threshold Voltage VTN VTO 7 2 FVSB v vm y 2 FvSB W VT for Enhancement Mode ENgtO EPltO 53 Small Signal Model MOSFET 54 For small signalslinear relationship A ID ALL r VD VDsa V VDS T VGS K IDSZYnVGSVTN21I V05 for VDSZVGSVTN 55 MOSFET Small Signal Model and Analysis Linearize i over small i 1 2 signal 1 2 Nonlinear 17V range L1near rela onshi V1 m p V1 V1 Two Port Vz 39 MOSFET 39 39 Network 39 6 etc General yparameter Network 11YI1V1 Y12Vz IZYZ1V1 YZsz MOSFET yparameter Network gsy11vgs Y12Vds 1d5y21vgs 3 2sz EQUIVALENT CIRCUIT FOR TWO PORT NETWORK ADMITTANCE MATRIX 1123 11 71 Y12V2 122Y21V1 Y22V2 i1 X 1 2 w av v 0 712v2 Y2101 0 U2 0 o CALCULATING TWO PORT NETWORK PARAMETERS Z i v lgs YIIVgs YIZVds gs y gs vd50 idSZYZIVgs YZZVds y V ds 21 gs vdszo ids 39 Q i 95 TWop network O all nal Vds ET ng 0 o CALCULATING TWO PORT NETWORK PARAMETERS 1gSZYIIVgs YIZVds lgs ylzvds Vgs 0 idSZYZIVgs YZZVds V ds y22 ds Vgszo ids Q i 95 TWop network all nal Vds ET vgs o CALCULATING TWO PORT NETWORK PARAMETERS i A D 139 di 3 21 2 A d DS Vgs VdS0 Vgs VGSZVDS This is the slope of the linear relationship between i0IS and vgs therefore we calculate the slope at the DC bias point in the large signal model CALCULATING TWO PORT NETWORK PARAMETERS MOSFET Ampli ers are biased into Saturation or Active Mode K 2 n IDS 2 VGS VTN 1 239 VDS far VDS 2 VGS VTN lgs les lgs leS y d ylz v dv Vgs VdS VGS VGS 13 V 0 DS VDS VDS 21 22 v dv gs VdS 0 VGS VGS ds V 0 VDS VDS 61 1gSZYIIVgs YIZVds 1dSZYZIVgs YZZVds gs ids 0 O y12vds V 95 o Vds 0 y21vgs C lgs leS i leS yll y12 v gs V450 VGS VGSVGS d5 vg 0 D5 VDSVDS ids diDS ldS dlDS 3 21 Z d y22 v dv v33 vdx 0 V65 V05 VGS d5 Vg 0 D5 VDSVDS 1gSZYIIVgs YIZVds 1dSZYZIVgs YZZVds 3998 Ids 0 Y12Vds O I V98 711 V d5 o o l y21vgs i leS lg leS y 11 v 3 12 v gs V450 GS VGSVGS d5 vg 0 D5 vDSDS Ids dle y lds dlps ym V dv 22 v dv 35 150 GS VGSVGS d vgx0 DS VDSVDS CALCULATING TWO PORT NETWORK PARAMETERS MOSFET Ampli ers are biased into Saturation or Active Mode Kn zDS 7VGS VTN2 1 A VDS for VDS 2 VGS VTN ids diDS d 2 j V V 1 A V y21 V85 vdS0 dVGS VGsVGs dVGS 2 G TN DS y21KnlVG VTN 1 A V05 64 CALCULATING TWO PORT NETWORK PARAMETERS MOSFET Ampli ers are biased into Saturation or Active Mode Kn IDS 7VGS VTN2 1 239 VDS far VDS 2 VGS VTN 1i d Kn V 2 1 A 3 22 Vds Vdszo dVDS VDSZVDS VGSZVGS dVDS 2 VGS TN VDS yzz 1Vas Vm 1 65 MOSFET Small Signal Model and Analysis Putting the mathematical model into a small signal equivalent circuit G A Q79 D 8 g m V83 9 o 275 G v v S S 66 MOSFET Small Signal Model and Analysis Putting the mathematical model into a small signal equivalent circuit G r 05 D o gt O lt39 o 85 gm VGS go 275 C v v S S Compare this to the BJT small signal equivalent circuit B ib in C 0 lt O vbe r75 gmvbe r0 use 0 w v v 0 E 67 MOSFET Small Signal Model and Analysis Example Jaeger 1394 L V3 Hg Meg vgs 231519 v Calculate the voltage gain AVVOVs Given Knl mAV2 A00lS V391 Bias Point of IDS2 mA VDS75V 68 MOSFET Small Signal Model and Analysis Example Jaeger 1394 FIE VD j 1 I p V3 Rig 1r1eg vgs 231 9m V93 g D Pd 29k F I3 27M 1 K g0 2nVGS VTZ gmanVGSVTX1IVDS Need to nd VGSVT K IDS 2n KVGS VTNZ12 VDS 2 2 mA M KVGS VTN 2 1 0015 75 4 VG VTN gm 2llmS g0 27l u Sgt r0 369kQ MOSFET Small Signal Model and Analysis Example Jaeger 1394 RE V I I l 0 um F 1 l l 1 l VS If R39g 1n1eg vgs gm Vgs go Rd Hz NOR l A VJZV L V vs vs VGS vGS lAeg vs lOklAeg 2099 and v0 gm r0 VGS Rd R3 2lmS348k 735 A 2023 Va V 727 VV v s vs VGS 70 MOSFET Small Signal Model and Analysis Add in capacitances Overlap of Overlap of Gate Oxide Gate Oxide LD Gate to channel to Bulk capacitance Reverse Bias Junction capacitances MOSFET Small Signal Model and Analysis Complete Model of a MOSFET Due to effective gvtergn g g 3 modulation of the a e X e mb m threshold voltage 2quot VSB 2 F ng gate J I i 39 l I r J drain 39 V8 C8 gmvgg g 0 source TX 39 vb Csb C db Overlap of R 1 Gate Oxide gum Ga39te to 39 7 If and Gate to channel to channel Bulk Reverse Bias Junction capacitances caPaCitance capacitance 72 MOSFET Small Signal Model and Analysis SPICE MOSFET Model SPICE models the drain current IDS of an nchannel MOSFET using the following parametersequations SPICE variables are shown in ALL CAPPITAL LETTERS Cutoff IDS 0 Linear KP W IDs DS 2VGS VTH VDS 11 LAMBDAVDS 2 LEFF Saturation IDS E W KVGS VTH211 LAMBDAVDS 2 LEFF Threshold Voltage VTH VTO GAMMA QZPHI VBS JZPHI Channel Length LEFFL2LD 73 MOSFET Small Signal Model and Analysis SPICE MO SFET Model Additional Parameters SPICE takes many of it s parameters from the integrated circuit layout design Source Gate Drain L polysilicon gate length W polysilicon gate width AD drain area AS source area PD perimeter of drain diffusion not including edge under gate PS perimeter of source diffusion not including edge under gate NRD number of squares in drain diffusion Specified in terms Of the 74 NRS number of squares in source diffusion minimum feature size MOSFET Small Signal Model and Analysis SPICE MOSFET Model Additional Parameters Model Parameters scc MODEL statement Default value Units LEVEL model type 1 2 or 3 t L channel length DEFL meter channel width DEFW meter lateral diffusion length 0 meter lateral diffusion widthl 0 meter zerobias threshold voltage 0 volt transconductance 2E 5 ampvolt2 bulk threshold parameter 0 voltm surface potential 6 volt channellength modulation LEVEL 1 or 2i 0 voltquot drain ohmic resistance 0 ohm source ohmic resistance 0 ohm gate ohmic resistance 0 ohm bulk ohmic resistance 0 ohm drainsource shunt resistance in nite ohm drain source diffusion sheet resistance 0 ohmsquare bulk pn saturation cunent 1E 14 amp bulk p n saturation currentarea 0 ampmeter bulk p n potential 8 vo bulkdrain ternbias pn capacitance O fared bullocource zerobias p n capacitance 0 fared CJ bulk p n zerobias bottom capacitancearea 0 faredmeter2 CJSW bulk pon zerobias perimeter capacitancelength O faredmeter MJ bulk pn bottom grading coef cient 5 MJSW bulk p n sidewall grading coef cient 33 FC bulk pn forwardsbias capacitance coefficient 5 C650 gatesource overlap capacitancechannel width 0 faredmeter CGDO gatedrain overlap capacitancechannel width 0 faredmeter CGBO gatebulk overlap capacitancechannel length 0 faredmeter NSUB substrate doping density 0 ircmJ NSS surface state density 0 tlcm2 NFS fast surface state density 0 lcrn2 TOX oxide thickness in nite meter TPG gate material type 1 1 opposite of substrate 1 a same as substrate 0 aluminum XJ metalluraical iunction death 0 meter UO surface mobility 600 cmllvoltsec UCRIT mobility degradation critical eld LEVEL 2 1E4 voltcm UEXP mobility degradation exponent LEVEL 2 0 UTRA not used mobility degradation transverse field coefficient VMAX maximum drift velocity 0 metersec NEFF channel charge coefficient LEVEL 2 1 XOC fraction of channel charge attributed to drain 1 DELTA width effect on threshold 0 THETA mobility modulation LEVEL 3 0 volt ETA static feedback LEVEL 3 0 KAPPA saturation eld factor LEVEL 3 2 KF flicker noise coefficient 0 AF flicker noise exponent 1 MOSFET Ampli ers What is the Maximum Gain Possible Is it saturated Constant current VDS gt VGS 7 VTF but VDS VGS and VTF 2 0 for a depletion mode MOSFET so 0 gt 7V7 is alwayssatisfied gt Is Saturated gm is internal to the transistor and can not b 7KWVGS7VTX1AVDS AVva A 19ng 7 VT1 used as the load instead ofblas resistors 1n 7 1 A VDS ampli er circuits Am 7 76 71VGS7VT MOS Transistor Bias CircuitryEnhancement Mode NMOS Due to zero DC current ow in the gate the bias analysis of a MOSFET is significantly easier than a BIT M W 7 v1 1 L vmw 2 P2 30k mamw Form Thevenin circuits looking out the gate drain and source MOS Transistor Bias CircuitryEnhancement Mode NMOS 3V rare VGS 10V 1mm VDS IBut IG0 so VGS3V IAssume Saturation operation selected for easy math because IDS does not depend on VDS since no Y Was given 7 F0 K in 7 n VGS VTNYJfOr V0 2 V6 VTN 2 0 25x105 2 1m 7 Thy 1 1 501 A Check VD 10V 50uAl 00k VDS VDS 5V gtVGS Vm 2V IAssumption of Saturation operation Was correct If it Were not correct simply make another assumption Ie linear region and resolve MOS Transistor Bias CircuitryDepletion Mode NMOS Bias circuit of a depletion mode device is much simpler due to the fact that the device conducm drain current for VGS0V Vn7 73V 7 11 I I K 200 14 What value of R1 results 111 100 uA dram current Again Assuming saturation 21 211001414 VGSV 0573V 7272V K zoomV m R17V ii20KQ IDS 100uA Check VDS 10V 105111 VDS 100uA20k VDS VDS 8V gt V65 7V 72V 7 73V 1V IAssumption of Saturation operation Was correct If it were not correct simply make another assumption Le linear region and resolve 79 MOSFET Small Signal Model and Analysis Just as we did with the BJT we can consider the MOSFET ampli er analysis in two parts Find the DC operating point Then determine the ampli er output parameters for very small input signals 80 PIERRET CHAPTER 1 1 BJT STATIC DC CHARACTERISTICS Jeff Davis ECE304O REFERENCES Prof Alan Doolittle s Notes usersecegatecheduaanindexfilesECE3040indexhtm Prof Farrokh Ayazi s Notes usersecegatecheduayaziece3040 Figures for Require Textbooks Pierret and Jaeger GOAL Derive quantitative solution to BJT currents ASSUMPTIONS Nondegenerate doping amp step junctions Steady state operation 1D analysis Lowlevel injection Only drift diffusion thermal RG ln depletion regions EB amp CD no thermal RG Quasineutral regions emitter amp collector are greater than diffusion length VARIABLE DEFINTIONS FOR ANALYSIS Emitter Base Collector 4 H x x E 0 W x I O I 0 I I I I I I Doping Concentratio NE NAE N NDB NC NAC Diffusion Coefficient DE DN DB DP DC DN Minority Carrier Lifetime TE In TB 7713 TC Tn Diffusion Length LE LN LB LP LC LN Equilibrium Minority nEo npo 1730 Pno quotC0 quotp0 Carrier Concentrations BIPOLAR JUNCTION TRANSISTOR BJT QUANTITATIVE SOLUTION FOR EMITTER REGION Emitter Base Collector 7 P N P l H x i x n 0 W gt x 0 As usual start with the Minority Carrier Diffusion Equation 0 aAnE D azAnE AnE G at E 8x2 In L Steady state 2 X No light source a An An 0 DE 2E E 8x 139 I1 Boundag Conditions Vi AnExquotOnE0eVT 1 AnEx oo0 BIPOLAR JUNCTION TRANSISTOR BJT QUANTITATIVE SOLUTION FOR BASE REGION xquot E W x 0 0 I g i H I Base Collector N 0 Base Region The diffusion equation to be solved is dZApB 0 DB dx2 TB subject to the boundary conditions APB0 PBoquEBkT 1 APBW pBOquCBkT 1 BIPOLAR JUNCTION TRANSISTOR BJT QUANTITATIVE SOLUTION FOR COLLECTOR REGION Emitter Base Collector P N P l 4 H x l xquot I 0 W x n J1 Collector Region The diffusion equation to be solved is 0 C d 2Anc AnC dx39 2 Tc subject to the boundary conditions Anc x39 gt 00 0 Ancx O nCOe 1VcBkT 1I The problem solution in the emitter and collector quasineutral regions mitte Base Collector 7 Lquot O 0 x X39 n L LE AHEOC Ame E A2Ee AquotC x Awe LC AzceLC V Jquot h i AnExquotnEo eVT 1 6 LE AquotCx39nco eVT 1 6 LC dAn dAn En IE I C E dx x0 C q C dx x 0 D ICn amp ncoquCBkT LC The problem solution in the base quasineutral region Emitter Base Collector P N P H x xquot 0 W a x O 0 ApBx Ale LB AzeXLB APBO PBoquEBkT 1 A1 A2 APBW pB0quCBkT Ale WLB AZeWLB SOLVING FOR A2 ApBO A1 A2 K K ApBW Ale LB A26LB W W ApBW ApBO A2e LB AzeLB Solving for A2 gives W ApBltWgt Ap3lt0gte3 W W A2 egeLB SOLVING FOR A1 E A W A 0 6 LB AlepB0 A2Ap30 1 3 1 19 310 6L3 e LB 1 1 E A APB0eLB e LB ApBW Ap30e LB 1 W W W W ea ea 6E 6 3 1 1 E A APB0eLB e LB ApBWApB0e LB 1 E K eLB e LB 1 A ApBlt0gteLB ApBW 1 W W a E 12 6 6 74 3 13 3 Mam dw M a M 3ogdvxgdv 57 57 4 gm gm 57 3 573 57 3 573 Z I ad lamfdv mgdv x V M a a I I 774 mgdv 230ng M a 5171an WK 31V xHdV NOLLF FIOS TVHHNEIE OLNI EV CINV IV ONIL LILS af IS MINORITY CARRIER CONCENTRATION IN THE BASE eW xLB e WxLB APBOC APB0 W exLB e XLB APBW eWLB e WLB g sinhf E sinhW xLB AP W sinhxLB B A1713 5 A7B O sinh WLB sinh WLB MINORITY CARRIER CURRENT IN THE BASE dAp Ev WADE 73 313 sinhW xLB ApBX APB sinhWLB fax 6 sinhax e e7 2 H i sinhax 1 dx dx a 7 a 66 0 It 3g equotE coshf E T x W sinhxLB APBW sinhWLB 2 j a coshax MINORITY CARRIER CURRENT IN THE BASE dAPB 1E qADB p dx xtU d d sinhax a c0shax dAPB x C3 I B dx xW sinhW xLB sinhxLB APB APBm sinhWLB p30 sinhWLB 9 EBk CB 15quot qALBpB0SinhWLBqu T 1 sinhWLBqu quot 7 1 g 1 EB coshWLB CB ICquot qA LB pBOsinhWLB qu M 1 sinhWLB qu 1 HOLE AND ELECTRON CURRENTS FOR EMITTER AND COLLECTOR Electron and hole emitter currents D En qA E quot50quEBkT 1 LE D coshW 1 IEP qA 3 B0 EBk CB LBP sinhWLBqu T 1 sinhWLBqu M 1 Electron and hole collector currents D ICp qA B p30 quEBkT 1 MB 1 I quCBkT LB s1nh WLB s1nhWLB D Ic qA C quotc0quCBkT 1 LC ADDING IT A IEEEIE i LL TOGETHER IC 101 Icp cosh WLB sinhWLB WEBCT 1 LB sinh WLB DE DE n p 9 Equot LB 3quot 1 1 IE amprgtwwm 1C D 4A 13 PBo quEBkT 1 LB sinhWLB DC DE quotco E P30 coshWLB CB sinhWLBgt qu W 1 EMITTER EFFICIENCY IE 212 coshWLB EB 1 CB IEP qA LB pBOLinMWlqg qu m sinhWLB qu I 1 D D h W 15 qAlti nEo 23 p30 quEBkT 1 amp p 1 quCBkT LB 30 sinhWLB 1 1 g LB E sinhWLB DB LE NE coshWLB y EMITTER EFFICIENCY VEB VCB D cosh W L i 1 inBPBJ VT 1 6 VT 1 LB s1nhW LB s1nhW LB D D h W L qAKi nEo A p50 COS 5 LE LB s1nhW LB y VEB D 1 VCB VT 1 B VT 1 6 7L5 PBg Sian LB 20 EMITTER EFFICIENCY V V D cosh W L 1 6114751750 6 VT 1 6 VT 1 y LB s1nhW LB s1nhW LB VEB VCB D D cosh W L i D 1 qAltinE0 751950 xe VT 1 ltipBD lteVT 1 LE LB s1nhW LB LB s1nhW LB Assume in active mode V V V gt0 forward bias EB 39unction EB l eVT 1lteVT 1 VCB lt 0 reverse bias CD junction V Therefore neglect terms with e VT 1 DB V cosh W L E pBo B6VT LB s1nhW LB VEB D D cosh W L qAlt EnE0 BpBO We 1 LE LB s1nhW LB 21 y EMITTER EFFICIENCY V D cosh W L i inBpBg B 6 VT 7 2 LB s1nhW LB D D cosh W L nEa TBPBO E B s1nhW LB 1 6 T 1 amp coshW LB LB p3 s1nhW LB DB coshW LB 7 LE E LB p3 s1nhWLB 7 7 1 n n z E0 Independent of quotE0 W 1 NE LE DB p30 coshW LB n2 biasingquot 7 1 B DE LB NB sinhWLB 1 22 DB L E VB coshWLB EMITTER EFFICIENCY 1 y ICIency Emitter Eff 1 12 1 9 00 I O m I 9 4s I 02 amp 5 5 sinhWLB DB LE NE cosh WLB Assumes DEDB LELB100NBNE Assumes Unity Ratio Condition DEDBI LELBINBNE High emitter doping helps with emitter efficiency as expected 23 BASE TRANSPORT FACTOR I C19 OCT I Ep D 1 Vi c0shWL V673 inBPBD 6VT 1 B6VT 1 a LB s1nhWLB s1nhWLB T v v D cosh W L 1 inpBD We 1 eVT 1 LB s1nhW LB s1nhW LB Assume in active mode VcB VEB V gt0 f d b39 EB 39 t39 EB orwar Ias junc ran 6 VT 1 lt e VT 1 VCB lt 0 reverse bias CD junction V Therefore neglect terms with e VT 1 24 BASE TRANSPORT FACTOR V D 1 A B eVT 1 1 LB pBosinhWLB coshW LB 6 1 OCT DB LB p30 sinhW LB 1 ocT coshW LB BASE TRANSPORT FACTOR 1 OCT coshW LB 5 08 E How do we improve the base transport factor go 6 E 04 02 0 I I I I I 0 2 4 6 8 10 WLB 26 OTHER METRICS Common base Dc current gain adc yaT D L N GO h WL E B B 39 s B D NE smhWLB Common emitter Dc current gain 1 1 Bdc 1 1 h WL E 5 ado COS 3 DB LE NE SlIlhWLB 1 CAN WE SIMPLIFY FURTHER sinhW xLB sinh WLB sinhxLB APBW sinhWLB ApB x ApBO When the base Width is much less than the minority carrier diffusion length 2 sinh gt f f lt 1 cosh gt 1 3 Apgoc Ame ApBam ApBlt0gt1viV CAN WE SIMPLIFY FURTHER APBOC APB0 ApBW APB0 In Active Mode Excess minority carrier starts out positive due to forward biased emitterbase junction and ends up negative due to reverse biased collectorbase junction APBOC i ApBltWgt 0 W Excess minority carrier profile is linear with distance x 29 Bipolar Junction Transistor BJT Quantitative Solution Insight into transistor performance 7 E Heavier emitter doping than base doping NEgtgtNB improves emitter efficiency gtl dc common base current gain gtl and dc common emitter current 1 gain larger e In m2 I3 m l s aT 1 W 2 A narrow base WltltLB improves base transport 1 factor gtl dc common base current gain gtl LB and dc common emitter current gain larger 1 ado 3 a n E 11 DB NE LE 2 LB 1 dc 2 E E l K DB NE LE 2 LB 30 Bipolar Junction Transistor BJ T Quantitative Solution Insight into transistor performance If LBgtgtW most of the minority carriers make it across the base 1 1 DC aDC DEWNB 1 W 51 1I3Dc DBLENE 2L3 DBLENE and 1 aDC 31 Bipolar Junction Transistor BJ T Quantitative Solution Insight into transistor performance If LBgtgtW most of the minority carriers make it across the base 1 1 DC aDC DEWNB 1 W 51 1I3Dc DBLENE 2L3 DBLENE and 1 aDC 32 LARGE SIGNAL MODEL BJT 33 EBERSMOLL MODEL Biasing Biasing Polarity Biasing Polarity Mode E B Junction C B Junction Saturation Forward Forward Active Forward Reverse Inverted Reverse Forward Cutoff Reverse Reverse 34 EBERSMOLL MODEL Emitter Base Collector P N P If VCB 0 then derived equation has the form of ideal diode equation for EB junction D D E qALE nEO B p30 quEBkT 1 LE LB SlnhWLB amp p quCBkT LB B0 sinhWLB WEB VT VC320 1FO e 1 IE 35 EBERSMOLL MODEL Emitter Base Collector P N P If VEB 0 then derived equation has the form of ideal diode equation for GB junction quEBkT 1 0 DC DE coshWLB qV kT LC quotC0 LB 1 30 sinhWLB 3 CB 1 VcB I eVT 1 VEBZO R0 IC 36 EBERSMOLL MODEL 13 JUNCTION CURRENT V CB Junction Current D 1 Ag A B eVT 1 C q LB pBosinhWL w Fraction CB junction current that makes it to H the EB junction CB heW 1 V075 D 1 V075 06 I eVT 1 B 6V7 1 RR LB pB sinhWLB 05 g 1 0 LBpB sinhWLB 37 EBERSMOLL MODEL BE JUNCTION CURRENT EB junction current Fraction CB junction current that makes it to the EB junction C qA V578 D 1 Vii e T 1 B eVT 1 FF L8p30sinhWLB a 4 F LBpBosinhWLB 38 EBERSMOLL MODEL Emitter Base Collector I 39c E P N P VEB VCB IEIFO eV l aRIR0 eVT 1 Vi VcB VT VT IC OCFIFO e 1 1 N gt6 0 N 39 EBERSMOLL MODEL IE CURRENT Emitter Base Collector I IE c forward bias EB current current from CB junction IF Emitter IE 40 O RIR EBERSMOLL MODEL IC CURRENT Emitter Base 39 gt Collector IE 39c P N P gt r current from EB junction forward bias CB current Collector 41 LARGE SIGNAL MODEL OF A BJT EBERsMOLL MODEL PNP Ideal Diodes E VCB IFIF0e T 1 and IR IRJe VT l 1 3 Ii Emitter N l Collector OM RV gt gt IE Ic DEVELOPMENT OF THE LARGE SIGNAL MODEL OF A BJT EBERsMOLL MODEL W NPN 1F 1F0eV 4 and IR 1RoeV 1 IF IR Emitter IA Collector J gt I IE IC A FEW DEVIATIONS FROM THE IDEAL 44 WHAT HAPPENS HERE lB1lt 1B2lt 1B3 amp 1 lt 1 lt 1 ac B1 B2 B3 53 K iB3 theory x52 i132 thCOFY i131 theory VEC VEC 45 N THEORY WIDTH OF QUASINEUTRAL REGION 18 CONSTANT D 1 1 A B qV kT C 1 ltLB pBosinhWLB 6 BB 1 1i DB 3 CB Lo quotC0 L p30 sinhWI 3 V M 1 lBllt 39Bzlt 3933 Theory assumes that the i3 theory effective width of the quasi Eim mom neutral region in the base is i theory constant VEC 46 WIDTH OF QUASI NEUTRAL BASE REGION HOWEVER MUST CHANGE Increasing the VEC voltage increase the reverse bias across CB region Emitter Base Collector P V V 2 N in This decreases the effective width of the base 47 VVHYDOESTTMSCHANGETHECXHLECTOR CURRENT Emitter Base Collector I I Ic E P N P gt lt I APBOC APB0 concentration gradient 0 Increases the Ap W x B T W BASE WIDTH MODULATION OR EARLY EFFECT IC 1B1lt lelt 133 ewa 33 49 PIERRET CHAPTER 10 BJT FUNDAMENTALS Jeff Davis ECE304O REFERENCES Prof Alan Doolittle s Notes usersecegatecheduaanindexfilesECE3040indexhtm Prof Farrokh Ayazi s Notes usersecegatecheduayaziece3040 Figures for Require Textbooks Pierret and Jaeger Bipolar Junction Transistor Fundamentals Emitter P Eo I Base P Collectorl C At rst glance i Pnp Eo I npn this sort of like H W two diodes back to back pnp mnemonic Pouring N Pot npn mnemonic Not Pouring N Emitter Base Collector I O C N P N B Eo I P Emitter Base Colle Imp P ctorl C E I N USO I m npn N Emitter Base Collec torl C Emitter emits holes Narrow Base controls number of holes emitted Collector collects holes emitted by the emitter Emitter emits electrons Narrow Base controls number of electrons emitted Collector collects electrons emitted by the emitter Bipolar Junction Transistor Fundamentals Bipolar Junction Transistor Fundamentals Bipolar Junction Transistor Fundamentals VEB VCB out B B Common base Both the input and output share the base in common VEB in Common emitter Both the input and output share the emitter in common Common collector Both the input and output share the Collector in common NPN BJT IN EQUILIBRIUM Base Collector Emltter Fermi Level is flat Emitter is heavily doped PNP BJT IN EQUILIBRIUMI Emitter is heavily doped WWidth of the base quasineutral region WBTotal Base width WEBBaseEmitter depletion width WCBBaseCollector depletion width WEBlt WCB Emitter Doping gtBase DopinggtCollector Doping EWB Emitter gt Base Collector P N P quot115 W WCBgt BJT IN EQUILIBRIUM X X v BaseCollector l T built in voltage built in voltage p How MIGHT WE BIAS THE E B AND C B JUNCTIONS Biasing Biasing Polarity Biasing Polarity Mode E B Junction C B Junction Saturation Forward Forward Active Forward Reverse Inverted Reverse Forward Cutoff Reverse Reverse NPN BJT IN FORWARD ACTIVE MODE Electrons injected in the base emitted from the emitter O Em1tter Accelerated by the Electric Field Forward bias EB junction Collector Reverse bias BC Junc on Base needs to be narrow so that electrons will not recombine 11 SLIGHT REVIEW NP JUNCTION FORWARD BIAS BOUNDARY CONDITIONS For npn BJT more electrons are emitted into base than holes into emitter for forward bias single sided junction I I I n I I p I I I I ND NA xn xp 2 VA n v Anpxxp e T 1 NA For n ND is large and Apn is small FORWARD ACTIVE MODE PNP BJT Few electrons injected into the emitter F mil39llimiz e dt I Narrbw Ba require OOO Injected holes diffuse through the base and are collected by the huge electric eld at the BC RB junction oo gt oo O O Many holes injected into the base FORWARD ACTIVE MODE EMMITER CURRENT PNP 1131 132 1133 V E B t IB B C depletion region depletion region electron current Holes current i IEIEPIEn Since emitter is more heavily doped than the base IEnltltIEp 14 FORWARD ACTIVE MODE COLLECTOR CURRENT PNP 11311321133 V J E B LIB depletion region depletion region Hole emitted from the Electron in emitter amp collected at collector collector base junction wandering into C ICP 1C depletion region Since the basecollector junction is reverse biased ICnltltICp 15 FORWARD ACTIVE MODE BASE CURRENT PNP Assumes small recombination the base 11311132 B3 J E B i113 1pc depletion region depletion region B E IC is very small because IEp 2 GP Components of Base Current 131 I En I 32 electron recombination current due to hole recombination in base 33 ICn Bipolar Junction Transistor Fundamentals Summary gt 1c I I I Neglecting Notc Subscript indicates M emittercollector current EC and B C recom blnatlon holeelectron contribution pn EB i 13 generation In eans depletion region depletlon regIon I I IEIEPIEH CP EP Since emitter is more heavily doped than the base IEnltltIEp Since the basecollector junction is reverse biased ICnltltICp IC IE and 13 IE IC is small compared to IC and IE Bipolar Junction Transistor Fundamentals 4 4 Hole current large OUT 7 ES B C junction junction IN E Electron current Consider a pnp Transistor A small electron base current owing into the emitter from the base controls a larger hole current owing from emitter to collector Effectively we can have the collectoremitter current controlled by the baseemitter current 18 WHAT ABOUT CURRENT CHARACTERISTICS CB Junction cB Junction Forward Bias Reverse Bias KVL VCE VBElVcB Saturation Active 13 O VEC Imp VCE npn Both forward bias diodes start to cancel out in saturation region SATURATION AND CUTOFF Saturation O Collector E Emitter Forward Forward Biased Biased VBE gt0 VBC gt0 20 CUTOFF MODE Cutoff Emitter Reverse Reverse Biased Biased VBE lt0 VBC lt0 Collector 21 WHAT ABOUT CURRENT CHARACTERISTICS CB Junction Forward Bias CB Junction Saturation Reverse Bias Active B 0 VEC P7117 VCE lm How MIGHT WE BIAS THE E B AND 08 JUNCTIONS Biasing Biasing Polarity Biasing Polarity Mode E B Junction C B Junction Saturation Forward Forward Active se nverted Reverse Forward Cutoff Reverse Reverse Rarely used and not CONSIDERED in this discussion 23 CURRENT IN INVERTED REGION Saturation Active B 0 VEC IMP VCE lm Cutoff Cutoff Inverted active Saturation EMITTER EFFICIENCY We want emitter efficiency to approach one to get large amplification because base current is electrons for pnp I DC Current Gain 2 C B THEREFORE we want large HOLE current for small electron current in the BASE Said another way the emitter hole current needs to dominate the total emitter current Common emitter I E19 E19 Emitter Ef ciency Characterizes how effective the large hole current is controlled by the small electron current Unity is best zero is worst 25 BASE TRANSPORT FACTOR We want this to be BIG for amplification IC DC Current Gain 2 I B Common emitter We want the recombination in the base to be as small as possible so that Ic can be big Base Transport Factor Characterizes how much of the injected hole current is lost to recombination in the base Unity is best zero is worst 26 Common Base Current Gain EIE E Forward Reverse B Biased Biased IC achE ICBo ocdc common base DC current gain ICp aTIEp yaTIE IC ICp ICn 705T VEB k I VCB r39 in 0L1 l L Collector current for ZERO emitter current IEICn ado yaT and ICBO ICn 27 Pierret Chapter 16 MOS Fundamentals Jeff Davis ECE304O Spring 2006 References Prof Alan Doolittle s Notes usersecegatecheduaanindexfilesECE3040indexhtm Prof Farrokh Ayazi s Notes usersecegatecheduayaziece3040 Figures for Require Textbooks Pierret and Jaeger New Devices CMOS transistors AW bAH A new device MOSFET glass silicon dioxide Gate Source Drain Silicon wafer surface 0Xide Add lots phosphorus to Channel sowceanddm i n n junctions Semiconduct0r 3 things we must understand 1 MOS Capacitor 2 Metal Semiconductor Contact OXide Semiconductor n n 3 MOSFET Current Operation MOS Capacitor Gate voltage VG Metal Gate actually heavily doped polysilicon in MOSFETs Insulator SioZ 0 Semlconductor Si 392 Substrate grounded Analyze MOS Capacitor under certain assumptions Key assumptions 1 Metal is an equipotential region 2 Oxide is a perfect insulator with zero current ow 3 Neither oxide nor oxidesemiconductor interface have charge centers 4 Semiconductor is uniformly doped 5 An ohmic contact has been established on the back side of the wafer 6 Analysis will be onedimensional 7 The semiconductor is thick enough to have a quasineutral region where electric eld is zero and all energy bands are at 8 Certain energy relationships exist PM 18 X i EC EF FB terms de ned in next few slides 7 Definition of Work Function E0lti Vacuum Level HEO Electron affinity Metal Semiconductor W work function of the metal cps work function of the semiconductor MOS Materials Capacitor Metal Insulator Semiconductor MOS Capacitor MOS Capacitor Capacitor under bias Q charge Charge Block Diagram position M O Note a positive bias has been applied to the metal Accumulation VG gt O with ntype substrate Accumulation VG gt 0 Accumulation of MAJORITY carriers Depletion VG lt O for ntype substrate Ionized donors Depletion small VG lt 0 Depletion region forms at surface of semiconductor 13 Inversion VG lt VT for ntype substrate Note that VT is negative for this case Holes Onset of x inversion VG VT Fn EikT Inversion layer of minority carriers holes is created at surface 14 Q n 6 6Ei FpkT P Strong Inversion VG ltlt VT for ntype substrate Holes Ionized donors Inversion VG lt VT For an ntype semiconductor oFor still higher magnitudes of bias VG lt 0 the hole concentration continues to increase resulting in a very high concentration of holes near the interface oThis is known as strong inversion MOS Capacitor Capacitor under bias for Ptype material ACCUMULATION Energy band diagram Applied dc VG 0 voltage Charge diagram Name Flat band Accumulation DEPLETION vTgt v0gt o l I I QE I I I i I Q l Depletion Q INVERSION V V gt VT i l l l I Exposed acceptors I I Electrons Invcrsion 16 MOS Capacitor Capacitor under bias Summary Inversion I Depletion Accumulation l l VG VT 0 N type material Accumulation Depletion Inversion l l VG 0 VT Ptype material Quantitative Solution to MOS Capacitance Electrostatic Potential De nition P Let 1X electrostatic potential inside q S the sem1conductor at a depth X measured from the ox1de 1nterface Oxide I Semiconductor x 1 Z x E l BULK E I x E electrostat1c potent1a1 Ptype Example 4 and is 5 g i BULK Ei INTERFACE 5 surface porenllal TWP AEF I EV along wzlh gt Bulk 1 F i BULK EF j gtx q 0 Reference taken at the bulk 19 Condition for threshold voltage Minority concentration at the interface is equal to majority concentration in the bulk Ei BULK EFykT EF Ei BULKykT NA and nBULK nie 2ND kT N ln A for a p type semlconductor N n for a n type semlconductor 20 Condition for threshold voltage Concentration at the interface is equal to concentration in the bulk Ec 5 f 1i E Ix T 61 r i Ev gt Bulk LM 0 2 at the depletion invertion transition point VG VT 21 How do we calculate the threshold voltage Why do we care This voltage is tells us at What GATE voltage gives conduction from source to the drain ie when our switch starts to turn on 22 Threshold voltage is the GATE voltage that gives a surface potential of 2 VGZ OXid6 DS Potential drop across oxide Potential drop across the bulk which is surface potential 23 Threshold voltage calculation VGZ 0Xide DS 2 T L In for a ptype semlconductor 1 3 2 F I for a ntype semiconductor i 24 What about voltage drop across the oxide l OXide VGZQ OXide I S Semiconduct0r QCV Q 0xide IC Bl oxide l l Depletion region is Q formed first I I I I Q 1 l Depletion 25 What about voltage drop across the oxide VG oxide PS IQBI C 0xide oxide C can be approximated with parallel plate capacitance oxide eWL CDXWL 0X oxide Cox iFcmz 0X What about QB Need to solve for depletion depth 26 USE POISSON S EQUATION GATE a Ptype V E B e Ez Vw Will 2 p dzw gtgt dzll d2w 8 1 D A t39 v dxz dyz a dzz ssump Ion q 2wpnNaNd 27 Depletion Region Approximations Once again if we apply the Depletion Region Approximation neglect all charges but those due to ionized dopants and assume ptype material p qp n ND NA qNA for 0 S X S W where Wis the depletion width 2 222 dx2 8 8 Boundary Conditions 28 AND NOW THE SOLUTION L3 2 am dx2 8 Integrating both sides gives d qNA dxw x A1 Applying the boundary condition ExWO gives d N 1xWOq AWA1 dx 8 N A1 q AW 8 29 AND NOW THE SOLUTION d N mo woiimuo dx 8 Integrating both sides again gives wwo Wfamp Applying the boundary condition I06 W 0 11xW0A2 wo Qo Wf 28 30 AND NOW THE SOLUTION W ue WY 28 Slight changein notation x qNA W x2 31 Depletion Width W in terms of surface potential qNA 2 mm Egg w x CINA 2 Wx m Q ZK JW W 2KS80 S V qNA 32 Depletion Width at threshold The depletion Width at the inversiondepletion transition WT can be found by noting that 2 F S T s amp q quoti WT KSEOZICT 111 q NA quot139 NOTE To obtain the equations for ntype substrates we simply repeat the above procedure replacing N A with ND 33 What is the relationship between surface potential and gate voltage How is the gate voltage VG distributed throughout the structure VG S 0Xide no drop in the metal 34 What is the relationship between surface potential and gate voltage How is the gate voltage VG distributed throughout the structure VG S 0Xide no drop in the metal N W 0xide g q A xox Cox 510280 N 2K 8 0xide q A x0 S 0 S 510280 CIN A 12qNAKS80 S 0xide x0 510280 35 What is the relationship between surface potential and gate voltage How is the gate voltage VG distributed throughout the structure VG S 0Xide no drop in the metal 2NK8 VGZ QAs0 sx s 510280 4qu KS802 VG SZZ F VT 2 F x X 510280 Threshold voltage 0 0 36

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