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Digital Integ Circuits

by: Cassidy Effertz

Digital Integ Circuits ECE 4420

Cassidy Effertz

GPA 3.64

Jeffrey Davis

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Jeffrey Davis
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This 0 page Class Notes was uploaded by Cassidy Effertz on Monday November 2, 2015. The Class Notes belongs to ECE 4420 at Georgia Institute of Technology - Main Campus taught by Jeffrey Davis in Fall. Since its upload, it has received 16 views. For similar materials see /class/233869/ece-4420-georgia-institute-of-technology-main-campus in ELECTRICAL AND COMPUTER ENGINEERING at Georgia Institute of Technology - Main Campus.



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Date Created: 11/02/15
Power Estimation in Digital Circuits ECE4420 Reading 58 Average Power Consumption Over a Clock Period Isupply Digital Circuits vdd Cf Understand instantaneous power vs average power concept L 7 clk 7 clk 1 Pswitching T J39 Vdd supplytdt fCk J39 VCC suppytdt 0 0 ck Average power per clock period Power Components 7 clk P f Vdd l Clt le supply 0 Dynamic Power Static Power ca acitive switchin DC Standby Power p g Leakage currents eg pseudonmos short Circuit power CirCUitS glitch power Dynamic Power Capacitive Switching Due to charging and discharging of capacitors E E T l Dissipates 1ZCV2 as heat Stores 1ZCV2 on cap Dynamic Power Capacitive Switching During discharge event cap energy dissipates as heat through resistor Vdd RC model Dissipates 1ZCV2 as heat 11 1 Cap is initially charge Dynamic Power Capacitive Switching During a single binary transition dissipates 1ZCV2 energy as heat To reduce power dissipation Reduce capacitance 1 den E Cded fck Reduce supply voltage Reduce clock frequency NOTE I will generally just refer to this component as just the dynamic power Dynamic PowerCapacitive Switching Activity factor 1 fraction of clock periods where output has a binary transition I3a1cvzf 2 dd ck Activity factor 2 fraction of clock periods where the output is switching lowtohigh i PZaomcvdzdfck Short Circuit Power Dissipation DC voltage source E vdd t T V l Pulse input voltage source With nite risetime Tse Short Circuit SC Power Dissipation so short circuit aka crowbar current 393 ISO Vdd Q E vow Both nFE T and pFE T are conducting when input voltage is in the range th Vdd 39Ivtpl vin th Fast rise and fall times ie edge rates can reduce SC power DefinitionCauses of Glitches Glitches are caused by having inputs that are not switching simultaneously Glitches occur when the output node temporarily has a value that is not the steadystate value Example Consider OUTAB when going 01gt10 the following could occur if both inputs do not change simultaneously 01 gt 10 A4 g B 1 OUT W l g litch Inputs not changing at the same time so glitch can occur Dynamic Power Glitches Glitches can cause significant dynamic power dissipation because they represent at least two binary transitions per clock period Designer should minimize glitches to minimize dynamic power dissipation To minimize glitches one must have signals arrive at roughly the same time Designing equal rise and fall times helps to control this because this CAN help to synchronize signal arrival times Static Power Subthreshold leakage currents are the dominate source also pn junction leakage VDS W X ekTq leak 0C I L leak lleak 0C 6 high VT more like dual VT Cool transistors not practical oMinimize size of transistors Static Power W VT VDS 0C 7 kTq leak L leak 0C 6 kTq Ileak 0C e High VDS rres beak Which has more leakage 2W H31 EIE 2W 4W E lt2W VDS is less than inverter 2 2W E 2W Body bias increase VT Clock PeriodSwitching Assumption The following slides assume that we have one binary transition during a clock period ie glitch free v m I Vinputt P t0 t Tdk t2TCk Static Power Measurements in HSPICE Static power low output Static power high output Vdd 1 E Vdd E i a make these DC voltage sources Static power low output Static power high output E o E Q E Static Power Measurements staticpowertestsp option post NGOLD2 T T op Iib 39mosib39 PMOS130nm Iib 39mosib39 NMOS130nm param supply 13 Vlowoutput1 0 39supply39 Vhighoutput 3 0 39supply Iow output mn 21 0 0 n 0130u w20u mp 21 1 1 p 0130u w30u Iow input mn2 4 0 0 0 n 0130u w20u mp2 4 0 3 3 p 0130u w30u end For this case lhave put in both circuits in one file so lhave specified TWO supply voltages If you use the command hspice staticpowertestsp gt log The power supplied by each voltage source is in the log file Search for the text in log operating point and you will find the data you require NOTE In vi use in command mode type operating point ltreturngt and it will take you to this next occurrence static power measurements operating point information tnom 25000temp 25000 operating point status is all simulation time is 0 node votage node votage node votage o1 1300e0002 1472e0703 1300e00 o4 1300e00 voltage sources subckt element 0vowoutp 0vhighout volts 1300e00 1300e00 current 3737e10 1440e11 power 4858e10 1872e11 Lowto High SC Power E lowtohigh transitions For this case the short circuit current can be determined from the nFET Highto Low SC Power E1 SC lowtohigh transitions amplt m m For this case the short circuit current can be determined from the pFET HSPICE simulation L E E E ck Vdd j impdt scHL O 2Tck Vdd j imn dt Tck scLH t Tclk t2TCk HSPICE Sample Code Short Circuit Power Measurements option post NGOLD2 Iib 39moslib39 PMOS lBOnm Iib 39moslib39 NMOS lBOnm param supply 13 Vsupply Vdd 0 39supply39 Vinput l 0 pulse 0 39supply39 0 30p 30p 1n 2n mn 21 O O n O130u w20u mp 2 1 Vdd Vdd p 0130u w40u Cout 2 O 100f tran 1p 3n measure the hightoIow transition measure tran QHL integral imp FROM O TO 1n measure highowSCenergy param 39supplyQHL39 measure the lowtohigh transition measure tran QLH integral imn FROM 1n TO 2n measure LowtohighSCenergy param 39supplyQLH39 end Average Binary Switching Energy per Clock Period Vdd Vinputt P 39139 1 i0 T tTCIk i2Tclk V ck I EtotaIHL Vdd I Vdddt 0 2 Tck This represents total energy supplied by A V I dt power supply during these time intervals totaILH dd d Tck E EtotaHL EtotaLH HL and LH are from the fatal 2 perspective of the output Because we are focused on the output for this calculation we are ignoring energy from Vinput Average Binary Switching Power per Clock Period E1 I Vinputa V T T i0 i Tclk i2 Tclk E E E totaHL totaLH total 2 Etota T clk E For this calculation we are ignoring energy from Vmput Note The words in bold are keywords in HSPICE HSPICE Code Total Power Measurements option post NGOLD2 Iib 39mosib39 PMOS130nm Iib 39mosib39 NMOS130nm param supply 13 Vsupply Vdd 0 39supply39 Vinput 1 0 pulse 0 39supply39 0 30p 30p 1n 2n mn 21 O O n l0130u w20u mp 21 Vdd Vdd p l0130u w40u Cout 2 0100fC supply tran 1p 3n measure the hightolow transition gt measure tran QHL integral iVsupply FROM O TO 1n measure highlowtotalenergy param 39supplyQHL39 measure the lowtohigh transition measure tran QLH integral iVsupply FROM 1n TO 2n measure Lowtohightotalenergy param 39supplyQLH39 print tran v1 v2 end Results Total Energy EtotaLHL 512m EtotaLLH 01851 pJ Short Circuit Enerqv ESQHL 5690fJ ESQLH 3265fJ Leakaqe Power Plow 4858pW Phigh 1872pW Calculation of Dynamic Energy with HSPICE You cannot measure the dynamic power directly with HSPICE however you can solve for dynamic components because all OTHER components are known Etotal LH ESC LH Edyn LH Estatic H Etotal HL ESC HL Edyn HL Estatic L Average Dynamic Binary Switching Energy per Clock Period E E E E dynLH totalLH SCLH staticH EdynHL EtotalHL ESCHL EstaticL Ed EdynHL EdynLH yn 2 Calculation of Dynamic Energy with HSPICE E E E P T total LH SC LH dyn LH static high clk 01851 pJ 3265fJ EMLH 1872pW1ns E 181 83fF dyn LH How does this compare to 1ZCV2 E 218183fF dyn LH gCded O51OOfF132 845fJ Because we ignored drain areas in the HSPICE simulation this should be approximately 12 EdynLH and it is Calculation of Dynamic Energy with HSPICE EtotalHL ESCHL EdynHL PlowTCLK 5127fJ 5690fJ EdynHL 4858pW1ns EdynHL O563fJ This should be much smaller than the 120Vdd and it is because the power supply is not providing energy to the circuit The circuit is discharging energy stored in capacitive node WHY IS THIS NEGATIVE This is due to the feedthrough current that is provided by Vmput see next page Feedth rough Current feedthrough current capacitive current from gate to drain feedthrough current cause voltage overundershoot 39v h V 1 1ft A vE v 4 l Vinput T T L R t K 0 30 EOO 500E10 1W 150E0 200E09 250E09 02 CoACMoch o VIH W MP2 SaWod39lon Mn Y1qu in 2 1 VIH AH jg v p WWI Fn v sn39VTnBVOSn V54 Von39 Im Yasn Vm Wash V001 quot 1F lt V0 V pb39vm Kl VIN 39an Vout 395 Tqye alm39vodwt o bo h sues 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