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Microelectronic Circuits

by: Cassidy Effertz

Microelectronic Circuits ECE 3040

Cassidy Effertz

GPA 3.64

Jeffrey Davis

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Jeffrey Davis
Class Notes
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This 0 page Class Notes was uploaded by Cassidy Effertz on Monday November 2, 2015. The Class Notes belongs to ECE 3040 at Georgia Institute of Technology - Main Campus taught by Jeffrey Davis in Fall. Since its upload, it has received 23 views. For similar materials see /class/233867/ece-3040-georgia-institute-of-technology-main-campus in ELECTRICAL AND COMPUTER ENGINEERING at Georgia Institute of Technology - Main Campus.



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Date Created: 11/02/15
Fabrication of CMOS ICs ECE3 040 Jeff Davis Images taken from textbook J Uymura Introduction to VLSI Circuits and Systems John Wiley and Sons 2002 Outline Overview of Silicon Processing Material Growth and Deposition Lithography CMOS Process Flow Integrated Circuits created on Silicon Wafers 100 300mm Diameter Wafer Die sites Flat The Waier Is sunjecteu to 39quus 01 InuIVquaI processing steps to make each ICE Fabrication Yield Yampx100 N T NG Number of good working die NT Total number of die sites Yield enhancement is complex and time consuming Yield over product lifetime AYicld A B 100 1 w A A2 7 I Initial J i 1 Yield i y Rate of Yield I wo gtquotquot39 Leaming I 4 xg 39 Time V 0 ea E gt W Maly et al Design for Manufactumhility DFM in Suhmicron Domain ICCAD 1993 TSMC 130nm started at 50 Yield in early 2002 and reached 70 by the end of the year K Total of Die NT Estimation l d d9 NT n l L 4Adie J d wafer diameter de wasted edge distance 2 note that this indicates floor function 45 Yield and Die Size 12 YiedD006cmquot2 2m 1 gnm YieldD025cmquot392 1 on YieldD1cmquot392 4 Intel 180nm P4 Chip Area Lesson for VLSI Designer Keep die size SMALL Example AMD vs Intel AMD Athlon XP 180nm 129mm2 200mm wafers Intel s P4 180nm 217mm2 200mm wafers AMD Athlon XP 130nm 80mm2 200mm wafers Intel s P4 130nm 116mm2 300mm wafers Outline Overview of Silicon Processing Material Growth and Deposition Lithography CMOS Process Flow Oxidation For our case we mean adding oxygen to silicon to form silicon dioxide Thermal Oxide Growth put in oxidation furnace from 800 C 12000C O 2 Flow x51 Si02 layer i 39 x xox surfacev T T Silicon wafer Silicon wafer a Growth phase b Final structure XS z 046XOX themial oxide SiO 50ch above original surface 50 below odginal surface Si Wafer Si Wafer Dry VS Wet Oxidation Dry Oxidation Slow but high quality Heat accelerates reaction 8 02 a 802 Wet Oxidation Fast an lower quality Heat accelerates reaction Si H20 a 802 2H2 WetDry Combo Example START 100 ptype 10 ohm cm wafers CLEAN in H2SO4H202 piranha etch 2 min Clean rinse dry RINSE 1 4 min RINSE 2 4 min DRY OXIDIZE 1 hr at 1000 C in Wet Oxygen place wafers in quartz oxidation boat insert into furnace anteChamber push at 12quot per sec at 800 C in Oxygen ramp to 1000 C 10 Cmin 20 min turn on steam 60 min ramp down to 800 C in Oxygen pull at 12quot per sec unload into plastic carriers Diffusion The use of heat to distribute dopant atoms in a region of crystal Doping Silicon Layers selective doping is very important 2 Step Diffusion Process Pre Deposition PreDep Example phosphorus oxychloride POCl3 gas in furnace eventually deposils phosphorus on the surface of a silicon wafer for example Drive In Example Turn o dopanl source and ramp up the temperature to drive in dopanl aloms deeper into the silicon Dopant 1 k Concentration drive in W Distance from surface Ion Implantation primarily mechanism used today Ion source Magnetic Accelerator Mass Separator more precise control shallower junctions som Trimurme an Ion Implantation magnet Inn Snurce wafer target The Ion Stopping Process Ion energies control depth SkeV k to 1MeV Silicon nuclei 0 i Can penetrate thin oxide layers 10 Kev 4 electron clouds oDamage can resultbut is xed With an moderate heated ie Silicon wafer annealing l gtX 0 Physics 101 One electron volt is equal to the amount of energy gained by an electron dropping through a potential difference of one volt which is 16 10quot9 joules Gaussian Implant Pro le lX Rp2 2 AR Np NionXNpe quot Nionbd Straggle Prolecteu any Other materials of interest Chemical Vapor Deposition CVD Gas components react or decompose to form a thin lm of materials This can be at atmospheric pressure APCVD or CVD at low pressure LPCVD and plasma enhanced PECVD chemical vapor deposition CVD Oxide Process Deposited 102 on a surface Where no Si is present Si02 molecules ca 0 600 09 3 O o 00 06900 00 0000 000 Substrate Silane SiH4 gas 202 gas a SiO2 soid 2H20gas LTO Low Temperature Oxides Silicon Nitride Si3N4 0 Often called nitride only 0 Strong barrier to most items 0 Use as an overglass layer to protect chip 38iH4gas 4NH3 gas a Si3N4solid 12H2gas l Silane Ammonia Silicon Nitride Polysilicon Silicon Depositing silicon on silicon dioxide produces small crystallites areas Called poly for short Used for gate eletrotrode in FETs Even heavily doped this has high sheet resistance 0 Refractory metals such Ti coating on poly to decrease sheet resistance this is called a silicide SivH4 a Si 2H2 5006oooc Silane Metal Deposition Metals Aluminum vs Copper 0 aluminum bulk resistivity 286e 6 Q Cm 0 copper bulk resistivity 167e 6 Q Cm Electromigration Current ow displace metal ions in metals dent High current density highcurnt density moves the dent High current density Electromi gration Hillocks current density Metal Deposition techniques Evaporation A vacuum chamber is evacuated and material is evaporated and covers the substrate Not used anymore in industry IC fabrication Sputtering A sputtering gas eg Ar is made into a plasma Ions eg Ar are accelerated toward a metal source Metal atoms are ejected from the source and travel to the wafer source This is referred to as a physical vapor deposition PVD and can be used to deposit insulating lms as well Electro plating Not in book Other terms Chemical Mechanical Polish CMP Deposited oxide Substrate Substrate a After oxide deposition b After CMP Epitaxial Layer Growth EPI Tri TCS 10001180 C HCl Suuvce mm semmunducm amech cummummy edmun 15 15 Mama 5 pm Outline Overview of Silicon Processing Material Growth and Deposition Lithography CMOS Process Flow Photo 2 light Laser Sources 0 250 130nmKrypton Fluoride KrF 248nm 90nm Argon Fluoride ArF 193nm 65nm Fluorine F2 157nm Extreme UV might be the future Reticle or Mask De nition A Glass Pattern on underside Photoresist Application U Photoresist coating Photoresist spray I Spinning wafer 39 9 Vacuum chuck a Resist application b Coated wafer Edge bead Edge bead Flat resist Wafer c Beading Exposure Step Reticle I Projection I I optics ll not shown resistcoated wafer surface Characteristics of positive photoresist ii 4 Reticle y Transmitted light lt Resist Wafer Wafer b After development and rinsing magma i a Exposure pattern Negative photoresist works in opposite way Etching an Oxide Layer Hardened resist layer Patterned oxide layer WWW W M l layer Substrate Substrate a Initial patterning of resist b After etching process Traditional approach wet etch oxide With hydro uoric acid Reactive Ion Etching RF 1356 WWW lt pusnm NIH wqfelis RlE Etching work well with both ion bombardment and chemical reaction etching39quot A Hracqu maunonFIGuq u mm r on pm 1 BEGESa Sillcuu hm Ru Iimm 5 MSource wwwatechsystemcokrcustomriepdf Reactive Ion Etch RIE Anisotropic Etch specieR No undercut Source wwwatechsystemcokrcustomriepdf Ion Implantation of Doped Si Patterns Arsenic ions 039 t e quot o mink trio 1 Lit li fl lifl m a quot 3 i K n K 11 Substrate f M a Incoming ion beam moped ntype regions note lateral doping Step and Repeat Process I die site quot 33 test site I in I a I I u I I v I I I I a 6 I d I v I u Ila I I I I I i I I I 6 I 39 I i 6 ll masking steps Clean Room De nitions Use HEPA lters that are 9997 effective of removing particles that are 05micr0ns or larger Class X clean rooms means that there are less than X particles per cubic foot With diameter greater than 05 micron OTypical clean room facilities have various class levels 0e g TSMC Fab 6 190000sqft 32000 wafer per month Class 100 ballroom has Class 01 minienviroments Outline Overview of Silicon Processing Material Growth and Deposition Lithography CMOS Process Flow nWell and Active Area Masking Steps p epitaxial layer p substrate a Starting wafer with epitaxial layer p Na nWell I maSK b Creation of n Well in p epitaxial layer nFET and pFET will eventually go here Nitride Active Area Mask C Active area definition using nitride oxide Needed to define oxide electrical isolation between devices Field Oxide FOX growth d Silicon etch FOX FOX a m p Na e Field oxide growth f Surface preparation FiEld quotHue Ileeueu to Menu unlue eleuulual IaUIauuu nelweell ueViCES Self Aligned Gate Process GateDrainSource Regions are automatically aligned m p Na n Well a Gate oxide growth X poly poly Poly Mask p Na nWell b Poly gate deposition and patterning Self Aligned Gate Process p gate electrode boron implant pSelect Mask p implants c pSelect mask and implant n gate electrode arsemc implant nSelect Mask n implants d nSelect mask and implant SourceDrain Contacts I 17 39quotquotquotI jquot K n i p nvwell 7 p Na a After anneal and CVD oxide tive Contact Mask Poly Contact b After CVD oxide active contact W plugs Mask Metal Masking Steps etal 1 Mask c M ta11 coating and patterning Via Mask Metal 2 Mask Bonding Pad Structure H To package pin Metal pad Overglass cut To silicon a Top View b Side View Lightly Doped Drain LDD nFET n implant n implant n implant spacers no additional mask needed d Heavy donor implant Lightly Doped Drain LDD nFET n implant n implant n implant spacers no additional mask needed d Heavy donor implant Sthldes oDefined as a refractory metaleg TiTaPt etc coated over silicon or polysilicon oReduce sheet resistance of gate from 25 S2 to 10s mm Ti Si I I I A TlSl 33933quot 39 11 7 39 ptype a LDD FET structure b Silicide formation Silicide reduces contact resistance of Tungsten Contact Copper Interconnect Damascene Oxide trenches for cu copper patterns H810 quot 33quot I 39 fr Wafer Wafer C After planarization Copper needs a barrier layer eg TiN to block diffusion to Si02


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