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Adv VLSI Systems

by: Cassidy Effertz
Cassidy Effertz

GPA 3.64

Jeffrey Davis

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About this Document

Jeffrey Davis
Class Notes
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This 0 page Class Notes was uploaded by Cassidy Effertz on Monday November 2, 2015. The Class Notes belongs to ECE 6130 at Georgia Institute of Technology - Main Campus taught by Jeffrey Davis in Fall. Since its upload, it has received 11 views. For similar materials see /class/233872/ece-6130-georgia-institute-of-technology-main-campus in ELECTRICAL AND COMPUTER ENGINEERING at Georgia Institute of Technology - Main Campus.



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Date Created: 11/02/15
Fabrication of CMOS ICs ECE613O Jeff Davis Images taken from textbook J Uymura Introduction to VLSI Circuits and Systems John Wiley and Sons 2002 Outline Overview of Silicon Processing Material Growth and Deposition Lithography CMOS Process Flow Integrated Circuits created on Silicon Wafers 100 300mm Diameter Wafer Die sites Flat The wafer is subjected to 10005 of individual processing steps to make each ICE Fabrication Yield YN Gx 00 N T NG Number of good working die NT Total number of die sites Yield enhancement is complex and time consuming Total of Die NT Estimation I d d2 e d wafer diameter de wasted edge distance note that this indicates floor function de calculation More exact calculation till1 NT 2 l i0 2b Min R R a I I1J Rj REV jab RW2 Rw radius of wafer a amp b dimensions of the wafer Square Die Approximation Yield and Die Size yieldD 0 06cm quot 2 AMD 180nm yiedoo25cmquot2 1 Athlon XP YieldD1cmquot2 K Intel 180nm P4 08 e E 2 06 gt 04 02 M o I I I I I I I o 1 2 3 Chip Area Yield over product lifetime 11m iii initial View Q quotl r Rate 3139 Yield Learning 2quot W Maly et al Design for Manufacturability DFM in Submicron Domain ICCAD 1993 Lesson for VLSI Designer Keep die size SMALL Example AMD vs Intel AMD Athlon XP 180nm 129mm2 200mm wafers Intel s P4 180nm 217mm2 200mm wafers AMD Athlon XP 130nm 80mm2 200mm wafers Intel s P4 130nm 1165mm2 300mm wafers Outline Overview of Silicon Processing Material Growth and Deposition Lithography CMOS Process Flow Thermal Oxide Growth O 2 Flow x51 SiO2 layer i 4 I XOX surface T T Silicon wafer Silicon wafer a Growth phase b Final structure XS z 046XOX thermal oxide 10 50 above original surface 50 below original surface Si Wafer Si Wafer Dry VS Wet Oxidation Dry Oxidation Slow but high quality Heat accelerates reaction 8 02 a 802 Wet Oxidation Fast but high quality Heat accelerates reaction Si H20 9 802 2H2 WetDry Combo Example START 100 ptype 10 ohm cm wafers CLEAN in H2SO4H202 piranha etch 2 min Clean rinse dry RINSE 1 4 min RINSE 2 4 min DRY OXIDIZE 1 hr at 1000 C in Wet Oxygen place wafers in quartz oxidation boat insert into furnace anteChamber push at 12quot per sec at 800 C in Oxygen ramp to 1000 C 10 Cmin 20 min turn on steam 60 min ramp down to 800 C in Oxygen pull at 12quot per sec unload into plastic carriers CVD Oxide Process Deposited 102 on a surface Where no Si is present 8102 molecules 0 o o 609 09 o O 0600 0000 000000 009 Substrate Silane SiH4 gas 202 gas a SiO2 soid 2H20gas LTO Low Temperature Oxides Silicon Nitride Si3N4 0 Often called nitride only 0 Strong barrier to most items 0 Use as an overglass layer to protect chip 38iH4gas 4NH3 gas a Si3N4solid 12H2gas l Silane Amm0I Iia Silicon Nitride Polysilicon Silicon Depositing silicon on Silicon Dioxide produces small crystallites areas Called poly for short Used for gate eletrotrode in FETs Even heavily doped this has high sheet resistance 0 Refractory metals such Ti coating on poly to decrease sheet resistance this is called a silicide SLH4 a Si 2H2 50060000 Silane Metals Aluminum vs Copper 0 aluminum bulk resistivity 286e 6 Q Cm 0 copper bulk resistivity 167e 6 9 Cm Electromigration Current ow displace metal ions in metals dent High current density High current density highcurnt density moves the dent Electromigration Hillocks Design Rules limit current density Doping Silicon Layers selective doping is very important Ion Implantation 1011 source Magnetic Accelerator Mass Separator Boron Tri ouride BF3 Ion Source Ion Implantation magnet wafer target The Ion Stopping Process Ion energies control depth Ck Silicon nuclei Can penetrate thin oxide layers 94 ODamage can resultbut is fixed 1033300 Kev 4rquot electron clouds With an moderate heated ie anneallng Silicon wafer l hx 0 Physics 101 One electron volt is equal to the amount of energy gained by an electron dropping through a potential difference of one volt which is 16 10 19 joules Gaussian Implant Profile X Rp 2 ARp A 1 2 Np NionXYpe Afton Straggle Em Chemical Mechanical Polish CMP Deposited oxide a x33 77 E qu t Substrate Substrate a After oxide deposition 1 After CMP Epitaxial Layer Growth EPI Triclllorosilane TCS 10001180 C HCl Shame WWW semmmuummamcn cummuma sEunnn wma pub 15215 pm Outline Overview of Silicon Processing Material Growth and Deposition Lithography CMOS Process Flow Photo 2 light EXCimer Laser Sources 0 250 130nmKrypton Fluoride KrF 248nm 90nm Argon Fluoride ArF 193nm 65nm Fluorine F2 157nm Reticle or Mask Definition A Glass Pattern on underside Remember During Layout using CAD tools this is what you are designing Photoresist Application U Photoresist coating Photoresist spray I Spinning wafer 39 9 Vacuum chuck a Resist application b Coated wafer Edge bead Edge bead Flat resist Wafer c Beading Exposure Step Reticle I Projection optics not shown resistcoated wafer surface Characteristics of positive photoresist ii 4 Reticle y Transmitted light lt Resist Wafer Wafer b After development and rinsing swims i a Exposure pattern Negative photoresist works in opposite way Etching an Oxide Layer Hardened resist layer Patterned oxide layer WWWe W M layer l Substrate J l Substrate a Initial patterning of resist b After etching process Reactive Ion Etching RF 1356 mm lt pasnm MHZ H 394 611839 RIE Etching work well with both ion bombardment and chemical reaction etching39quot A y nFIGH39m muFna u mluh on Only a l sahcuu ham Rug Isluh Source wwwatechsystemcokrcustomriepdf Reactive Ion Etch RIE Anisotropic Etch No undercut Source wwwatechsystemcokrcustomriepdf Ion Implantation of Doped Si Patterns f Lil x Substrate 11 Su fLI ate a Incoming ion beam note lateral doping b Doped ntype regions Step and Repeat Process I die site quot 33 test site registration targets for alignment between masking steps Clean Room Definitions Use HEPA filters that are 9997 effective of removing particles that are 05micr0ns or larger Class X clean rooms means that there are less than X particles per cubic foot With diameter greater than 05 micron OTypical clean room facilities have various class levels 0e g TSMC Fab 6 190000sqft 32000 wafer per month Class 100 ballroom has Class 01 SMIF minienviroments Outline Overview of Silicon Processing Material Growth and Deposition Lithography CMOS Process Flow nWell and Active Area Masking Steps p epitaxial layer p substrate a Starting wafer with epitaxial layer p N nWell Mask a b Creation of n Well in p epitaxial layer Nitride nFET and pFET will eventually go here Active Area Mask 0 Active area definition using nitride oxide Needed to define oxide electrical isolation between devices Field Oxide FOX growth f Surface preparation Field Oxide needed to define oxide electrical isolation between devices Self Aligned Gate Process GateDrainSource Regions are automatically aligned m p Na n Well a Gate oxide growth X poly poly Poly Mask p Na nWell b Poly gate deposition and patterning Self Aligned Gate Process p gate electrode boron implant pSelect Mask p implants c pSelect mask and implant n gate electrode arsenic implant nSelect Mask n implants d nSelect mask and implant SourceDrain Contacts Active Contact Mask P Poly Contact b After CVD oxide active contact W plugs Mask Metal Masking Steps Metal 1 Mask c Mstall coating and patterning Via Mask Metal 2 Mask Bonding Pad Structure H To package pin Metal pad Overglass cut To silicon a Top View b Side View Lightly Doped Drain LDD nFET n implant n implant n implant ffff 939quot quot Oxide etch to create sidewall b OX1 d6 coating spacers no addltlonal mask needed Sidewall spacers p Na d After etching d Heavy donor implant Lightly Doped Drain LDD nFET n implant n implant n implant ffff 939quot quot Oxide etch to create sidewall b OX1 d6 coating spacers no addltlonal mask needed Sidewall spacers p Na d After etching d Heavy donor implant Sthldes oDefined as a refractory metaleg TiTaPt etc coated over silicon or polysilicon oReduce sheet resistance of gate from 25 Q to 10s mQH Ti Si I I I A TlSl 33933quot 39 11 7 39 ptype a LDD FET structure b Silicide formation Silicide reduces contact resistance of Tungsten Contact Copper Interconnect Damascene Oxide trenches for copper patterns quotxquotxquotequot ii is 5102 a 39 Wafer Wafer c After planarization Copper needs a barrier layer eg TiN to block diffusion to Si02


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