Digital Systems Test
Digital Systems Test ECE 6140
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This 0 page Class Notes was uploaded by Cassidy Effertz on Monday November 2, 2015. The Class Notes belongs to ECE 6140 at Georgia Institute of Technology - Main Campus taught by David Keezer in Fall. Since its upload, it has received 13 views. For similar materials see /class/233884/ece-6140-georgia-institute-of-technology-main-campus in ELECTRICAL AND COMPUTER ENGINEERING at Georgia Institute of Technology - Main Campus.
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Date Created: 11/02/15
43 Ducmline the oulpul Tnnnlion of If circuit of Fgue417 or the following I mulls a AND bridge belwcen ianIIs of gale G b The mulxipie faun x vnl x2 raO mm 417 Zf xix 3 352X3x4 E X3 x z X3X4 Zf 371964 44 III me circuit of Figure 427 which if any of lhe following lesls delccl the fault x M 7 a 01JJ XI 6 b llll c II0I d LOVLU x a n mun 414 I 21 I 2 a Does notactiva ce O 390 b x21 zo o o cX21 ZU o 0 dX40 Z0 o o or me circuil of gure 427 nd a Boolean expmssion or me sel of all lcsls max delecl lhc laull a x3544 b 2 10 X c 12mm x H A kmm xam Z xgsiuin 0 by substitution 1mm g setZEBZf 1 I 271972263264 ea 0 1 ng a 1 x1x2x3x4 0011 only one test c z EJTZX3X4 339 Z 9712x3954 2 271x3x4 Z xzsiail 0 by substitution 0 setZGB Zf 1 EEX3X4EBXTX3X41 I setzezf1 x1x2x3x4 1 xix 293 ED 0 1 x1x2x3x4 0111 only one test Ex 2X3X4 1 x1x2x3x4 0011 only one test 46 Fur Pt cimuil of Figum 4le 1 End the sol of all lam um damn me laull r xnl I nd lhc scl ol all was 1M dclecl the fault 1 HM c Find Illa m a nu mm mm dawn the mullipl faull r IltHL 11 504 AZABABCAB xxyx C Z AB AB1 AB Figureua 0 Z EB Zf 1 has no solution B ZABABCAB frompartA Zf0BABCABC ZGBZ1 ABEBADC1 A1B1C0 C ZABABC AB from part A Z 03 AB1 0AB AB 39 zeazf1 Q ABEBAB1 which has no solution 53 For the circuit and the fault set used in Example 51 determine the faults detected by the test 11010 by deductive simulation e Liam b 39 l J f ch11 7 J p 19 l 0 1 ll 01 i i s g d L c1 gt71 0 quot Given the circuit above and the collapsed fault list see Example 48 ama1b1coc1d1e0g0huh1 determine the faults detected by 11010 by deductive simulation 7 ReLmber if C 2 then L2 L1 UzsaCL jel else L2 L1 UCLjD UZs a E Bi jEC je I Comparing the collapsed fault list with the input vector we have La 2 510 Lb 3 La 01 La 2 Le 3 Apply to the AND gate f LfLaULbUUs o LaULbaoU ao Not in fault list Lg Cl Lh Cllhl Applyj f to the NOR gate j Lj Lf Lg 10 c1 as Not in fault list Apply fto the AND gate i uLh uljgpgm Lw uawn oqma Not in fault list Apply f to the OR gate k Lk Li ULe Li ULe 51 h1U Clih1 Not in fault list Finally apply fto the OR gate rn FQUUM1FUM m h Not in fault list 39 a0c1 h1 are detected 55 For the latch shown inFigure 536 assume 0 y 1 ends R 1 Assume S 1 I 0 the initial fault lists associated with lines y i R and S are Ly Ly LR and Ls Let S change to a0 Determine the new output fault lists in terms of the given fault lists produced by this input event Also include all sufaults associated with this circuit Assume the initial values y 0 y 1 s 1 R 1 R 1 y Assume the initial fault lists Ly L37 LR L5 Figure 536 Let 590 then find the new output fault list First determine the correct fault free behavior Immaaaa S 1 0 0 0 O R 1 1 1 1 1 7 O n 1 1 y 1 1 1q 0 Next apply f for 2input NAND gate Note for NAND c0 i1 c 63 i 1 E 69139 0 So we can make a table of the fault lists as a function of time We want to continue until the circuit is stable I Lg L5 L5 L3 L5 LR LR LR LR LR Ly Ly LS LYU370EA A A BLsLyU70 Ly Ly Ly AUigyl LS LyU70ULRUy1 Remember 1 for NAND if C a then L2 Lj UZsa Q jeI else L2 L1 U L UZs a IJ jec je 6 O for NAND 57 Repeal the simulation carried out in Example 51 using the concurrent method Show the faull lists after simulating each vector Faults to consider after collapsing ama1b1cocld1eogohmhll if 7 139 Lgllxt 1 4 l 39 d 1 i 3 li 4 m l 1 e 0l Ur Start with the AND gate with output f 5 I l l Next consider the NORgate with output j a 0 f f o Note that none of the b 0 gm J faults considered on i i the AN D gatef effect Note that a a b this NORgate so we a o 1 1 are local faults so x consider only local 1 they are included faults and faults even though f is not effecting g The only a differentfrom the x localfaultm ourllstls correct operation go But co has the i same effect 039 p O O Next consider the ANDgate with output i h 1 d 1 1 I Note the only local faults are d1 ho hi i We also consider c0 1 1 1 Next consider the ORgate with output k Local faults eD But we must also consider the effects of the AND gate with output i Li e ED 8 Finally consider the OR gate with output m Local faults none However we must consider faults from the NOR output j and OR output k gates J o k 1 m ell x Note Looking at the NOR gate we see that its faults do not effect the output m geeeg Therefore is detected 59 For the circuit in Figure 538 detennine the faults detected by the test Ill by a concurrent fault simulation start with a collapsed set of faults b critical path tracingi Part A checkpoint faults 30allbolb1ICOIc1Id10Idlll blo b112 bzobutdzord21te101e111e20321 a Figure 538 Remove equivalent faults collapse awaybob1c0c1d10dn bu b21d20d21 elvezo o Detected faults are aoco e11 dzo