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# Intro to Computer Engr ECE 2030

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This 0 page Class Notes was uploaded by Cassidy Effertz on Monday November 2, 2015. The Class Notes belongs to ECE 2030 at Georgia Institute of Technology - Main Campus taught by Yalamanchili in Fall. Since its upload, it has received 10 views. For similar materials see /class/233895/ece-2030-georgia-institute-of-technology-main-campus in ELECTRICAL AND COMPUTER ENGINEERING at Georgia Institute of Technology - Main Campus.

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K INTRO TO COMP ENG CHAPTERV CHAPTERVl1 COMBINATIONAL LOGIC f CHAPTER VI COMBINATIONAL LOGIC BUILDING BLOCKS RKMDanse 10 KINTRO TO COMP ENG COMBNATONAL LOGIC CHAPTER VI2 NTRODUCTION COMBINATIONAL LOGIC INTRODUCTION Combinational logic Output at any time is determined completely by the current input We will later consider circuits where the output is determined by the input and the current state memory of the system In this chapter we will consider some useful building blocks that can be pieced together and used in larger designs This will include Multiplexers selectors and demultiplexers distributors Encoders priority encoders decoders Adders full and half Parity generators and parity checkers Shifters and rotators Comparators K RM Dansereau V10 KINTRO TO COMP ENG COMBNATONAL LOGIC NTRODUCTON COMBINATIONAL LOGIC BASIC DECODER Standard decoder is an ntomline decoder where m 52quot Example 3to8line decoder Example 0 Do lnputof110 0 0 A0 20 1 D1 020 1 0 00 00 A121 9 3 D3 121 9 3 0 38 4 D4 38 4 0 5 D 5 0 2 5 2 Az 2 6 D6 1 2 6 1 7 D7 7 0 All outputs Dm are low except for the one corresponding to the binary value of the input AnA1A0 x RM Dansereau V10 KINTRO TO COMP ENG COMBNATONAL LOGIC CHAPTER VI4 DECODERS BASC DECODER COMBINATIONAL LOGIC DECODERS WITH ENABLE Often combinational logic building blocks will also have an enable line that turns on outputs or leaves them off 3to8 Decoder with Enable A0 20 0 D0 1 D1 A121 00L 2 D2 9 3 D3 A22 a 8 4 D4 2 D 5 D5 6 7 Module Enable E K RM Dansereau V10 KINTRO TO COMP ENG CHAPTER VI5 COMBINATIONAL LOGIC Truth table for a 3to8line decoder DECODERS TRUTH TABLES BASC DECODER WTH ENABLE k RM Dansereau V10 Inputs Outputs A2 A1 A0 E D7 D6 D5 D4 D3 D2 D1 D0 X X X 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 1 0 0 0 1 1 1 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 0 1 0 1 1 0 0 1 0 0 0 0 0 1 1 0 1 0 1 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 COMBNATONAL LOGIC DECODERS OIgtumN ltm OOltwZgtOZgt FOG O ON A gtmgt4gto N40 N40 gtNgtAo WK Umsmmmom lt90 3230 40 ooltu mzm UmOOUme H wrm3m2agtHHOZ 0ltlt om m amooam Um 3om3m3m n 3 6 089 gtN gt4 gt0 Um Um o Um N o gt wgtm0 UmOOUmW ltlt mzgtwrm NC gtwumm KINTRO TO COMP ENG CHAPTER VI7 COMBINATIONAL LOGIC Inputs Outputs A2A1Ao 1 2 o o o o o o AO20 1 BF 0 o 1 1 1 005 2 F 1 o 1 o o 1 A1 21 5 3 o 1 1 1 o 3 g 1 o o o 1 A2 22 6 QB 1 o 1 o 1 7 1 1 o o o 1 1 1 1 o X DECODERS DESIGNING WITH DECODERS ORing together the function s minterms DECODERS WTH ENABLE TRUTH TABLES MPLEMENTATON Any Boolean function can implemented using a decoder and OR gates by J RM Dansereau V10 KINTRO TO COMP ENG oDECODERS CHAPTER VI8 TRUTH TABLES MPLEMENTATON COMBINATIONAL LOGIC DESGNNG WDECODERS We can also use multiple decoders to form a larger decoder 3to8 Decoder Implemented with two 2to4 Decoders A2 used wrth enable Input 1 V g 1 D to control which decoder A1 2 3 8 2 D1 will output the 1 N 8 2 A2 gto E 3 D3 A1 and A0 used to select 20 L 0 D4 which output on specific 1 V g 1 D5 decoder will output 1 2 4C7 8 2D N G 6 E D 3 D7 K RM Dansereau V10 KINTRO TO COMP ENG oDECODERS CHAPTER V9 MPLEMENTATON DESGNNG WDECODERS COMBINATIONAL LOGIC BASIC ENCODER DECODER NETWORKS Standard binary encoder is an mtonline encoder where m 52 Example 8 to3line encoder Module Enable I Exam 39 ple D0o E Input of00010000 0 0 2 D11 20 Ao 0 2 0 02 2 03 m 5 D3 3 3 21 A 98 21 0 D4 4 9 8 1 1 4 5 8 0 C 0 5 UJ D5 5 LU 2 22 1 D6 6 2 A2 06 0 7 D7 7 Ac Module Active X RM Dansereau V10 KINTRO TO COMP ENG CHAPTER VI10 COMBINATIONAL LOGIC ENCODERS ENCODER TRUTH TABLE Truth table for an 8to3line encoder DECODERS ENCODERS BASC ENCODER k RM Dansereau V10 Inputs Outputs D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 1 1 1 Assumed that only one input is 1 What happens if more then one is 1 J KINTRO TO COMP ENG DECODERS ENCODERS Warsaw COMBINATIONAL LOGIC DESIGNING WITH ENCODERS TRUTH TABLE Encoders are useful when the occurrence of one of several disjoint events needs to be represented by an integer identifying the event 1 Example Wind direction encoder I E O 1 2O 1 2 L 3 03 c39gt U 21 o 4 7 00 0 C 5 LIJ 22 6 O 7 K pp 253254 of Ercegovac Lang and Moreno Introduction to Digital Systems 1999 RM Dansereau v10 KINTRO TO COMP ENG CHAPTER VI12 COMBINATIONAL LOGIC that index to the output ENCODERS PRIORITY ENCODERS ENCODERS BASC ENCODER TRUTH TABLE DESGN W ENCODERS A priority encoder takes the input of 1 with the highest index and translates k RM Dansereau V10 Inputs Outputs D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 X 0 0 1 0 0 0 0 0 1 X X 0 1 0 0 0 0 0 1 X X X 0 1 1 0 0 0 1 X X X X 1 0 0 0 0 1 X X X X X 1 0 1 0 1 X X X X X X 1 1 0 1 X X X X X X X 1 1 1 J INTRO TO COMP ENG oENCODERS ENCODERS COMBINATIONAL LOGIC DESIGN WITH P39ENCODER PRORTY ENCODERS K Priority encoders are useful when inputs have a predefined priority and we wish to select the input with the highest priority Example Resolving interrupt requests Request Lines 1 Priority 0 gt B E 8 1 Processor 2 39 9 o 2 3 a 5 Highest A c K pp 253256 of Ercegovac Lang and Moreno Introduction to Digital Systems 1999 RM Dansereau V10 KINTRO TO COMP ENG CHAPTER VI14 COMBINATIONAL LOGIC MULTIPLEXERS BASIC MULTIPLEXER MUX ENCODERS DESGN W ENCODERS PRORTY ENCODERS DESGN W PENCODERS E 4X1 Multiplexer k RM Dansereau V10 x gn lt g Selects one of many inputs to be directed to an output Module Enable Inputs Output X Y A3 A2 A1 A0 F 0 0 X X X 0 A0 0 1 X X 0 X A10 1 0 X 0 X X A20 1 1 0 X X X A30 0 0 X X X 1 A01 0 1 X X 1 X A11 1 0 X 1 X X A21 1 1 1 X X X A31 KINTRO TO COMP ENG oENCODERS CHAPTER VI15 MULTPLEXERS COMBINATIONAL LOGIC USING PASS GATES BASIC MULTIPLEXER lt o The 4x1 mux can be implemented with pass gates as follows Y X 0 gtOi gt gtoi I At 6 39 0 Out f 33 E A Only one of An gets passed to output 3 Depends on the value of X and Y K RM Dansereau V10 K INTRO TO COMP ENG MU T PLEXE RS IEEEIEE ERS CHAPTER Vl16 BASIC MULTIPLEXER COMBINATIONAL LOGIC DESIGN WITH MULTIPLEXERS USNG PASS GATES Any Boolean function can be implemented by setting the inputs corresponding to the function and the selectors as the variables Example l Module Enable gtltZ F1 E o o o o 0 0 o o 1 1 1 1 L 0 2 a 0 1 0 0 13 5 gtltE f 0 1 1 1 O4 ODE 5 1 0 0 0 o5 g 1 0 1 0 0 6 1 1 1 0 0 7828180 1 1 1 1 l K RM Danscrcau V10 KINTRO TO COMP ENG MULTPLEXERS CHAPTER VI17 BASC MULTIPLEXER USNG PASS GATES COMBINATIONAL LOGIC BASIC DEMULTIPLEXER DESGN W MULTIPLEX Takes one input and selects one of many outputs to direct the input Module Enable Inputs Outputs E X Y w D3 02 D1 D0 5 0 90 0 o o o o o W0 5 o 1 o o o W0 o 1 D W 3 1 1 o o o W O o o g 2D2 1 1 o W0 o o o G 0 3 03 0 o 1 o o w1 o 1 1 o o w1 o S1S0 1 o 1 o w1 o 0 XY 1 1 1 10 o o K RM Dansereau V10 KINTRO TO COMP ENG MULTPLEXERS CHAPTER Vl18 DEMULTPLEXERS DESIGN W DEMULTIPLEXERS BASIC DEMULTIPLEXER COMBINATIONAL LOGIC lt o A demultiplexer is useful for routing an input to a desired location Example 1 E Processing Unit 0 gt O Q g 1 Processing Unit 1 gt Input Data 2 2 E M Processing Unit 2 gt 3 S1 80 Processing Unit 3 gt Selects Wthh PU to send X Y the input data 39 K RM Dansereau V10 KINTRO TO COMP ENG oMULTIPLEXERS CHAPTER VI19 DEMULTPLEXERS BASIC DEMULTIPLEXER COMBINATIONAL LOGIC DESGN W DEMULTIPLEX o A shifter takes a set of inputs and shifts it to the right or left 4bit Shifter A3 A2 A1 A0 I I I I It i E Shift 8 YN 2 fa 0 YesNo if it A it E Module Enable Direction 1 UR M quot Kw y IXquot X It II Leftngm D3 D2 D1 D0 k RM Dansereau V10 KINTRO TO COMP ENG oMULTIPLEXERS CHAPTER Vl20 DEMULTPLEXERS oSHIFTERS COMBINATIONAL LOGIC COMMON SHIFTERS BASC SHIFTERS o A whole variety of other shifters are possible such as A3 A2 A1 A0 A3 A2 A1 A0 3 2 1 O 3 2 1 O S YN d LR 4bit E 4bIt E d LR Shifter 50 d t ShIfter s Is ance q ms 3 2 1 o 1 1 o I I I I I I I I I D3 D2 D1 D0 DdIsc D3 D2 D1 D0 Value to Value discarded Distance in binary insert into from shift of how far to shift empty spot K RM Dansereau V10 KINTRO TO COMP ENG DEMULTPLEXERS CHAPTER VI21 SHFTERS BASIC SHIFTERS COMBINATIONAL LOGIC BASIC ROTATOR COMMON SHIFTERS A rotator takes a set of inputs and rotates it to the right or left This is similar to a shifter except that instead of dropping the bit off of the end in the shifting the normally discarded bit is taken and moved to fill the empty spot on the end 4bit Rotator A3 A2 A1 A0 Rotate YesNo S E Module Enable Direction d LeftRight K RM Dansereau V10 KINTRO TO COMP ENG oDEMULTIPLEXERS CHAPTER VI22 SHFTERS ROTATORS COMBINATIONAL LOGIC HALF AND FULL ADDERS BASC ROTATOR Two basic building blocks for arithmetic are half and fulladders as depicted by the block diagrams below if if COUT lt HA COUTlt FA lt CIN Carryout Carryout Carryin S 8 Sum Sum Halfadder Fulladder K RM Dansereau V10 KINTRO TO COMP ENG CHAPTER VI23 COMBINATIONAL LOGIC HALFADDER HA SHFTERS ROTATORS ADDERS ADDERS HALF amp FULLADDERS First of all how do we add k RM Dansereau V10 Inputs Sum Carryout A B S COUT 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 2 s complement arithmetic allows us to add numbers normally 3 KBA AeB COUTZAB F DS 3 COUT KINTRO TO COMP ENG CHAPTER VI24 COMBINATIONAL LOGIC additional carryin Inputs Carryin A DDE RS FULLADDER FA 1 Sum Carryout k RM Dansereau V10 A B CIN 3 COUT 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 ROTATORS ADDERS HALF amp FULLADDERS HALFADDER HA Halfadder missed a possible carryin A fulladder FA includes this s A B CIN J KINTRO TO COMP ENG oADDERS CHAPTER VI25 HALF amp FULLADDERS HALFADDER HA COMBINATIONAL LOGIC FULL ADDER FA 2 FULLADDER FA F Halfadder Halfadder RM Dansereau V10 KINTRO TO COMP ENG oADDERS CHAPTER VI26 HALF amp FULLADDERS HALFADDER HA COMBINATIONAL LOGIC BINARY ADDITION FULLADDER FA o A 4bit binary adder can be formed with four fulladders as follows A3 B3 A2 B2 A1 B1 A0 B0 C3 C2 C1 FA FA lt FA lt FA lt Co S3 S2 S1 S0 K RM Dansereau V10 K INTRO TO COMP ENG COM PA RATO RS quot P ff ADDER HA CHAPTER Vl27 FULLADDER FA COMBINATIONAL LOGIC MAGNITUDE COMPARATOR BNARY ADDITION j Given two n bit magnitudes A and B a comparator indicates whether ABAgtBorAltB n bit input magnitudes Cascaded input A B values from other Results of comparators r comparisons Greater cinG gt 4 Bt gt G Greater A gt B Equal cinE gt Comparator E Equal A B Less cinL gt gt L Less A lt B K RM Dansereau V10 KINTRO TO COMP ENG g niiiATORs CHAPTER VI28 MAGNITUDE COMPARATOR 39MAG COMPARATOR COMBINATIONAL LOGIC lt o The approach is to use the XNOR function equivalence on each of the n bits as follows Xi AiBiKIEI WI The Boolean functions for a 4bit magnitude comparator is as follows A B X3X2X1XO A gt B Asa 3 st232 X3X2A1B 1 X3X2X1AOB O AltB EB3X3ATZBZX3X2AT1B1X3X2X1EBO Note AIEI indicates whether Agt 3 EB indicates whether Ailt Bi and X indicates whether A B K RM Dansereau V10 KINTRO TO COMP ENG CHAPTER IV1 GATE DESIGN X 1 CHAPTER IV GATE DESIGN CHAPTER IV f k KINTRO TO COMP ENG GATE NETWORKS CHAPTER IV2 GATE DESIGN Gate network consists of Gates External inputs and outputs Connections Gate inputs Only one connection to input is allowed unless tristate device is used Connected to constant value 0 or 1 Connected to an external input Connected to a gate output Gate outputs Output load should not be greater then the fanout factor for the gate and technology being used RM Dansereau V10 J K INTRO TO COMP ENG GATE NETWORKS CHAPTER M3 GATE NETWORKS INTRODUCTION GATE DESIGN VALIDINVALID NETWORKS K 3 Valid or Invalid Valid or Invalid igt Ea Valid or Invalid Valid or Invalid x RM Dansereau v10 CHAPTER IV4 GATE DESIGN X A F B F AB 6 transistors BUFFER RM Dansereau V10 KINTRO TO COMP ENG LOGIC GATES NONINVERTING OPERATORS ABF 000 010 100 111 FAB 6 transistors AF 00 11 GATE NETWORKS NTRODUCTON VALDNVALD NET F A AB A B 8 transistors J KINTRO TO COMP ENG oGATE NETWORKS CHAPTER IV5 LOGC GATES NONINVERTNG OPER GATE DESIGN INVERTING OPERATORS K A B F NAND 0 0 1 A 0 1 1 0 F 1 0 1 B 1 1 0 F A B F A B 4 transistors 4 transistors A B F XNOR 0 1 A 0 1 0 1 1 1 FK FABK A B 2 transistors 8 transistors K RM Dansereau V10 KINTRO TO COMP ENG oGATE NETWORKS CHAPTER IV6 LOGC GATES GATE DESIGN INVERTERS NONNVERTNG OPER NVERTNG OPERATOR Inverters can also be implemented with a NAND or with a NOR gate NAND A F A A F A XFF o 1 A bF o o 1 1 o 1 1 o FA FnA NAND NOR agt L n ogt O 39l1 gt n ogt ogt O 39l1 RM Dansereau V10 W INTRCOHXSTCEORNIICJENG I C N LOGIC GATES NONNVERTNG OPER NVERTNG OPERATORS GATE DESIGN FROM BOOLEAN FUNCTIONS INVERTERS lt Implement the following Boolean function using logic gates F ABC2DCDE Possible solution E F 3 x SAND 3 x 6OR 3 x ZNOT 42 transistors for CMOS technology k RM Danscrcau V10 K INTRO TO COMP ENG LOGC NETWORKS 832 g zRKs CHAPTER N39s FROM BOOL FUNCTIONS GATE DESIGN USING SPECIFIC GATES j Because of various implementation reasons it may be desired to use only specific sorts of logic gates in an implementation For instance many CMOS implementations use only NAND gates Some implementations use on NOR gates This can be done in a number of manners One is to rework the Boolean functions so that only the specific gates desired are used May reduce the physical number of transistors required if the appropriate types of gates are used K RM Dansereau V10 KINTRO TO COMP ENG oLOGlC GATES CHAPTER N9 LOGIC NETWORKS LOGIC NETWORKS FROM BOOL FUNCTIONS GATE DESIGN EXAMPLE USING NAND GATES USNG SPECIFIC GATES Implement the following Boolean function using NAND gates F ABC2DCDE This Boolean function can be expressed as F KBEDEDE A BC DC DE A gt0 How to implement B 3f 4input NAND C 3 I 9amp3 D J 6 x 4W ND2 8NAND4 32 transistors E 3 X 4NAND2 8NAND4 3 x ZNOT 26 transistors k RM Dansereau V10 KINTRO TO COMP ENG oLOGlC NETWORKS CHAPTER lv10 FROM BOOL FUNCTIONS USNG SPECIFIC GATES GATE DESIGN INTRODUCTION EXAMPLE USING NAND Mixed logic is one approach that makes it easier to redesign a logic network to use desired types of gates Mixed logic is also selfdocumenting This means that you can see what the original designer started with and see how the logic network was changed for the implementation The idea behind mixed logic is to diagram out the logic network from the Boolean equations given and then make small changes to the logic network to achieve desired results for implementation K RM Dansereau V10 KINTRO TO COMP ENG LOGIC NETWORKS CHAPTER IV11 D MXED LOGIC GATE DESIGN DEMORGAN S SQUARE NTRODUCTION lt DeMorgan s Square RM Dansereau V10 KINTRO TO COMP ENG LOGIC NETWORKS CHAPTER IV12 MXED LOGIC NTRODUCTON GATE DESIGN MIgtltED LOGIC PROCEDURE DEMORGAN S SQUARE The procedure for performing mixed logic conversions is as follows Draw the logic network for the given Boolean equation Use only AND and OR gates Replace all complements with a bar no bubbles or inverters yet Once the initial Boolean equation is drawn with AND gates OR gates and bars the selfdocumenting redesign begins Add complement bubbles and NOT gates within the network to appropriately convert logic gates to desired gate sets The rules in adding complement bubbles and NOT gates All bubbles must cancel each other out Exactly one and only one bubble needed on each bar K RM Dansereau v10 KINTRO TO COMP ENG MXED LOGIC CHAPTER IV13 D NTRODUCTON DEMORGAN S SQUARE GATE DESIGN MXED LOGIC PROC Implement the following Boolean function using NAND gates and then also using NOR gates F AB ED Solution Start by drawing the logic network for the Boolean function with the complements as bars c l D This completes the information needed to get back original equation K RM Danscrcau V10 KINTRO TO COMP ENG oMlXED LOGIC CHAPTER IV14 DEMORGAWSSQUARE PROCEDURE GATE DESIGN EXAMPLE 1 2 EXAMPLE 1 K lt continued using NAND gates A B 3 This logic network now only uses NAND gates and inverters This results in the following Boolean function as obtained previously FA B c D E A BE k RM Dansereau V10 KINTRO TO COMP ENG oMlXED LOGIC CHAPTER IV15 DEMORGAN S SQUARE PROCEDURE GATE DESIGN EXAMPLE 1 3 EXAMPLE 1 lt continued using NOR gates This logic network now only uses NOR gates and inverters This results in the following Boolean function as obtained previously FABCDE K CE k RM Dansereau V10 KINTRO TO COMP ENG MIXED LOGIC CHAPTER IV16 DEMORGAN S SQUARE PROCEDURE GATE DESIGN EXAMPLE 2 1 EXAMPLE 1 Implement the following Boolean function using NAND gates F ABC2DCDE Solution Start by drawing the logic network for the Boolean function with the complements as bars A 3 1 CH D E F K RM Danscrcau V10 K INTRO TO COMP ENG CHAPTERVI CHAPTER VIII1 FINITE STATE MACHINES f CHAPTER VIII FINITE STATE MACHINES FSM RKMDanse 10 KINTRO TO COMP ENG CHAPTER VIII2 FINITE STATE MACHINES INTRODUCTION From the previous chapter we can make simple memory elements Latches as well as latches with control signals Flipflops Registers The goal now is to use the memory elements to hold the running state of the machine The state of the machine can be used to perform sequential operations This chapter will discuss how to represent the state of the machine for design and communication purposes K RM Dansereau V10 KINTRO TO COMP ENG CHAPTER VIII3 FINITE STATE MACHINES MEALY amp MOORE MACHINES Mealy machine Sequential system where Iquot Sequential system 1 output depends on current npUt Combinational Output input and state Logic Memory state Moore machine L J Sequential system where lr S eaue tiaT ysfe r 1 OUtpUt depends only on M Combinational current state Logic 1 Memory 39 Output I gt state K RM Dansereau V10 KINTRO TO COMP ENG oSTATE MACHINES CHAPTER VIII4 NTRODUCT0N MEALY amp MOORE MACH FINITE STATE MACHINES SYNC amp ASYNC SYSTEMS Synchronous sequential system Behaviour depends on the inputs and outputs at discrete instants of time Flipflops registers and latches that are enabledcontrolled with a signal derived from clock form a synchronous sequential system Asynchronous sequential system Behaviour depends on inputs at any instant of time Latches without control signals behave in an asynchronous manner The state machines discussed in this chapter will be synchronous sequential systems ie controlled by a clock This allows us to form timed Boolean functions such as Nt DAt 1 where N is the next state ofa D flipflop DA x RM Dansereau v10 KINTRO TO COMP ENG oSTATE MACHINES CHAPTER VIII5 NTRODUCT0N MEALY amp MOORE MACH FINITE STATE MACHINES ELEMENTS OF DIAGRAMS stc s ASYNC svsmws o A state diagram represents a finite state machine FSM and contains Circles represent the machine states Labelled with a binary encoded number or 8k reflecting state Directed arcs represent the transitions between states Labelled with inputoutput for that state transition ap Input Xt e a b Output zt e p q a State st 6 80 5 State bq nitia state 50 8k InputOutput K RM Dansereau V10 KINTRO TO COMP ENG oSTATE MACHINES CHAPTER VIII6 STATE DIAGRAMS ELEMENTS OF DIAGRAMS FINITE STATE MACHINES PROPERTIES Some restrictions that are placed on the state diagrams FSM can only be in one state at a time Therefore only in one state or one circle at a time State transitions are followed only on clock cycles synchronous Mealy machines and Moore machines can be labelled differently Mealy machine Since output depends on state and inputs Label directed arcs with inputoutput for that state transition Moore machine Since output depends only on state Label directed arcs with input for that state transistion Label state circles with Skoutput K RM Danscrcau V10 KINTRO TO COMP ENG oSTATE MACHINES CHAPTER VIII7 STATE DIAGRAMS ELEMENTS OF DIAGRAMS FINITE STATE MACHINES STATE DIAGRAM EXAMPLES PROPERTES j o The following is a simple example What does this state machine do 01 00 lnput Xt 6 01 Output zt e 0 1 State st e 80 S1 lnitial state 50 80 An input of 0 or 1 causes the transition with output 1 and 0 respectively K RM Dansereau V10 KINTRO TO COMP ENG oSTATE DIAGRAMS CHAPTER VIII8 ELEMENTS OF DIAGRAMS PROPERTES FINITE STATE MACHINES BIT FLIPPER EXAMPLE STATE DIAGRAM EX Consider the simple bit flipper looked at the in previous chapter How would a state diagram be formed Below is one possible way of drawing the state diagram for the bit flipper K RM Dansereau V10 KINTRO TO COMP ENG oSTATE DIAGRAMS CHAPTER VIII9 PROPERTES STATE DIAGRAM EX FINITE STATE MACHINES PATTERN DETECT EXAMPLE BIT FLIPPER EX Suppose we want a sequential system that has the following behaviour Input Xt 6 01 Output zt e 0 1 1 ifxt 3 t 1101 Function zt 0 othenNise Effectively the system should output a 1 when the last set of four inputs have been 1101 For instance the following output zt is obtained for the input Xt t 0123456789 Xt 100100100100110101101101001101001 zt 000000000000100001001000001000 K RM Danscrcau V10 KINTRO TO COMP ENG oSTATE DIAGRAMS CHAPTER VIII10 STATE DIAGRAM EX BT FLIPPER EX FINITE STATE MACHINES PATTERN DETECT EXAMPLE PATTERN DETECT EX The following state diagram gives the behaviour of the desired 1101 pattern detector Consider SO to be the initial state 81 when first symbol detected 1 82 when subpattern 11 detected and 83 when subpattern 110 detected 00 K RM Dansereau V10 KINTRO TO COMP ENG STATE DIAGRAMS CHAPTER VIII11 STATE DIAGRAM EX BT FLIPPER EX FINITE STATE MACHINES INTRODUCTION PATTERN DETECT EX State tables also express a systems behaviour and consists of Present state The present state of the system typically given in binary encoded form or with 8k So a state of S5 in our state diagram with 10 states would be represented as 0101 since we require 4 bits lnputs Whatever external inputs used to cause the state transitions Next state The next state generally in binary encoded form Outputs Whatever outputs other then the state for the system Note that there would be no outputs in a Moore machine K RM Danscrcau v10 KINTRO TO COMP ENG STATE DIAGRAMS CHAPTER VIII12 STATE TABLES NTRODUCTON FINITE STATE MACHINES BIT FLIPPER EXAMPLE lt Consider again the bit flipper example with state diagram The state table for this state diagram would be Present State Input Next State Output SO 39 1 39 S1or1 0 K RM Dansereau V10 KINTRO TO COMP ENG CHAPTER VIII13 FINITE STATE MACHINES STATE DIAGRAMS STATE TABLES NTRODUCTON STATE TABLES TRANSLATE FROM DIAGRAM From a state diagram a state table is fairly easy to obtain Determine the number of states in the state diagram the state table have 22 4 possible inputs for a total of 3412 rows Write out for each state the 2 possible input rows determine the next state and the output k RM Dansereau V10 BT FLIPPER EX Ifthere are m states and n 1bit inputs then there will be m2quot rows in Example If there are 3 states and 2 1bit inputs each state will For each stateinput pair follow the directed arc in the state diagram to J KINTRO TO COMP ENG CHAPTER VIII14 FINITE STATE MACHINES STATE TABLES PATTERN DETECT EXAMPLE STATE TABLES NTRODUCTON BT FLIPPER EX TRANSLATE DIAGRAM following would be the state table If we consider the pattern detection example previously discussed the k RM Dansereau V10 Present State Input Next State Output P1 P0 X N1 N0 Z 80 or 0 0 0 80 or 0 0 0 80 or 0 0 1 S1 or 0 1 0 S1 or 0 1 0 80 or 0 0 0 S1 or 0 1 1 52 or 1 0 0 82 or 1 0 o 83 or 1 1 o 82 or 1 0 1 82 or 1 0 o 83 or 1 1 0 80 or 0 0 o 83 or 1 1 1 S1 or 0 1 1 KINTRO TO COMP ENG oSTS EF39IILAPBPLEERSEX CHAPTER VIII15 TRANSLATE DIAGRAM FINITE STATE MACHINES TRANSLATE TO DIAGRAM PATTERN DETECT EX o If given a state table the state diagram can be developed as follows Determine the number of states in the table and draw a state circle corresponding to each one Label the circle with the state name for a Mealy machine Label the circle with the state nameoutput for a Moore machine For each row in the table identify the present state circle and draw a directed arc to the next state circle Label the arc with the inputoutput pair for a Mealy machine Label the arc with the input for a Moore machine K RM Danscrcau V10 KINTRO TO COMP ENG oSTATE TABLES CHAPTER VIII16 TRANSLATE DIAGRAM PATTERN DETECT EX FINITE STATE MACHINES INTRODUCTION TRANSLATE TO DIAGRAM K With the descriptions of a FSM as a state diagram and a state table the next question is how to develop a sequential circuit or logic diagram from the FSM Effectively we wish to form a circuit as follows In uts 390 Combinational gt Outputs Network Mealy machine State Present State 1 2 Next State 39 gt Outputs 1 2 Moore machine K RM Dansereau V10 KINTRO TO COMP ENG oSTATE TABLES CHAPTER VIII17 SEQUENTIAL CIRCUITS NTRODUCTON FINITE STATE MACHINES FROM STATE TABLE lt K The procedure for developing a logic circuit from a state table is the same as with a regular truth table Generate Boolean functions for each external outputs using external inputs and present state bits each next state bit using external inputs and present state bits Use Boolean algebra Karnaugh maps etc as normal to simplify Draw a register for each state bit Draw logic diagram components connecting external outputs to external inputs and outputs of state bit registers which have the present state Draw logic diagram components connecting inputs of state bits for next state to the external inputs and outputs of state bit registers which have the present state K RM Dansereau V10 KINTRO TO COMP ENG oSTATE TABLES CHAPTER VIII18 SEQUENTIAL CIRCUITS NTRODUCTON FINITE STATE MACHINES PATTERN DETECT EXAMPLE DEVEL LOGIC CIRCUITS Following the procedure outlined Boolean functions for the pattern detector state table can be formed using Karnaugh maps as follows 13930 13930 13930 X 00 011110 X 00 011110 X 00 011110 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 1 0 1 0 0 1 0 N1 N0 Z N1 XP1P1P0 N0 P1P0XP1P0XP 1P o P 1P0XP1 Po z XP1P0 K RM Dansereau V10 KINTRO TO COMP ENG SEQUENTIAL CIRCUITS CHAPTER VIII19 INTRODUCTION DEVEL LOGIC CIRCUITS FINITE STATE MACHINES PATTERN DETECT EXAMPLE PATTERN DETECT EX Notice that the previous Boolean functions can also be expressed with time as follows N1t P1t1 XtP1tTtP1tPot N0t P0t1 TtP1tP0tXtP1tP0t MurrowWt WmPotXtP1tepot Zt XP1tP0t An important thing to note in these equations is the relation between the present states P and the next states N k RM Dansereau V10 KINTRO TO COMP ENG CHAPTER VIII20 FINITE STATE MACHINES SEQUENTIAL CIRCUITS NTRODUCTON PATTERN DETECT EXAMPLE 39DEVEL LOG39C C39RCU39TS PATTERN DETECT EX w o The following logic circuit implements the pattern detect example 391ltl2 if N1 P1 0 3 D1 12 X Q a K RM Dansereau V10 W U KINTRO TO COMP ENG SEQUENTIAL CIRCUITS CHAPTER quot41 39L L ESE39ENCRCUTS FINITE STATE MACHINES EXAMPLE 1 PATTEiN DETECT EX Consider the following system description A sequential system has One input a b c One output p q Output is q when input sequence has even of as and odd of Us p othenNise K RM Dansereau V10 KINTRO TO COMP ENG SEQUENTIAL CIRCUITS CHAPTER VIII22 FSIIEAXEAIEAI1IELE1 FINITE STATE MACHINES EXAMPLE 1 J We can begin forming a state machine for the system description by reviewing the possible states In addition assign each state a state name SEE even of as and even of Us output is p SE0 even of as and odd of Us output is q 800 odd of as and odd of Us output is p 80E odd of as and even of Us output is p Note that this machine can be a Moore machine So we can associate the output with each state k RM Dansereau v10 KINTRO TO COMP ENG SEQUENTIAL CIRCUITS CHAPTER VIII23 FSM EXAMPLES EXAMPLE 1 FINITE STATE MACHINES EXAMPLE 1 j Now draw a circle with each state K RM Dansereau V10 KINTRO TO COMP ENG SEQUENTIAL CIRCUITS CHAPTER VIII24 FSM EXAMPLES EXAMPLE 1 FINITE STATE MACHINES EXAMPLE 1 j Finally for each state consider the effect for each possible input For instance starting with state SEE the next state for the three input a b and c are determined as follows t 0 e K RM Dansereau V10 KINTRO TO COMP ENG SEQUENTIAL CIRCUITS CHAPTER VIII25 FSM EXAMPLES EXAMPLE 1 FINITE STATE MACHINES EXAMPLE 1 j Finishing the state diagram the following is obtained K RM Dansereau V10 KINTRO TO COMP ENG SEQUENTIAL CIRCUITS CHAPTER VIII26 FSM EXAMPLES EXAMPLE 1 FINITE STATE MACHINES EXAMPLE 1 j A state table can also be formed for this state diagram as follows First assign a binary number to each state SEE 00 SEO 01 800 10 80E 11 Assign a binary number to each input a00b01c10 Assign a binary number to each output p 0 q 1 Then for each state find the next state for each input In this case there are three possible input values so three possible state transitions from each state The state table on the following slide shows the results for this example K RM Dansereau V10 KINTRO TO COMP ENG CHAPTER VIII27 FSM EXAMPLES SEQUENTIAL CIRCUITS FSM EXAMPLES FNTE STATE MACHINES EXAMPLE 1 EXAMPLE 1 j K Present State Input Next State output P1 P0 X N1 N0 2 SEE0 0 a00 SOE1 1 po SEE0 0 b01 SEO0 1 po SEE0 0 c10 SEEzo 0 p0 SEO0 1 a00 300 o q1 SEO0 1 SEE0 0 11 SEO0 1 c10 SEO0 1 q1 8001 0 300 SEo0 1 p0 8001 0 b01 SOE1 1 po 8001 0 1 3001 0 p0 SOE1 1 300 SEE0 0 po SOE1 1 800 0 pzo SOE1 1 c10 30E 1 po K RM Dansereau V10 KINTRO TO COMP ENG SEQUENTIAL CIRCUITS CHAPTER VIII28 FSM EXAMPLES EXAMPLE 1 FINITE STATE MACHINES EXAMPLE 1 j The Boolean function for the output can be determined from a Karnaugh map as follows Note that an input of 11 is not possible since we only have three inputs that we have assigned to 00 01 and 10 We can therefore use don t cares for this possible input P1Po X1Xo 00 01 11 10 00 0 1 01 0 11 X 10 0 gtlt gtlt 1 X 1 K RM Dansereau V10 KINTRO TO COMP ENG CHAPTER VIII29 FINITE STATE MACHINES SEQUENTIAL CIRCUITS FSM EXAMPLES EXAMPLE 1 FSM EXAMPLES EXAMPLE 1 o The Boolean function for the next state bit can also be determined from Karnaugh maps as follows 13930 13930 X1X0 00 01 11 10 X1Xo 00 01 11 10 00 1 1 0 0 00 1 0 0 1 01 0 0 1 1 01 1 0 0 1 11 X X X X 11 X X X X 10 0 0 1 1 10 0 1 1 0 N1P1 X1 Xo N0P0x10T1P0eax1 k RM Dansereau V10 J KINTRO TO COMP ENG SEQUENTIAL CIRCUITS CHAPTER VIII30 FSM EXAMPLES EXAMPLE 1 FINITE STATE MACHINES EXAMPLE 1 j The following logic circuit can be made with these Boolean functions N1 P1 63 X1 63 X0 N0 POCJBX1 z P1P0 NO P X1 0 1 DIZ Xo wm P1 32 in 2 K RM Dansereau V10 KINTRO TO COMP ENG SEQUENTIAL CIRCUITS CHAPTER VIII31 FSM EXAMPLES EXAMPLE 1 FINITE STATE MACHINES EXAMPLE 2 j K o A sequential circuit is defined by the following Boolean functions with input X present states P0 P1 and P2 and next states N0 N1 and N2 N2 XP1 P0P1 P0 N123932 N023931 ZXP1P2 Derive the state table Derive the state diagram K RM Dansereau V10 KINTRO TO COMP ENG SEQUENTIAL CIRCUITS CHAPTER VIII32 FSEIIX gt MELE1 FINITE STATE MACHINES EXAMPLE 2 EXAMPLE 2 K lt o The state table is formed as follows Present State Input Next State Output P2 P1 P0 X N2 N1 N0 Z 0 o o 0 1 o o 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 o o 1 1 1 o o 0 0 1 0 0 0 0 1 0 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 1 0 0 1 0 1 0 0 0 1 1 0 0 1 0 0 1 0 1 0 0 1 o 1 0 o 1 o 0 1 0 1 1 1 1 0 0 1 1 0 0 0 1 1 0 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 0 1 1 1 1 0 1 1 1 K RM Dansereau V10 K INTRO TO COMP ENG CHAPTERVI CHAPTER VII1 SEQUENTIAL SYSTEMS f CHAPTER VII SEQUENTIAL SYSTEMS LATCHES amp REGISTERS RKMDHSC 10 KINTRO TO COMP ENG oSli gggECl gSNTEMS CHAPTER VII2 SEQUENTIAL SYSTEMS INTRODUCTION lt So far So far we have dealt only with combinational logic where the Input Combinational Output gt output is formed from the 39 Logic current input Sequential systems Sequential systems extend the idea of combinational logic by including a system state or in other words memory to our system This allows our system to perform operations that build on past operations in a sequential manner ie one after another Timing diagrams will be needed to analyze the operation of many sequential systems K RM Dansereau V10 KINTRO TO COMP ENG oSli gggECl gSNTEMS CHAPTER VII3 SEQUENTIAL SYSTEMS MEALY amp MOORE MACHINES lt Mealy machine Sequential system where lr au e ti aI S y Sfer n 1 InpUt I I Output output depends on current I Combmatlonal I input and state Logic Memory state Moore machine L J Sequential system where Ir S eaue tiaT ysfe r 1 OUtpUt depends only on M Combinational current state Logic 1 Memory 39 Output I gt state K RM Dansereau V10 KINTRO TO COMP ENG SEQUENTIAL SYSTEMS CHAPTER VII4 NTRODUCTON MEALY 8 MOORE SEQUENTIAL SYSTEMS STORING A BIT Since there are propagation delays in real components this time delay can be used to store information For instance the following buffer has a propagation delay of tpd A gt F tpd Timing Diagram A i F m l L K RM Dansereau V10 KINTRO TO COMP ENG SEQUENTIAL SYSTEMS CHAPTER VII5 STORNG BITS STORNG A BIT SEQUENTIAL SYSTEMS FEEDBACK LOOPS Ifwe wish to store data for an indefinite period of time then a feedback loop can be used to maintain the bit 0 0 Can also use two inverters tpd 1 1 4 tpd How do we get the bit in there K RM Dansereau V10 KINTRO TO COMP ENG SEQUENTIAL SYSTEMS CHAPTER VII6 STORNG BITS STORNG A BIT SEQUENTIAL SYSTEMS LOADING A BIT FEEDBACK LOOPS To store a bit we need a way of loading an input bit into the structure and makingbreaking the connection in the feedback look One way of breaking connections is to use transmission gates S2 Note The latch is levelsensitive i lfA changes while S1 1 S1 then Q will change as well A Wk Q 6 A gets temporarily stored in the inverters when S1 1 and S2 0 Then setting S1 0 and S2 1 A gets held in the feedback loop x RM Dansereau V10 KINTRO TO COMP ENG STORING BITS CHAPTER VII7 STORING A BIT D FEEDBACK LOOPS SEQUENTIAL SYSTEMS LOADNG A BIT The previous example is a data latch D latch if both S1 and S2 are controlled by a single line C as follows C 0gtO Note The latch is levelsensitive Enable If D changes while C 1 TG then Q WI change as well 6 The control line C might be derived from the clock signal or a signal from the controllersequencer in the microprocessor K RM Dansereau V10 KINTRO TO COMP ENG LATCHES CHAPTER VII 8 D LATCH WITH TG SEQUENTIAL SYSTEMS s LATCH NAND GATES IE SHEFQWR ESA LATCH K NAND gates can also be used to create a latch this time an SR latch s set s R Q 6 Q 1 0 0 1 1101afterS1R0 0 1 1 0 111 0afterS0R1 R reset Q WT Notice that this latch is levelsensitive K RM Dansereau V10 KINTRO TO COMP ENG LATCHES CHAPTER Vquot9 CONSTRUCTNG A LATCH S R LATCH NAND GATES SEQUENTIAL SYSTEMS SR LATCH NOR GATES MXED LOGIC EQUIV o The SR latch also uses feedback to store a bit 3 R Q 6 1 0 1 0 0 010afterS1R0 0 1 0 1 0 0 01afterS0R1 1 1 0 0 Recall A B NOR 0 0 1 0 1 0 1 0 0 1 1 0 Notice that this latch iS levelsensitive K RM Dansereau V10 KINTRO TO COMP ENG LATCHES CHAPTER V 10 S R LATCH NAND GATES MXED LOGIC EQUIV SEQUENTIAL SYSTEMS SR LATCH WITH CONTROL SR LATCH NOR GATES K o A control line can be added to the S latch as follows forming an SR latch s s Q Enable This control line makes it possible to decide when the inputs S and R OI are allowed to change the state of the latch K RM Dansereau V10 KINTRO TO COMP ENG LATCHES CHAPTER VII11 MXED LOGIC EQUIV SR LATCH NOR GATES SEQUENTIAL SYSTEMS D LATCH WITH LATCH SR LATCH WICONTROL A D latch can be implemented using what iS effectively the SR latch with a control line as follows D S Q Enable 3L Note that aS long aS C 1 that the latch will change according to the OI value of D K RM Dansereau V10 KINTRO TO COMP ENG LATCHES CHAPTER v12 SR LATCH NOR GATES TIMING D1 AGR AMS SR LATCH WI CONTROL SEQUENTIAL SYSTEMS D LATCH Timing diagrams allow you to see how a sequential system Changes with time using different inputs For instance a timing diagram for a D latch might look like the following Enable OI V Time K RM Dansereau V10 KINTRO TO COMP ENG LATCHES CHAPTER VII13 SR LATCH W CONTROL D LATCH SEQUENTIAL SYSTEMS TRANSPARENCY 1 TMING DIAGRAMS Latches like the D latch are termed transparent or levelsensitive This is because when enabled the output follows the input Enable Transparent D lt Note LatCh OUT Transparent j w OI K RM Dansereau V10 K INTRO TO COMP ENG LATCHES CHAPTER VII 14 glglAGRAMS SEQUENTIAL SYSTEMS TRANSPARENCY 2 TRANSPARENCY o The following behaviour is observed for Enable O and Enable 1 Transparent IN Latch OUT When Enable 0 input disconnected and Enabe When Enable 1 stored bit outputed latch acts like wire i quotquotquot 39 quoti i quotquotquot 39 quoti I Stored I I I l l l l blt l l l l l I I t I OUT 2 OUT 0 1 k RM Dansereau V10 KINTRO TO COMP ENG oLATCHES CHAPTER VII 15 lglAGRAMS SEQUENTIAL SYSTEMS PROBLEMS W TRANSPARENCY TRANSPARENCY o A problem With latches IS that they are levelsensntlve A momentary change of input changes the value passed out of the latch This is a problem if the input of a latch depends on the output of the same latch Example Design a system that flips a stored bit whenever Enable goes high An inexperienced engineer might design the following How will this design behave Will the bit flip once when the Transparent Enable signal goes high Latch Answer The output will follow the input which Enable happens to keep changing K RM Dansereau v10 K INTRO TO COMP ENG LATCH EXAMPLE t g EEiAMPLE CHAPTER VII16 PROB WTRANSPARENCY SEQUENTIAL SYSTEMS PROBLEMS W TRANSPARENCY lt Let s analyze the timing behaviour of this poor design Notice that instead of the desired quotquotquot 39 39 bit flip when Enabe1 that the input oscillates This is because L T J the output depends directly on the Enabe input since A and B appear to be connected by a wire I 39 A mm B 1 W K RM Danscrcau V10 KINTRO TO COMP ENG oLATCHES CHAPTER VII17 LATCH EXAMPLE PROB WTRANSPARENCY SEQUENTIAL SYSTEMS ELIMINATING TRANSPARENCY The problem with transparent levelsensitive latches can be fixed by splitting the input and output so that they are independent New solution Consider the following improved design that flips a stored bit whenever Enable goes high This design now uses a master and a slave transparent latches to separate the input from the output Transparent Transparent Latch Latch Master Enable m Slave K RM Dansereau v10 KINTRO TO COMP ENG CHAPTER VII18 SEQUENTIAL SYSTEMS LATCH EXAMPLE TIMING DIAGRAM LATCHES LATCH EXAMPLE PROB WTRANSPARENCY ELMN TRANSPARENCY Let s analyze the timing behaviour of this improved design k RM Dansereau V10 Enable Enable A B C Transparent Transparent Latch Latch I Enable Enable gt0 KINTRO TO COMP ENG LATCH EXAMPLE PROB WTRANSPARENCY CHAPTER VII19 ELMN TRANSPARENCY SEQUENTIAL SYSTEMS LATCH BEHAVIOUR TMNG DIAGRAM The behaviour of the master and the slave transparent latches can be thought of as follows Enable 1 I I Enable 0 I I K RM Dansereau V10 K INTRO TO COMP ENG FLIPFLOPS LATCH EXAMPLE CHAPTER VII20 ELMN TRANSPARENCY TMNG DIAGRAM SEQUENTIAL SYSTEMS SINGLE BIT STORAGE LATCH BEHAVIOUR A flipflop is a single bit storage unit with two stages masterslave First stage or master to accept input flip Second stage or slave to give output as received by the first stage flop Transparent Transparent N 1bit OUT IN Latch Latch OUT fleflop l l Enable Enable Enable A number of different types of flipflops exist such as the SR SR D and JK flipflops You may wish to review Chapter 4 regarding these types K RM Dansereau v10 KINTRO TO COMP ENG CHAPTER VII21 SEQUENTIAL SYSTEMS F U PF LO PS EDGE TRIGGERED Positive edge triggered flipflops oLATCH EXAMPLE oFLlPFLOPS SNGLE BIT STORAGE A common and useful type of flipflop are edge triggered flipflops N Negative edge triggered flipflops N k RM Dansereau V10 Transparent Transparent Latch Latch OUT I Enable Enable Transparent Transparent Latch Latch OUT Enable Enable J KINTRO TO COMP ENG oLATCH EXAMPLE CHAPTER VII22 FLPFLOPS SNGLE BIT STORAGE SEQUENTIAL SYSTEMS NEGATIVE EDGE TRIGGERED EDGE TRIGGERED The output C which is also the bit stored appears to change on the negative edge of the Enable transitions Transparent Transparent IN Latch Latch OUT I I Enable Enable Enable Enable A B C x RM Dansereau V10 K INTRO TO COMP ENG FLIPFLOPS onus nouns CHAPTER VII23 SNGLE BIT STORAGE EDGE TRIGGERED SEQUENTIAL SYSTEMS POSITIVE EDGE TRIGGERED NEG EDGE TRIGGERED The output C which is also the bit stored appears to change on the positive edge of the Enable transitions Transparent Transparent IN Latch Latch OUT I I Enable Enable Enable Enable A B C x RM Dansereau V10 KINTRO TO COMP ENG CHAPTER VII24 SEQUENTIAL SYSTEMS 11 2 n l FLIPFLOPS NONIDEAL W DUALPHASE l k RM Danscrcau V10 oFLlPFLOPS EDGE TRIGGERED NEG EDGE TRIGGERED POS EDGE TRIGGERED o The previous timing diagrams are in an ideal case In reality an implementation with delays might have the following timing diagram Propagation delays shift the outputs and slew transitions Notice that EnableEnable are replaced with 1l 2 which are non overlapping phases normally generated from a dualphase clock K INTRO TO COMP ENG FLIPFLOPS onus nouns CHAPTER VII25 NEG EDGE TRIGGERED POS EDGE TRIGGERED SEQUENTIAL SYSTEMS DUAL PHASE ENABLE NONIDEAL WIDUALI Why use nonoverlapping dualphase signals for the latch enable What happens if the latch enable input flip simultaneously How about if propagation delays cause one latche to change enable state slightly before the other The goal is to ensure that the master latch has latched the input before the slave latch tries takes this bit from the master Transparent Transparent 1bit IN Latch Latch OUTEgt39N flipflop OUT I I I 11 12 4 1 4 2 If the master has not latched the slave sees the input transparently A nonoverlapping dualphase enable solves this problem X RM Dansereau v10 KINTRO TO COMP ENG oFLIPFLOPS CHAPTER V 26 POS EDGE TRIGGERED NONIDEAL WIDUAL SEQUENTIAL SYSTEMS REGISTERS FROM FLIP FLOPS DUALPHASE ENABqu f o In essence a flipflop IS a 1 1bit bit register Ao ip op D0 An nbit register can be 1452 formed by groupign n flip A 1bit 1 flipflop D1 flops together I I 4 14 2 O O O 1bit A quot1 flipflop Dn 1 I I 4 14 2 I I 4 14 2 K RM Dansereau V10 KINTRO TO COMP ENG FLPFLOPS REG39STERS regattas SEQUENTIAL SYSTEMS READWRITE CONTROL 1 J K When a clock is used such as the nonoverlapping dualphase clock 11 and 12 we want control over when a new value is written into a register instead of writing a new value every clock cycle A readwrite control is therefore required One poor design might be as follows for a 1bit register IN Transparent Transparent OUT ReadWrite Latch Latch 11 4 2 What is the problem with this design x RM Dansereau v10 KINTRO TO COMP ENG oFLIPFLOPS CHAPTER VII28 REGSTERS REGSTERS FFLlPFLOPS SEQUENTIAL SYSTEMS READWRITE CONTROL 2 READIWRITE CONTROL A better design might be as follows i Transparent Transparent Latch Latch OUT IN 11 4 2 ReadWrite When ReadWrite 0 the output is feed back into the master latch When ReadWrite 1 the input is feed into the master latch K RM Dansereau V10

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