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# Intro to Computer Engr ECE 2030

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Cmpe 2030 A Introduction to Computer Engineering Quiz 1 April 16th 1999 There are 6 questions and 10 pages including the cover sheet and two blank work sheets Please make sure that you have all of them This examination is open textbook No calcula tors class notes or other material is allowed 1 Please show all of your work 2 State any assumptions you feel you have to make or ask for clari cation 3 Keep in mind it is dif cult to give partial credit without written material Please make sure you document any partial solutions 4 Points are stated next to each problem Use them to plan your work Question Points Graded Name Student Number 1 Provide a switch level implementation of the following expression using ntype and ptype switches FAEC 2 Complete the following switch level circuit by designing the pull down network Provide the expressions that describes the operation of the pullup network and the pulldown net work 3 Implement the following expression using only NOR and NOT gates Use the mixed logic notation we have used in class Do not assume that the complements of the inputs are avail able Do not simplify the expression Provide the number of transistors in the implementa tion F 21 BCE AE Transistors 4 Consider the following schematic that is provided with no information other than the designer used a mixed logic design strategy Express the function computed by this circuit and provide the number of transistors required to implement the circuit A B C A D F B E Function Transistors 5 Consider the following truth table 5 a Express the truth table as a sum of minterms 5 b Express the truth table as a product of maxterms 5 c How many gates will the twolevel implementation of each of the above expressions require Sum of Minterms Product of Maxterms 6 This questions deals with logic minimization using KMaps 6 a Simplify the following expression to a sum ofproducts form F A BE AD Function 6 b Fill in the KMap for the preceding function CD C 00 01 Instruction Fetch and Branching Web Reading Branching Instmction Fetch with no branchng to sta address Instruction Memory data Instruction Register 32 bit register Conditional Branching Formats beq RZRX branch target bne RZRX branch target IFormat Instruction I opcode IZ I X I 16 bit quotbranch offsetquot remember an mm is a igned number axing 2 39 mmplement IF branch taken then Program CounterPC becomes PC PC 4 4offset EL SE PC PC 4 quotPCrelative addressing Conditional Branching Formats jump statement unconditional jumps to another portion 0fthe program Jformat Instruction 32 bits I opcode I 26 bit Jump Address JA Address is word address but we have a byte addressed memory Multiple JA by 4 to converllo abyle addressed memory Only have a 28 bit byte address and we need 32 Cuncztenzm the upper fuur big at the PC m AHA quotPseudodirect Addressingquot Pseudodirect addressing has a limitation Must exist Within 228 256Mbyte Address space jr RX RX is the put into the 32bit PC which can jump to any location IFTHEN STATEMENT HighLevel IFTHEN Statement Assembly IF T HEN Statement R3 32 sub 110 R0R0 R2 2 addi 16810332 11 R1 R2 addi R2R02 114 1644sz bne R1R2 ELSE ELSE add R4IBR2 114 16 3112 j ENDiELSE R4 8mm ELSE sub R4R3R2 ENDiELSE sai R4R43 WHILELOOP STATEMENT W W 112 32 sub 110 R0R0 18 0 addi R2R032 R4 0 sub R3R3R3 While R2 16 sub R4R4R4 R4 R4 m LOOP beq R2K ENDiLOOP K5 K5 1 add R4R4K R5 R4 AND R3 addi 105931 jLOOP ENDiLOOP and R5R4R3 Add beq and j instructions to our datapath Add two control lines to the datapath 0 otherw1se beq 1 if branching instruction is to be executed jmp sel 1 ifjump instruction is to be executed 0 otherwise Add one output Zero to the Arithmetic Unit AU 0 otherwise Zero 1 ifresult ofAU is zero I opcode IZ I X I 16 bit quotbranch offset I IFurmatlnxb ut nn Z Y Z X beq sI sI 5 Z X Y Mmmm rwe Adding beq and j instructions to our datapath address Instruction Memory data Instruction Register 32 bit register jumpiaddress beq Zero Native Instmctions Thexe im h uctionx can be directly implemented in our GT datapath R format 1 format J format add R1R2R3 addi R1R2 100 j JumpiTaIget sub R1R2R3 subi R1R2 100 and R1R2R3 andi R1R2 100 or R1R2R3 Ori R1R2 100 xor R1R2IB xon39 R1R2100 sa R1R2R3 saiR1R2100 SI R1R2R3 sli R1R2 100 rot R1R2R3 roti R1R2 100 1w 111 R2 SW R1 R2 beq R1R2 branchitarget Pseudoinstmctions register indirect addressing is native to our datapath index addressing 1W R10 100 R2 R10 MR2 100 sw R10 100 R2 MR2 100 R10 Index Address addi 112390100 1w 1110 100 SW 1W 1110 R2 subl R2R2gt 100 addi R2R2 100 39 SW 1110 R2 SW R10 100 R2 subi 3R2 R2 100 Other pseudoinstructions for GT Datapath 1i la KRDEST address move regs KROPI into KRDEST Microcode The datapath below incorporates an adder subtractor and a one bit shifter The arithmetic operation is speci ed by the addsub control line The subtraction is X Y The shift direction is controlled by the 39ri glzt lza f t control line The enable signals determine which functional unit drives the Z bus The datapath also contains a register le with four registers On each cycle one add sub or shift operation can occur in the datapath XYZ 222 WE X Register File 32 32 W V rightE away shifter en shift en Part A Write microcode for this datapath to compute the average of the four initial values in the register le leaving the result in register zero You may modify other any register once its value has been summedl Put your answers in decimal ie to select register two on the X bus put a 2 in the X column 4 Part 13 Write microcode for this datapath to compute the function Re R1 R12 4R2 Re You may modify any register once its initial value has been used Put your answers in decimal 4 Part C The datapath below incorporates an adder subtractor multiplydivider and a one bit shifter An arithmetic operation is speci ed by the addsub and quotmldiv control lines Subtraction is X Y division is X Y The shift direction is controlled by the right control line The enable signals determine which functional unit drives the Z bus The datapath also contains a register le with four registers X Y Z 2I 2I 2I X RWE Register A Fl 32 Y 32 1 e I W 3392 AddSub mama 1mm Shifter ghtE an en shi en Write microcode for this datapath to compute the function below The initial values of the registers should be used in the equation Any register may be modi ed once its initial value has been used for the last time Express all signals in octal notation ie to select register two on the X bus put a 2 in the X column Ho2R1Rz R0 33H0T an Part D Using tho datapath above Wi39ito microcode for this datapath to compute tho function bolowl R3331Rz RO R1R an Part E For the datapath above write rnicrocode for this datapath to compute the function below The initial values of the registers should he used in the equation Modify only R All other registers should he unchanged by this procedure Use only registers R4 R1 R2 and R34 RI 12R22 RU R3 an Part F Write rnicrocode for this datapath to compute the value 51173 leaving the result in R04 an Part G Write rnicrocode for this datapath to exchange the contents of R1 and R24 Use only registers R1 and R24 Don t worry about over ows Part E Write microcode for this datapath to compute the function below For this part use only R4R1R24 R0 3R03132R1R0 2 an Part I For the datapath above describe each microcode instruction below using register transfer notation e I lt R2 Then deduce the expression computed by the nlicrosequence X Y Z an an R0 Cmpe 2030 A Introduction to Computer Engineering Quiz 1 September 16th 1999 There are 10 questions and 13 pages including the cover sheet and two blank work sheets Please make sure that you have all of them No textbook calculators class notes or other material is allowed 1 Please show all of your work 2 State any assumptions you feel you have to make or ask for clari cation 3 Keep in mind it is dif cult to give partial credit without written material Please make sure you document any partial solutions 4 All problems carry equal weight Plan your work 5Remember the Georgia Tech Honor Code Question Points Graded 10 10 10 l 2 3 4 5 6 7 8 9 l O Name Student Number Number Systems The following problems concern binary representation 1 For the following integer value enter the binary equivalent l a For the following binary values provide the integer equivalents Binary Integer l 01 l 00 0010101 l b How many bits are required to represent the following numbers Integer N o Bits 23 129 Switch Design 2 Provide a switch level implementation of a three input NAN D gate using ntype and ptype switches 3 Provide a switch level implementation of the following expression using ntype and ptype switches Your design should contain no shorts or oats Use as few transistors as you can F ABCA 4 Complete the following switch level circuit by designing the pull down network Provide the expressions that describes the operation of the circuit Out Gate Design 5 Implement the following expression using only NAND gates and NOT gates Use the mixed logic notation we have used in class Do not assume that the complements of the inputs are available Do not simplify the expression Provide the number of transistors in the implementation F BCD 2 Transistors 6 Consider the following schematic No additional information is provided other than the designer used a mixed logic design strategy Determine the lnction computed by this cir cuit and provide the number of transistors required to implement the circuit Function Transistors 7 Now redraw the circuit in the Question 6 to use only NAN D and NOT gates Accomplish this only by adding buffers and changing bubble pairs Boolean Expressions and SOPPOS 8 Simplify the following boolean expression to a form that contains AND and OR ofthe inputs and their complements F A C 9 Consider the following truth table 9 a Express the Boolean lnction captured in this truth table as a sum of minterms 9 b Express the truth table as a product of maxterms KINTRO TO COMP ENG CHAPTER X1 MEMORY SYSTEMS K CHAPTER X CHAPTER X MEMORY SYSTEMS READ MEMORY NOTES ON COURSE WEBPAGE CONSIDER READING PAGES 285310 FROM MANO AND KIME OTHER USEFUL RAM MATERIAL AT ARS TECHNICA k RM Dansereau V10 KINTRO TO COMP ENG oMEMORY SYSTEMS XZ NTRODUCTON MEMORY SYSTEMS INTRODUCTION F o A number of different types of memories and programmable logic deVIces exist Randomaccess memory RAM Memories Readonly memory ROM Programmable logic devices PLDs Programmable logic arrays PLAs Programmable array logic PAL Programmable gate arrays PGAs Programmable sequential arrays PSAs E Fieldprogrammable gate arrays FPGAs E Due to time limitations we will only cover RAM Twolevel combinational networks and sequential networks Two Ieve combinational Multilevel K RM Dansereau V10 k KINTRO TO COMP ENG MEMORY SYSTEMS NTRODUCTON MEMORY SYSTEMS TYPES OF RAM CHAPTER X3 MEMORY SYSTEMS Two main categories of randomaccess memory RAM exist Static memory or static RAM SRAM Information bits are latched such as with a latch or a flipflop Typical SRAM implementations require 4 to 6 transistors Dynamic memory or dynamic RAM DRAM Information bits are stored in the form of electric charges on capacitors The capacitors will discharge over time Refreshing the memory cell is required before the capacitor has discharged to much of the electric charge Most DRAM implementations use 1 transistor and 1 capacitor RM Dansereau V10 J KINTRO TO COMP ENG MEMORY SYSTEMS CHAPTER X4 NTRODUCTON MEMORY SYSTEMS SRAM CELLS 1 TYPES OF RAM lt An inefficient SRAM bit cell can be formed as follows Select word line gt TG I I TG lt U D o How many transistors required for this design 24 for inverters 22 for TGs 12 transistors Very expensive in terms of silicon real estate K RM Dansereau V10 K INTRO TO COMP ENG MEMORY SYSTEMS CHAPTER x5 STATIC RAM STATIC RAM SRAM CELLS MEMORY SYSTEMS SRAM CELLS 2 The structure for a 6 transistor implementation of an SRAM 1bit cell is as follows We will refer to this as the 6T design Select word line 4 6T design UI D The select or word line chooses the bit cell when high When selected the new DH is latched into the feedback loop K RM Dansereau V10 K INTRO TO COMP ENG MEMORY SYSTEMS CHAPTER X6 STATIC RAM STATIC RAM SRAM CELLS MEMORY SYSTEMS SRAM CELLS 3 Of course the previous SRAM cell structure can be drawn as follows replacing each inverter with 2 transistors Select word line l Vi l39 6T design 39 K RM Danscrcau V10 K INTRO TO COMP ENG MEMORY SYSTEMS CHAPTER x7 STATIC RAM STATIC RAM MEMORY SYSTEMS SRAM CELLS 4 39SRA39V39 CELLS lt A 4 transistor design for an SRAM bit cell is as follows Select word line V VDD as E t Notice replacement of pMOS transistors with load resistors 4T design UI This is for your own information We won t be testing on the 4T design K RM Dansereau V10 KINTRO TO COMP ENG oMEMORY SYSTEMS CHAPTER X8 DYNAMIC RAM SRAM CELLS MEMORY SYSTEMS DRAM CELLS 1 o A dynamic RAM cell stores the bit as a charge in a capacitor This bit must be refreshed periodically gt100s of times a second Select word line 7 Transmission gate opens when selected to charge or discharge capacitor TG This charge stores the bit o How many transistors required for this design D 21 for TG and 21 for inverter 4 transistors Still expensive considering the extra refresh circuitry required X RM Dansereau V10 KINTRO TO COMP ENG CHAPTER X9 MEMORY SYSTEMS MEMORY SYSTEMS STATC RAM DYNAMC RAM DRAM CELLS DYNAMIC RAM DRAM CELLS 2 o The capacitor charging structure can be simplified as follows Select word line A Transmission gate opens when selected to charge 1T design or discharge capacitor This structure for a DRAM bit cell is what is used in practice in real implementations Very little chip real estate is used k RM Dansereau V10 This charge stores the bit KINTRO TO COMP ENG oMEMORY SYSTEMS CHAPTER X10 oSTATlC RAM DYNAMC RAM MEMORY SYSTEMS SPECIFICATION DRAM CELLS lt Having developed bit cells either SRAM or DRAM bit cells they can now be pieced together forming a memory unit What do we want to specify in the design of a memory unit The number of bits This gives the total number of bits that the memory unit can store The grouping of bits into words Accessing 1 bit at a time might be inconvenient so grouping bits into words is often done Common examples of word bit sizes are 4 8 16 32 and 64 The number of words in the memory unit addressable words This is a function of the word size and total number of bits K RM Dansereau v10 STATC RAM DYNAMC RAM MEMORY UNITS SPECFCATON KINTRO TO COMP ENG CHAPTER X11 MEMORY SYSTEMS MEMORY UNITS DESCRIPTION In describing the capacity of a memory unit the following is used addresses x word size Example 1Mx8 If a memory unit is described as 1Mx8 then it has 1M 220 1048576 addresses 8 bits per word at each address location 8 data lines for the 8 bit words 20 address lines to specify the 1M 220 1048576 addresses and 10485768 8388608 bits in the entire memory unit k RM Dansereau V10 J K39NTnglgchngzENG MEMORY UNITS mm mils MEMORY SYSTEMS DESCRIPTION EXAMPLES 23223334133 j Some further examples of memory descriptions are given below Note that the last four columns are all described with the information in the first column Try to fill in the empy cells for the last two rows Memory Total bits of addresses address lines data lines 1Mx8 8388608 1048576 20 8 1Kx4 4096 1024 10 4 2Mx4 8388608 2097152 21 4 4Mx1 4194304 4194304 22 1 2Mx32 67108864 2097152 21 32 16Kx64 8MX8 x RM Dansereau V10 KINTRO TO COMP ENG oMEMORY UNITS CHAPTER X13 SPECFCATION DESCRPTION MEMORY SYSTEMS DESCRPTION EXAMPLES Below is a general block diagram for a memory unit n data input lines k address lines J4 Memory unit Read gt R 2quot words Write gtW n bits per word n data output lines The k address lines access a word in the memory for input or output To simplify drawing we now form buses of n or k lines K RM Dansereau V10 KINTRO TO COMP ENG oMEMORY UNITS CHAPTER X14 DESCRPTION DESCRPTON EXAMPLES MEMORY SYSTEMS BLOCK DIAGRAM 2 BLOCK DIAGRAM lt To conserve pins the following layout is more common in practice k k address lines Memory unit ReadWrite gt w 2quot words Enable gt CS n bits per word n data lines input and output The data lines are both input and output lines not simultaneously This is done by using tristate buffers to form a tristate bus or sometimes referred to as a threestate bus K RM Dansereau V10 KINTRO TO COMP ENG CHAPTER X15 MEMORY SYSTEMS J MEMORY UNITS INTERNAL STRUCTURE MEMORY UNITS DESCRIPTION DESCRIPTION EXAMPLES BLOCK DIAGRAM The bit cells are arranged in matrix more efficient Row and column decoders access specific bit ces Bit Cell Matrix EEG 39 Accessed bit GED E GED U GEES EEG 3333 E E EU Guam E E 39C r 0 O a o D E 0 II E Writing a bit iii ii Input Output Reading gt a bIt Column Decoder J KINTRO TO COMP ENG oMEMORY UNITS CHAPTER X16 DESCRPTON EXAMPLES BLOCK DIAGRAM MEMORY SYSTEMS 1 NTERNAL STRUCTURE o In read mode Row decoder activates all bit cells in that row Each bit cell in the row outputs their stored bit Column decoder takes the bit from only one column of the activated row ln write mode Row decoder activates all bit cells in that row Each bit cell in the row effectively outputs their stored bit Column decoder selects the appropriate column and writes the input bit SRAM This writing is done by overpowering what is being read by the bit cell with a stronger voltagecurrent DRAM This writing is done by recharging the capacitor for writing a 1 or discharging the capacitor for writing a 0 K RM Dansereau V10 KINTRO TO COMP ENG CHAPTER X17 MEMORY SYSTEMS Address lines IO 57 Igt MEMORYUNHS CONTROLIJNESD MEMORY UNITS BLOCK DIAGRAM NTERNAL STRUCTURE READIWRTE OF BIT Now include k address lines 1bit data line Enable and ReadWrite Row Decoder Bit Cell Matrix WV EEG EDD DDD E D EDD D DDDD Vll DDDD EEG DDDD lll ll Enable Input Output Column Decoder 3 WW TG k RM Dansereau V10 kI0 Address lines J KINTRO TO COMP ENG oMEMORY UNITS ME U N NTERNAL STRUCTURE CHAPTER X48 READWRITE OF BIT MEMORY SYSTEMS CONTROL LINES 2 CONTROL LINES Things to note about the previous implementation The k address lines are split into two parts not necessarily equal parts p of the k address lines are sent to the row decoder kp of the k address lines are sent to the column decoder There is only one bit line for inputoutput D If we desire multiple bits say n bits for each address location the entire structure must be duplicated n times The enable line or often called chip select CS either allows the transmission gates to be closed or prevents them from being closed This makes it so that the D can be in one of three modes reading writing or high impedence The readlwrite line controls which transmission gate is closed K RM Danscrcau V10 KINTRO TO COMP ENG oMEMORY UNITS ME U N NTERNAL STRUCTURE CHAPTER X19 READIWRTE OF BIT MEMORY SYSTEMS BITS FOR ROWSCOLUMNS CONTROL LINES In general given a certain size memory chip such as a 1Mx1 memory chip we would not know how the internal matrix is configured For a 1Mx1 memory chip we know it has 20 address lines for our purposes in any case there are exceptions in the real world Any combination of address lines for the row and column decoder could be used to form the matrix Example 10 row address lines and 10 column address lines for a 1024x1024 matrix of bit cells Example 12 row address lines and 8 column address lines for a 4096x256 matrix of bit cells Example 5 row address lines and 15 column address lines for a 32x32768 matrix of bit cells K RM Dansereau V10 KINTRO TO COMP ENG oMEMORY UNITS CHAPTER X20 READIWRTE OF BIT CONTROL LINES MEMORY SYSTEMS BITS FOR ROWSCOLS K As noted the described internal bit cell matrix structure accesses only 1 bit at a time Multiple bits to form an n bit word could be accessed in a few different methods One method is to have the column decoder select a set of n columns simultaneously to form the word This only works if the entire word is stored in one row Hence there should be a multiple of n columns in the bit cell matrix For instance the given bit cell matrix with 8 columns could easily have words of size 1 2 4 or 8 Another method though arguably very similar is to duplicate the entire bit cell matrix n times to form the n bit word K RM Dansereau V10 KINTRO TO COMP ENG oMEMORY UNITS U CONTROL LINES CHAPTER X21 BITS FOR ROWSCOLS MEMORY SYSTEMS MULTPLE BITS WORDSj o The following illustrates these approaches for accessing a 4bit word On the left four column bits from the second row are selected to form the 4bit word On the right the first column bit from the second row for 4 duplicates of the bit cell matrix are accessed to form the 4bit word K RM Dansereau V10 KINTRO TO COMP ENG oMEMORY UNITS CHAPTER x22 CONTROL LINES BITS FOR ROWSCOLS MEMORY SYSTEMS DESIGNING MEMORY MULTPLE BITS WORDSU K o What if we don t have the right type of memory chips to build a desired computer system Must learn to use combinations of existing memory chips to form a memory system according to specifications Example We want a 1Mx8 memory system but can only cheaply buy 1Mx4 memory chips What to do Become Bill Gates so you can afford it Geta betterjob Go back to storing your valuable information on little pieces of paper in your pocket be careful of washing machines Design a memory system that uses 1Mx4 memory chips but logically forms a 1Mx8 memory system K RM Danscrcau V10 CHAPTER X23 KINTRO TO COMP ENG MEMORY SYSTEMS EXAMPLE 1 BUILDING SYSTEMS MEMORY UNITS BULDNG SYSTEMS DESGNNG MEMORY SYST Build a 1Mx8 memory system using 1Mx4 memory chips First identify the specifications for the 1Mx4 memory chips and the desired 1Mx8 memory system Memory Total bits of addresses address lines data lines 1Mx8 8388608 1048576 20 8 J 1Mx4 4194304 1048576 20 4 k RM Danscrcau V10 As the table shows the of addresses and of address lines are the same for both So we do not have to change that The number of data lines for the 1Mx8 are double that of the 1Mx4 as well as the total of bits stored in the memory Therefore we require two 1Mx4 memory chips arranged with the same address lines and concatenated data lines KINTRO TO COMP ENG oMEMORY UNITS CHAPTER x24 BULDNG SYSTEMS DESGNNG MEMORY SYST MEMORY SYSTEMS EXAMPLE 1 EXAMPLE 1 Forming the described 1Mx8 memory system with 1MX4 chips the following 1Mx8 memory system can be designed A191A0 gt 0 DO 1MX4 0 D1 gt C8 H D2 gt RW 0 D3 H D4 4 D 1MX4 H D5 Enable gt 8 6 K RM Dansereau V10 KINTRO TO COMP ENG CHAPTER X25 MEMORY SYSTEMS EXAMPLE 2 BUILDING SYSTEMS MEMORY UNITS BULDNG SYSTEMS DESGNNG MEMORY SYST EXAMPLE 1 Build a 2Mx4 memory system using 1Mx4 memory chips First identify the specifications for the 1Mx4 memory chips and the desired 2Mx4 memory system k Memory Total bits of addresses address ines data lines 2Mx4 8388608 2097152 21 4 1Mx4 4194304 1048576 20 4 As the table shows the of data lines are the same for both There is an extra address line in the 2Mx4 giving double the of addresses and double the of bits Therefore we require two 1Mx4 memory chips arranged where one address line is used to decode which 1Mx4 chip is enabled RM Danscrcau V10 J KINTRO TO COMP ENG oBUlLDlNG SYSTEMS DESGNNG MEMORY SYST CHAPTER X26 EXAMPLE 1 MEMORY SYSTEMS EXAMPLE 2 EXAMPLE 2 j The following implements the desired 2Mx4 using 1Mx4 memory A191A0 gt DO 1Mx4 D1 7 D 7 cs 2 A20203 OJ gtRW 39D3 quotT39 0 1 Enable E V 8 1Mx4 gtos RNV gtRw lt Notice that A20 is used to activate one of the 1Mx4 memory chips K RM Dansereau V10 KINTRO TO COMP ENG BULDNG SYSTEMS CHAPTER X27 DESGNNG MEMORY SYST EXAMPLE 1 MEMORY SYSTEMS PROGRAMMER S MODEL EXAMPLE 2 j Goal is to abstract the memory model so that a programmer of the system does not need to know the physical layout of the memory Below is an example 232 addressable memory map of byte This for instance could be implemented with a 4Gx8 memory system 0x00000000 0x43 0x00000001 0X78 0x00000002 0x12 0x00000003 0x04 O O O OXFFFFFFFF 0x7c K RM Dansereau V10 KINTRO TO COMP ENG BULDNG SYSTEMS CHAPTER X28 MEMORY MODEL MEMORY SYSTEMS ENDIAN BYTE ORDERING 1 39PROGRAMMER S MODEL lt How should a multiple byte word be stored The two most common orderings are Big endian The address is of the most significant byte location Sun Workstations and Macs use this ordering Little endian The address is of the least significant byte location Intel x86 architectures use this ordering Origins of the terms big and little endian Gulliver s Travels Feud between the two mythical islands Lilliput and Blefescu over the correct end big or little at which to crack an egg K RM Dansereau V10 KINTRO TO COMP ENG BULDNG SYSTEMS CHAPTER X29 MEMORY MODEL PROGRAMMER S MODEL MEMORY SYSTEMS ENDIAN BYTE ORDERING An example of a 4byte word stored in big endian order 0x12345678 would be stored as 0x10010000 0x12 0x10010001 0x34 12345678 0x10010002 0x56 0x10010003 0x78 An example of a 4byte word stored in little endian order 0x12345678 would be stored as 0X10010000 0X78 0X10010001 0X56 78563412 0x10010002 0X34 0x10010003 0X12 K RM Dansereau V10 KINTRO TO COMP ENG BULDNG SYSTEMS CHAPTER X30 MEMORY MODEL PROGRAMMER S MODEL MEMORY SYSTEMS ENDIAN BYTE ORDERING K Let s assume we have a memory system with 32 bit words using little endian byte ordering word n10 Store the value n10 in memory as a 32 bit word binary value byte n10 Store the value n10 in memory as a byte value 8 bits asciiz string Store the ASCII string in memory with a null character space n10 Skip the next n bytes align k Force loader to go to next 2quot byte boundary K RM Dansereau v10 KINTRO TO COMP ENG oMEMORY MODEL CHAPTER X31 PROGRAMMER S MODEL ENDIAN BYTE ORDERING MEMORY SYSTEMS ASSEMBLER DIRECTIVES One example assembly memory directive set could be as follows Assume loader starts 0x10010000 Ox18 at 0x10010000 0X00 0x00 data 0X00 0x10010004 0x07 word 2739 0x68 h 0X65 e byte 7 W60 I ascii help 0x10010008 0x70 l3 0x00 0 Notice null character 39 K RM Dansereau V10 KINTRO TO COMP ENG oMEMORY MODEL CHAPTER x32 ENDIAN BYTE ORDERING ASSEMBLER DIRECTIVES MEMORY SYSTEMS EXAMPLE DIRECTIVE USE EXAMPLE DIRECTIVE USE Continuing with the previous example 0x10010008 0x70 P 0x00 0 align 2 I 0x10010000 0x43 word 186548547 0X81 N 0x1E byte 52 0X08 0x10010010 0x34 K RM Dansereau V10 This section examples how to design and implement a simple state machine First a state diagram is constructed where edges represent states the machine can be in and arcs represent transitions between edges The arc labeling notation is inputOutput where inputs are the high inputs which cause the transition and outputs are the high outputs during that transitions Each state must have outgoing arcs representing each possible input combination The state diagram for the 15 cent coke described in class is show below This diagram is optimized in that the 15 cent state has been removed A coke is dispensed as soon as the last coin is inserted 0 cents 00 NC inputs 5C NC n0 coin 5 nickle 1521112 t 10 dime C coke BC bad coin 10R NC BCR The state digram is converted directly into a state table First each state is assigned a uniun binary state starting with zero Then an entry is added to the state table for each arc in the state diagram 30 and 31 represent the current state N30 and NS represent the next state If there are states in a state diagram the will be laggN state variables state bits Since the state 11 is not used and disallowed the outputs in this state are donquott cared 31 5 0 10 NS N30 Coke Reject 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 1 0 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 1 0 0 0 1 0 1 1 0 0 0 0 1 1 0 0 0 1 0 0 1 1 1 0 1 0 1 1 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0 1 0 1 0 1 0 0 1 1 0 1 1 1 0 0 1 1 1 X X X X X X From this state table simpli ed expressions can be generated for each output using a simpli cation technique like Karnaugh maps Barrel ShifterSingle Cycle Datapath ECE2030 Shifter Implementation with Multiplexers l shi er logical shi A3 A2 A1 A0 0 A2 A3 A1 I A2 A0 I A1 0 l 11100100 11100100 11100100 11100100 d d d so so 41MUX so 41MUX 41MUX s 51 s 51 s 51 S I I I I 51 133 B2 B1 B0 41MUX I 80 no shift 1 shift dl shift ght d0 shi le Shifter Implementation with Multiplexers 1 shi er arithmetic shi A3 A2 A1 A0 A3 A2 A3 A1 1 A2 A0 ri A1 0 H Ill IL 01 00 11 10 01 00 11 10 01 I 11 10 01 00 so 41 MUX 1450 41MUX d so 41MUX d so 41MUX 51 S 51 S 51 B3 B2 B1 B0 80 no shift 81 shift d1 shi light d0 shift le Shifter Implementation with Multiplexers l shi er rotational shift A3 A2 A1 A0 A0 A2 A3 A1 1 A2 A0 ri A1 A3 H i1 i0 0100 11100100 11100100 11100100 d so d so 41MUX s 51 s 51 l l l l 41 MUX 41MUX 41MUX 51 S 51 133 B2 B1 B0 1 80 no shift 81 shift dl shi Iight d0 shift le Shifter Implementation with Multiplexers 2 shi er logical shi A3 A2 A1 A0 NH 0 AH A3 0H W Fl 11 J0 0100 11100100 11100100 11100100 d4 so d4 so d so d s0 MMUX s s s1 s s1 l l l l B3 B2 B1 B0 s1 1 80 no shift 1 shift dl shift ght d0 shi le How do you build a arbitrary shi er with a collecu39on of oneshi ers Direction PROBLEM NOT VERY EFFICIENT To nd a more ef cient implementation consider 21 unsigned binary number Hk Hk1 H2 H1 H0 2k 2101 4 2 1 If H is 1 then add 2 to the total to get a decimal number Barrel Shifter Hk Hm H2 H1 HuShi Am0unt Direction 4 bit Barrel Shifter Let H 2H0 be the shift amount Let d1 mean shift right and d0 mean shift left Example H 10 andH11 Shi er Unit in our datapath Y Contains the 32 32 shi amount Ygt0 shi n39ght st Ylt05hift1eft suen stlst0 32 0 0 Logical 0 1 AIithmetic 1 0 Rotational 1 1 SINGLE CYCLE DATAPATH General Purpose Register Architecture o o 2 rotational o 1 1151 1 o 1152 1 1 1153 7 v 2 a s LU SU St 1u en 5 en rwe v39register write enablequot Immediate Register Immediate Value Ctth mine mnt come directly from inxtmction to datath Clk Immediate Value 3ZbitImmediate Register 1quot v 4 2 AU LU 1 SU an en st In an 5 en im en 10w 1m Reginer 0mqu inthe high impedance mute im en high Yout it in the high impedance xtate Sign extension of Immediate Value n Immediate Value will be only 16 bits ime 11511411311211111019181716151413121110 TITTT T T T T T T T T T T T T THT T THT TTTTTTJII I Assume negative number uses 239s complement Single Cycle Datapath with Sign Extension Immed ate Value sign extension In an Timing of Single Cycle Datapath z andDr Wm values Rea andDr Wm values mmLn register le RF mmLn register le RF amqu values Amy arSU Clock cycle time is limited by the slowest metional unit How do I control the datapath to do what I want R0 R1 R2 Ragga Transfer me RTL rwelimmenlimvzl zuenl Es linen I 10X10 0 How do I control the datapath to do what I want Y Immedme 21 R3R1 XOR R5 5 5 X YZ rwelimmen imsz zuenl Es man If Isuen 5 I 153I1 0 leo Ix I1 I01100 I XL How do I control the datapath to do what I want mm m R54R6 16 z rweimmen imsz zuenl Es linen If Isuen A lxlslll 1I39ZIOIXI0 IWI1 1 Datapath Control control word OR micrainstmctian I smp XYZ rwelimmenlimvz as hmlu suen I 5 AnLhmem Lngjc unit umt eld 1 Field Associated group of control signals Shiner unit dd K INTRO TO COMP ENG CHAPTERVI CHAPTER VIII1 FINITE STATE MACHINES f CHAPTER VIII FINITE STATE MACHINES FSM RKMDanse 10 KINTRO TO COMP ENG CHAPTER VIII2 FINITE STATE MACHINES INTRODUCTION From the previous chapter we can make simple memory elements Latches as well as latches with control signals Flipflops Registers The goal now is to use the memory elements to hold the running state of the machine The state of the machine can be used to perform sequential operations This chapter will discuss how to represent the state of the machine for design and communication purposes K RM Dansereau V10 KINTRO TO COMP ENG CHAPTER VIII3 FINITE STATE MACHINES MEALY amp MOORE MACHINES Mealy machine Sequential system where Iquot Sequential system 1 output depends on current npUt Combinational Output input and state Logic Memory state Moore machine L J Sequential system where lr S eaue tiaT ysfe r 1 OUtpUt depends only on M Combinational current state Logic 1 Memory 39 Output I gt state K RM Dansereau V10 KINTRO TO COMP ENG oSTATE MACHINES CHAPTER VIII4 NTRODUCT0N MEALY amp MOORE MACH FINITE STATE MACHINES SYNC amp ASYNC SYSTEMS Synchronous sequential system Behaviour depends on the inputs and outputs at discrete instants of time Flipflops registers and latches that are enabledcontrolled with a signal derived from clock form a synchronous sequential system Asynchronous sequential system Behaviour depends on inputs at any instant of time Latches without control signals behave in an asynchronous manner The state machines discussed in this chapter will be synchronous sequential systems ie controlled by a clock This allows us to form timed Boolean functions such as Nt DAt 1 where N is the next state ofa D flipflop DA x RM Dansereau v10 KINTRO TO COMP ENG oSTATE MACHINES CHAPTER VIII5 NTRODUCT0N MEALY amp MOORE MACH FINITE STATE MACHINES ELEMENTS OF DIAGRAMS stc s ASYNC svsmws o A state diagram represents a finite state machine FSM and contains Circles represent the machine states Labelled with a binary encoded number or 8k reflecting state Directed arcs represent the transitions between states Labelled with inputoutput for that state transition ap Input Xt e a b Output zt e p q a State st 6 80 5 State bq nitia state 50 8k InputOutput K RM Dansereau V10 KINTRO TO COMP ENG oSTATE MACHINES CHAPTER VIII6 STATE DIAGRAMS ELEMENTS OF DIAGRAMS FINITE STATE MACHINES PROPERTIES Some restrictions that are placed on the state diagrams FSM can only be in one state at a time Therefore only in one state or one circle at a time State transitions are followed only on clock cycles synchronous Mealy machines and Moore machines can be labelled differently Mealy machine Since output depends on state and inputs Label directed arcs with inputoutput for that state transition Moore machine Since output depends only on state Label directed arcs with input for that state transistion Label state circles with Skoutput K RM Danscrcau V10 KINTRO TO COMP ENG oSTATE MACHINES CHAPTER VIII7 STATE DIAGRAMS ELEMENTS OF DIAGRAMS FINITE STATE MACHINES STATE DIAGRAM EXAMPLES PROPERTES j o The following is a simple example What does this state machine do 01 00 lnput Xt 6 01 Output zt e 0 1 State st e 80 S1 lnitial state 50 80 An input of 0 or 1 causes the transition with output 1 and 0 respectively K RM Dansereau V10 KINTRO TO COMP ENG oSTATE DIAGRAMS CHAPTER VIII8 ELEMENTS OF DIAGRAMS PROPERTES FINITE STATE MACHINES BIT FLIPPER EXAMPLE STATE DIAGRAM EX Consider the simple bit flipper looked at the in previous chapter How would a state diagram be formed Below is one possible way of drawing the state diagram for the bit flipper K RM Dansereau V10 KINTRO TO COMP ENG oSTATE DIAGRAMS CHAPTER VIII9 PROPERTES STATE DIAGRAM EX FINITE STATE MACHINES PATTERN DETECT EXAMPLE BIT FLIPPER EX Suppose we want a sequential system that has the following behaviour Input Xt 6 01 Output zt e 0 1 1 ifxt 3 t 1101 Function zt 0 othenNise Effectively the system should output a 1 when the last set of four inputs have been 1101 For instance the following output zt is obtained for the input Xt t 0123456789 Xt 100100100100110101101101001101001 zt 000000000000100001001000001000 K RM Danscrcau V10 KINTRO TO COMP ENG oSTATE DIAGRAMS CHAPTER VIII10 STATE DIAGRAM EX BT FLIPPER EX FINITE STATE MACHINES PATTERN DETECT EXAMPLE PATTERN DETECT EX The following state diagram gives the behaviour of the desired 1101 pattern detector Consider SO to be the initial state 81 when first symbol detected 1 82 when subpattern 11 detected and 83 when subpattern 110 detected 00 K RM Dansereau V10 KINTRO TO COMP ENG STATE DIAGRAMS CHAPTER VIII11 STATE DIAGRAM EX BT FLIPPER EX FINITE STATE MACHINES INTRODUCTION PATTERN DETECT EX State tables also express a systems behaviour and consists of Present state The present state of the system typically given in binary encoded form or with 8k So a state of S5 in our state diagram with 10 states would be represented as 0101 since we require 4 bits lnputs Whatever external inputs used to cause the state transitions Next state The next state generally in binary encoded form Outputs Whatever outputs other then the state for the system Note that there would be no outputs in a Moore machine K RM Danscrcau v10 KINTRO TO COMP ENG STATE DIAGRAMS CHAPTER VIII12 STATE TABLES NTRODUCTON FINITE STATE MACHINES BIT FLIPPER EXAMPLE lt Consider again the bit flipper example with state diagram The state table for this state diagram would be Present State Input Next State Output SO 39 1 39 S1or1 0 K RM Dansereau V10 KINTRO TO COMP ENG CHAPTER VIII13 FINITE STATE MACHINES STATE DIAGRAMS STATE TABLES NTRODUCTON STATE TABLES TRANSLATE FROM DIAGRAM From a state diagram a state table is fairly easy to obtain Determine the number of states in the state diagram the state table have 22 4 possible inputs for a total of 3412 rows Write out for each state the 2 possible input rows determine the next state and the output k RM Dansereau V10 BT FLIPPER EX Ifthere are m states and n 1bit inputs then there will be m2quot rows in Example If there are 3 states and 2 1bit inputs each state will For each stateinput pair follow the directed arc in the state diagram to J KINTRO TO COMP ENG CHAPTER VIII14 FINITE STATE MACHINES STATE TABLES PATTERN DETECT EXAMPLE STATE TABLES NTRODUCTON BT FLIPPER EX TRANSLATE DIAGRAM following would be the state table If we consider the pattern detection example previously discussed the k RM Dansereau V10 Present State Input Next State Output P1 P0 X N1 N0 Z 80 or 0 0 0 80 or 0 0 0 80 or 0 0 1 S1 or 0 1 0 S1 or 0 1 0 80 or 0 0 0 S1 or 0 1 1 52 or 1 0 0 82 or 1 0 o 83 or 1 1 o 82 or 1 0 1 82 or 1 0 o 83 or 1 1 0 80 or 0 0 o 83 or 1 1 1 S1 or 0 1 1 KINTRO TO COMP ENG oSTS EF39IILAPBPLEERSEX CHAPTER VIII15 TRANSLATE DIAGRAM FINITE STATE MACHINES TRANSLATE TO DIAGRAM PATTERN DETECT EX o If given a state table the state diagram can be developed as follows Determine the number of states in the table and draw a state circle corresponding to each one Label the circle with the state name for a Mealy machine Label the circle with the state nameoutput for a Moore machine For each row in the table identify the present state circle and draw a directed arc to the next state circle Label the arc with the inputoutput pair for a Mealy machine Label the arc with the input for a Moore machine K RM Danscrcau V10 KINTRO TO COMP ENG oSTATE TABLES CHAPTER VIII16 TRANSLATE DIAGRAM PATTERN DETECT EX FINITE STATE MACHINES INTRODUCTION TRANSLATE TO DIAGRAM K With the descriptions of a FSM as a state diagram and a state table the next question is how to develop a sequential circuit or logic diagram from the FSM Effectively we wish to form a circuit as follows In uts 390 Combinational gt Outputs Network Mealy machine State Present State 1 2 Next State 39 gt Outputs 1 2 Moore machine K RM Dansereau V10 KINTRO TO COMP ENG oSTATE TABLES CHAPTER VIII17 SEQUENTIAL CIRCUITS NTRODUCTON FINITE STATE MACHINES FROM STATE TABLE lt K The procedure for developing a logic circuit from a state table is the same as with a regular truth table Generate Boolean functions for each external outputs using external inputs and present state bits each next state bit using external inputs and present state bits Use Boolean algebra Karnaugh maps etc as normal to simplify Draw a register for each state bit Draw logic diagram components connecting external outputs to external inputs and outputs of state bit registers which have the present state Draw logic diagram components connecting inputs of state bits for next state to the external inputs and outputs of state bit registers which have the present state K RM Dansereau V10 KINTRO TO COMP ENG oSTATE TABLES CHAPTER VIII18 SEQUENTIAL CIRCUITS NTRODUCTON FINITE STATE MACHINES PATTERN DETECT EXAMPLE DEVEL LOGIC CIRCUITS Following the procedure outlined Boolean functions for the pattern detector state table can be formed using Karnaugh maps as follows 13930 13930 13930 X 00 011110 X 00 011110 X 00 011110 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 1 0 1 0 0 1 0 N1 N0 Z N1 XP1P1P0 N0 P1P0XP1P0XP 1P o P 1P0XP1 Po z XP1P0 K RM Dansereau V10 KINTRO TO COMP ENG SEQUENTIAL CIRCUITS CHAPTER VIII19 INTRODUCTION DEVEL LOGIC CIRCUITS FINITE STATE MACHINES PATTERN DETECT EXAMPLE PATTERN DETECT EX Notice that the previous Boolean functions can also be expressed with time as follows N1t P1t1 XtP1tTtP1tPot N0t P0t1 TtP1tP0tXtP1tP0t MurrowWt WmPotXtP1tepot Zt XP1tP0t An important thing to note in these equations is the relation between the present states P and the next states N k RM Dansereau V10 KINTRO TO COMP ENG CHAPTER VIII20 FINITE STATE MACHINES SEQUENTIAL CIRCUITS NTRODUCTON PATTERN DETECT EXAMPLE 39DEVEL LOG39C C39RCU39TS PATTERN DETECT EX w o The following logic circuit implements the pattern detect example 391ltl2 if N1 P1 0 3 D1 12 X Q a K RM Dansereau V10 W U KINTRO TO COMP ENG SEQUENTIAL CIRCUITS CHAPTER quot41 39L L ESE39ENCRCUTS FINITE STATE MACHINES EXAMPLE 1 PATTEiN DETECT EX Consider the following system description A sequential system has One input a b c One output p q Output is q when input sequence has even of as and odd of Us p othenNise K RM Dansereau V10 KINTRO TO COMP ENG SEQUENTIAL CIRCUITS CHAPTER VIII22 FSIIEAXEAIEAI1IELE1 FINITE STATE MACHINES EXAMPLE 1 J We can begin forming a state machine for the system description by reviewing the possible states In addition assign each state a state name SEE even of as and even of Us output is p SE0 even of as and odd of Us output is q 800 odd of as and odd of Us output is p 80E odd of as and even of Us output is p Note that this machine can be a Moore machine So we can associate the output with each state k RM Dansereau v10 KINTRO TO COMP ENG SEQUENTIAL CIRCUITS CHAPTER VIII23 FSM EXAMPLES EXAMPLE 1 FINITE STATE MACHINES EXAMPLE 1 j Now draw a circle with each state K RM Dansereau V10 KINTRO TO COMP ENG SEQUENTIAL CIRCUITS CHAPTER VIII24 FSM EXAMPLES EXAMPLE 1 FINITE STATE MACHINES EXAMPLE 1 j Finally for each state consider the effect for each possible input For instance starting with state SEE the next state for the three input a b and c are determined as follows t 0 e K RM Dansereau V10 KINTRO TO COMP ENG SEQUENTIAL CIRCUITS CHAPTER VIII25 FSM EXAMPLES EXAMPLE 1 FINITE STATE MACHINES EXAMPLE 1 j Finishing the state diagram the following is obtained K RM Dansereau V10 KINTRO TO COMP ENG SEQUENTIAL CIRCUITS CHAPTER VIII26 FSM EXAMPLES EXAMPLE 1 FINITE STATE MACHINES EXAMPLE 1 j A state table can also be formed for this state diagram as follows First assign a binary number to each state SEE 00 SEO 01 800 10 80E 11 Assign a binary number to each input a00b01c10 Assign a binary number to each output p 0 q 1 Then for each state find the next state for each input In this case there are three possible input values so three possible state transitions from each state The state table on the following slide shows the results for this example K RM Dansereau V10 KINTRO TO COMP ENG CHAPTER VIII27 FSM EXAMPLES SEQUENTIAL CIRCUITS FSM EXAMPLES FNTE STATE MACHINES EXAMPLE 1 EXAMPLE 1 j K Present State Input Next State output P1 P0 X N1 N0 2 SEE0 0 a00 SOE1 1 po SEE0 0 b01 SEO0 1 po SEE0 0 c10 SEEzo 0 p0 SEO0 1 a00 300 o q1 SEO0 1 SEE0 0 11 SEO0 1 c10 SEO0 1 q1 8001 0 300 SEo0 1 p0 8001 0 b01 SOE1 1 po 8001 0 1 3001 0 p0 SOE1 1 300 SEE0 0 po SOE1 1 800 0 pzo SOE1 1 c10 30E 1 po K RM Dansereau V10 KINTRO TO COMP ENG SEQUENTIAL CIRCUITS CHAPTER VIII28 FSM EXAMPLES EXAMPLE 1 FINITE STATE MACHINES EXAMPLE 1 j The Boolean function for the output can be determined from a Karnaugh map as follows Note that an input of 11 is not possible since we only have three inputs that we have assigned to 00 01 and 10 We can therefore use don t cares for this possible input P1Po X1Xo 00 01 11 10 00 0 1 01 0 11 X 10 0 gtlt gtlt 1 X 1 K RM Dansereau V10 KINTRO TO COMP ENG CHAPTER VIII29 FINITE STATE MACHINES SEQUENTIAL CIRCUITS FSM EXAMPLES EXAMPLE 1 FSM EXAMPLES EXAMPLE 1 o The Boolean function for the next state bit can also be determined from Karnaugh maps as follows 13930 13930 X1X0 00 01 11 10 X1Xo 00 01 11 10 00 1 1 0 0 00 1 0 0 1 01 0 0 1 1 01 1 0 0 1 11 X X X X 11 X X X X 10 0 0 1 1 10 0 1 1 0 N1P1 X1 Xo N0P0x10T1P0eax1 k RM Dansereau V10 J KINTRO TO COMP ENG SEQUENTIAL CIRCUITS CHAPTER VIII30 FSM EXAMPLES EXAMPLE 1 FINITE STATE MACHINES EXAMPLE 1 j The following logic circuit can be made with these Boolean functions N1 P1 63 X1 63 X0 N0 POCJBX1 z P1P0 NO P X1 0 1 DIZ Xo wm P1 32 in 2 K RM Dansereau V10 KINTRO TO COMP ENG SEQUENTIAL CIRCUITS CHAPTER VIII31 FSM EXAMPLES EXAMPLE 1 FINITE STATE MACHINES EXAMPLE 2 j K o A sequential circuit is defined by the following Boolean functions with input X present states P0 P1 and P2 and next states N0 N1 and N2 N2 XP1 P0P1 P0 N123932 N023931 ZXP1P2 Derive the state table Derive the state diagram K RM Dansereau V10 KINTRO TO COMP ENG SEQUENTIAL CIRCUITS CHAPTER VIII32 FSEIIX gt MELE1 FINITE STATE MACHINES EXAMPLE 2 EXAMPLE 2 K lt o The state table is formed as follows Present State Input Next State Output P2 P1 P0 X N2 N1 N0 Z 0 o o 0 1 o o 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 o o 1 1 1 o o 0 0 1 0 0 0 0 1 0 0 1 0 1 1 0 1 0 0 1 1 0 1 0 1 0 0 1 1 1 0 0 1 0 1 0 0 0 1 1 0 0 1 0 0 1 0 1 0 0 1 o 1 0 o 1 o 0 1 0 1 1 1 1 0 0 1 1 0 0 0 1 1 0 1 1 0 1 1 1 1 1 1 1 1 0 1 1 1 0 1 1 1 1 0 1 1 1 K RM Dansereau V10

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