### Create a StudySoup account

#### Be part of our community, it's free to join!

Already have a StudySoup account? Login here

# Analog Integ Circuit Dgn ECE 6412

GPA 3.64

### View Full Document

## 10

## 0

## Popular in Course

###### Class Notes

##### ANT 204 - 09 (Anthropology, Angela L Reed, Introduction to Cultural Anthropology)

###### Brooke Yaffa

verified elite notetaker

## Popular in ELECTRICAL AND COMPUTER ENGINEERING

This 0 page Class Notes was uploaded by Cassidy Effertz on Monday November 2, 2015. The Class Notes belongs to ECE 6412 at Georgia Institute of Technology - Main Campus taught by Staff in Fall. Since its upload, it has received 10 views. For similar materials see /class/233904/ece-6412-georgia-institute-of-technology-main-campus in ELECTRICAL AND COMPUTER ENGINEERING at Georgia Institute of Technology - Main Campus.

## Reviews for Analog Integ Circuit Dgn

### What is Karma?

#### Karma is the currency of StudySoup.

#### You can buy or earn more Karma at anytime and redeem it for class notes, study guides, flashcards, and more!

Date Created: 11/02/15

Lecture 250 7 lntroto Feedback Concepts 22802 Page 25071 LECTURE 250 INTRODUCTION TO FEEDBACK CONCEPTS READING GHLM 553563 Objective The objective of this presentation is 1 Introduce the background and basic concepts of negative feedback Outline Influence of negative feedback Feedback configurations with ideal sourceload Examples Summary ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 250 7 lntroto Feedback Concepts 22802 Page 25072 Ideal Feedback Equation Ideal Negative Feedback Configuration 8 fb Feedback Network SeSi S Si f50 SgaSgaSi afSo So a A W gt Closed Loop Gain T afgt Loop GainT So a 1 AS im forTgtgt1 A7 Sfb T Feedback signalInput signal m 56 1 Error signalInput signal 1 T Some authors Allen and Holberg de ne the loop gain as agf ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 250 7 lntroto Feedback Concepts 22802 Page 25073 Gain Sensitivity Sensitivity of the closed loop gain with respect to the open loop gain 1 af af 1 1 a A L dd 1af2 1T2 a1T2 a1T e 1 da A 1 T a Example An amplifier with a gain of 10 has a gain variation of 33 Use these amplifiers to design an amplifier with a gain of 10 and a gain variation 3 01 Solution We must cascade several amplifiers together and feedback around the cascade With feedback dAA 0001 For three cascaded stages da 10100333 1000 a1000 and 7T dA 1 da 01023 7m7 1T 0001gtT101 1000 101 A 1101 980 a 1000 f 1000 0101 Gain is close to 10 but not exactly However the tolerance will be 01 01023 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 250 7 lntroto Feedback Concepts 22802 Page 25074 Effect of Negative Feedback on Nonlinear Distortion The major cause of nonlinear distortion in amplifiers is due to changes of gain with signal level 80 Basic Ampli er So It Feedback Amplifier a 0 A 0 502 3 802 3 A 801 a 2 801 2 Slope 31 801 Se slope A1 501 1 a 0 Si 31 a1 1 a2 801 A2 7 801 330 39502 A30 802 Key points 1 Three gain regions exist for each case 2 Horizontal scale compression for feedback ampli er 3 No distortion improvement for hard saturation cases 4 Distortion improvement with feedback z 1 T ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 250 7 lntroto Feedback Concepts 22802 Page 25075 I atiun 1 Redlwtinn 0f l T quot itv bv Negative F 3L 39 Consider the following circuit for this demonstration Fig240Ol Assume that the ampli ers have the following voltage transfer functions V3 VIIax quotquotquot 39 Vmax 5 l 10 l X r 1 v1 10 l 5 i 7r H i 7 39mec Fig 250702 quot7 39mec Fig 250703 Fig 250704 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 250 7 lntroto Feedback Concepts 22802 Page 25076 Demonstration 1 Continued Now let us apply feedback around the second stage resulting in a gain of x2 and increase the gain of the first stage from x10 to x50 To find the value of f we can solve the following X2 V3 A2 FigZ4005 a m 2 gt f 04 The resulting transfer function is 83 I r r Vmax Fig 25006 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 250 7 Introto Feedback Concepts 22802 Page 25077 Demonstration 1 Continued The demo circuit 715V VVV 10R R f Fig 250 07 ECE 6412 7 Analog Integrated Circuit Design 7 II PE Allen 7 2002 Lecture 250 7 Introto Feedback Concepts 22802 Page 25078 Effects of Ne ative Feedback on Si nal Distortion Consider the output stage of an amplifier where distortion occurs because this stage is being driven very hard and a distortion signal Sd is introduced Examine the two cases of with and without feedback 5 d S S o 39 gt Open oop Amplifier Feedback Network azSi Sd SO SO 1 a2f1 azf a l 561 Now choosefa 2 SodSi7 Key points 1 Desired output signal is the same in both cases 2 With feedback distortion is reduced by gain a 3 T azf a l 4 Improved performance with inferior amplifier if used in large quantities sometimes more can be better ECE 6412 7 Analog Integrated Circuit Design 7 II PE Allen 7 2002 Lecture 250 7 Introto Feedback Concepts 22802 Page 25079 In uence of Negative F AL I on Freauencv When negative feedback is used with an ampli er having a single dominant low and a single dominant high frequency pole gain and bandwidth can be traded evenly as shown Gain a 1 T flow1T flow thigh fhigh1TFreq ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 250 7 Introto Feedback Concepts 22802 Page 250710 Four Basic Amplifiers Parameter Amt Type Voltage Transconductance Transresistance Current 7 lgt Small Signal Model R R0 R1 7 i l R R0 1 4 R 7 Ve vg Ve e vg 7 Avvg 7 7 va8 R17 Rng 7 A115 RA7 Ideal Forward Gain v0 Avve i0 vae v0 Rmie i0 Aiie IdealRi gt0 2 9009 gt09 gt09 IdealRU gt0 2 gt0 2 gt0 2 gt0 S2 Si Sfb and Se Voltage Voltage Current Current S0 Variable Voltage Current Voltage Current SS Model with Source and Load R v t V R 0 I Vquot I l i ii 3 Ideal source RS RSO or RSltltRi RSO or RSltltRi R5oo or RSgtgtRi R5oo or RSgtgtR Ideal load RL RL00 or RpgtR0 R LO 01 R LltltR0 RL00 or RpgtR0 R LO 01 R LltltRl Overall Forward ain RiRlAv R iRa Gm RSRiRLRo RSRiRLRo RSRLRm RstAi RSRiRLRo RSRiRLRo ECE 6412 7 Analog Integrated Circuit Design 7 II FEEDBACK WITH IDEAL SOURCE AND LOAD PE Allen 7 2002 Lecture 250 7 Introto Feedback Concepts 22802 Page 250711 Four Basic F quot 39 T 39 series series shunt shunt 39 mIXIng sampiing mixing 398amplmg Fls le l ogt Voltage gt V R L Current lt1gtR o gt i V gt L Amplifier l lt gt lt Amplifier 3 ltlgt Vi l Feedback Feedback Network Network series series 39 mixing lsampling Shunt I shunt R o mixing le sampling s gt Trans l conductance V ltgtR 39 gtR o lt I resistance V ltgt L Amplifier I Amplifier 0 i Feedback Network ECE 6412 7 Analog Integrated Circuit Design 7 11 J Feedback Network PE Allen 7 2002 Lecture 250 7 Introto Feedback Concepts 22802 Page 250712 SeriesShunt Feedback Am lifier Series shunt configuration ii i lt o Ri R0 Vi ave v0 Basic Amplj er o V0 Feedback Fig 25008 Network 0 Find the equivalent voltage gain input resistance Rif and output resistance Raf V a 0 v0 ave dog71 avi avfb avi aftU v01af avi W ECE 6412 7 Analog Integrated Circuit Design 7 11 vevamp vefva veafve i Ri ye Ri ye Ri ye Ri1df R10 vU ave VUaVfb v0afv0 R0 R0 RT T R U Rafm FT PE Allen 7 2002 Lecture 250 7 Introto Feedback Concepts 22802 Page 250713 ShuntShunt Feedback Am lifier Shunt shunt feedback configuration z A egt 4 a gtRi R0 1139 Vi gt We V0 Basic ifb Amplifier gt o fvo V0 Feedback Network 0 Fig 250 09 a v0 me Mil7 ml mfg avi aftU v0laf ml 9 Ti 1af Vi ieRi ieRi ieRi Ri Ri Rif zi iei iefi0 m W FT v I Raf Taiizo v0 R0iaie Rana w RUi afva a valaf Rai V0 amp Ra Rafi 1af1T ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 250 7 Introto Feedback Concepts 22802 Page 250714 ShuntSeries Feedback Am lifier Shunt series feedback con guration A Ri 1 vi 39 me Raf Basic V Ampli er fig Feedback Fig 25010 Network a 10 me dot7 ml asz ml a a 10laf ml 9 Ti 1af ieRi ieRi ieRi Ri Ri Rif zi iei iefv0 ieafie 1af 1T l I 1 Racy die R0i0a a Raf jail0 Raf i0 i0 i0 Ra1df PE Allen 7 2002 ECE 6412 7 Analog Integrated Circuit Design 7 II Lecture 140 7 Simple Op Amps 21102 Page 14071 LECTURE 140 SINIPLE 0P AMPS READING TextGHLM 425434 453454 AH 249253 INTRODUCTION The objective of this presentation is l Illustrate the analysis of BJT and CMOS op amps 2 Prepare for the design of BJT and CMOS op amps Outline Simple CMOS Op Amps Two stage Folded cascode Simple BJT Op Amps Two stage Folded cascode Summary ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 140 7 Simple Op Amps 21102 Page 14072 SIMPLE TWOSTAGE CMOS OP AMPS TwoStage CMOS Op Amp Circuit DC Conditions 15 117m 11 12 0515 0511mm I7 16 quotIBias Vicmmax VDD V303 V71 Vicmmin Vss VDSSSat VGSl Vom nax VDD VSD Sat Mg Vom nin Vss VDs7sat Notice that the output stage is class A Fig 14001 KN W6 sink17 and Isome 2L6 VDDVssVT217 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 140 7 Simple Op Amps 21102 Page 14073 DC Balance Conditions for the TwoStage OD AmD For best performance keep all transistors in VDD saturation M4 is the only transistor that cannot be forced into saturation by internal connections or external voltages Therefore we develop conditions to force M4 to be 39 in saturation V 1 First assume that V564 VSG6 This will cause proper mirroring in the M3 M4 mirror Also the gate and drain of M4 are at the same V55 F 140 02 potential so that M4 is guaranteed to be in 1g39 saturation W1quot S6 2 Let Si 2 zfvsg4 V506 then 16 E 4 S7 S7 3 However 17 214 S6 257 4 For balance 16 must equal 17 gt which is called the balance conditions 5 So if the balance conditions are satisfied then Vpg4 O and M4 is saturated ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 140 7 Simple Op Amps 21102 Page 14074 SmallSi nal Performance of the TwoSta e CMOS 0 Am VSS Cc V1 v2 I II 1 1 L0 T C gm1vm C g 6 12 rdslllrd M gm3 2 gm4V1 1 myzllrd m rdsGllrds CL T T g 3 8 gt gds2gds4 3 Cc amp gt GB I II 0 V2 J J3 V C Vout in gmlvl I TdlelrdM gm6vz rds6llrds7 II T I Fig 140703 ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 140 7 Simple Op Amps 21102 Page 14075 SmallSignal Performance of the TwoStage CMOS Op Amp Summary of the small signal performance Midband performance A0 gmigmiiRiRii z gmigm6rds2rds4rds6rds7 Rout rds llrdsm Rin w Roots Z gmll gm6 610 CC CC 1 gds2gds4gds6gds7 ng1 gm6 P0165 P1 ngIRIRIICc gm6Cc and P2 C11 CL Assume that gml lOOpS gm6 lmS rdsz rds4 2M9 rds6 rds7 05MQ CC SpF and CL lOpF A0 lOOpSXlMQXlOOOHSO25MQ 25000wv Rm e Rom 250m Zero lOOOpSSpF 2x108 radssec or 3183MHZ l p1 lmS1MQO25MQ5pF gxlogif 800 radssec or 1273Hz 338 quotI 23108 6 GB 3178MHZ Fig 14004 and p2 71000uSlOpF 108 radssec or 15915MHZ ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 140 7 Simple Op Amps 21102 Page 14076 Slew Rate of a TwoStage CMOS OD AmD Remember that slew rate occurs when currents owing in a capacitor become limited and is given as de Ilim C 7 where vC is the voltage across the capacitor C 393 v 3939539 7 Assume a Assume a V viItural V irtural XMgtgt0 ground vlltlt0 ground lb 1 M7 M7 V55 1 Vss Positive Slew Rate Negative Slew Rate Fig 14005 15 161517 15 15 1715 15 SR mi C d CL C C because I6gtgtI5 SR39 min C d C L C C if I7gtgtI5 Therefore if C L is not too large and if 17 is significantly greater than 15 then the slew rate of the two stage op amp should be 15 SR C C ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 140 7 Simple Op Amps 21102 Page 14077 Folded Cascode CMOS Op Amp Circuit VDD 114 M5115 A B Comments The bias currents I4 and 5 should be designed so that 16 and 17 never become zero ie I5I61513 This amplifier is nearly balanced would be exactly if RA was equal to R B Self compensating Poor noise performance the gain occurs at the output so all intermediate transistors contribute to the noise along with the input transistors Some first stage gain can be achieved if RA and R3 are greater than gml or gmz Fig 14006 ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 140 7 Simple Op Amps 21102 Page 14078 WW1 Model Recalling what we learned about the resistance looking into My the source of the 2 cascode transistor Fig 14007 rds6R21gm10 l d R rds7 R11 R11 h R z an z were z r r A 1 gm rgs gm 3 1 gm7rds7 gm7rds7 H 8 d d The small signal voltage transfer function can be found as follows The current 13910 is written as gm1rds1 rds4vm gm1Vm 10 2RA rdsillrds4 2 and the current i7 can be expressed as gm2rds2rds5vm gmzvm gmzvm RIIgds2gds4 l7 R11 RIIgds2gds5 21k Where k gm7rds7 2i8m7rds7 rdszllrds5i 2 gm7rds7 i The output voltage vow is equal to the sum of i7 and 13910 owing through Rom Thus M gm gm2 2k Vin 2 2lk out 22k ngRom ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 140 7 Simple Op Amps 21102 Page 14079 Frequency Response of the Folded Cascode Op Amp The frequency response of the folded cascode op amp is determined primarily by the output pole which is given as 1 pm Rautcaut where Com is all the capacitance connected from the output of the op amp to ground All other poles must be greater than GB gmllCout The approximate expressions for each pole is 1 Pole at node A pA z lRACA 2 Pole at node B pB z lRBCB 3 Pole at drain of M6 p6 z W 4 Pole at source of M8 p8 z gm8C8 5 Pole at source of M9 p9 z gm9C9 6 Pole at gate ofMlO p10 z gm10C10 where the approximate expressions are found by the reciprocal product of the resistance and parasitic capacitance seen to ground from a given node One might feel that because RE is approximately rds that this pole might be too small However at frequencies where this pole has in uence Com causes Row to be much smaller making p3 also non dominant ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 140 7 Simple Op Amps 21102 Page 140710 Example 1 Folded Cascode CMOS Op Amp Assume that all gmN gmp lOOpS rdsN 2M9 rdsp 1M9 and CL lOpF Find all of the small signal performance values for the folded cascode op amp 04x10903xlO6 RH 04GQ RA lOkQ and R3 4M9 k T M 212 Vin 292 10057143 4354Vv Rom R11gm7rds7rds5llrdsz 4OOMQII100O667MQ 57143MQ 12 Ipml m m 1750 radssec gt 278Hz gt GB 121MHz Comments on the Folded Cascode CMOS Op Amp Good PSRR Good ICMR Self compensated Can cascade an output stage to get extremely high gain with lower output resistance use Miller compensation in this case Need rst stage gain for good noise performance Widely used in telecommunication circuits where large dynamic range is required ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 140 7 Simple Op Amps 21102 Page 140711 SIMPLE TWOSTAGE BJ T OP AMPS B IT TwoStage Op Amp Circuit VEE Fig 140708 DC Conditions 15 117m 11 12 0515 0511mm 17 16 quotIBias Vicm nax VCC VEB3 VCE1Sat VBEi Vicmmin VEE VCE5sat VBEi Vom nax VCC VEC6Sat Vom nin VEE VCE7Sat Notice that the output stage is class A gt sink 17 and source 3115 I7 ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 140 7 Simple Op Amps 21102 Page 140712 TwoSta e B T 0 Am Continued Small Signal Performance Assuming differential mode operation we can write the small signal model as C I I I V lt lt quot lt gt V39 gt gt glein R1gt C1Lv1 gm m R jgtC va R3gtC3L Vom 2 gt gm4V1 2 gt 2 gm6V2 gt Fig 14009 where 1 1 R1 Ilr gllr 4llr03 z R2 r736 r02 r04 z r736 and R3 r06 r07 C1 Cn3C7r4Ccs1Ccs3 C2 Cn6Ccs2Ccs4 and C3 CL Ccs6Ccs7 Note that we have ignored the base collector capacitors C39u except for M6 which is called Cc Assuming the pole due to C1 is much greater than the poles due to C2 and C3 gives I I 0 ltgt ltgt glein gt 2132 R3ltgtC3 Vow Rf C2 gm6V2 I Fig 140 10 ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 140 7 Simple Op Amps 21102 Page 140713 TwoSta e B T 0 Am Continued Summary of the small signal performance Midband performance A0 gmigmHRIRH z gmlgm6r7z6ro6 ro7 gml F6ro6 ro77 Rout r06r077 Rm 2 Roots Z ngI gm6 CI O CC CC 8 m1 ngI 8 m6 1 1 gmHRIRHCc gm6r7r6r06 r07Cc AoCc and p2 C11 CL Assume that m 100 gm1lmS gm6 10mS r06r0705MQ CC5pF and CL10sz A0lmS100 250kQ25000VV Rm 2 Fgm12100k 2200k 2 Rom250k 2 Poles at p1 z lOmS 9 Zero 5pF 2x10 radssec jm or 3183MHz 8X103 J X 0 6 41115 2X108 109 quoti 2X109 Fig 140 11 P1 250005pF 25000 8000 radssec or 1273Hz and p2 10mS10pF 109 radssec or 15915MHZ ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 140 7 Simple Op Amps 21102 Page 140714 Slew Rate of the TwoStage BJT OD Amn Remember that slew rate occurs when currents owing in a capacitor become limited and is given as de Ilim C 7 where vC is the voltage across the capacitor C v Assume a virtural gro und V V VEE V VEE Posmve Slew Rate Negative Slew Rate Fig 140712 15 161517 15 15 1715 15 SR miriC C CL C cbecause I6gtgtI5 SR mi LC C C L C C if I7gtgtI5 Therefore if C L is not too large and if 17 is significantly greater than 15 then the slew rate of the two stage op amp should be 5 SR CC ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 140 7 Simple Op Amps 21102 Page 140715 FoldedCascode B T 0 Am Circuit VCC VCC 11 VBE 1 Q1 licu Vc sat E Vin 10m Vout 10m Vow lIC4 lICS V3131 VBia chsao 3 Q4 I VEE VEE Flg 14043 Simpli ed circuit Biasing details of the output DC Conditions 13 117m 11 12 0515 051bias I4 15 kIBias 110 111 kIBiaS39O51bias kgt1 Vicmmax VccVCE3SatVEBi Vicmmin VEEVCE4SatVEC1530VBE1 Vom nax VccVEC9SatVEC11sat Vom nin VEEVCE5SatVCE7Sat Notice that the output stage is push pull gt I sink and I source are limited by the base current ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 140 7 Simple Op Amps 21102 Page 140716 FoldedCascode B T 0 Am Continued Small Signal Analysis gmGVbEG gm7Vbe7 R B I ll I 7gt 10 h A A A I ngZVm Vb r07 ilo Vow r02 r05 rn7 r01 gmlvin 2 Fig 140 14 ro7 Pr0112 where RA z lgm6 and RB z 1gm7r07 z 2 1f r07 z r011 gmlrn6Vin glein gm2r7r7Vin gm2r7r7Vin ngVin l10 2r7r6RA z 2 17 z 2r7r739l39RB z 2r7r7O5r7r7 3 5 Vout 5 Voul W HOWPRomlin 8 gml PRoulVin 1fgm1 gm2 2 8 gml PRoul Rout Prollll N r05r02 and Rin 2amp1 Assume that FNlOO Fp 50 gml gmz lmS roN 1M9 and rap O 5M9 V l 14285VV R0 l 14285 M9 and Rm 100m ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 060 7 Push7Pull Output Stages 11104 Page 06071 LECTURE 060 PUSHPULL OUTPUT STAGES READING GHLM 362384 AH 226229 Objective The objective of this presentation is Show how to design stages that 1 Provide sufficient output power in the form of voltage or current 2 Avoid signal distortion 3 Be efficient 4 Provide protection from abnormal conditions short circuit over temperature etc Outline Push Pull MOS Class B Push Pull BJT Class B Summary ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 060 7 Push7Pull Output Stages 11104 Page 06072 PUSHPULL MOS OUTPUT STAGES Class AB and B PushPull Source Follower Can both sink and source current and provide a slightly lower output resistance VDD RL Efficiency Depends on how the T transistors are biased V55 F g39 060701 Class B one transistor has current ow for only 1800 of the sinusoid half period V0U7P ak2 PRL ZRL 7r VOU Peak Ef cwncy P VDD 1 2V0U7P ak 2 VDD VSS VDD VSS T Maximum efficiency occurs when v0U7peak VDD and is 785 Class AB each transistor has current ow for more than 1800 of the sinusoid Maximum efficiency is between 25 and 785 ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 060 7 PushePull Output Stages 11104 Page 06073 Illustration of Class B and Class AB PushPull Source Follower Output current and voltage characteristics of the push pull source follower RL 119 OmA 1mA 2 1 0 l 2 2 1 0 l 2 VmV Class B push pull source follower Class AB pushpull source follower Fig 06002 Comments Note that VOUT cannot reach the extreme values of VDD and VSS 10U7max and IOUT IIIaX is always less than VDDRL or VSSRL For VOUT 0V there is quiescent current flowin g in M1 and M2 for Class AB Note that there is significant distortion at VIN OV for the Class B push pull follower ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 060 7 PushePull Output Stages 11104 Page 06074 SmallSi nal Performance of the PushPull Follower Model Vii1 C1 E vm rdsl 7112 RL C23 Vout gmlvgsl gmbslvbsl ngVgSZ gmszVbs E V531 U C1 5 vm RL C2vom gmlv39m m1Vout gmbslvout rdsl ngVm m2V0ut gmbs2V0ut 70152 E Fig 060703 Vaut gml ng Vin gdslgds2gmlgmbslgm2gmbs2GL 1 Ram does not include RL gdslgds2gmlgmbslgm2gmbs2 If VDD VSS 25V Vow 0V ID1 DZ SOOHA and WL 20um2um AV 0787 RLoo and Ram 44852 A zero and pole are located at gmlgm2 gdslgds2gmlgmbslgm2gmbs2GL Z C1 p C1C2 These roots will be high frequency because the associated resistances are small ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 060 7 PushePull Output Stages 11104 Page 06075 PushPull Common Source Am lifiers Similar to the class A but can operate as class B providing higher efficiency Fig 06004 Comments The batteries VTR1 and VTR2 are necessary to control the bias current in M1 and M2 The efficiency is the same as the push pull source follower ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 060 7 PushePull Output Stages 11104 Page 0606 Practical Im lementation of the PushPull Common Source Am lifier Method 1 V55 Fig 06005 Vggg and Vgg4 can be used to bias this amplifier in class AB or class B operation Note that the bias current in M6 and M8 is not dependent upon VDD or VSS assuming V003 and Vgg4 are not dependent on VDD and V55 ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 060 7 PushePull Output Stages 11104 Page 06077 P ractical Im lementation of the PushPull Common Source Am lifier Method 2 Vss Fig 060055 In steady state the current through M5 and M6 is 21b If W4L4 W9L9 and W3L3 ngLg then the currents in M1 and M2 can be determined by the following relationship W1L1 W2L2 Wm 0W i If vin goes low M5 pulls the gates of M1 and M2 high M4 shuts off causing all of the current owing through M5 21b to ow through M3 shutting off M1 The gate of M2 is high allowing the buffer to strongly sink current If V goes high M6 pulls the gates of M1 and M2 low As before this shuts off M2 and turns on Ml allowing strong sourcing ECE 6412 7 Analog Integrated Circuits and Systems 11 hhn PE Allen 7 2002 Lecture 060 7 PushePull Output Stages 11104 Page 06078 Illustration of Class B and Class AB PushPull Inverting Ampli er Output current and voltage characteristics of the push pull inverting amplifier RL 119 2V 1V 0V 2V lV 0V lV 2V 2V lV 0V 1V 2V VIN Class B pushpull inverting amplifier Comments VIN Class AB pushpull inverting amplifier Fig060706 Note that there is significant distortion at VIN OV for the Class B inverter Note that VOUT cannot reach the extreme values of VDD and VSS 10U7max and IOUT IIIaX is always less than VDDRL or VSSRL For VOUT 0V there is quiescent current owing in M1 and M2 for Class AB ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 060 7 PushePull Output Stages 11104 Page 06079 Use 0139 Ne ative Shunt Feedback to Reduce the Out ut Resistance Concept rdsrllrdsz Rout 1Loop Gain Comments Can achieve output resistances as low as 1052 If the error ampli ers are not balanced it is difficult to control the quiescent current in M1 and M2 Great linearity because of the strong feedback Can be efficient if operated in class B or class AB ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 060 7 PushePull Output Stages 11104 Page 060710 Simnle 39 inn 0139 Ne2 Shunt Feedback to Reduce the Output Resistance VIN R1 gm1gm2 LOOP gal R1R2 gds1gds2GL R rdsrllrdsz 0W 1 R1 gm1gm2 R1R2 gds1gds2GL Let R1 R2 RL 00 Bias SOOHA W1L1 lOOpmlum and W2L2 200umlum Thus gml 3316mS gmz 3162mS rdsl 50kg and rm 40119 50ks2u40k9 2222119 Rout 33163162 1051439 3049 Rout 542 If RL 119 04 ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 060 7 Push7Pull Output Stages 11104 Page 060711 What about the use of BJTs in CMOS Technolo v Vom Vom Q1 1 VSS T n well CMOS PWell CMOS Fig 06009 Comments Can use either substrate or lateral BJTs Small signal output resistance is lgm which can easily be less than 10052 Unfortunately only PNP or NPN B Ts are available but not both on a standard CMOS technology In order for the BIT to sink or source large currents the base current i3 must be large Providing large currents as the voltage gets to extreme values is difficult for MOSFET circuits to accomplish If one considers the MOSFET driver the emitter can only pull to within VBEVON of the power supply rails This value can be 1V or more ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 060 7 Push7Pull Output Stages 11104 Page 060712 PUSHPULL BJT OUTPUT STAGES Class AB and B Simple Class B Output Stage V0 T Ql Saturates A A VCC39VBEI Slope s 1 Q1 on VBEWH Q2 off VBEon VEE VBE2 VCE1sat VIN e VCCVBE1VCE1Sat Slopes 1 Q1 off Q2 on Q2 Saturates VEEVMZ2 Flg 06010 Class B operation Two active devices are used to deliver the power instead of one Each device conducts for alternate half cycles Efficiency can approach 785 Can suffer from crossover distortion the transition from one device to the other ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 060 7 Push7Pull Output Stages 11104 Page 060713 Class AB Output Stage V0 T n VCCVBE1 Ql Saturates VC C VCC IQ D V IN K i VOUT VBEon VIN T VEEFVEB2 Fig 06011 IQ sets up the bias current in Q1 and Q2 when there is no input signal Each transistor is biased so that there is a region in the middle where both are on Class AB ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 060 7 Push7Pull Output Stages 11104 Page 060714 Power Considerations in the Class B Output Stage Voltage and current waveforms for a Class B ampli er Vin Vout icl 06012 ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 060 7 Push7Pull Output Stages 11104 Page 060715 Efficiency Considerations of the ClassB PushPull Output Stage Load line for one device in a class B stage Load Line Peak device dissipation Constant Power Curve 3 Point L ad Line 0 05VCC VCC ZVccVCE1Sat icgi gsorn Efficiency 1 VoulPeak2 PL 2 R L 1 T Icpeak 2 VCC and Psupply 2VCCIsupply 2VCC T CUWI 2VCC 5 RL V0ulPeak 0 PL 2 V0ulPeak 2 n Psupply 4 VCC gt max 4 WVCC VCEsat Max eff1c1ency for the above class B push pull output stage is nmax 1 VCC ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 060 7 Push7Pull Output Stages 11104 Page 060716 709 Output Stage Flg39 06039 06 061 062 063 064 065 066 067 VIN 709 Output Stage Voltage Transfer Function VIN 1 5 MODEL BITN NPN IS1E 14 BF100 VAF50 RL 2 0 1KILOHM MODEL BITP PNP Is1E14 BF50 VAF50 R1 4 3 20K1LOHM Q1 4 3 2 BITN DC VIN 060 067 0001 Q2 5 3 2 BITP PRINT DC V2 Q3 3 1 5 BITN PROBE VCC4 0DC10V END VEE 5 0 DC 710V This stage assumes that feedback will be used around the amplifier which will linearize the nonlinearity of the output stage ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 060 7 Push7Pull Output Stages 11104 Page 060717 741 Output Stage 15 10 5 t4 3 0 3 75 Fig 060715 VEE 71362 063 064 065 066 067 VN 741 Output Stage Voltage Transfer Function RL Q13C 6 6 7 BIT P lKilohm VCC 7 0 DC 15V MODEL BJTN NPNIS1E714 BF100 VAF50 VEE 8 0 DC 15V MODEL BJTP PNP IS1E 14 BF50 VAF50 IBIAS 6 0 220UA Q23 8 1 3 BJTP VIN 9 8 DC 0645 Q20 8 3 2 BJTP R10 4 3 40KlLOHM Q14 7 5 2 BJTN RL 2 01KILOHM Q17 1 9 8 BJTN DC VIN 0625 0665 00005 Q18 5 4 3 BJTN PRINT DC V 2 Q19 5 5 4 BJTN PROBE Q13A5 67BJTP END Q13B 16 7 BJTP 30 ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 060 7 Push7Pull Output Stages 11104 Page 060718 OnaciC 39 V Output Stages Quasi complementary connections are used to improve the performance of the PNP or PMOS tran51stor E s s V VEB IE SG VSG E B 39 Go I E Go39 110 Q2 110 C 11D D Composite connections Fig 060716 PNP Equivalent PMOS Equivalent E M 2 C 1f3 2 1C1 1f3 21sexp Vt ID 1f3 2 1D1 1f3 2 2L1 VGsVT The composite has the beta of an The composite has an enhanced K ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 200 7 Cascode Op Amps 7 11 21802 Page 20071 LECTURE 200 CASCODE 0P AlVlPS II READING GHLM 443453 AH 293309 Objective The objective of this presentation is 1 Develop cascode op amp architectures 2 Show how to design with the cascode op amps Outline Op amps with cascoding in the first stage Op amps with cascoding in the second stage Folded cascode op amp Summary ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 200 7 Cascode Op Amps 7 11 21802 Page 20072 In ut Common Mode Ran e for Two T es of Differential Am lifier Loads VDD VSD3 VTN VDD VDD VssVDs5VGs1 99SVDSSVGS1 I 5 im LBias VBiaS VSS T V33 7 Differentlal ampllfler Wlth Differential amplifier with a current mirror load current source loads Fig 20001 In order to improve the ICMR it is desirable to use current source sink loads without losing half the gain The resulting solution is the folded cascode op amp ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 200 7 Cascode Op Amps 7 11 21802 Page 20073 The Folded Cascode Op Amp V55 Fig 20002 We have examined the small signal performance and the frequency response in an earlier lecture ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 200 7 Cascode Op Amps 7 11 21802 Page 20074 PSRR of the Folded Cascode 0 Am Consider the following circuit used to model the PSRRz Fig 200703 This model assumes that gate source and drain of M11 and the gate and source of M9 all vary with VSS We shall examine VowV33 rather than PSRR39 Small VowV33 will lead to large PSRR39 The transfer function of VowV can be found as Vaut Sng9R0ut Vss z SCUMRUMI1 for ngg lt Com The approximate PSRR is sketched on the next page ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 200 7 Cascode Op Amps 7 11 21802 Page 20075 Frequency Response of the PSRR of the Folded Cascode Op Amp dB A IPSRRI 1V t IAvdltoogtI i 1 1 i i 3 ng9R0m Dominantl pole frequency 013 3 39 10 100 ng9 1 GB g Cont V Vout Fig 200 04 quot39 Vss Other sources of Vss injection ie r439 We see that the PSRR of the cascode op amp is much better than the two stage op amp ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 200 7 Cascode Op Amps 7 11 21802 Page 20076 Design Approach for the FoldedCascode Op Amp Step Relationship Design EquationConstraint Comments 1 Slew Rate 13 SRCL 2 Bias currents in output 14 15 1213 to 1513 Avoid zero current in scodes c sco es 81 81 Maxunum output 5 7 V 5sat VSD7sat 3 s s z LetS 5 8 amp SD Voltage Vouz ax 5 KP VSD52 7 KP VSD72 4 14 5 05VDDV0mmin S13Sc3S7 81 I Minimum output 11 V sat V sat 4 S S z LetS S amp D59 DSH Voltage VailH1111 11 KN VDSHZ 9 KN VDSQZ 10 11 05V0mmmIVSSI 8 5 Selfbias cascode R1 VSD14sat114 and R2 VDSgSat16 6 gm gmlz GBch2 GB CL Slzszz K I K I N 3 N 3 213 7 Minimum input CM 53 I 3 2 K M VinmlmVss 39VTl 8 M CM 214 S4 and S5 must meet or aximum in ut s s z p 4 5 KP VD DVmmaxVT12 exceed the value in step 3 9 Differential Voltage Vom gml ng 2k Gain vm 2 21k Rout 22kgm1R0m 10 Power dissipation Pdl39ss VDDVss13112110111 ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 200 7 Cascode Op Amps 7 11 21802 Page 20077 Example 3 Design of a FoldedCascode Op Amp Follow the procedure given to design the folded cascode op amp when the slew rate is IOVus the load capacitor is IOpF the maximum and minimum output voltages are iZV for 25V power supplies the GB is IOMHZ the minimum input common mode voltage is 715V and the maximum input common mode voltage is 25V The differential voltage gain should be greater than 5000VV and the power dissipation should be less than SmW Use channel lengths of lum Solution Following the approach outlined above we obtain the following results 13 SRCL10x1061O 11100uA Select 14 15 125uA Next we see that the value of 05VDD V0mmax is 05V2 or 025V Thus 2125uA 212516 S4 55 S14 SOuAVZO25V2 50 8 and assuming worst case currents in M6 and M7 gives 2125uA 212516 56 57 513 SOuAV2O25V2 50 80 The value of 05V0utmin IVSSI is also 025V which gives the value of S8 S9 S10 and S11 23918 2125 as Sg 59 510 SH KN VDSgZ 3636 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 200 7 Cascode Op Amps 7 11 21802 Page 20078 Example 3 Continued The value of R1 and R2 is equal to 025V125uA or 2kg In step 6 the value of GB gives S1 and S 2 as GBZCL2 2075x1062lO112 51Szwm359 The minimum input common mode voltage defines S3 as 213 200x10 6 S3 20 I3 2 6 100 2 KN Vinmmvsy m VT1 110x10 1525 110359 7075 We need to check that the values of S4 and S5 are large enough to satisfy the maximum input common mode voltage The maximum input common mode voltage of 25 requires 214 2125uA S4 55 Z Kp VDD VmmaxVT12 50X10396pAV2O7V2 10392 which is much less than 80 In fact with S4 S5 80 the maximum input common mode voltage is 3V Finally S12 is given as 125 512 W S3 25 The power dissipation is found to be Pdiss 5V125uA125uA125uA1875mW ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 200 7 Cascode Op Amps 7 11 21802 Page 20079 Example 3 Continued The small signal voltage gain requires the following values to evaluate S4 55 513 514 gm 21255080 rooops and gds 125x106O05 625uS S6 57 gm 275508O 7746uS and gds 75x106O05 375115 Sg 59 510 Sn gm 2751103636 7746uS and gds 75x106OO4 3uS 5152 gm 250110359 628uS and gds 50x10 6004 2115 Thus 1 1 RH z gmgrdsgrdsll 7746pS 8607MQ 1 1 Ram z 8607MQII7746HSWW 194OMQ k RIIgds2gds4 8607MQ2HS625uS375pS HS gm7rds7 7746 The small signal differential input voltage gain is 2k 234375 Avd ngRm 0628x103194Ox106 7464 VV The gain is larger than required by the specifications which should be okay 34375 ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 200 7 Cascode Op Amps 7 11 21802 Page 200710 Comments on Folded Cascode Op Amps Good PSRR Good ICMR Self compensated Can cascade an output stage to get extremely high gain with lower output resistance use Miller compensation in this case Need first stage gain for good noise performance Widely used in telecommunication circuits Where large dynamic range is required ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 320 7 Differential Output Op Amps 32702 Page 32071 LECTURE 320 DIFFERENTIAL OUTPUT 0P AIVIPS READING AH 384393 GHLM 808857 Objective The objective of this presentation is 1 Design and analysis of differential output op amps 2 Examine the problem of common mode stabilization Outline Advantages and disadvantages of fully differential operation Six different differential output op amps Techniques of stabilizing the common mode output voltage Summary ECE 6412 7 Analog Integrated Circuit Design 7 II PE Allen 7 2002 Lecture 320 7 Differential Output Op Amps 32702 Page 32072 Why Differential Output Op Amps Cancellation of common mode signals including clock feedthrough Increased signal swing 777777777777 H 2A 7 7 7 7 7 7 H 7 72A Fig73l Cancellation of even order harmonics Symbol o Vin Voul O O Fig 73 1A ECE 6412 7 Analog Integrated Circuit Design 7 II PE Allen 7 2002 Lecture 320 7 Differential Output Op Amps 32702 Page 32073 Common Mode Output Voltage Stabilization If the common mode gain not small it may cause the common mode output voltage to be poorly de ned Illustration VDD CM output voltage 0 VDD V CM output voltage 05VDD d VSS CM output voltage 05VSS Fig 732 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 320 7 Differential Output Op Amps 32702 Page 32074 TwoSta e Miller DifferentialIn DifferentialOnto Am VDD M6 V02 M7 VSS Fig 733 Output common mode range OCMR VDD IVSSI VSDpsat VDSMsat The maximum peak to peak output voltage 5 20CMR Conversion between differential outputs and single ended outputs Fig 73 4 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 320 7 Differential Output Op Amps 32702 Page 32075 DifferentialOut ut FoldedCascode ClassA0 Am VDD Mf ll L IIM15 M14L II IF MS II II FII II M13 M63 1 11347 R1 v2 V391 V392 v c l 141 M2 ol lt1 gt R2 HIMM M3 i l I V112 M8 39r E quot 39 M9 El C if 3MH M10 F39 F39MN 39 Vss Fig735 OCMR VDD IVSSI ZVSDPsat 2VDSNsat ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 320 7 Differential Output Op Amps 32702 Page 32076 TwoSta e Miller DifferentialIn DifferentialOnto Am with PushPull Out ut VDD lJrBP M3 M4 M114 quot 39 M6 M7 quot EMM V0 C0 Rz RzCC V02 AAA AAA vvv m Viz vvv l o I M1 M2 0 VBN M9 I l M10 o M5 MizFll l M8 VSS Fig 736 Comments Able to actively source and sink output current Output quiescent current poorly de ned ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 320 7 Differential Output Op Amps 32702 Page 32077 TwoSta e Differential Out ut FoldedCascodeO Am VDD L IIM4L II MZOL II II JM5 II JM13 I r39 M6El M7 M15 3 M11 v02 O IIIm M g2 Rz v01 M18 M16 M8 1 M3L39l l 1 M17 T Vss Fig 737A Note that the followers Ml l Ml3 and MlO M12 are necessary for level translation to the output stage Ml ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 320 7 Differential Output Op Amps 32702 Page 32078 Unfolded Cascode Op Amp with DifferentialOutputs VDD M7 M13 V55 Fig 738 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 320 7 Differential Output Op Amps 32702 Page 32079 CrossCon led Differential Am lifier Sta e One of the problems with some of the previous stages is that the quiescent output current was not well de ned The following input stage solves this problem Operation Voltage 100p Vil Viz VGS1 VGSl VSG4 VSG4 VSG3 VSG3 VGSZ VGSZ Using the notation for ac dc and total variables gives Viz Vil Vid ng1 Vgs4 ng3 Vgsz If M1 M2 M3 M4 then half of the differential input is applied across each transistor with the correct polarity gleid gm4Vid ngVid ngVid 11 2 2 and 12 2 2 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 320 7 Differential Output Op Amps 32702 Page 320710 Class AB Differential Out utO Am usin aCrossCou led Differential In ut Stage VDD Mlj L END1 L JMro M26 M25 quotII i I II J I M13ll m 341m Viz M24 M21 Fl M22 R1 M14 V01 0 E M3M4 M20 M M Mr R2 393quot 39 M16 IHMIZ Vss Fig 73 10 Quiescent output currents are defined by the current in the input cross coupled differential ampli er ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 320 7 Differential Output Op Amps 32702 Page 32071 1 CommonMode Out ut Volta e Stabilization VDD Common mode IllMl feedback circuit M2 lt lt i 0k ltR02 lt ltgt 101source V01 v I v V02 t ltgt ltgt l01Smk R03gt gtR04 i 2sink gt Vss Model of output of differential output op amp Fig 7311 Operation M1 and M2 sense the common mode output voltage If this voltage rises the currents in M1 and M2 decrease This decreased current owing through R03 and R04 cause the common mode output voltage to decrease with respect to V55 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 320 7 Differential Output Op Amps 32702 Page 320712 TwoStage Miller DifferentialIn DifferentialOut Op Amp with CommonMode Stabilization VDD EMIO 1 Vgp l Mlll VSS Fig 7342 Comments Simple Unreferenced ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 320 7 Differential Output Op Amps 32702 Page 320713 A Referenced CommonMode Out ut Volta e Stabilization Scheme VDD To correction circuitry Vss Fig 7343 Operation 1 The desired common mode output voltage Vocm creates 100m 2 The actual common mode output voltage creates current 15 which is mirrored to 16 3 If Ml through M4 are matched and the current mirror is ideal then when 100m 16 the actual common mode output voltage should be equal to the desired common mode output voltage 4 The above steps assume that a correction circuitry exists that changes the common mode output voltage in the correct manner ECE 6412 7 Analog Integrated Circuit Design 7 II PE Allen 7 2002 Lecture 320 7 Differential Output Op Amps 32702 Page 320714 Common Mode Feedback Circuits Implementation of common mode feedback circuit Common mode feed back circuit Self resistances of Ml M4 V2 VCM O MBH 1 H VSS Fig7313A This scheme can be applied to any differential output amplifier Caution Be sure to check the stability of common mode feedback loops particularly those that are connected to 0p amps that have a cascode output The gain of the common mode feedback loop can easily reach that of a two stage amplifier ECE 6412 7 Analog Integrated Circuit Design 7 II PE Allen 7 2002 Lecture 320 7 Differential Output Op Amps 32702 Page 320715 Common Mode Feedback Circuits Continued The previous circuit suffers in performance when the differential output voltage becomes too large and one of the MC2A MC2B transistors shuts off The following circuit alleviates this disadvantage VDD Common mode feed back circuit MBF4I IFW VSS Fig 7315New ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 320 7 Differential Output Op Amps 32702 Page 320716 External CommonMode Out ut Volta e Stabilization Scheme for DiscreteTime Applications Vocm Hg7344 Operation 1 During the p1 phase both Ccm are charged to the desired value of Vocm and CMbias Vocm 2 During the m phase the Ccm capacitors are connected between the differential outputs and the CMbias node The average value applied to the CMbias node will be Vocm ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 160 7 MOSFET Op Amp Design 13004 Page 16071 LECTURE 160 MOSFET OP AMP DESIGN READING GHLM 472480 AH 269286 INTRODUCTION Objective The objective of this presentation is 1 Develop the design equations for a two stage CMOS op amp 2 Illustrate the design of a two stage CMOS op amp Outline Design relationships Design of Two Stage CMOS Op Amp Summary ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 160 7 MOSFET Op Amp Design 13004 Page 16072 OP AMP DESIGN Unbuffered TwoStage CMOS Op Amp VDD VBias L1 M5 VSS Fig 16001 Notation i Si Tl WL of the ith transistor ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 160 7 MOSFET Op Amp Design 13004 Page 16073 Design Relationships for the TwoStage Op Amp 15 Slew rate SR C CAssuming I7 gtgtI5 and CL gt Cc 2gml g ml rst Stage gam A gdsz gds4 1542 M gm6 gm6 Second stage gain Avg gds6 gd 606 A7 gml Cc Gain bandwidth GB gm6 Output pole p2 C L gm6 RHP zero Z1 C C 600 phase margin requires that gm6 22gm2ClCC if all other roots are 2 10GB 15 Positive ICMR Vimmax VDD pg wiggling Vnmin 15 Negative ICMR Vimmm V55 T VT1max VDSS330 21 D5 Saturation voltageVDSsat VT all transistors are saturated ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 160 7 MOSFET Op Amp Design 13004 Page 16074 Op Amp Specifications The following design procedure assumes that specifications for the following parameters are glVCIl Gain at dc AVO M6 gm 0139 116 Proper Mirroring VSG4VSG6 Gain bandwidth GB Vout 1 2 3 Phase margin or settling time 4 Input common mode ran ge ICMR 5 Load Capacitance C L 6 Slew rate SR 7 Output voltage swing 8 Power dissipation Pdiss Vss Fig 160702 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 160 7 MOSFET Op Amp Design 13004 Page 16075 Unbuffered Op Amp Design Procedure This design procedure assumes that the gain at dc Av unity gain bandwidth GB input common mode range VMmin and Vinmax load capacitance CL slew rate SR settling time Ts output voltage swing V0mmax and V0mmin and power dissipation PmSS are given Choose the smallest device length which will keep the channel modulation parameter constant and give good matching for current mirrors 1 From the desired phase margin choose the minimum value for CC ie for a 600 phase margin we use the following relationship This assumes that z 2 10GB CC gt 022CL 2 Determine the minimum value for the tail current 15 from the largest of the two values VDD lVSSl 2 Ts 3 Design for S3 from the maximum input voltage specification I5SRCC or 15510 15 53 KatvDD vinanax lVToaKmaX Vnltmin2 4 Verify that the pole of M3 due to C W and Cgs4 067W3L3C0x will not be dominant by assuming it to be greater than 10 GB gm3 zcg gt 10GB ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 160 7 MOSFET Op Amp Design 13004 Page 16076 Unbuffered 0 Am Desi n Procedure Continued 5 Design for S1 S2 to achieve the desired GB ngZ gml GB 39 Cc 52 215 6 Design for S5 from the minimum input voltage First calculate VD55sat then find S5 15 215 VD55sat Vinmrn VSS 7T VT1max z 100 mV 9 S5 K v5VDS5sat2 7 Find S6 by letting the second pole p2 be equal to 22 times GB and assuming that VSG4 VSG6 gm6 gm6 228m2CICC gt 56 548 8 Calculate 16 from gm62 16 2K 6S6 Check to make sure that S6 satisfies the ngmax requirement and adjust as necessary 9 Design S7 to achieve the desired current ratios between 15 and 16 S7 1615S5 Check the minimum output voltage requirements ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 160 7 MOSFET Op Amp Design 13004 Page 16077 Unbuffered Op Amp Design Procedure Continued 10 Check gain and power dissipation speci cations 28m28m6 Av 150L2 91606 A7 Pdiss 15 16VDD lVSSD ll Ifthe gain specification is not met then the currents 15 and 16 can be decreased or the WL ratios of M2 andor M6 increased The previous calculations must be rechecked to insure that they are satis ed If the power dissipation is too high then one can only reduce the currents 5 and 16 Reduction of currents will probably necessitate increase of some of the WL ratios in order to satisfy input and output swings l2 Simulate the circuit to check to see that all specifications are met ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 160 7 MOSFET Op Amp Design 13004 Page 16078 Example 1 Design of a TwoStage Op Amp Using the material and device parameters given in Tables 31 1 and 31 2 design an amplifier similar to that shown in Fig 63 1 that meets the following specifications Assume the channel length is to be 1 pm AV gt 3000VV VDD 25V V55 725V 600 phase margin GB SMHZ C L lOpF SR gt lOVus V0 range iZV ICMR 71 to 2V Pdiss s 2mW Solution 1 The rst step is to calculate the minimum value of the compensation capacitor CC CC gt 221010 pF 22 pF 2 Choose CC as 3pF Using the slew rate specification and CC calculate 15 I5 3xlO1210X106 30 HA 3 Next calculate WL3 using ICMR requirements 3OxlO6 WL3 50x10 625 2 85 05512 15 WL3 WLM 15 ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 160 7 MOSFET Op Amp Design 13004 Page 16079 Example 1 Continued 4 Now we can check the value of the mirror pole p3 to make sure that it is in fact greater than 10GB Assume the CM 04fFpm2 The mirror pole can be found as gm3 2K p5313 9 p3 z 2C8S3 2O667W3L3C0x 281X10 radssec or 448 MHZ Thus p3 is not of concern in this design because p3 gtgt 10GB 5 The next step in the design is to calculate gml to get gml 5x1062rc3x1012 9425uS Therefore WL1 is gmlz 94252 WL1 WL2 m m 279 z 30 gt WL1 WL2 3 6 Next calculate VDS5 30x106 VDSS lt 1 lt 25 85 035V Using VD55 calculate WL5 from the saturation relationship 230x10 6 WL5 W 449 z 45 gt WL5 45 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 160 7 MOSFET Op Amp Design 13004 Page 160710 IExample 1 Continued 7 For 600 phase margin we know that gm6 2 10gm1 2 9425uS Assuming that gm6 9425uS and knowing that gm4 150uS we calculate WL6 as 9425x10396 150X106 9425 z 94 WL6 15 8 Calculate 16 using the small signal gm expression M 16 250x1069425 945 95 If we calculate WL6 based on Vautmax the value is approximately 15 Since 94 exceeds the speci cation and maintains better phase margin we will stay with WL6 94 and I6 95pA With 16 95 HA the power dissipation is Pdiss 5V 3OHA95HA 0625mW ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 160 7 MOSFET Op Amp Design 13004 Page 160711 Example 1 Continued 9 Finally calculate WL7 95x10quot6 1425 14 a Let us check the Vautmin speci cation although the WL of M7 is so large that this is probably not necessary The value of Vautmin is WL7 45 Vautmin VDS7sat 0351V which is less than required At this point the first cut design is complete 10 Now check to see that the gain specification has been met 9245x1069425x106 AV 15x106 04 0595x106 04 05 77697VV which exceeds the specifications by a factor of two An easy way to achieve more gain would be to increase the W and L values by a factor of two which because of the decreased value of it would multiply the above gain by a factor of 20 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 160 7 MOSFET Op Amp Design 13004 Page 160712 Incorporating the Nulling Resistor into the Miller C T quot mm On Amn Circuit M7 VSS Fig 160703 We saw earlier that the roots were ng gml p1 AVCC AVCC p2CL P4 i Z1 m Where Av gmlgm RIRII Note that p4 is the pole resulting from the nulling resistor compensation technique ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 160 7 MOSFET Op Amp Design 13004 Page 160713 Design of the Nulling Resistor M8 In order to place the zero on top of the second pole p2 the following relationship must hold 1 CL Cc CCCL 1 Zgm6 Cc Cc 12K PS6I6 The resistor RZ is realized by the transistor M8 which is operating in the active region because the dc current through it is zero Therefore RZ can be written as aVDS8 I 1 Z aiD8 VD58O K P58VSG8IVTP The bias circuit is designed so that voltage VA is equal to V3 W11 110 W6 lVGsrol lV lVGssl 1V gt VSG11 VSG6 gt E In the saturation region 2110 lVGsrol lV KPW10L10 lVGssl 1171 1 K Psro L 510 RZK P58 2110 58 ZK PIIQ W8 Cc 5105616 Equatrng the two expressrons for R2 grves T8 CL CC 110 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 160 7 MOSFET Op Amp Design 13004 Page 160714 qumnln 2 Zero 1 inn Use results of Ex 1 and design compensation circuitry so that the RHP zero is moved from the RHP to the LHP and placed on top of the output pole p2 Use device data given in Ex 1 Solution The task at hand is the design of transistors M8 M9 M10 M11 and bias current 110 The first step in this design is to establish the bias components In order to set VA equal to V3 then VSG11 must equal VSG6 Therefore 511 111I6S6 Choose 11 110 19 15pA which gives 511 15uA95pA94 148 z 15 The aspect ratio of M10 is essentially a free parameter and will be set equal to 1 There must be sufficient supply voltage to support the sum of VSGH VSGlo and VD59 The ratio of 11015 determines the WL of M9 This ratio is WL9 11015WL5 153045 225 z 2 Now WLg is determined to be 3pF 19495uA IVD8 3pF10pF 15uA 563 6 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 380 7 Two7Stage Open7Loop Comparators7ll 4502 Page 38071 LECTURE 380 TWOSTAGE OPENLOOP CONIPARATORS II READING AH 445461 Trip Point of an Inverter VDD In order to determine the propagatron delay trme 1t 1s necessary to know when the second stage of the two stage o M6 comparator begins to turn on v1 116 Second stage I VOW l7 M7 Trrp pornt VBW Assume that M6 and M7 are saturated We know that the V steepest slope occurs for this condition 55 Fig 8 Equate i6 to 1397 and solve for Vin which becomes the trip point KNW7L7 Vin VTRP VDD IVTPI KPW6L6 VBiaS VSS VTN Example If W7L7 W6L6 VDD 25V VSS 725V and VBiaS 0V the trip point for the circuit above is VTRP 25 07 11050 0 25 707 7087OV ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 380 7 Two7Stage Open7Loop Comparators7ll 4502 Page 38072 Pro a ation Dela Time of a Slewin TwoSta e O enLoo Com arator Previously we calculated the propagation delay time for a nonslewing comparator If the comparator slews then the propagation delay time is found from dvi AV ii Cid 1 Ci where Ci is the capacitance to ground at the output of the i th stage The propagation delay time of the i th stage is AVZ ti Ali CiI l The propagation delay time is found by summing the delays of each stage tpt1t2t3 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 380 7 TworStage OpeneLoop Comparatorle 4502 Page 38073 Example 25 Propagation Time Delay of a TwoStage OpenLoop Comparator For the two stage comparator shown VDD 25V assume that C1 02pF and CH 5pF Also assume that v61 0V and that v62 has the waveform shown If the input voltage is large enough to cause slew to dominate nd the propagation time delay of the rising and falling output of the comparator and give the propagation time delay of the comparator 30M VSS 25V Fig 8275A tots 25V quot Fig 825 Solution 1 Total delay sum of the first and second stage delays 1 and t2 2 First consider the change of v62 from 25V to 25V at 02us The last row of Table 82 1 gives v01 25V and v0 25V 3 t requires C AVOl and 15 C1 02pF I5 30uA and AV can be calculated by finding the trip point of the output stage ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 380 7 TworStage OpeneLoop Comparatorle 4502 Page 38074 Example 25 Continued 4 The trip point of the output stage by setting the current of M6 when saturated equal to 234uA l56 2342 7 VSG6IVTPI2 234 gt V566 07 m Therefore the trip point of the second stage is VTRPZ 25 1035 1465V Therefore AVl 25V 1465V V566 1035V Thus the falling propagation time delay of the first stage is 1035V fol 02pF 69ns 5 The rising propagation time delay of the second stage requires C AVUW and 16 C11 is given as 5pF AVUW 25V assuming the trip point of the circuit connected to the output of the comparator is 0V and 16 can be found as follows VG6guess z 05VG6I6234uA VG6min 215 V66m111 VGl VGSlUSS2 VDsz VGSIUSSZ 07 m 100V VG6guess z O51465V 100V 0232v l5 3850 Therefore V566 227v and I6 76 VSG6 IVTPI2 T 227 072 2342uA ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 380 7 Two7Stage Open7Loop Comparators7ll 4502 Page 38075 Example 25 Continued 6 The rising propagation time delay for the output can expressed as 25V trout 5PF 2342HA234HA 593ns Thus the total propagation time delay of the rising output of the comparator is approximately 128ns and most of this delay is attributable to the first stage 7 Next consider the change of v62 from 25V to 725V which occurs at 04us We shall assume that v62 has been at 25V long enough for the conditions of Table 82 1 to be valid Therefore v01 z VSS 725V and v0 z VDD The propagation time delays for the first and second stages are calculated as W 1465V 113V ml 02pF T 173ns 2V 25V 1V four SPF 234 5342113 W 8 The total propagation time delay of the falling output is 7072ns Taking the 391V average of the rising and falling propagation time delays gives a propagation time delay for this two stage open loop comparator of 3V about 76115 ZOOHS 300ns 39 400ns 600ns Time Fig 8276 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 380 7 Two7Stage Open7Loop Comparators7ll 4502 Page 38076 Design of a TwoStage OpenLoop Comparator Table 82 2 Design of the Two Stage Open Loop Comparator of Fig 82 3 for a Linear Response Specifications 1 C11Vmmin VOH VOL Vicm Vicm39 and overdrive Constraints Technology VD D and VSS Step Design Relationships Comments 1 1 IPHICH Choose m 1 391 quot W rpm and 17 16 Amp 2 W6 2 16 W7 217 VSD6Sat VDDVOH E 2 and E 2 K1 VSD6sat KN VDS7sat VDS7sat VOL VSS 3 2C A result of choosing m 1 Guess C as 01pF to 05pF I5 2 I7 C H Will Check Cllater W W I 4 L 3 L 4 4 VSG3 VDD39VicmVTN 3 4 KP VSG339VTP392 5 Av0g y2g y4g y6g y7 amp gmlz w A 0 V0HY0L m1 gm6 L1 L2 KNI5 gm6 L6 V Vin ln 6 Find C1 and Cheek assumption If C is greater than the guess in step 3 then C Cg cgd4cgs6cbd2cbd4 increase C1 and repeat steps 4 through 6 7 W 2I5 If VDS5sat is less than 100mV increase W1L1 5 VDS5Sat Vicm 39VGS139VSS L5 KNVDS5Sat 2 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 380 7 TworStage OpeneLoop Comparatorsell 4502 Page 38077 Exam le 26 TwoSta e O enLoo Com arator Desi n for a Linear Res onse Assume the speci cations of the comparator shown are given below p SOns V011 2v VOL 2v 13931 VDD VSS 25V C1 SPF Vinmin lmV Vicm 2V Vicm l25V Also assume that the overdrive will be a factor leo of 10 Use this architecture to achieve the above specifications and assume that all channel lengths are to be 1 pm Solution Following the procedure outlined in Table 82 2 we choose m l to get Fig 823 109 Ip Ipnl 5m 632x106 radssec This gives 632x1065xlO12 I6 17 W3SIHA I6 17 400uA Therefore W6 2400 64 dW7 2400 29 L6 05250 an L7 052110 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 380 7 TworStage OpeneLoop Comparatorsell 4502 Page 38078 Example 26 Continued Next we guess C1 02pF This gives 15 32uA and we will increase it to 40uA for a margin of safety Step 4 gives V563 as 12V which results in E E 40 32 E E 4 L3 L4 5012 072 39 9 L3 L4 The desired gain is found to be 4000 which gives an input transconductance of 400000920 8m 4444 1646 This gives the WL ratios of M1 and M2 as W2 E E 1622 E L1LZ1104O596 L1L26 To check the guess for C1 we need to calculate it which is done as C ng2ng4Cgs6de2de4 O9fFl3fFl 195fF204fF368fF 1789fF which is less than what was guessed so we will make no changes ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 380 7 Two7Stage Open7Loop Comparators7ll 4502 Page 38079 Example 26 Continued Finally the WL value of M5 is found by nding V651 as 0946V which gives VDS5sat 0304V This gives E 240 L5 03042110 73987 z 8 Obviously M5 and M7 cannot be connected gate gate and source source The value of 15 and 17 must be derived separately as illustrated below The W values are summarized below assuming that all channel lengths are 1pm W1 W2 6pm W3 W4 4pm W5 8m W6 64pm W7 29pm VDD l 40nA M7 1400M 21 81 31 291 Vss Fig 827 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 380 7 Two7Stage Open7Loop Comparators7ll 4502 Page 380710 Design of a TwoStage Comparator for a Slewing Response Table 82 3 Two Stage Open Loop Comparator Design for a Slewing Response Specifications 1 C11Vmmin VOH VOL Vim Vicm39 Constraints Technology VDD and VSS Step Design Relationships Comments 1 dvaut CI VOHVOL Assume the trip point of the output is VOH I7 I6 C11 d p VOL2 2 W6 216 W7 217 VSD6sat VDDVOH Q 2 and E 2 K1 VSD6sat KN VDS7sat VDS7sat VOL VSS 3 2C Typically 01pfltC1lt05pF Guess C as 01pF to 05pF I5 17C 11 4 dval C VOHVOL Assume that v01 swings between VOH and 15 CIT 1 VOL 5 W W I L 3 L 4 4 VSG3 VDD39Vz39cm VTN 3 4 KP VSG339VTP392 6 Avlt0gtltg y2g y4gtltg y6gmgt E amp gmlz w A M m1 gm6 L1 2 L2 KNIS gm L6 V Viimm 7 Find C1 and check assumption If C is greater than the guess in step 3 increase C1 Cg ng4Cgs6de2de4 the value of C1 and repeat steps 4 through 6 8 W 2I5 If VDS5sat is less than lOOmV increase W1L1 5 VDS5Sat Vicm VGs1VSS L5 KNVDS5Sat 2 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 380 7 TWOAStage OpeneLoop Comparatorsrll 4502 Page 38071 1 Example 27 TwoStage OpenLoop Comparator Design for a Slewing Response Assume the specifications of Fig 82 3 are given below p 50113 VOH 2V VOL 2V VDD 25V V55 25V CH 5pF Vinrnin lmV Vicm 2V Vicm 125V Design a two stage open loop comparator using the circuit of Fig 82 3 to the above specifications and assume all channel lengths are to be 1 pm Solution Following the procedure outlined in Table 82 3 we calculate I6 and 17 as 5xlO124 I6 17 W 400uA Therefore W6 2400 2400 W7 L6 05250 64 andL7 052110 29 Next we guess C1 02pF This gives O2pF4V 15 50ns 16uA a 1520uA Step 5 gives V563 as 12V which results in E E 20 1 6 E n 2 L3 L4 5012 072 39 9 L3 L4 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 380 7 TWOAStage OpeneLoop Comparatorsrll 4502 Page 380712 Example 27 Continued The desired gain is found to be 4000 which gives an input transconductance of 400000910 gml W 81H5 This gives the WL ratios of M1 and M2 as 2 Vii iiV 118d2to 149 iVTliV 22 2 To check the guess for C1 we need to calculate it which done as C1 ng2ng4CgS6de2de4 O9fFO4fF1 195fF204fF153fF 1565fF which is less than what was guessed Finally the WL value of M5 is found by nding V651 as 100V which gives VDS5sat 025V This gives W5 220 L 5 0232110 5398 z 6 As in the previous example M5 and M7 cannot be connected gate gate and source source and a scheme like that of Example 82 6 must be used The W values are summarized below assuming that all channel lengths are 1 pm W1 W2 W3 W4 W5 W6 W7 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 180 7 Power Supply Rejection Ratio 21602 Page 18071 LECTURE 180 POWER SUPPLY REJECTION RATIO READING GHLM 434439 AH 286293 Objective The objective of this presentation is l Illustrate the calculation of PSRR 2 Examine the PSRR of the two stage Miller compensated op amp Outline Definition of PSRR Calculation of PSRR for the two stage op amp Conceptual reason for PSRR Summary ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 180 7 Power Supply Rejection Ratio 21602 Page 18072 What is PSRR AvVdd0 PSRR m How do you calculate PSRR You could calculate AV and Add and divide however Fig 18002 Vout AddVdd AvV1V2 AddVdd Avvout gt Vout1Av AddVdd Vout Add 1 l Vdd Av z Av PSRR Good for frequenc1es up to GB ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 180 7 Power Supply Rejection Ratio 21602 Page 18073 gm6V1 Vdd lt 4 lt d56 d gt13 ICIC ltgt 5 lt V1 C CH jgtf s7 T TVUMZ Positive PSRR of the TwoSta e 0 Am U n vo Z lt m6V1 Vdd lt rdszt lt1 use d V lt gml V0 C5 lt Vdd g dd lt Z s Q lt i lt gt gt 0132 TVUM 747 1C T Fig180703 The nodal equations are gdsl gds4 Vdd gdSZ gds4 SCC SCI V1 gml SCC Vout gm6 gmde gm6 ch V1 gds6 gds7 ch SCIDVOMI Using the generic notation the nodal equations are GIVdd G1 ch SCIV1 8m chWaut ngI gdedd ngI chV1 G11 ch sCIIVaut WhereGI gdsl gds4 gdsz gds4 G11 gm gm ng gml gmz and ngI 8m ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 180 7 Power Supply Rejection Ratio 21602 Page 18074 Positive PSRR of the TwoStage Op Amp Continued Using Cramers rule to solve for the transfer functionVUmVdd and inverting the transfer function gives the following result Vdd SziccCICICII CIICc1 SiGICcCII GIICcCI Ccgm11 8mm GIGIIngngI Vaut SCcngIGIgds6 CIngI gds6 GIgds6 We may solve for the approximate roots of numerator as SCC SCCCCCHCCCH Vdd ngngI 8 ngI Cc 1 PSRR Vaut E GIgds6 ngHCC J GIgds6 where gm gt gm and that all transconductances are larger than the channel conductances SCC SC I L i Vdd ngngI ng g 1 GIIAVU GB 1 11721 1 PSRR Vaut Glgds6 ngIICC gds6 SGIIAVU GIgds6 m ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 180 7 Power Supply Rejection Ratio 21602 Page 18075 Positive PSRR of the TwoStage Op Amp Continued GIIAVO gdss 2D quotU E D U E s i t D 843603 GB P2 Fig 18004 GIIAVO At approximately the dominant pole the PSRR falls off with a 720dBdecade slope and degrades the higher frequency PSRR of the two stage op amp Using the values of Example 63 1 we get PSRRO688dB Z15MHZ z2715MHz and p1 7906Hz ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 180 7 Power Supply Rejection Ratio 21602 Page 18076 Conce tof the PSRR for the TwoSta e 0 Am Other sources of PSRR besides Cc Fig 180705 1 The M7 current sink causes V306 to act like a battery 2 Therefore Vdd couples from the source to gate of M6 3 The path to the output is through any capacitance from gate to drain of M6 Conclusion The Miller capacitor C0 couples the positive power supply ripple directly to the output Must reduce or eliminate Cc ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 180 7 Power Supply Rejection Ratio 21602 Page 18077 Ne ative PSRR of the TwoSta e 0 Am withVMS Grounded J M6 VDD M3 E C E V l I out 1 quot r C l 11 I I T 393 RI C1 C11 RH Vm M7 ngVom gmHVl I gm7Vss Vss o VSS E Fig 180706 VBl39as grounded Nodal equations for VBiaS grounded O G1 SCCSCDV1 gmchV0 gm7Vss gMIISCcV1 G11SCcSC11Vo Solving for VOWV and inverting gives amp SZCCCI CICIICIICc1SiGICcCIIGIICc CICcngI ngGIGIIngngI Vaut 5CcCIGIgm7 ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 180 7 Power Supply Rejection Ratio 21602 Page 18078 Negative PSRR of the TwoStage OD Amn withVMS Grounded Continued Again using techniques described previously we may solve for the approximate roots as SCC SCCCCCHCCCH V C 1 ss ngngI gm ngI c PSRR Vaut E GIgm7 SCCCI GI l This equation can be rewritten approximately as L L Vss ngngI gm ngI 1 GHAVO GB 1 Ipzl 1 PSRR m5 GIgm7 SCC gm7 S ng a 1 EH Comments PSRR39 zeros PSRR zeros DC gain z Second stage gain PSRR39 pole z Second stage gain X PSRR pole Assuming the values of Ex 63 1 gives a gain of 237 dB and a pole 7147 kHz The dc value of PSRR is very poor for this case however this case can be avoided by correctly implementing VBlas which we consider next ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 180 7 Power Supply Rejection Ratio 21602 Page 18079 Ne ative PSRR of the TwoSta e 0 Am withVMS Connected to Vgs VBias connected to V55 L Fig 18007 If the value of VBlas is independent of V then the model shown results The nodal equations for this model are 0 GI SCC SCIV139ng SCCVUMI and 8m Sng7Vss ngI SCch GII SCc SCH Sng7Vaut Again solving for VOWV and inverting gives amp SzCcCIC1CHCIICcC1ng7Ccng71SGICcCIrthd7GIICcCICcgrrJIgmlGIGIInggsz Vom Sng7gd 7sCfi39CcGI ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 180 7 Power Supply Rejection Ratio 21602 Page 180710 Negative PSRR of the TwoStage OD Amn withVMS Connected to Vgs Continued Assuming that gm 1 gt gm and solving for the approximate roots of both the numerator and denominator gives SCC SCCCCCCCCH ngI Cc 1 ng Vss ngngI PSRR39 V0 5 ngd scg sC1CC 1 8m G1 This equation can be rewritten as L L V GnAVo GB 1 Isz 1 PSRR Vaut z gds7 Sng7 amp gm 1 G1 1 Comments DC gain has been increased by the ratio of GH to gm Two poles instead of one however the pole at gdS7ng7 is large and can be ignored Using the values of Ex 63 1 and assume that C0137 lOfF gives PSRRO 767dB and Poles at 712kHZ and 149MHZ ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 180 7 Power Supply Rejection Ratio 21602 Page 180711 Fre uenc Res onse of the Ne ative PSRR of the TwoSta e 0 Am with VBlas Connected to V GHAVO gm CD 3 E P m m E 0 ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 180 7 Power Supply Rejection Ratio 21602 Page 180712 A roximate Model for Ne ative PSRR with VBlas Connected to Ground sz VDD VBias VBia grounded V55 T I Fig 180709 Path through the input stage is not important j l as long as the CMRR is high A Path through the output stage 20 t0 Vout isszout gm7Z0utVSS 40dB I Vout l E VSS gm7Z0ut gm7R0ut sRoutCout1 I I 0an 139 o Routcout Fig18010 ECE 6412 7 Analog Integrated Circuit Design 7 ll PE Allen 7 2002 Lecture 180 7 Power Supply Rejection Ratio 21602 Page 180713 Approximate Model for Negative PSRR with VM Connected to V Vout C11 D V out What 13 Z01 VBms Path through ng7 is negligible t VBms connected to V55 V55 Z0qu It gt Fig 180711 8 m1 Vt C C C It It ngIV1 gm GISCISCC I a 11 gm i lt H Jlds llrd Th Z GIS CI CC V C1 RI jV1 ngIVi Vout Vt gt us out nggMH gm out T T 139 Fig180712 1 rds7 Vss Z0qu SCc C1 GIngngITdS7 G1 Vow 1 sCcC1 G gt P016 at CCC1 ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 180 7 Power Supply Rejection Ratio 21602 Page 180714 The two stage op amp will never have good PSRR because of the Miller compensation ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 360 7 Characterization of Comparators 4402 Page 36071 LECTURE 360 CHARACTERIZATION OF COlVlPARATORS READING AH 439444 Objective The objective of this presentation is 1 Introduction to the comparator 2 Characterization of the comparator Outline Static characterization Dynamic characterization Summary ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 360 7 Characterization of Comparators 4402 Page 36072 What is a Comparator The comparator is essentially a 1 bit analog digital converter Input is analog Output is digital Types of comparators 1 Open loop op amps without compensation 2 Regenerative use of positive feedback latches 3 Combination of open loop and regenerative comparators ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 360 7 Characterization of Comparators 4402 Page 36073 Circuit Symbol for a Comparator VP VN V0 Fig 81 1 Static Characteristics Gain Output high and low states Input resolution Offset Noise Dynamic Characteristics Propagation delay Slew rate ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 360 7 Characterization of Comparators 4402 Page 36074 Noninverting and Inverting Comparators The comparator output is binary with the two level outputs defined as VOH the high output of the comparator VOL the low level output of the comparator Voltage transfer function of an Noninverting and Inverting Comparator V0 V0 A k A k VOH V0H gtvpVN gtvpVN VOL V0L Noninverting Comparator Invertng Comparator Fig 812A ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 360 7 Characterization of Comparators 4402 Page 36075 Static Characteristics Zeroorder Model for a Comparator Voltage transfer function curve V0 n V0H gtvPVN VOL Fig 812 Model VP 0 vP VN f 0VPVN vo v N Comparator f VOH for VPVN gt 0 0 VP39VN VOL for VPVN lt 0 Fig 813 VOH VOL Gain AV hm A where AV is the input voltage change V40 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 360 7 Characterization of Comparators 4402 Page 36076 Static Characteristics FirstOrder Model for a Comparator Voltage transfer curve Fig 8174 where for a noninverting comparator V1H smallest input voltage at which the output voltage is VOH VIL largest input voltage at which the output voltage is VOL Model VP o 39 VOH VOL vP VN f1VPVN V0 The voltage gain 1s Av m V N Comparator V0H for VPVN gt VIH f1VPVN AvVP VN for V1Llt VP39VNltV1H VOL for VP VN lt VIL Fig 815 ECE 6412 7 Analog Integrated Circuit Design 7 II PE Allen 7 2002 Lecture 360 7 Characterization of Comparators 4402 Page 36077 Static Characteristics FirstOrder Model including Input Offset Voltage Voltage transfer curve Fig 8176 V0HV0L V05 the 1nput voltage necessary to make the output equal T when vp vN Model VP vp iVOSVPLVN VN C VN Comparator v Fig 8L7 Other aspects of the model ICMR input common mode voltage range all transistors remain in saturation Rm input differential resistance Ricm common mode input resistance ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 360 7 Characterization of Comparators 4402 Page 36078 Static Characteristics Comparator Noise Noise of a comparator is modeled as if the comparator were biased in the transition region 7 7 Transition Uncertainty Fig 818 Noise leads to an uncertainty in the transition region which causes jitter or phase noise ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 360 7 Characterization of Comparators 4402 Page 36079 Dynamic Characteristics Propagation Time Delay Rising propagation delay time 0 V0H VOL V1HVIL l l 2 Fig 819 Rising propagation delay time Falling propagation delay time Propagatron delay time 2 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 360 7 Characterization of Comparators 4402 Page 360710 Dynamic Characteristics SinglePole Response Model Av0 AV0 AVG s src1 70 where AVO dc voltage gain of the comparator we 73dB frequency of the comparator or the magnitude of the pole Step Response V00 Av0 1 e39Wle n where Vin the magnitude of the step input ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 360 7 Characterization of Comparators 4402 Page 36071 1 Dynamic Characteristics Propagation Time Delay The rising propagation time delay for a single pole comparator is VOHVOL 1 T AVO 1 etprcwm gt F we In W 1 2Avlt0vzn De ne the minimum input voltage to the comparator as VOH VOL 1 Viimm AVO p 16 1 Vinmin 1 2Vm Define k as the ratio of the input step voltage Vin to the minimum input voltage Vinmin Vin 2k k Vznltmin p Tc 1 izk li Thus if k 1 p 069310 Illustration V t 39 V lt7 Vin gt Vinm1n OH rrrrrrrrrrrrrrrrrrrrrrrrrr 77 Obviously the more overdrive Vin Vom 7 Y mquot V0H VOL applied to the input the smaller 1 Vin marlin 2 the propagation delay time T VOL quotquot quot t IP Wm Fig 8110 ECE 6412 7 Analog Integrated Circuit Design 7 II PE Allen 7 2002 Lecture 360 7 Characterization of Comparators 4402 Page 360712 D namic Characteristics Slew Rate of a Com arator If the rate of rise or fall of a comparator becomes large the dynamics may be limited by the slew rate Slew rate comes from the relationship dv 1CE where i is the current through a capacitor and v is the voltage across it If the current becomes limited then the voltage rate becomes limited Therefore for a comparator that is slew rate limited we have AV V0H VOL I0 AT W W where SR slew rate of the comparator ECE 6412 7 Analog Integrated Circuit Design 7 II PE Allen 7 2002 Lecture 140 7 Simple CMOS Op Amps 12804 Page 14071 LECTURE 140 SINIPLE CMOS 0P AlVlPS READING TextGHLM 425434 453454 AH 249253 INTRODUCTION The objective of this presentation is 1 Illustrate the analysis of CMOS op amps 2 Prepare for the design of CMOS op amps Outline Simple CMOS Op Amps Two stage Folded cascode Summary ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 140 7 Simple CMOS Op Amps 12804 Page 14072 SIMPLE TWOSTAGE CMOS OP AMPS TwoStage CMOS Op Amp Circuit DC Conditions 15 117m 11 12 0515 0511mm 17 16 quotIBias Vicmmax VDD V303 V71 Vicmmin Vss VDSSSat VGSl Vommax VDD VSD6Sat Mg Vommin Vss VDs7sat Notice that the output stage is class A Fig 14001 KN W6 39 sin17 and Isome 2L6 VDDVssVT217 ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 140 7 Simple CMOS Op Amps 12804 Page 14073 DC Balance Conditions for the TwoStage OD Amn For best performance keep all transistors in VDD saturation M4 is the only transistor that cannot be forced into saturation by internal connections or external voltages Therefore we develop conditions to force M4 to be 39 in saturation V 1 First assume that V304 VSG6 This will M7 cause proper mirroring in the M3 M4 mirror VBW Also the gate and drain of M4 are at the same Vss potential so that M4 is guaranteed to be in Flg39 140702 saturation W1quot S6 2 Let Si 2T1 zfvsg4 V506 then 16 EI4 S7 S7 3 However 17 214 S6 257 4 For balance 16 must equal 17 gt which is called the balance conditions 5 So if the balance conditions are satisfied then Vpg4 O and M4 is saturated I5 ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 140 7 Simple CMOS Op Amps 12804 Page 14074 SmallSi nal Performance of the TwoSta e CMOS 0 Am VSS 3 cc V1 v2 I II gmlvm J gt J Jvm T C L gm1vm C g 6 12 rdslllrd M gm3 2 gm4V1 1 myzllrd m rdsGllrds CL T T g 3 8 gt gds2gds4 3 Cc amp gt GB I II 0 V2 J J V C V t 1 gmwm IT dsZHVdM 8 rds6rds7 II T 0u I Fig 140703 ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 140 7 Simple CMOS Op Amps 12804 Page 14075 SmallSignal Performance of the TwoStage CMOS Op Amp Summary of the small signal performance Midband performance A0 gmigmiiRiRii gmigm6rds2rds4rds6rds7 Rout rds llrdsm Rm 0 Roots Z gmll gm6 CI O CC CC 1 gds2gds4gds6gds7 ng1 gm6 P0165 P1 ngIRIRHCc gm6Cc and P2 C11 CL Assume that gml lOOpS gm6 lmS rdsz rds4 2M9 mm rds7 05MQ CC SpF and CL lOpF A0 1OOHSXlMQ1000uSO25MQ 25000VV Rm so Rom 250k 2 Zero lOOOpSSpF 2x108 radssec or 3183MHZ 1 Jo P1 lmS1MQO25MQ5pF 3x102 J 7800 radssec or 1273Hz x8 I c 7 0 GB 3178MHz 3910 MOS Fig714004 and p2 IOOOHSIOpF 108 radssec or 15915MHZ ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 140 7 Simple CMOS Op Amps 12804 Page 14076 Slew Rate of a TwoStage CMOS OD AmD Remember that slew rate occurs when currents owing in a capacitor become limited and is given as de Ilim C 7 where vC is the voltage across the capacitor C VDD VDD CC 15 o Vow gt Vow T 39Assume a T 39Assume a C Vingtgt0 Virtural WE 1 Virtural th I ground ground 7 M7 M7 V55 1 Vss Positive Slew Rate Negative Slew Rate Fig 14005 15 161517 15 15 1715 15 SR min CC CL CC because I6gtgtI5 SR min CC CL CC if I7gtgtI5 Therefore if C L is not too large and if 17 is significantly greater than 15 then the slew rate of the two stage op amp should be 15 SR C C ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 140 7 Simple CMOS Op Amps 12804 Page 14077 Folded Cascode CMOS Op Amp Circuit VDD 114 M5115 A B Comments The bias currents I4 and 15 should be designed so that 16 and 7 never become zero ie I4I51513 This amplifier is nearly balanced would be exactly if R A was equal to R B Self compensating Poor noise performance the gain occurs at the output so all intermediate transistors contribute to the noise along with the input transistors Some first stage gain can be achieved if R A and R3 are greater than gml or gmz Fig 14006 ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 140 7 Simple CMOS Op Amps 12804 Page 14078 WW1 Model Recalling what we learned about the resistance looking into My the source of the 2 cascode transistor Fig 14007 rds6R21gm10 l d R rds7 R11 R11 h R an were z r r A 1 gm rds gm 3 1 gm7rds7 gm7rds7 H 8 d d The small signal voltage transfer function can be found as follows The current 13910 is written as gm1rds1 rds4vm gm1Vm 10 2RA rdsrllrds4 2 and the current i7 can be expressed as gm2rds2rds5vm ngVin ngVin RIIgds2gds4 l7 R11 RII8ds2gds5 21k Where k gm7rds7 2i8m7rds7 rdszllrd 2 gm7rds7 The output voltage vow is equal to the sum of i7 and 13910 owing through Rom Thus 8amp1 gmz 2k 2 21k Rom 22k 8mIRom ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 1 Vom Vin Lecture 140 7 Simple CMOS Op Amps 12804 Page 14079 Frequency Response of the Folded Cascode Op Amp The frequency response of the folded cascode op amp is determined primarily by the output pole which is given as 1 pm Rautcaut where Com is all the capacitance connected from the output of the op amp to ground All other poles must be greater than GB gmllCout The approximate expressions for each pole is 1 Pole at node A pA z 1RACA 2 Pole at node B pB z 1RBCB 3 Pole at drain of M6 p6 z W 4 Pole at source of M8 p8 z gm8C8 5 Pole at source of M9 p9 z gm9C9 6 Pole at gate ofMlO p10 z gm10C10 where the approximate expressions are found by the reciprocal product of the resistance and parasitic capacitance seen to ground from a given node One might feel that because RE is approximately rds that this pole might be too small However at frequencies where this pole has in uence Com causes Row to be much smaller making p3 also non dominant ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 140 7 Simple CMOS Op Amps 12804 Page 140710 Example 1 Folded Cascode CMOS Op Amp Assume that all gmN gmp lOOpS rdsN 2M9 rdsp 1M9 and CL lOpF Find all of the small signal performance values for the folded cascode op amp 04x10903x106 RHO4G 2RA 10k9 andRB4M 2 kT 12 v 212 10057143 072957143 4156Vv Rom RH gm7rds7rds5llrdsz 4OOMQ100O667M 2 57143MQ 1 1 Ipml m m 1750 radssec gt 278Hz gt GB 121MHz Comments on the Folded Cascode CMOS Op Amp Good PSRR Good ICMR Self compensated Can cascade an output stage to get extremely high gain with lower output resistance use Miller compensation in this case Need rst stage gain for good noise performance Widely used in telecommunication circuits where large dynamic range is required ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 300 7 Buffered Op Amps 32102 Page 30071 LECTURE 300 BUFFERED 0P AlVlPS READING AH 352368 Objective The objective of this presentation is l Illustrate the method of lowering the output resistance of simple op amps 2 Show examples Outline Open loop MOSFET buffered op amps Closed loop MOSFET buffered op amps BJT output op amps Summary M Buffered To illustrate the degrees of freedom and lefeie nal choices of different circuit architectures that can enhance the performance of a given op amp High Frequency LOW Power Low Noise Low Voltage Fig 701 ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 300 7 Buffered Op Amps 32102 Page 30072 What is a Buffered Op Amp A buffered op amp is an op amp with a low value of output resistance R0 Typically 109 5 R0 5 10009 Requirements Generally the same as for the output amplifier Low output resistance Large output signal swing Low distortion High efficiency Types of Buffered Op Amps Buffered op amps using MOSFETs With and without negative feedback Buffered op amps using BJTs ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 300 7 Buffered Op Amps 32102 Page 30073 SourceFollower PushPull Output Op Amp M22 t EVSS G322 Vout I CL VSGZl 39IE VDD M21 er Fig 7171 1 Ram m S 10009 AV0 65dB IBiaS50pA and GB 60MHZ for CL lpF Output bias current Ml 8 Ml9 M21 M22 100p gt VSGl 8Vg519 VSGZlVGS22 2118 2119 2121 2122 Wthh gIVeS KPS18 IKNS 19 KP521 IKN522 ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 300 7 Buffered Op Amps 32102 Page 30074 CrossoverInverter Buffer Stage OD Amn Principle If the buffer has high output resistance and voltage gain common source this is okay if when loaded by a small RL the gain of this stage is approximately unity E VDD I MFG I 24 5 I 75 i Vout RL 5 Ms vi 5 MA I 14 Input E C i V O S stage ross over stage SS ugpug tage Fig 71 This op amp is capable of delivering l60mW to a 1009 load while only dissipating 7mW of quiescent power ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 300 7 Buffered Op Amps 32102 Page 30075 CrossoverInverter Buffer Sta e 0 Am Continued How does the output buffer work The two inverters Ml M3 and M2 M4 are designed to work over different regions of the buffer input voltage Vin Consider the idealized voltage transfer characteristic of the crossover inverters Vout quot M1M3 M2M4 Inverter p Inverter 39 Vin39 VSS VA VB VDD Fig 71 3 Crossover voltage 5 VC VB VA 2 0 VC is designed to be small and positive for worst case variations in processing Maximum value of VC z llOmV ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 300 7 Buffered Op Amps 32102 Page 30076 CrossoverInverter Buffer Stage Op Amp Continued Performance Results for the Crossover Inverter Buffer Stage CMOS Op Amp Speci cation Performance Supply Voltage i 6 V Quiescent Power 7 mW Output Swing 1009 81 Vpp Load Open Loop Gain 1009 781 dB Load Unity Gainbandwidth 260kHz Voltage Spectral Noise 17 V IHZ Density at lkHz M PSRR at lkHz 55 dB CMRR at lkHz 42 dB Input Offset Voltage 10 mV Typical ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 300 7 Buffered Op Amps 32102 Page 30077 Com ensation of 0 Am 5 with Out ut Am lifiers Compensation of a three stage amplifier This op amp introduces a third pole p 3 what POIeS P016175 d about zeros F1 in 172 With no compensation VJ 39 V in am V0ut5 Avo Vins S S S Unbuffered w T 1 172 1 173 1 op amp Stage Fig7l4 Illustration of compensation choices 13900 13900 Compensated poles X Uncompensated poles P2 Miller compensation applied around Miller compensation applied around both the second and the third stage the second stage only Fig 715 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 300 7 Buffered Op Amps 32102 Page 30078 Low Output Resistance Op Amp To get low output resistance using MOSFETs negative feedback must be used Ideal implementation Gain Error Amplifier Amplifier ViiL Fig 715A Comments The output resistance will be equal to rdslllrdsz diVided by the loop gain If the error amplifiers are not perfectly matched the bias current in M1 and M2 is not defined ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 300 7 Buffered Op Amps 32102 Page 30079 Low Out ut Resistance 0 Am Continued Offset correction circuitry VDD em Cci V0S Vout n quotquotquotquot Error Loop A M8 39 quotquot 39 M 8A Unbuf f cred op amp I v16A M13 M12l M11 as VBi lt M10 Vss Fig 716 The feedback circuitry of the two error amplifiers tries to insure that the voltages in the loop sum to zero Without the M9 M12 feedback circuit there is no way to adjust the output for any error in the loop The circuit works as follows When V05 is positive M6 tries to turn off and so does M6A 1M9 reduces thus reducing 111412 A reduction in 111412 reduces 114 thus decreasing VasgA VGS3A ideally decreases by an amount equal to V05 A similar result holds for negative offsets and offsets in EA2 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 300 7 Buffered Op Amps 32102 Page 300710 Low Output Resistance Op Amp Continued Error ampli ers M6A Fig 71 7 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 300 7 Buffered Op Amps 32102 Page 300711 Low Output 39 A on Amp p r a Lip VDD VBiasP VBiasN VS vim Fig 7178 Compensation Rc Cc Uses nulling Miller compensation Short circuit protection 2 r MP3 MN3 MN4 MP4 MP5 gt gt MN3A MP3A MP4A MN4A MN5A Rig C i max output 60mA ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 300 7 Buffered Op Amps 32102 Page 300712 Low Output Resistance Op Amp Continued Table 71 2 Performance Characteristics of the Low Output Resistance Op Amp T Simulated Results Measured Results Power Dissipation 70 mW 50 mW Open Loop Volmge Gain 82 dB 83 dB Unity Gainbandwidth 500kHz 420 kHz Input Offset Volmge 04 mV 1 mV PSRR0PSRR 0 85 dB104 dB 86 dB106 dB PSRR1kHZp3RR 1kHZ 8l dB98 dB 80 dB98 dB THD V in 33Vpp RL 3009 003 0131 kHz CL lOOOpF 008 0324 kHz THD V in 40Vpp RL 15K 2 005 0131 kHz CL 200pF 016 0204 kHz Settling Time 01 3 M5 lt5 M5 Slew Rate 08 VMs 06 VMs lfNoise at lkHz 130 11VVE Broadband Noise 49 nV rds6rds6A 50kg Rout Loop Gain 5000 109 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 300 7 Buffered Op Amps 32102 Page 300713 LowOutput Resistance Op Amp Continued Component sizes for the low resistance op amp TransistorCapacitor urnMm or pF Tran sistor Cap acitor MIDM111 0f pF M16 1849 M8A 4816 M17 6612 M13 6612 M8 1846 M9 276 M1M2 3610 M10 622 M3 M4 1946 M11 146 M3HM4H 1612 M12 1406 M5 145 1 2 MP3 86 M6 26476 MN3 2446 MRC 4810 MP4 4312 CC 1 1 O MN4 126 MlA M2A 8812 MP5 66 M3A M4A 19 6 6 MN3A 6 6 M3HA M4HA 10 1 2 MP3A 3376 M5A 22912 MN4A 2412 M6A 24206 MP4A 20 1 2 CF 100 MNSA 6 6 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 300 7 Buffered Op Amps 32102 Page 300714 Simpler 39 inn of Negative F quot 39 to Achieve Low Output 39 VDD v M j LJM3 letj M6 ZOOMA 101 11 11 10 c Vom i LI W M J L Output Resistance Vin 10 10 I R Ra 1 1 01 1LG MS where M10 101 11 101 1 M M7 R0 gds6gds7 and VSS Fig 719 gmz ILGI 2gm4 gm6gm7Ra Therefore the output resistance is 1 Ram gmz gds6gds7 1 2gm4 gm6gm7Ro ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 300 7 Buffered Op Amps 32102 Page 300715 Example 711 Low Output Resistance Using the Simple Shunt Negative Feedback Buffer Find the output resistance of above op amp using the model parameters of Table 31 2 Solution The current owing in the output transistors M6 and M7 is 1mA which gives R0 of 1 1000 Ra ANAP1mA 009 1111k9 To calculate the loop gain we find that gmz 2KN 1O1OOHA 469uS gm4 IZKP 11OOuA 100uS gm6 2Kp 101000uA 1mS Therefore the loop gain is ILGI m 121111 1042 and Solving for the output resistance Ram gives 11kg Ram 1 1042 1069 Assumes that RL is large ECE 6412 7 Analog Integrated Circuit Design 7 II PE Allen 7 2002 Lecture 300 7 Buffered Op Amps 32102 Page 300716 B lTs Available in CMOS Technology Illustration of an NPN substrate BJT available in a p well CMOS technology Base Collector 0 VDD Emitter Collector VD D n Emitter T p39 well Base n39 substrate Collector 1 Fig 7110 Base Emitter Comments gm of the BJT is larger than the FET so that the output resistance wo feedback is lower Can use the lateral or substrate BJT but since the collector is on ac ground the substrate BJT is preferred Current is required to drive the BJT ECE 6412 7 Analog Integrated Circuit Design 7 II PE Allen 7 2002 Lecture 300 7 Buffered Op Amps 32102 Page 300717 TwoStage On Amn with a ClassA BIT Output Buffer Stage Purpose of the M8 M9 source follower 1 Reduce the output resistance includes whatever is seen from the base to ground divided by 1 F 2 Reduces the output load at the drains of M6 and M7 Small signal output resistance Fig71711 mm 1gm9 L 1 ROW 5 1 F gmro gm91 F 516Q67Q 5839 where 10500uA 18lOOpA W9L9100 and3F is 100 Maximum output voltage 2KP V0UTmaX VDD 39 V3086 39 VBEro VDD 39 I8 WSLS 39 V5111 IS10 Voltage gain M gml W gmo V gm9 W gmlORL l Vin Lgds2gds4JLgds6gds7JLgm9gmbs9gds8gnlOJL1gmlORLJ Compensation will be more complex because of the additional stages ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 300 7 Buffered Op Amps 32102 Page 300718 Exam 1e 712 Desi nin the ClassA Buffered 0 Am Use the parameters of Table 31 2 along with the BJT parameters of Is 103914A and 31 100 to design the class A buffered op amp to give the following specifications Assume the channel length is to be 1m VDD 25V VSS 725V GB SMHZ Avd0 2 SOOOVV Slew rate 2 lOVus RL 5009 ROW 5 1009 CL lOOpF ICMR 71V to 2V Solution Because the specifications above are similar to the two stage design of Ex 63 1 we can use these results for the first two stages of our design However we must convert the results of Ex 63 1 to a PMOS input stage The results of doing this give W1 W2 6pm W3 W4 7pm W5 llum W6 43pm and W7 34pm B T follower SR lOVus and lOOpF capacitor give 111 lmA If W13 44pm then W11 44um1000uA3OHA l467um 1111mA gt lgm10 00258V1mA 2589 MOS follower To source lmA the BJT must provide 2mA which requires ZOpA from the MOS follower Therefore select a bias current of lOOpA for M8 If W12 44pm then W8 44pmlOOpA3OHA 146um ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 300 7 Buffered Op Amps 32102 Page 300719 Example 712 Continued If llgmlo is 2589 then design gmg as 1 1 gm9RUW llgm101 F 100258101 1334115 gmg and 19 gt WL 0809 Let us select WL 10 for M9 in order to make sure that the contribution of M9 to the output resistance is sufficiently small and to increase the gain closer to unity This gives a transconductance of M9 of 469uS To calculate the voltage gain of the MOS follower we need to find gmbsg gm9YN 46904 gmbs 2 2 F V359 24072 where we have assumed that the value of V539 is approximately 2V 469uS AMOS 469uS571uS4uS5uS 08765 VV The voltage gain of the BJT follower is 571115 00 AB m 0951 VV Thus the gain of the op amp is Avd0 7777O8765O951 6483 VV The power dissipation of this amplifier is Pdim 5V1255pA 627mW ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 300 7 Buffered Op Amps 32102 Page 300720 TwoStage OD Amn with a ClassAB BJT Outnut Buffer Stage This amplifier can reduce the quiescent power dissipation Vout VSS Output T Buffer Fig 7112 Slew Rate IOUT 1 FI7 59000 1V IVSSI VTO2 SR CL CL and SR39 ZCL If 3 100 CL 1000pF and I7 95pA then SR 859Vus Assuming a W9L9 60 19 133pA 25V power supplies and C L 1000pF gives SR 359Vus The current is not limited by 17 as it is for the positive slew rate ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 300 7 Buffered Op Amps 32102 Page 300721 TwoSta e 0 Am with a ClassAB B T Out ut Buffer Sta e Small signal characteristics Cc lt gmlvm EVIE IIVEE gt m Nodal equations Fig 7H3 gmVin G1 SCCV1 SCCVZ OVaut 0 ngI chV1 G11 8n ch anV2 8n SCnV0ut O E gm9V1 gm13 anV2 gm13 5amp5ng Where g gt G3 The approximate voltage transfer function is V9s szl 1 szz 1 VinS Av0sp1 hrs122 1 where A gm1gm11 1 gm13 ngI gm9 V0 GIGII Z1 Cc Cw 1 gm Z2 Cu Cc ngI ngI gm13 ngI GIGII gm9 Cn GIGII 1 gm13ngI E p1 ngICc FngI Cc gm13gm11 p2 ngI gm9Cn ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 300 7 Buffered Op Amps 32102 Page 300722 TwoStage OD Amn with a ClassAB BJT Output Buffer Stage Continued Output stage current 1C8 Sg 60 CS ID9 5 61D6 E 95HA 133HA Small signal output resistance rE RH 19668k9 11696k9 rout 1 3F 101 1353Q if I6 17 95uA and 7 100 Loading effect of R L on the voltage transfer curve increasing W9L9 will improve the negative part at the cost of power dissipation VOUT Volts 05 0 05 1 15 2 VIN Volts Fig 7114A ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 150 7 Simple BJT Op Amps 12804 Page 15071 LECTURE 150 SIMPLE BJT 0P AlVlPS READING TextGHLM 425434 453454 AH 249253 INTRODUCTION The objective of this presentation is 1 Illustrate the analysis of BJT op amps 2 Prepare for the design of BJT op amps Outline Simple BJT Op Amps Two stage Folded cascode Summary ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 150 7 Simple BJT Op Amps 12804 Page 15072 SIMPLE TWOSTAGE BJ T OP AMPS B IT TwoStage Op Amp Circuit VEE Fig 150701 DC Conditions 15 117m 11 12 0515 0511mm I7 16 quotIBias Vicmmax VCC VEB3 VCE1sat VBEi Vicmmin VEE VCE5Sat VBEi Vom nax VCC VEC6Sat V0ulmin VEE VCE7Sat Notice that the output stage is class A gt sink 17 and source 3115 I7 ECE 6412 7 Analog Integrated Circuit Design 7 n PE Allen 7 2002 Lecture 150 7 Simple BJT Op Amps 12804 Page 15073 TwoSta e B T 0 Am Continued Small Signal Performance Assuming differential mode operation we can write the small signal model as C f v I ngVin I I g 1V39 R C Lv 1v R3 C 1 Vout mg m 1 1 1 2 gm4V1 R2 C2 ngsvz 3 Fig 150 02 where 1 1 R1 Ilrngllrn4llr03 z R2 r 6ll r02 r04 z r116 and R3 r06 r07 C1 Cn3Cn4CcslCcs3 C2 Cn6Ccs2Ccs4 and C3 CL Ccs6Ccs7 Note that we have ignored the base collector capacitors CH except for M6 which is called Cc Assuming the pole due to C1 is much greater than the poles due to C2 and C3 gives I I 0 gt gt gmlvm R gtC V2 R3gtC3 V0 2 2 gm6V2 I I c Fig 15003 ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 150 7 Simple BJT Op Amps 12804 Page 15074 TwoSta e B T 0 Am Continued Summary of the small signal performance Midband performance A0 gmrgmHRIRH gmrgm rndro llm gmr F6r06ro7 Rout r06r077 Rm 2amp1 Roots Z gmllgm6 610 CC CC gmll 8 m6 71 71 gml P0163 at P1 gmHRIRHCc gm6rn6ro6 ro7cc AoCc and P2 C11 CL Assume that 3F100 gm11mS gm6 10mS r06r0705MQ Cc5pF and CL10sz A01mS100 250k925000VV Rm 2 Fgm12100k 2200k 2 Rom250k 2 10mS 9 Zero 5pF 2x10 radssec jm or 3183MHZ 8X103 J X O gt O 1mS 72X108 109 quotI 2X109 Fig 15004 P1 250005pF 25000 78000 radssec or 1273HZ and p2 710mS10pF 7109 radssec or 15915MHZ ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 150 7 Simple BJT Op Amps 12804 Page 15075 Slew Rate of the TwoStage B IT Op Amp Remember that slew rate occurs when currents owing in a capacitor become limited and is given as VC Ilim C W where vC is the voltage across the capacitor C Assume a virtural VEE VEE Positive Slew Rate Negative Slew Rate Fig 15005 16 15 17 15 15 17 15 15 SR min C C CL C c because I6gtgtI5 SR min C 0 CL 1 C c if I7gtgtI5 Therefore if C L is not too large and if 17 is significantly greater than 15 then the slew rate of the two stage op amp should be 15 SR Cc ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 150 7 Simple BJT Op Amps 12804 Page 15076 FoldedCascode B T 0 Am Circuit VCC VCC VBE L Q10 Q1 1 VCEsat 2 v v Vin 10m Vow 10m Vow 11 C4 lICS VBE l T V3111 VC sat 3 Q4 I VEE VEE Flg 15005 Simplified Circuit Biasing details of the output DC Conditions 13 biasy 11 12 0515 0511mm 14 15 kIBiasy 110 111 kIBiasOSlbias kgt1 Vicmmax VccVCE3SatVEBr Vicmmin VEEVCE4SatVEC1530VBE1 Vom nax VCCVEC9satVE011sat Vommin VEEVCE5satVCE7sat Notice that the output stage is push pull gt I sink and I source are limited by the base current ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 150 7 Simple BJT Op Amps 12804 Page 15077 FoldedCascode B T 0 Am Continued Small Signal Analysis gm6Vbe6 gm7Vbe7 RA RB i7 IL lilo I A A gt c gimlvi ltr 6Vb 6 r06 gimzvi i lt Vb 7 07 v e e i 2 r01lt r04ltgt n lt gnilO 2 r02ltgtr05ltgtrn7lt 110 mm m Fig 150 07 ro7l3Pr011l2 r717 where RA 1gm6 and RB z Ww 2 if r07 z r011 gml rn6Vin glein gm2rn7Vin gm2rn7Vin ngVin l10 2rn6RA 2 l7 2r 7RB 2r 705r 7 3 M 2 Voul 17 110R0ulVin 6 gmlRoulVin 1f gml gm2 gt Vin 6 gmlRoul Rout Proll 5Nr05 r02 and Rin 2r711 Assume that SFN lOO SFP 50 gml gmz lmS r0N 1M9 and rap O 5M9 Voul W 14285VV Rom 14285 M9 and Rm lOOkQ ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 150 7 Simple BJT Op Amps 12804 Page 15078 FoldedCascode B T 0 Am Continued Frequency response includes only 1 dominant pole at the output self compensation 1 p1 Rout CL There are other poles but we shall assume that they are less than GB If CL 25pF then Ipll 2800 radssec or 446Hzgt GB 6371 MHZ Checking some of the nondominant poles gives 1 gm6 IpAI mC A gt 159MHz 1f CA 1pf the capacitance to ac ground at the emitter of Q6 2 IpBI m m gt 637MHZ if C3 1pf the capacitance to ac ground at the H 00 80 60 40 20 emitter of Q7 This indicates that for small capacitive loads this op amp will suffer from higher poles with respect to phase margin Capacitive loads greater than 25pF will have better stability and less GB VdB3 20 40 8 100 1000 10 Frequency Hz Fig 150708 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 340 7 Low Noise Op Amps 32602 Page 34071 LECTURE 340 LOW NOISE OP AlVlPS READING AH 402414 GHLM 788798 Objective The objective of this presentation is 1 Review the principles of low noise design 2 Show how to reduce the noise of op amps Outline Review of noise analysis Low noise op amps Low noise op amps using lateral BJTs Low noise op amps using doubly correlated sampling Summary ECE 6412 7 Analog Integrated Circuit Design 7 II PE Allen 7 2002 Lecture 340 7 Low Noise Op Amps 32602 Page 3402 Introduction Why do we need low noise op amps VDD Dynamic range Signal 0110136 ratio SNR Dynamic Range 2 6deNumber of bits Maximum RMS Signal Noise Noise Distortion Fig 750B SNDR includes both norse and distortion Consider a 14 bit digital to analog converter with a 1V reference with a bandwidth of lMHz 05V Maximum RMS signal is W 03535 Vims A 14 bit DA converter requires l4x6dB dynamic range or 84 dB or 16400 03535 The value of the least significant bit LSB m 216uVims Ifthe equivalent input noise of the op amp is not less than this value then the LSB cannot be resolved and the DA converter will be in error An op amp with an equivalent input noise spectral density of lOnVxHZ will have an ims noise voltage of approximately lOnVxHleooo lOerms in a lMHz bandwidth ECE 6412 7 Analog Integrated Circuit Design 7 II PE Allen 7 2002 Lecture 340 7 Low Noise Op Amps 32602 Page 34073 Transistor Noise Sources LowFrequency Drain current model D D Ml M1 2 Go I Q Go znl M1 is M1 is noisy s noiseless S FigTSVOA 2 Mg Kelp 2 8kTgmlt1m Kelp ln 3 fC0xL2 or ln 3 fC0xL2 1vaS O gm Recall that n Gate voltage model assuming common source operation D D 2 M1 en1 1 Go I 3 Go M115 Ml is noisy S n01seless S Fig757m 2 2 1N 8kT 2 i w en gmz 3gm2fC0xWLK l or 6n KF 3gm ZfCOXWLK 1fVBSO ECE 6412 7 Analog Integrated Circuit Design 7 II PE Allen 7 2002 Lecture 340 7 Low Noise Op Amps 32602 Page 34074 up inn of Noise in OD Amns l Maximize the signal gain as close to the input as possible As a consequence only the input stage will contribute to the noise of the op amp 2 To minimize the lf noise a Use PMOS input transistors with appropriately selected dc currents and W and L values b Use lateral BJTs to eliminate the lf noise c Use chopper stabilization to reduce the low frequency noise Noise Analysis 1 Insert a noise generator for each transistor that contributes to the noise Generally ignore the current source transistor of source coupled pairs 2 Find the output noise voltage across an open circuit or output noise current into a short circuit 3 Reflect the total output noise back to the input resulting in the equivalent input noise voltage ECE 6412 7 Analog Integrated Circuit Design 7 II PE Allen 7 2002 Lecture 340 7 Low Noise Op Amps 32602 Page 34075 A LowNoise TwoStage Miller Op Amp Fig 7571 2 The total output noise voltage spectral density em is as follows where gmgeff z lrdsl 2 2 2 2 2 2 2 2 2 em gmanz emsen7 R12gm12en1gm22enzgm32enagm4zen4 ensr2512 mgmm 2 Divide by gmlRIgm6RH2 to get the eq input noise voltage spectral density eeq as 2 EH 2 Enl ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 2 2 em 26 2 n6 2 2 1 6n3 6n8 66 gmlgmoRIRII2 gmlzRIZ 6 2 2 2 2 2 2 z 2621 6n1 gmlzrdSIZenl 2 2 2 2 2 2 2 2 where em m7 673 6n4 em 6n2 and em 679 and gmlRI 1s large gm3 gml g m3 1 gml Lecture 340 7 Low Noise Op Amps 32602 Page 34076 llt Noise 0139 a TwoStage Miller Op Amp Consider the lf noise Therefore the noise generators are replaced by 2 B 2 ZBK Ii em39 v2Hz and im W AZHZ Therefore the approximate equivalent input noise voltage spectral density is 2 2 KN BN L1 2 2 egg Zenl 1 m E V Hz Comments 2 Because we have selected PMOS input transistors enl has been minimized if we choose W1L1 WZLZ large Make L1ltltL3 to remove the in uence of the second term in the brackets ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 340 7 Low Noise Op Amps 32602 Page 34077 Thermal Noise of a TwoSta e Miller 0 Am Let us focus next on the thermal noise The noise generators are replaced by 2 M 2 2 Mg 2 eni3gm V HZ and 1mquot 3 A HZ where the in uence of the bulk has been ignored The approximate equivalent input noise voltage spectral density is 2 2 E 2 6n1 Comments The choices that reduce the 1f noise also reduce the thermal noise KNW3L1 2 1 m V2Hz 2 gm3 eeq 26ml gm 26 1 Noise Corner Equating the equivalent input noise voltage spectral density for the 1f noise and the thermal noise gives the noise corner f0 as 3gmB fc 8kTWL ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 340 7 Low Noise Op Amps 32602 Page 34078 Example 751 Design of A TwoStage Miller Op Amp for Low llt Noise Use the parameters of Table 31 2 along with the value of KF 4x10quot28 PA for NMOS and 05x103928 PA for PMOS and design the previous op amp to minimize the 1f noise Calculate the corresponding thermal noise and solve for the noise corner frequency From this information estimate the nns noise in a frequency range of 1Hz to lOOkHZ What is the dynamic range of this op amp if the maximum signal is a 1V peak to peak sinusoid Solution 1 The 1f noise constants BN and Bp are calculated as follows KF 4x103928FA 22 2 EN 2CoxKN 2247x104Fm2110x106A2V 736x10 V m and KF 05x103928FA 22 2 BF ZCUxKP 2247x1O394Fm250x10396A2V 202x10 VIII 2 Now select the geometry of the various transistors that in uence the noise performance 2 To keep em small let W1 100nm and L1 1m Select W3 100nm and L3 20pm and leth and L3 be the same as W1 and L1 since they little in uence on the noise ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 340 7 Low Noise Op Amps 32602 Page 34079 Example 751 Continued Of course M1 is matched with M2 M3 with M4 and M8 with M9 2 BP 202x103922 202x103912 m mm T VZIHZgt 2 A 202x103912 110736212 404x103912 4689x103912 2 egg x f 1 K 50202 20 f 11606 f V HZ Note at 100Hz the voltage noise in a 1Hz band is z 47x103914V2rms or O216uVrms 3 The thermal noise at room temperature is 2 8kT 8138X1039233OO an 387 W 1562x1017 V2Hz which gives 1101001 2 egg 21562x103917 1 W ammo17133 4164x103917 vzHz 2 4 The noise corner frequency is found by equating the two expressions for egg to get 4689x1012 fC W1126kHz This noise comer is indicative of the fact that the thermal noise is much less than the 1f noise ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 340 7 Low Noise Op Amps 32602 Page 340710 Example 751 Continued 5 To estimate the rrns noise in the bandwidth from 1Hz to 100000Hz we will ignore the thermal noise and consider only the 1f noise Performing the integration gives 105 4689X103912 Veqrms2 fdf 4689x103912ln100000 ln1 1 054Ox103910 Vrms2 734 uVrms The maximum signal in rms is 0353V Dividing this by 734uV gives 48044 or 936dB which is equivalent to about 15 bits of resolution 6 Note that the design of the remainder of the op amp will have little in uence on the noise and is not included in this example ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 340 7 Low Noise Op Amps 32602 Page 340711 Lateral B T Since the lf noise is associated with current owing at the surface of the channel the lateral BJT offers a lower lf noise input device because the majority of current flows beneath the surface Vertical Lateral Vertical Collector VDD Collector Base Emitter Collector V1313 f Base gaffe x 1 B p well i A M 7 Emitter Cross section of a NPN lateral B T Symbol Fig 753 Comments Base of the BJT is the well Two collectors one horizontal desired and one vertical undesired Lateral collector current Collector eff1c1ency is defined asm and is 60 70 Reverse biased collector base acts like a photodetector and is often used for light sensing purposes ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 340 7 Low Noise Op Amps 32602 Page 340712 FieldAided Lateral B T Polysilicon gates are used to ensure that the region beneath the gate does not invert forcing all current ow away from the surface and further eliminating the lf noise Vertical G t Em tter Lateral Collector Base a 63 Collector V 1C 11 V VDD ertica o ector DD Lquot hl IEI ILl Gate Lateral W Baseo I Collector p well i 34 r 7 7 Emitter Cross section of a field aided NPN lateral BJT Symbol Fig 75 4 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 340 7 Low Noise Op Amps 32602 Page 340713 Ph sical La out of a Lateral PNP Transistor Experimental Results for a x40 PNP lateral B T K4 gtI4gtZ4gtI4K4K4 00061ng n sub strate K4 K4 K4 K4 K4 pwell K4N K4K4 K4K4 K4gtI4 K4 K4 gtI4gtI4 K4 K4 gt14 39 K4 Polys con 39 11 L Vertical Base Lateral Emitter Gate 1 5 Metal Collector Collector Flg 7 7A Generally the above structure is made as small as possible and then paralleled with identical geometries to achieve the desired BIT LowNoise On Amn using Lateral BlT s at the ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 340 7 Low Noise Op Amps 32602 Page 340714 Input 4L8 36 5L2 72 Experimental noise 10 performance A 8 N E S 6 E 4 2 Voltage of lateral 2 0 5 10 100 1000 10 Frequency Hz Fig 7577 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 340 7 Low Noise Op Amps 32602 Page 340715 Summary of Experimental Performance for the LowNoise Op Amp CLII I C Ilt current ECE 6412 7 Analog Integrated Circuit Design 7 II PE Allen 7 2002 Lecture 340 7 Low Noise Op Amps 32602 Page 340716 Cho erStabilizedO Am 5 Doubl Correlated Sam lin DCS Illustration of the use of chopper stabilization to remove the undesired signal vu form the desired signal Vin Vinf ECE 6412 7 Analog Integrated Circuit Design 7 II PE Allen 7 2002 Lecture 340 7 Low Noise Op Amps 32602 Page 340717 Cho erStabilized Am lifier Chopperstabilized Amplifier VDD VDD Vin 2 I 2 1 W Bias Bias Vss Vss T Vu2 Vueq Vul T1 Circuit equivalent during the 12 phlase Vuz M V Vu2 Vueq 4m if vueqaver 11 Fig 75 10 ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 340 7 Low Noise Op Amps 32602 Page 340718 EX erimental Noise Res onse of the Cho erStabilized Am lifier 1000 10 20 30 40 Frequency kHz Fig 7 511 Comments The switches in the chopper stabilized op amp introduce a thermal noise equal to kTC where k is Boltzmann s constant T is absolute temperature and C are capacitors charged by the switches parasitics in the case of the chopper stabilized ampli er Requires two phase non overlapping clocks Trade off between the lowering of lf noise and the introduction of the kTC noise PE Allen 7 2002 ECE 6412 7 Analog Integrated Circuit Design 7 11 Lecture 260 7 Shunt7Shunt Feedback 3502 Page 26071 LECTURE 260 SHUNTSHUNT FEEDBACK READING GHLM 563569 Objective The objective of this presentation is 1 Show how to identify the type of feedback topology 2 Illustrate the analysis of shunt shunt feedback circuits Outline Feedback identification procedure Shunt shunt feedback with nonideal source and load Examples Summary ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 260 7 Shunt7Shunt Feedback 3502 Page 26072 IDENTIFICATION OF THE FOUR SINGLELOOP FEEDBACK TOPOLOGIES TwoTerminal Rem quot of a SingleLoon Negative Feedback Svstem ii ie i0 2 Z gt a Signal V Mixing V Amph er 1 V Load Source 1 Network e of brward NEtWOFk 0 Network gain a 1 Feedback Vfb Network of reverse gain f Fig 26001 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 260 7 ShuntAShunt Feedback 3502 Page 26073 Feedback Topology Identification Procedure 1 Identify the feedback loop by tracing around the feedforward and feedback path Also check to see if the feedback is positive or negative 2 Identify whether or not the mixing network is series or shunt If the signal source has one terminal on ac ground then a If the input active device has one of its input terminals on ac ground then the mixing network must be shunt b If the signal and feedback sources are applied to different input terminals of the input active device then the mixing network is series this includes differential amplifiers where two devices form the input active device c If the signal source does not have one of its input terminals on ac ground or to check the above steps try to assign the variables xi 2 and xe on the schematic in such a manner as to implement the equation Xe xi i be If this equation can be written using voltages currents then the mixing circuit is series shunt l Tl l7 Ve Ve Vf v V Vfb J 39 T J T 4 Series Shunt Series 26002 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 260 7 ShuntAShunt Feedback 3502 Page 26074 Feedback To 010 Identification Procedure Continued 3 Next identify the sampling circuit as series or shunt If the load is grounded then a If the out active device has one of its two possible output terminals grounded then the feedback is shunt If the output active device has neither of its output terminals on ground and if the output signal is taken from one of its output terminals and the fed back signal from the other output terminal then the feedback is series If the load is not grounded or to check the above test identify the load resistor RL and apply the following test b v C v i If xfb becomes zero when RL 0 then the sampling network is shunt ii If x becomes zero when RL 00 then the sampling network is series i i 0 fb Shunt Fig 26003 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 260 7 Shunt7Shunt Feedback 3502 Page 26075 Transistor Examples of Negative Feedback Topology Identification 1K 10K 1 V1 Circuit 1 Cerult 2 12 i2 A lt A Q2 i gt gti1 1 10K 0 110K M9 Q 1K ltgt V2 gt AVVF V1 I 1 VVV 10Kgt v2 lt 10K lt gt 5K gt V1 2Kltgt 39 ltgt1K lt Circuit 3 Circuit 4 Fig 26004 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 260 7 Shunt7Shunt Feedback 3502 ShuntShuntF quot 39 J39 Configuration is R v ma RL v0 1 1 mm yzlavz 7 Basic Amplifier y11f YZZf Yum yzwz Feedback Network is RS vg 11f VIM yzlaVz ma YZZf RL 7 New Basic Amplifier S Yum New Feedback Network Fig 26005 La 2 A a Y21aY11Y22 ls quotl1 quot1df 1Y21aY11Y22Y12f ECE 6412 7 Analog Integrated Circuit Design 7 11 Source and Load Page 26076 39 4 o ShuntShunt v1 Feedback 11 Network 6 Fig 260706 i1 Y11V1 Y12V2 i2 mm Y22V2 where for the new basic amplifier l1 Y11 v20GsY11aY11f Ill Y12V2v100 ii I 3721 V1V20 y21a i2 I Y22 EV10 GL Y22a YZZf quot372111 Y11Y22 and fy12f PE Allen 7 2002 Lecture 260 7 Shunt7Shunt Feedback 3502 Page 26077 Example 1 Inverting Op Amp RF Find the closed loop transfer function A the closed loop input resistance Zl and the closed loop output resistance Zaf of the shunt shunt configuration shown The op amp has a differential input resistance of zi voltage gain of av and output resistance of za 7 T Fig 26007 T Voul ii RL Solution Equivalent circuit Feedback R 1 Equivalent Network F lt Feedback ii I 1 It is easy to show thatf y12f V Z39 Vlrzo R F The forward gain a is Va39 dVRF RL ZiRF aVRFRL w ZiRF a i v1 39 i tzaRFIIRLJinRFJ tzaRFzaRLRFRLJinRFJ where l a 0 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 260 7 Shunt7Shunt Feedback 3502 Page 26078 Example 1 Continued The loop gain is aVRFRL Zi T if zaRFzURLRFRL W The closed loop gain is aVRFRL ZiRF V0 a ZURFZURLRFRL m avRFZRLZi 7 1df aVRFRL Zi ZURF39l39ZaRL39l39RFRLXZi39l39RF dvRFRLZi 1 ZaRFZaRLRFRL m The closed loop input impedance is ZiRF Zi ZiR F ZUR FZUR LR FR L Zif F aVRFRL 2quot aVRL 1 zaRmaRnRFRL m The closed loop output impedance is g ZUIIR Fl IR L Z0f m aVRFRL 2quot 1 zaRFzURLRFRL m If av 200000 4 2M9 and Zn 759 RF 1M9 and RL 10kg then T 133333 Zl 21 0667MQ gt Zl 59 Zn z 759 gt Z0 0563mQ andA 79999929 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 260 7 Shunt7Shunt Feedback 3502 Page 26079 Example 2 Transistor Feedback Amplifier For the amplifier shown find v2v1 v1i1 and vzliz Assume that gm SmS and rds 00 for the MOSFET and rm r33 1000Q and 311 313 100 for the BJTs Fig 260709 Solution i3 1 Find the feedback topology and polarity of feedback Q3 The loop consists of base collector of Q1 gate drain of M2 and V1 R lt R lt R V2 base collector of Q3 A positive change at the base of Q1 gives 1amp2 1369 Elggg a 7 and the gate of M2 which gives a at the base of Q3 39 39 which gives a 7 at the base of Q3 feedback is negative quotquot 2 The mixing circuit is shunt because only the base terminal of Q1 is connected to the input and feedback Note that iC3 i and 31 i6 gt i6 139 i 3 The feedback circuit is shunt because the output transistor M2 has one of its possible output terminals on ac ground Also if RL R4 goes to zero ifb O 4 Draw the closed loop circuit 111 and small signal model 5 in 4 Fig 260710 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 260 7 Shunt7Shunt Feedback 3502 Page 260710 Example 2 Continued 5 AC open loop model is drawn by a Looking back into the feedback network Q3R1 to the left with v1 O b Looking back into the feedback network Q3R1 to the right with v2 O The result is i139i ibl Sim izv A A A v v v rnl ltgt ib339lgtrn3 ltgt gt ltgt V1 R ltgt R V V v 39v 39 2lt 3 gs2 ltgt 2 0 gt Y ltgt gt gm2Vgs2 lfb39T gt R1 R4 y gt 51123 39 T Fig 260711 6 Next find a and f Vai Vai VgsZV a vgsz i139 quotgm2R4 rn 31 3R1 153133 45542X106 9107MQ 22 L f vU lBl rn3lt1 3R1 r l a slB3 r fr 31 3R1098mslt1R1 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 390 7 Open7Loop Comparators 4802 LECTURE 390 OPENLOOP COMPARATORS READING AH 461475 Objective The objective of this presentation is 1 Show other types of continuous time open loop comparators 2 Improve the performance of continuous time open loop comparators Outline Push pull comparators Comparators that can drive large capacitors Autozeroing techniques Comparators using hysteresis Summary ECE 6412 7 Analog Integrated Circuit Design 7 II Page 39071 PE Allen 7 2002 Lecture 390 7 Open7Loop Comparators 4802 PushPull Comparators Clamped Vss Fig 831 Comments Gain reduced gt Larger input resolution Push pull output gt Higher slew rates ECE 6412 7 Analog Integrated Circuit Design 7 II Page 39072 PE Allen 7 2002 Lecture 390 7 Open7Loop Comparators 4802 Page 39073 C11 M6 M7 M12 M11 T in PushPull Comparators Improved Cascode output stage VSS Fig 83 2 Comments Can also use the folded cascode architecture Cascode output stage result in a slow linear response dominant pole is small Poorer noise performance ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 390 7 Open7Loop Comparators 4802 Page 39074 Comparators that Can Drive Large Capacitive Loads o Vaut ICU M9 M11 Fig 833 Comments Slew rate 3Vus into SOpF Linear risefall time 100ns into SOpF Propagation delay time z lus Loop gain z 32000 VV ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 390 7 OpeneLoop Comparators 4802 Page 39075 SelfBiased Differential AmplifierT VDD VDD VBias o I M6 Extremely large sourcing M3 M4 current M3 M4 Vin39 3V1 M1 M2 M1 M2 VBiasH M5 V VSS SS F1g834 Advantage Large sink or source current with out a large quiescent current Disadvantage Poor common mode range Vin slower than vin39 M Bazes quotTwo Novel Full Complementary SelfeBiased CMOS Differential Ampli ers IEEE Journal of SolidState Circuits Vol 26 No 2 Feb 1991 pp 165168 ECE 6412 7 Analog Integrated Circuit Design 7 II PE Allen 7 2002 Lecture 390 7 OpeneLoop Comparators 4802 Page 39076 Autozeroing Techniques Use the comparator as an op amp to sample the dc input offset voltage and cancel the offset during operation k Ideal k Ideal k Ideal Com arator Com arator Com arator VIN Model of Comparator Autozero Cycle Comparison Cycle Fig 841 Comments The comparator must be stable in the unity gain mode self compensating comparators are good the two stage op comparator would require compensation to be switched in during the autozero cycle Complete offset cancellation is limited by charge injection ECE 6412 7 Analog Integrated Circuit Design 7 II PE Allen 7 2002 Lecture 390 7 Open7Loop Comparators 4802 Page 39077 Differential 39 inn of Aut07er0ed omnaratorq T V05 Comparator during 11 phase VIN39 V0111quot VIN r r T V05 V05 D1fferent1al Autozeroed Comparator Comparator during 42 phase Fig 842 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 390 7 Open7Loop Comparators 4802 Page 39078 Sin leEnded Autozeroed Com arators Noninverting 462 C m V 39 p1 AZ OUT VIN lttgt2 lttgt1 J Fig 843 Inverting C VIN AZ VOU T lttgt2 lttgt1 ltIgt1 J T T Fig 844 Comment on autozeroing Need to be careful about noise that gets sampled onto the autozeroing capacitor and is present on the comparison phase of the process ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 390 7 Open7Loop Comparators 4802 Page 39079 In uence of Input Noise on the Comparator Comparator without hysteresis Comparator Vm threshold t Vom V0H t 1 VOL Fig 846A Comparator with hysteresis V0H VOL Fig 846B ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 390 7 Open7Loop Comparators 4802 Page 390710 Use of Hysteresis for Comparators in a Noisy Environment Transfer curve of a comparator with hysteresis v0 1T VOUT n V0H T V0H 4 4 A 4 gt L 4 4 4 A r I r r t 39 T R quot VTRP 7175V0HV0L7 quot Vmp M A p L W J IN 0 V 7le VIRP V n VIRP39 A V OL v lt K A 4 W0 I V V V 4 4 4 I Counterclockwise Bistable Clockwise Bistable Fig 845 Hysteresis is achieved by the use of positive feedback Externally Internally ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 390 7 OpeneLoop Comparators 4802 Page 39071 1 Noninverting Comparator using External Positive Feedback Circuit VOUT V 1 0H R2 R I gt 1 R1 F VOHVOL RIVOH VIN VOUT R2 0 b i 13 RIVOLv 0 T R2 Fig 847 S WOL Upper Trip Pornt Assume that valT VOL the upper trip point occurs when L L i i 1 O R1R2 VOL R1R2 VTRP VTRP 39 R2 VOL Lower Trip Point Assume that VOUT VOH the lower trip point occurs when 0 R1 V R2 V V 1 V R1R2 OH R1R2 TRP TRP 39 R2 OH Width of the bistable characteristic R1 AVm VTRP39VTRP R2 VOH 39VOL ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 390 7 OpeneLoop Comparators 4802 Page 390712 Inverting Comparator using External Positive Feedback Circuit VOUT V T 0H VIN VOUT A I 39 7 R12V0HV0L lt7 A 0 v 0 v 1 V R R2 R1V0L A R1VOH 1 R1R2 V0L R1R2 2 Fig 848 Upper Trip Point R1 VIN VTRP R1R2 VOH Lower Trip Point R1 VIN VTRP39 R1R2 VOL Width of the bistable characteristic R1 AVm VTRP39VTRP R1R2 VOH 39VOL ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 390 7 Open7Loop Comparators 4802 Horizontal Shifting of the CCW Bistable Characteristic Circuit Page 390713 V0 T R1 lt7ITZV0HV0L7gt A A A 4 R2 V0H A gt V R R VIN R1 1 REF VOUT 0 2 1 n 0quot 7 R1IV0LI 7 VREF 7 R1V0H 7 R2 A 39 R V v 3 L L Fig 84 9 0L 39 39 Upper Trip Point VREF R1R2 VOL R1R2 VTRP VTRP R2 Lower Trip Point VREF R1R2 VOH R1R2 VTRP39 VTRP39 R2 Shifting Factor R1R2 R2 VREF ECE 6412 7 Analog Integrated Circuit Design 7 11 1 VREF 39 R2 VOL 1 VREF 39 R2 VOH PE Allen 7 2002 Lecture 390 7 Open7Loop Comparators 4802 Horizontal Shifting of the CW Bistable Characteristic Circuit VIN VOAT R1 V V VOUT V0H39 R152 0 0E quot V V a T R1 v R1 R2 0 A R1R2LREF x 0 v V 1 R1V0H 7 VREF IfRRillng39 RHRZ VOL 41 2 A vgt 39 Fig8410 Upper Trip Point R1 R1 VIN VTRP R1R2 VOH R1R2 VREF Lower Trip Point 1 R1 VIN VTRP39 R1R2 VOL R1R2 VREF Shifting Factor R1 R1R2 VREF ECE 6412 7 Analog Integrated Circuit Design 7 11 Page 390714 PE Allen 7 2002 Lecture 390 7 Open7Loop Comparators 4802 Page 390715 Example 841 Design of an Inverting Comparator with Hysteresis Use the inverting bistable to design a high gain open loop comparator having an upper trip point of 1V and a lower trip point of 0V if V011 2V and VOL 72V Solution Putting the values of this example into the above relationships gives R1 R1 1 R1R2 2 R1R2 VREF and R1 R1 0 R1R2 R1R2 VREF Solving these two equations gives 3R1 R2 and VREF 2V ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 390 7 Open7Loop Comparators 4802 Page 390716 H steresis usin Internal Positive Feedback Simple comparator with internal positive feedback VDD M8 Fig 8411 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 390 7 OpeneLoop Comparators 4802 Page 390717 Internal Positive Feedback Upper Trip Point Assume that the gate of M1 is on ground and the input to M2 is much smaller than zero The resulting circuit is M1 on M2 off gt M3 and M6 on M4 and M7 off v02 is high W6L6 M6 would like to source the current 16 m11 As Vin begins to increase towards the trip point the current ow through M2 increases When i2 i6 the upper trip point will occur W6L6 W3L3l3 13 W6L6 i5 l W3L3 gt l113 1 W6L6W3L3 39 i5 i1i2 i3i6 i3 Also i2 i5 i1 i5 i3 Knowing i1 and i2 allows the calculation of vGSl and VGS2 which gives a a VTRP vosz VGSl 32 V12 51 VTl ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 390 7 OpeneLoop Comparators 4802 Page 390718 Internal Positive Feedback Lower Tri Point Assume that the gate of M1 is on ground and the input to M2 is much greater than zero The resulting circuit is M2 on Ml off gt M4 and M7 on M3 and M6 off v01 is high W7L7 M7 would like to source the current i7 m i2 As Vin begins to decrease towards the trip point the current ow through Ml increases When i1 i7 the lower trip point will occur VSS Fig 8471213 W7L7 W7L7 l5 1112 z7z4 14 14 14 1m is 6 i2 i4 1 W7L7W4L4 Also i1 i5 i2 i5 i4 Knowing i1 and i2 allows the calculation of vGSl and VGS2 which gives 2i2 2i1 VTRP39 vosz VGSl 5 V12 VTl ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 390 7 Open7Loop Comparators 4802 Page 390719 Exam le 842 Calculation of Tri Volta es for a Com arator with H steresis Consider the circuit shown Using the transistor device parameters given in Table 31 2 calculate the positive and negative C threshold points if the device lengths are all 1 13 um and the widths are given as W1 W2 W6 W7 10 um and W3 W4 2 pm The gate of M1 is tied to ground and the input is the gate of M2 The current 15 20 MA Solution To calculate the positive trip point assume that the input has been negative and is VSS Flg 84 heading positive WL6 is 20 MA l6 WL3 13 5003 gt 13 1 WL6WL3 11 1 5 333 MA 211 12 2333 12 12 15 11 20 333 1667 MA gt VGSl VT1 07 081V 212 12 21667 12 VGSZ V72 5110 07 0946V VTRP s VGS2 VGSl 0946 0810 0136V ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 390 7 Open7Loop Comparators 4802 Page 390720 Example 842 Continued Determining the negative trip point similar analysis yields i4 333 MA i1 1667 MA VGSZ 081V VGSl 0946V VTRP s VGSZ VG51 081 0946 O136V PSPICE simulation results of this circuit are shown below 26 24 22 2 V02 volts 39 16 14 12 1 705 704 703 702 701 00 01 02 03 04 05 Vin volts Fig 8413 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 390 7 Open7Loop Comparatols 4802 Page 390721 Com lete Com arator with Internal H steresis VDD M2 Vi 1 Viz O I Ml I O Vom M10 M1 1 VSS Fig 84 14 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 390 7 Open7Loop Comparatols 4802 Page 390722 Schmitt Trigger The Schmitt trigger is a circuit that has better defined switching points Consider the following circuit How does this circuit work Assume the input voltage Vin is low and the output voltage v0 is high M3 M4 and M5 are on and M1 M2 and M6 are off When Vin is increased from zero M2 starts to turn on causing out M3 to start turning off Positive feedback causes M2 to turn on further and eventually both M1 and M2 are on and the output is at zero g g The upper switching point VTRP is found as follows When Vin is low the voltage at the source of M2 M3 is Vsz VDDVIM VTRP Vin when M2 turns on given as VTRP VTNZ 1252 T Fig 84715 VTRP occurs when the input voltage causes the currents in M3 and M1 to be equal ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 310 7 High SpeedFrequency Op Amps 32304 Page 31071 LECTURE 310 HIGH SPEEDFREQUENCY 0P AMPS READING AH 368384 Objective The objective of this presentation is 1 Explore op amps having high frequency response andor high slew rate 2 Give examples Outline Extending the GB of conventional op amps Switched op amps Current feedback op amps Programmable gain amplifiers Parallel path op amps Summary ECE 6412 7 Analog Integrated Circuit Design 7 II PE Allen 7 2002 Lecture 310 7 High SpeedFrequency Op Amps 32304 Page 31072 What is the In uence of GB 0n the Fre uenc Res onse The op amp is primarily designed to be used with negative feedback When the product of the op amp gain and feedback gain loss is not greater than unity negative feedback does not work satisfactorily Example of a gain of 10 voltage amplifier Magnitude A IA 0 IdB 39 WK Op amp frequency response t 7Amplifier with a gain of lO 2ch 0D l 10g10w A w393dB GK Fig 721 What causes the GB We know that 8m 63 where gm is the transconductance that converts the input voltage to current and C is the capacitor that causes the dominant pole This relationship assumes that all higher order poles are greater than GB ECE 6412 7 Analog Integrated Circuit Design 7 II PE Allen 7 2002 Lecture 310 7 High SpeedFrequency Op Amps 32304 Page 31073 What is the Limit of GB The following illustrates what M d happens when the next higher pole is agililm e not greater than GB Avd0 dB quotquot x 0 p amp frequency response t y Amplifier with a gain of 10 2033 gt 7 40dBdec Next higher pole i 1 X For a two stage op amp the poles 053 m i x x gt 10g1000 and zeros are DA w393dBGB Fig 722 1 D 1 omrnant po e p1 AVOCC 2 O 1 M utput po e p2 CL 3 M 1 gm3 1rror po e p3 Cgs3CgS4 l 4 Nullrng pole p4 RZCI l 5 Nullrng zero Z1 RZCCCCgm6 ECE 6412 7 Analog Integrated Circuit Design 7 II PE Allen 7 2002 Lecture 310 7 High SpeedFrequency Op Amps 32304 Page 31074 A Procedure to Increase the GB of a TwoStage Op Amp 1 Use the nulling zero to cancel the closest pole beyond the dominant pole 2 The maximum GB would be equal to the magnitude of the second closest pole beyond the dominant pole 3 Adjust the dominant pole so that GB z 22xsecond closest pole beyond the dominant pole Illustration which assumes that p2 is the next closest pole beyond the dominant pole joo V n p T I o A V U quotP3 quot174 quot72 Z1 quot71 quotI71 I New Old Magnitude IAVd0 dB W W 1 Before cancelling 40dBdec 7p2 by z1 and 6 60dBdec 39 Increasmg 71 mg 723 80dBdec ECE 6412 7 Analog Integrated Circuit Design 7 II PE Allen 7 2002 Lecture 310 7 High SpeedFrequency Op Amps 32304 Page 31075 Example 721 Increasing the GB of the Op Amp Designed in Ex 631 Use the two stage op amp designed VDD25V in Example 63 1 and apply the above approach to increase the gainbandwidth as much as possible Solution 1 First find the values of p2 p3 and p4 i 95 l I 10pF a From Ex 63 2 we see that T p2 9425x106 radssec b p3 was found in Ex 63 1 as p3 28lx109 radssec c To find p4 we must find C I which is the output capacitance of the first stage of the op amp C1 consists of the following capacitors CF de2 de4 Cgs6 ngz ng4 For de2 the width is 3pm gt L1L2L3 3m gt ASAD9um2 and PSPD 12um For de4 the width is 15m gt L1L2L3 3m gt ASAD45um2 and PSPD 36pm From Table 32 1 de2 9um2770xlO6Fm2 12umX38OxlO12Fm 693fF456fF 115fF de4 45um2560x106Fm2 36pm350x1012Fm 252fF126F z 378fF ECE 6412 7 Analog Integrated Circuit Design 7 II PE Allen 7 2002 Fig 7273A v55 25v Lecture 310 7 High SpeedFrequency Op Amps 32304 Page 31076 Example 721 Continued C856 is given by Eq 10b of Sec 32 and is C 856 CGD0W6O67CUXW6L6220x101294x106O67247x10494xlO12 207fF 1548fF 1755fF ngz 220x1012x3um 066fF and ng4 220x1012x15um 33fF Therefore C1 115fF 378fF 1755fF 066fF 33fF 2288fF Although dez and de4 will be reduced with a reverse bias let us use these values to provide a margin In fact we probably ought to double the whole capacitance to make sure that other layout parasitics are included Thus let C1 be 300fF In Ex 63 2 RZ was 459le which gives p4 0726x109 radssec 2 Using the nulling zero zl to cancel p2 gives p4 as the next smallest pole For 600 phase margin GB p422 if the next smallest pole is more than 10GB GB 0726xlO922 033Ox109 radssec or 525MHZ This value of GB is designed from the relationship that GB gmllCC Assuming gml is constant then Cc gm1GB 9425xlO6O33Ox109 286fF It might be useful to increase gml in order to keep Cc above the surrounding parasitic capacitors ng6 207fF The success of this method assumes that there are no other roots with a magnitude smaller than 10GB ECE 6412 7 Analog Integrated Circuit Design 7 II PE Allen 7 2002 Lecture 310 7 High SpeedFrequency Op Amps 32304 Page 31077 Exam le 722 Increasin the GB of the Folded Cascode 0 Am of EX 653 Use the folded cascode op amp designed in Example 65 3 and apply the above approach to increase the gainbandwidth as much as possible Assume that the drainsource areas are equal to 2pm times the width of the transistor and that all voltage dependent capacitors are at zero voltage Solution The poles of the folded cascode op amp are 1 pA z m the pole at the source of M6 1 173 z m the pole at the source of M7 1 p6 z m the pole at the drain of M6 gm8 gm9 p8 z C 8 the pole at the source of M8 p9 quotC9 the p016 at the source 0f M9 8 10 and p10 z Ci the pole at the gates of M10 and M11 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 310 7 High SpeedFrequency Op Amps 32304 Page 31078 Example 722 Continued Let us evaluate each of these poles 1 For pA the resistance RA is approximately equal to gm6 and CA is given as CA Cgso der ngr de4 Cbso ng4 From Ex 65 3 gm6 7446uS and capacitors giving C A are found using the parameters of Table 32 1 as C856 220x10128Ox106 O678OxlO6106247xlO4 l49fF del 770x106359x1062xlO6 38OxlO122379x106 84fF ng1 220x1012359x106 8fF de4 Cm 560x1068OxlO62x106 350x1012282x106 l47fF and ng4 220x10128OxlO6 176fF Therefore CA l49fF 84fF 8fF l47fF 176fF l47fF 0553pF Thus 7446x106 pA m l346x109 radssec 2 For the pole p3 the capacitance connected to this node is CE ngz dez Cgs7 ngs des Cbs7 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 310 7 High SpeedFrequency Op Amps 32304 Page 31079 Example 722 Continued The various capacitors above are found as ngz 220x1012359x106 8fF dez 770x106359x1062XlO6 380x10122379x106 84fF Cgs7 220x10128Ox106 O678OxlO6106247xlO4 149fF ng5 220x10128Ox106 176fF and de5 Cm 560x1068OxlO62x106 350xlO12282x106 147fF The value of C B is the same as CA and gm is assumed to be the same as gm7 giving p B pA l346x109 radssec 3 For the pole p6 the capacitance connected to this node is C6 de6 ng6 CgsS Cgs9 The various capacitors above are found as CM 560x1068OxlO62xlO6 350xlO12282x106 147fF Cgsg 220x1012364x106 O67364xlO6106247x104 679fF and Cgs9 Cgs8 679fF ng6 ngs 176fF Therefore C6 147fF 176fF 679fF 679fF 0300pF ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 310 7 High SpeedFrequency Op Amps 32304 Page 310710 Example 722 Continued From Ex 65 3 R2 2kg and gm6 7446x10396 Therefore p6 can be expressed as 1 1 6 2x103 1067446O300x1012 0966X109 mdSSec39 4 Next we consider the pole pg The capacitance connected to this node is C8 de10 ng10 CgsS CbsS These capacitors are given as Cbsg de10 77Ox106364xlO62x106 380x10122384x106 852fF Cgsg 220x1012364xlO6 O67364x106lO6247xlO4 679fF and ngm 220xlO12364x106 8fF The capacitance Cg is equal to Cg 679fF 8fF 852fF 852fF 0246pF Using the gmg of Ex 65 3 of 7746uS the pole pg is found as pg 3149X109 radssec 5 The capacitance for the pole at p9 is identical with Cg Therefore since gmg is also 7746uS the pole p9 is equal to pg and found to be p9 3149x109 radssec 6 Finally the capacitance associated with p10 is given as C10 Cgle Cgsll de8 These capacitors are given as ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 310 7 High SpeedFrequency Op Amps 32304 Page 310711 Example 722 Continued Cgslo Cgm 220x1012364x106 O67364x106106247x104 679fF and deg 770x106364x1062x106 380x10122384x106 852fF Therefore C10 679fF 679fF 852fF 0221pF which gives the pole p10 as 7446x1O6O246x1012 3505x109 radssec The poles are summarized below pA 1346x109 radssec p3 1346x109 radssec p6 O966x109 radssec pg 3149x109 radssec p9 3149x109 radssec p10 3505x109 radssec The smallest of these poles is p6 Since pA and p are not much larger than p6 we will find the new GB by dividing p6 by 5 rather than 22 to get 200x106 radssec Thus the new GB will be ZOO27 or 32MHZ The magnitude of the dominant pole is given as GB 200x106 pdominant Avdm 774 64 26795 radssec The value of load capacitor that will give this pole is 1 1 CL Pdominant Rout 26795x103194M 2 1991 Therefore the new GB 32MHZ compared with the old GB IOMHZ ECE 6412 7 Analog Integrated Circuit Design 7 II PE Allen 7 2002 Lecture 310 7 High SpeedFrequency Op Amps 32304 Page 310712 Conclusion for Increasing the GB of Op Amps Maximum GB depends on the input transconductance and the capacitance that causes the dominant pole Quantity MOSFET Op BJT Op Amp Amp gm dependence W Ic Ic 2K TID kTq W Maximum gm z 1 mAV z 20 mAV GB for lOpF 15 MHz 300 MHz GB for lpF 150 MHZ 3 GHZ Note that the power dissipation will be large for large GB because current is needed for large gm Assumption All higher order roots are above GB The larger GB the more difficult this becomes Conclusion The best CMOS 0p amps have a GB of lO SOMHZ The best BJT 0p amps have a GB of lOO ZOOMHZ ECE 6412 7 Analog Integrated Circuit Design 7 II PE Allen 7 2002 Lecture 310 7 High SpeedFrequency Op Amps 32304 Page 310713 Switched Amplifiers Switched amplifiers are time varying circuits that yield circuits with smaller parasitic capacitors and therefore higher frequency response Such circuits are called dynamically biased Switched amplifiers require a nonoverlapping clock Switched ampli ers only work during a portion of a clock period Bias conditions are setup on one clock phase and then maintained by capacitance on the active phase Switched amplifiers use switches and capacitors resulting in feedthrough problems Simplified circuits on the active phase minimize the parasitics Typical clock 1 l l i l i Z 39T 2 A l i l i Z T o 05 1 15 2 Fig 7MB ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 310 7 High SpeedFrequency Op Amps 32304 Page 310714 D namicall Biased Invertin Am lifier VDD CB M2 1 in ID i Voat Vin 4 2 C s o M1 11 Fig72 4 J VSS During phase 1 the offset and bias of the inverter is sampled and applied to C05 and C 3 During phase 2 COS is connected in series with the input and provides offset canceling plus bias for M1 C B provides the bias for M2 This circuit illustrates the concept of switched amplifiers but is too simple to illustrate the reduction of bias parasitics ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 310 7 High SpeedFrequency Op Amps 32304 Page 310715 D namicall Biased PushPull CascodeO Am fVDD M4 39 39 M3 C1 1 Vin Vout o Push pull cascode amplifier Ml M2 and M3 M4 Bias circuitry M5 M6 C2 and M7 M8 C1 Parasitics can be further reduced by using a double poly process to eliminate bulk drain and bulk source capacitances at the drain of Ml source of M2 and drain of M4 source of M3 see Fig 65 5 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 310 7 High SpeedFrequency Op Amps 32304 Page 310716 D namicall Biased PushPull CascodeO Am Continued Operation VDD VDD VDDVBZVin39Vin39 M7 VDDVBzVm VDDVBZVin V v t 13 in m W Vin39VSS39 V31 Vin39VSS39 V31 M6 VSS V31 VmVm39 39 V55 V55 Equivalent circuit during the 11 clock period Equivalent circuit during the 12 clock period Fig 72 6 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 310 7 High SpeedFrequency Op Amps 32304 Page 310717 D namicall Biased PushPull Cascode 0 Am Continued This circuit will operate on both clock phasesT TVDD Performance 15pm CMOS 12 ltlgt1 16mW dissipation V32 GB z 130MHz CL 22pF M8 M M4 Tquot Settling time of lOns CLlOpF A I I p M7 I 1C2l C42 I M3 13 14 M6 CF IC3 4 M2 This amplifier was used with a I 12 11 39 286MHZ clock to realize a 5th order switched capacitor filter M5 4 1 4 91 1 1 having a cutoff frequency of V31 35MHZ JVSS Fig 72 7 1 S Masuda et al CMOS Sampled Differential PushrPull Cascode Op Amp Proc If984 International Symposium on Circuits and Systems Montreal Canada May 1984 pp 1211712714 ECE 6412 7 Analog Integrated Circuit Design 7 II PE Allen 7 2002 Lecture 310 7 High SpeedFrequency Op Amps 32304 Page 310718 Current Feedback Op Amps Why current feedback Higher GB Less voltage swing gt more dynamic range What is a current ampli er Ril CLu rent Ampli er Fig 72 8A Requirements i0 Aii1i2 Ril R12 09 R 0 00 Ideal source and load requirements Rsource 0 RLoad 09 ECE 6412 7 Analog Integrated Circuit Design 7 II PE Allen 7 2002 Lecture 310 7 High SpeedFrequency Op Amps 32304 Page 310719 Bandwidth Advanta e of a Current Feedback Am li er Consider the inverting voltage ampli er shown using a current amplifier with g negative current feedback The output current i0 of the current W gt V ampli er can be written as i0 Ai5i139i2 7415th i0 Voltage The closed loop current gain i0im can be Fig 729 T Amplifier Buffer found as io AiS ii 1AiS However v0 ioRz and vm ile Solving for the voltage gain VowVin gives Voat ioRZ RZ Ais Vin 1139an R1 1415 40 IfAis S then wA Voat RZ A0 WA1A0 RZAO vm Rf 1A0 s wAlA0 gt M0 R 11A0 and mm wA1Ao ECE 6412 7 Analog Integrated Circuit Design 7 II PE Allen 7 2002 Lecture 310 7 High SpeedFrequency Op Amps 32304 Page 310720 Bandwidth Advantage of a Current Feedback Amplifier Continued The unity gainbandwidth is RZAO R2 R2 GB IAVO w3dB m wAlA0 R1A0wA E GB where GB is the unity gainbandwidth of the current amplifier Note that if GBi is constant then increasing R2R1 the voltage gain increases GB Illustration 7 1 R726 A0 n KVoltage Amplifier gt K R1 1A0 voltage Amplifier Kgt1 KC AO dB 0 Current Amplifier A0 dB I E 1Aom OdB 39 quot 1 m 00A GB GB 1GBQ 5 10 Fig 7240 Note that GBZ gt GB1 gt GBi The above illustration assumes that the GB of the voltage amplifier realizing the voltage buffer is greater than the GB achieved from the above method ECE 6412 7 Analog Integrated Circuit Design 7 II PE Allen 7 2002 Lecture 310 7 High SpeedFrequency Op Amps 32304 Page 310721 A Sim le Current Mirror Im lementation of a Hi h Fre uenc Am lifier Since the gain of the current amplifier does not need to be large consider a unity gain current mirror implementation M3 Vtmt 131115 M M2 Mj t i t M9 i V55 Fig 72711 An inverting ampli er with a gain of 10 is achieved if R2 20R1 assuming the gain of the current mirror is unity What is the GB of this amplifier RZAO 1 A0 1 G3 WWWMB R 1lt1A0 39 m lt1A0R1C0 2R1C0 where C0 is the capacitance seen at the output of the current mirror If R1 10kg and C0 250fF then GB 3183MHZ Limitations R2 R1gtRm 1gm1 and R2 lt rdszllrdm gt R 1 ltlt gm1rds2rds6 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 310 7 High SpeedFrequency Op Amps 32304 Page 310722 A WideSwin Cascode Current Mirror Im lementation of a Hi h Fre uenc Amplifier The current mirror shown below increases the value of R2 by increasing the output resistance of the current mirror M12 Von Bias M3 I M15 39 M1 39 Mll Fig 7212 New limitations 1 R2 R1 gt gml and R2 lt gm4rds4rds2gm6rds6rds8 gt R l ltlt gm1gm4rds4rdszlgm6rds6rds8 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 310 7 High SpeedFrequency Op Amps 32304 Page 310723 Example 723 Design of a High GB Voltage Amplifier using Current Feedback Design the wide swing cascode voltage ampli er to achieve a gain of 10VV and a GB of 500MHz which corresponds to a 3dB frequency of 50MHZ Solution Since we know what the gain is to be let us begin by assuming that Co will be 100fF Thus to get a GB of 500MHz R1 must be 32kg and R2 32kg Therefore 1gm1 must be less than 32009 say 3009 Therefore we can write 1 W W gml 2KI WL m gt 556x106 K I T gt 00505 IT At this point we have a problem because if WL is small to minimize C0 the current will be too high If we select WL 200um1um we will get a current of 025mA However using this WL for M4 and M6 will give a value of C0 that is greater than 100fF Therefore select WL 200 for M1 M3 M5 and M7 and WL 20pm1um for M2 M4 M6 and M8 which gives a current in these transistors of 25uA Since R2R1 is multiplied by 111 let R be 110 times R1 or 352k9 Now select a WL for M12 of 20pm1pm which will now permit us to calculate Co We will assume zero bias on all voltage dependent capacitors Furthermore we will assume the diffusion area as 2pm times the W C0 can be written as C0 gd4 de4 ng6 de6 Cgs12 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 310 7 High SpeedFrequency Op Amps 32304 Page 310724 Example 723 Design of a High GB Voltage Ampli er using Current Feedback Cont The information required to calculate these capacitors is found from Table 32 1 The various capacitors are ng4 ng6 CGDOx10pm 220x101220x106 44fF de4 CJxAD4CJSWxPD4 770x10620x1012380x101244x106 154fF167fF 321fF CM 560x10620x1012350x101244x106 266fF Cgm 220x101220x106 06720x106106247x104 373fF Therefore C0 44fF321fF44fF266fF373fF 105fF Note that if we had not reduced the WL of M2 M4 M6 and M8 that Co would have easily exceeded 100fF Since 105fF is close to our original guess of 100fF let us keep the values of R1 and R2 If this value was signi cantly different then we would adjust the values of R1 and R2 so that the GB is 500MHz One must also check to make sure that the input pole is greater than 500MHz The design is completed by assuming that Blas 100pA and that the current in M9 through M12 be 100uA Thus W13L13 W14L14 20pm1um and W9L9 through W12L12 are 20um1pm ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 310 7 High SpeedFrequency Op Amps 32304 Page 310725 Example 723 Continued 30 20 Ivomlvinl dB L H O O O ti o L39u o 105 106 107 108 109 1010 Frequency Hz Fig 72713 Simulation Results f3dB z 38MHZ GB z 300MHz Closed loop gain 18dB Loss of 72dB is attributed to source follower and R1 Note second pole at about 1GHZ To get these results it was necessary to bias the input at 717VDC using i3V power supplies If R1 is decreased to 1kg results in Gain of 264dB f3dB 32MHz and GB 630MHz ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 310 7 High SpeedFrequency Op Amps 32304 Page 310726 A 71 MHz Pro rammable Gain Am lifier usin a Current Am li er The following circuit has been submitted for fabrication in 025 pm CMOS VDD o o o o o o Iquot Vlg I M R2 R M2 i gl E o V014 o Q X4 x2 x1 VSS x1 x2 x 18 14 12 12 14 18 Fig 727135A R1 and the current mirrors are used for gain variation R2 is xed Can cascade this amplifier for higher gains BW BWl xZln l for n 2 BW 064 BWl ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lec MSIOrIhg SpinEmmy OpAmps 3mm pigmazv 1 3quotquot 39 flflMHv HR arrama HR typ a mulmv a wands Hana Mien Dram IT 5056412 rAmJaglmzynm Omu Dtsxyr Lec MSIOrIhg SpinEmmy OpAmps 3mm mum Smmlammkm js Output voltage swing is 126V fox 3 25V poWeI supply oltage gain is 0 to 60dB in MB steps gain snot 017dB 5056412 rAmJaglmzynm Omu Dtsxyr p E Axuan m Lecture 310 7 High SpeedFrequency Op Amps 32304 Page 31072 A 71 MHz CMOS Programmable Gain AmplifierT Uses 3 ac coupled stages First stage O 20dB common source for matching and NF Fig 727137A Rm 3309 to match source driving requirement All current sinks are identical for the differential switches Dominant pole at 150MHz P Orsatti F Piazza and Q Huang A 71 MHz CMOS IFABasdband Strip for GSM IEEE J SolidState Circuits Vol 35 No 1an 2000 pp 104108 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 310 7 High SpeedFrequency Op Amps 32304 Page 31073 A 71 MHz PGA Continued Second stage 10dB to 20dB M6 vim Vam Fig 727137A Dominant pole is also at 150MHz For VDD 25V at 60dB gain the total current is 26mA IIP3 z 1dBm ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 310 7 High SpeedFrequency Op Amps 32304 Page 31074 Parallel PathO Am s This type of op amp combines a high gain low frequency path with a low gain high frequency path dB A IAvdl0dB lAvd1S s mvd2lt0IgtdB mvdzltsgtl 1 A i p3 06 p1 1321 GB Fig 7214 1057100 Comments Op amp will be conditionally stable Compensation will be challenging ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 310 7 High SpeedFrequency Op Amps 32304 Page 31075 Multi ath Nested iller Com ensationT Fig 7215 Comments All Miller capacitances must be around inverting stages Ensure that the RHP zeros generated by the Miller compensation are canceled Avoid pole zero doublets which can introduce a slow time constant 1 RGH Eschauzier and JHHuijsing Frequency Compensation Techniques for LowPower Operational Amplifiers Kluwer Academic publishers 1995 Chapter 6 ECE 6412 7 Analog Integrated Circuit Design 7 ll PE Allen 7 2002 Lecture 310 7 High SpeedFrequency Op Amps 32304 Page 31076 Illustration of H brid Nested Miller Com ensationT Note that this example is not multipath Compensating Results 1 le pushes p4 to higher frequencies and p3 down to lower frequencies 2 sz pushes p2 to higher frequencies and p1 down to lower Fig 72 16 frequencies 3 Cm3 pushes p3 to higher frequencies feedback path amp pulls p1 further to lower frequencies Equations GB gml C m3 P2 gm2Cm3 P3 gm3 Cm3 leCm2 P4 gm4 CL Design GB lt P27 P3 P4 39 RG H Eschauzier 82 Ill A Programmable 15V CMOS ClassrAB Operational Amplifier with Hybrid Nested Miller Compensation for 120dB Gain and 6MHZ UGTquot IEEE 527sz State Cnmzs vol 29 No 12 pp 149771504 Dec 1994 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 310 7 High SpeedFrequency Op Amps 32304 Page 31077 Illustration of the Hybrid Nested Miller Compensation Technique A joo P4 P3 P2 P1 r r t O l I I39 le Ill 1 Jm 139 4 P3 P2 P1 I t 0 I ll C1112 I A I P4 P2 1 P3 tPl q t 0 II I I C1113 II Jm I J74 173339 P2 31171 n n t O Fig7217 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 040 7 CE and CS Output Stages 11104 Page 0401 LECTURE 040 COMMON SOURCE AND EMITTER OUTPUT STAGES READING GHLM 384398 AH 218221 Objective The objective of this presentation is Show how to design stages that 1 Provide suf cient output power in the form of voltage or current 2 Avoid signal distortion 3 Be ef cient 4 Provide protection from abnormal conditions short circuit over temperature etc Outline 0 Common source stage 0 Common emitter stage 0 Summary ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 040 7 CE and CS Output Stages 11104 Page 0402 COMMON SOURCE OUTPUT STAGE Current source load inverter 139 VM 3 VOUT RL VDD 3 RL dominates 5 as the load line 0 b D Q 1 VIN 39 1 F lt41QRL7gt lt41QRLiVED D V VOUT VSS 7777777777777 1 A Class A circuit has current ow in the MOSFETs during the entire period of a sinusoidal signal Characteristics of Class A ampli ers Unsymmetrical sinking and sourcing Linear Poor ef ciency v0U7peak2 v0U7peak2 Ef PRL ZRL ZRL VOU peakN2 Clency PSupply VDD VSS1Q VDD VSS J VDD VSS VDD 39VSST Maximum ef ciency occurs when VOU peak VDD VSS which gives 25 ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 040 7 CE and CS Output Stages 11 104 Page 0403 Specifying the Performance of a Common Source Ampli er Output resistance l l VOW gds1 gdsz MHLZVD Current 0 Maximum sinking current is K 1 W1 10117 VDD 39VSS VT12 1Q 0 Maximum sourcing current is K 2 W2 10UTWWDD VGGZ WM2 5 1Q Requirements NOW gt CL39SR V0 U peak IIOUTl gt RL The maximum current Will be determined by both the current required to provide the necessary slew rate C L and the current required to provide a voltage across the load resistor RL ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 040 7 CE and CS Output Stages 11104 Page 0404 SmallSignal Performance of the Class A Ampli er Although we have considered the smallsignal performance of the Class A ampli er as the current source load inverter let us include the in uence of the load The modi ed smallsignal model iiCl 5 E 2 Vin gmlvin r6151 rds2 RL C2 E oul a 0 Fig 040 02 The smallsignal voltage gain is M 39gml Vin gds1gds2GL The smallsignal frequency response includes A zero at gml Z ng1 and a pole at gds1gds2GL p ng1ng2de1de2CL ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 040 7 CE and CS Output Stages 11104 Page 0405 Example 551 Design of a Simple ClassA Output Stage Use the values ofKN 110uAV2 KP 50uAV2 Vm07V and VHF07V and design the WL ratios of M1 and M2 so that a voltage swing of 2 volts and a slew rate of 51 voltus is achieved if RL 20 kg and CL 1000 pF Assume that VDD VSS 3 volts and VGGz 0 volts Let the channel lengths be 2 um and assume that ngl 100fF Solution Let us rst consider the effects of RL and C L 12V iOU peak 20k9 iIOOuA and CLSR 109106 10000A Since the slew rate current gtgt the current for RL we can safely assume that all of the current supplied by the inverter is available to charge C L Using a value of 1 mA 210UrIQ 4000 m L1 KN ltVDDVss Vmgt2 Z 110lt53gt2 21m and W2 ZIOUT 2000 15m L7 Kp ltVDDVGG2 VTP2 Z 50lt23gt2 2pm The smallsignal performance of this ampli er is AV 821 VV includes RL 2019 ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 040 7 CE and CS Output Stages 11 104 Page 0406 Broadband Harmonic Distortion The linearity of an ampli er can be characterized by its in uence on a pure sinusoidal input signal Assume the input is anoo Vp sinoot The output of an ampli er with distortion will be V0ww a1 Vp sin wt a2 Vp sin Zwt an Vp sinnwt Harmonic distortion HD for the ith harmonic can be de ned as the ratio of the magnitude of the ith harmonic to the magnitude of the fundamental For example secondharmonic distortion would be given as 02 HDz 61 1 Total harmonic distortion THD is de ned as the square root of the ratio of the sum of all of the second and higher harmonics to the magnitude of the rst or fundamental harmonic Thus THD can be expressed as 2 2 2 a2 a3 an12 T HD f The distortion of the class A ampli er is good for small signals and becomes poor at maximum output swings because of the nonlinearity of the voltage transfer curve for largesignal swing ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 040 7 CE and CS Output Stages 11104 Page 0407 COMMON EMITTER OUTPUT STAGE Common Emitter Class A Output Stage VIN RL2 ltRL 1 VEE VCE1Sat Fig 040 03 Large signal characteristic V1 IOUTZIQ39ICL VOUTZZOUTRL and 1C1 1s16XpT V Igi ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 VOUT RL Isiexp Lecture 040 7 CE and CS Output Stages 11104 Page 0408 Harmonic Distortion in the Common Emitter Output Stage Assume the input signal is VIN VBE Viquot Substltutmg th1s 1n the express10n on the last sllde glves L VBEI VOUT RL Islexp VZ 1Q RL Islexp VI exp VI IQ IQ RL exp VI 1 Using the expansion of expx z 1 x x22 x36 gives Vii 1 22 1 23 2 3 VOUT 1QRL VZ 2 VZ 6 VZ quot39 a1vmazvm a3vm where Q RL I RL I RL ai VZ az 2VZ2 and a3 6V Suppose vint Vpsinwt then VOUTU a1 Vpsinwt a2 V192 sinzwt a3 V193 sin3 wt an 2 03V 3 aleS1nwl 2L1COS2DI 4L3sinwt sin3wt HD d HD Km quot 2 2 ale 2611 4VZ an 3 4 ale 4611 24 V For Vp 05V HD2 125 and HD3 z 1 ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 040 7 CE and CS Output Stages 11104 Page 0409 Small Signal Performance of the Common Emitter Output Stage iout Rout C r 01 73902 RL Vout 5 E Fig 04004 Let r01r02 70 then 30 VORL Voul 39gmlro RL lout 3070 rORL 39gmlRL and 1m rOlRL If V0mpeak 06V RL le and IQ 186mA then 1C 1 86 06 0 6 Avg gmlRL7RLT1000706VV 3 VpW 7j6 85mV peak Rinzrnl gmlaRoulzrolRL Rb vm 1 85 1 85 2 HD2 1 0082 and HD3 00045 Where does the distortion come from 8606 The ac gain at the negative peak output voltage is 26 1000 946VV 1860 The ac gain at the positive peak output voltage is 26 1000 485VV Note the emitter follower is much more linear because of the inherent negative feedback ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 060 7 Push7Pu1 Output Stages 1602 Page 06071 LECTURE 060 PUSHPULL OUTPUT STAGES READING GHLM 362384 AH 226229 Objective The objective of this presentation is Show how to design stages that 1 Provide sufficient output power in the form of voltage or current 2 Avoid signal distortion 3 Be efficient 4 Provide protection from abnormal conditions short circuit over temperature etc Outline Push Pull MOS Class B Push Pull BJT Class B Summary ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 060 7 Push7Pu1 Output Stages 1602 Page 06072 PUSHPULL MOS OUTPUT STAGES Class AB and B PushPull Source Follower Can both sink and source current and provide a slightly lower output resistance VDD RL Efficiency Depends on how the T transistors are biased V55 F g39 060701 Class B one transistor has current ow for only 1800 of the sinusoid half period VOUnpeak2 PRL ZRL nVOU peak Eff1c1ency m 1 ZVOU peak 2 VD D OVSS VDD VSSj T Maximum efficiency occurs when VOU peak VDD and is 785 Class AB each transistor has current ow for more than 1800 of the sinusoid Maximum efficiency is between 25 and 785 ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 060 7 PushePull Output Stages 1602 Page 06073 Illustration of Class B and Class AB PushPull Source Follower Output current and voltage characteristics of the push pull source follower RL 119 VGl 1mA 2 1 0 l 2 2 1 0 l 2 VmV VmV Class B pushpull source follower Class AB pushpullyspurce follower Fig 06002 Comments Note that VOUT cannot reach the extreme values of VDD and VSS 10U7max and IOUT IIIaX is always less than VDDRL or VSSRL For VOUT 0V there is quiescent current flowin g in M1 and M2 for Class AB Note that there is significant distortion at VIN OV for the Class B push pull follower ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 060 7 PushePull Output Stages 1602 Page 06074 SmallSi nal Performance of the PushPull Follower Model Vii1 C1 E vm rdsl 7112 RL C23 Vout gmlvgsl gmbslvbsl ngVgSZ gmszVbs E V531 U C1 5 Vin RL C2vom gmlv39m m1Vout gmbslvout rdsl ngVm m2V0ut gmbs2V0ut 70152 E Fig 060703 Vaut gml ng Vin gdslgds2gmlgmbslgm2gmbs2GL 1 R0 gdslgds2gmlgmbslgm2gmbs2 does not mCIUde RL If VDD VSS 25V Vow 0V ID1 DZ SOOHA and WL 20um2um A 0787 RLoo and Ram 4489 A zero and pole are located at gmlgm2 quotgdslgds2gm1gmbs1gm2gmbs2GL Z C1 p C1C2 These roots will be high frequency because the associated resistances are small ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 060 7 PushePull Output Stages 1602 Page 06075 PushPull Common Source Am lifiers Similar to the class A but can operate as class B providing higher efficiency Fig 06004 Comments The batteries VTR1 and VTR2 are necessary to control the bias current in M1 and M2 The efficiency is the same as the push pull source follower ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 060 7 PushePull Output Stages 1602 Page 0606 Practical Im lementation of the PushPull Common Source Am lifier V55 Fig 06005 Vggg and Vgg4 can be used to bias this amplifier in class AB or class B operation Note that the bias current in M6 and M8 is not dependent upon VDD or VSS assuming V003 and Vgg4 are not dependent on VDD and V55 ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 060 7 Push7Pull Output Stages 1602 Page 06077 Illustration of Class B and Class AB PushPull Inverting Ampli er Output current and voltage characteristics of the push pull inverting amplifier RL 119 72V 1V 0V 1V 2V 2V 1V 0V 1V 2V VIN VIN Class B pushpull inverting amplifier Class AB pushpull inverting amplifier Fig060706 Comments Note that there is significant distortion at VIN OV for the Class B inverter Note that VOUT cannot reach the extreme values of VDD and V55 10U7max and IOUTmaX is always less than VDDRL or VsisL For VOUT 0V there is quiescent current owing in M1 and M2 for Class AB ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 060 7 Push7Pull Output Stages 1602 Page 06078 Use of Ne ative Shunt Feedback to Reduce the Out ut Resistance Concept rdsillrdsz Rout 1L00p Gain Comments Can achieve output resistances as low as 109 If the error amplifiers are not balanced it is difficult to control the quiescent current in M1 and M2 Great linearity because of the strong feedback Can be efficient if operated in class B or class AB ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 060 7 Push7Pull Output Stages 1602 Page 06079 Simnle 39 inn of Ne2 Shunt Feedback to Reduce the Output Resistance R1 gm1gm2 LOOP gal R1R2 gds1gds2GL rdslllrdsz Rout 1 R1 gm1gm2 R1R2 gds1gds2GL LetR1 R2 RL 00 Bias SOOHA W1L1 lOOpmlum and W2L2 200umlum Thus gml 33161nS gmz 31621nS rdsl 50k and rdsz 40kg SOkQI40kQ 2222kQ Rout 33163162 1051439 3049 Rout 542 If RL 119 105W ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 060 7 Push7Pull Output Stages 1602 Page 060710 What about the use of BlTs in CMOS Technolo v Vom Vom Q1 quot394 M3 1 VSS T n well CMOS PWell CMOS Fig 06009 Comments Can use either substrate or lateral BJTs Small signal output resistance is llgm which can easily be less than 1009 Unfortunately only PNP or NPN BJTs are available but not both on a standard CMOS technology In order for the BJT to sink or source large currents the base current i3 must be large Providing large currents as the voltage gets to extreme values is dif cult for MOSFET circuits to accomplish If one considers the MOSFET driver the emitter can only pull to within VBEVON of the power supply rails This value can be 1V or more ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 060 7 Push7Pull Output Stages 1602 Page 060711 PUSHPULL BJT OUTPUT STAGES Class AB and B Simple Class B Output Stage V0 T Q1 Saturates M VCCVBEl Slope 1 Q1 on Q2 off VEEVBE2VCE1sat WIN e VCCVBE1VCE1Sat Slope 1 Q1 off Q2 Saturates Q2 on VEEVBE2 Fig 06010 Class B operation Two active devices are used to deliver the power instead of one Each device conducts for alternate half cycles Ef ciency can approach 785 Can suffer from crossover distortion the transition from one device to the other ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 060 7 Push7Pull Output Stages 1602 Page 060712 Class AB Output Stage V0 T M VCCVBE1 Q1 Saturates VC C VCC IQ 393 VIN Re VOUT VBE0n VIN VEEVEBZ Fig 06011 IQ sets up the bias current in Q1 and Q2 when there is no input signal Each transistor is biased so that there is a region in the middle where both are on Class ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 060 7 Push7Pul Output Stages 1602 Page 060713 Power Considerations in the Class B Output Stage Voltage and current waveforms for a Class B ampli er Vin Vout icl 06012 ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 060 7 Push7Pul Output Stages 1602 Page 060714 Efficiency Considerations of the ClassB PushPull Output Stage Load line for one device in a class B stage Load Line Vg RL Peak device 5 dissipation Constant Power Curve Quiescent Point Load Lme 5 5 0 0 VCC VCC ZVCOVCE1Sat 13360713 Ef ciency 1 VonPeak2 PL 2 RL 1T Icpeak 2 VCC and Psupply2VCCIsupply 2VCC T CUWI 2VC 7 RL VonPeak 0 PL 2 VonPeak E T Psupply 4 VCC gt nmax 4 786 7r VCC VCEsat Max eff1c1ency for the above class B push pull output stage is nmax ZT ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 060 7 Push7Pull Output Stages 1602 Page 060715 709 Output Stage Fig 060714 0 06 061 062 063 064 065 066 067 VIN 709 Output Stage Voltage Transfer Function VIN MODEL BJTN NPN IS1E14 BF100 VAF50 RL 2 0 lKILOHM MODEL BJTP PNP IS1E14 BF50 VAF50 R1 4 3 20KlLOHM Q14 3 2 BJTN DC VIN 060 067 0001 Q2 5 3 2 BJTP PRINT DC V2 Q3 3 1 5 BJTN VCC 4 0 DC 10V END VEE 5 0 DC 710V This stage assumes that feedback will be used around the amplifier which will linearize the nonlinearity of the output stage ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 060 7 Push7Pull Output Stages 1602 Page 060716 741 Output Stage 15 Fig 060715 062 063 064 065 066 067 VIN 741 Output Stage Voltage Transfer Function RL Q13C 6 6 7 BJT P 1Kilohm VCC 7 0 DC 15V MODEL BJTN NPN IS1E14 BF100 VAF50 VEE 8 0 DC 715V MODEL BJTP PNP IS1E14 BF50 VAF50 IBIAS 6 0 220UA Q23 8 1 3 BJTP VIN 9 8 DC 0645 Q20 8 3 2 BJTP R10 4 3 40KlLOHM Q14 7 5 2 BJTN RL 2 01KILOHM Q17 1 9 8 BJTN DC VIN 0625 0665 00005 Q18 5 4 3 BJTN PRINT DC V2 Q19 5 5 4 BJTN Q13A5 67BJTP END Q13B 16 7 BJTP 30 ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 060 7 PushePull Output Stages 1602 Page 060717 QuasiP V Output Stages Quasi complementary connections are used to improve the performance of the PNP or PMOS transistor Composite connections s s V SG VSG Go 39 a E Go Q2 11D 1112 D Fig 060716 PNP Equivalent PMOS Equivalent VEB KP Wi 2 1C 1 2 1C1 1 2 IseXp v ID 1 21D1 1 2 2L1 VGsVT The composite has the beta of an The composite has an enhanced K N ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 060 7 PushePull Output Stages 1602 Page 060718 Overload Protection For circuits that can provide large amounts of output current it is necessary to provide short circuit current protection Example Fig 060717 iOUT iC1iC2 z iCi iOUT 1i31 B101quot 402 VBE2 iCiRLim But 1C2 z I szexp Vl z I szexp Vl iCiRLim lOUT 311139 Iszexp v As iOUT increases Q2 turns on and pulls base current away from Q1 limiting the output current ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 110 7 Intro and Characterization of the Op Amp 12802 Page 11071 LECTURE 110 INTRODUCTION AND CHARACTERIZATION OF THE OP AlVlP READING GHLM 404424 AH 243249 Objective The objective of this presentation is 1 Introduce and characterize the op amp Outline Static characteristics of the op amp Dynamic characteristics of the op amp Op amp architecture Two stage Folded cascode Summary ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 110 7 Intro and Characterization of the Op Amp 12802 Page 11072 INTRODUCTION AND CHARACTERIZATION OF OP AMPS HighLevel Viewpoint of an Op Amp Block diagram of a general two stage op amp Comp ensation Circuitry 1 Differential I High Output valTy Transconductance Gam Buffer Stage Stage Fig 110701 Differential transconductance stage Forms the input and sometimes provides the differential to single ended conversion High gain stage Provides the voltage gain required by the op amp together with the input stage Output buffer Used if the op amp must drive a low resistance Compensation Necessary to keep the op amp stable when resistive negative feedback is applied ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 110 7 Intro and Characterization of the Op Amp 12802 Page 11073 Ideal Op Amp Symbol 11 VDD l v1 01 V55 VOUT AvV1V2 V2 IT Fig 110 02 Null port If the differential gain of the op amp is large enough then input terminal pair becomes a null port A null port is a pair of terminals where the voltage is zero and the current is zero Ie v1 v2 vi O and i1 O and i2 0 Therefore ideal op amps can be analyzed by assuming the differential input voltage is zero and that no current flows into or out of the differential inputs ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 110 7 Intro and Characterization of the Op Amp 12802 Page 11074 General Confi uration of the 0 Am as a Volta e Am lifier Noniverting voltage amplifier R1R2 Vout Vin 0 gt R1 Vinp Inverting voltage ampli er R2 Vinp O 2 Vout R l Vinn ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 110 7 Intro and Characterization of the Op Amp 12802 Page 11075 Example 1 Simplified Analysis of an OD Amn Circuit The circuit shown below is an inverting voltage amplifier using an op amp Find the voltage transfer function VOWVin 0 Virtual Ground Fig 110 04 Solution If AV gt 00 then vi gt 0 because of the negative feedback path through R2 The op amp with fb makes its input terminal voltages equal Vi O and ii 0 Note that the null port becomes the familiar virtual ground if one of the op amp input terminals is on ground If this is the case then we can write that Vin d Vout l an 1 1 R1 2 R2 Vow R2 Srnce zl 0 then 11 12 O g1v1ng the desired result as Vin R l ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 110 7 Intro and Characterization of the Op Amp 12802 Page 11076 Linear and Static Characterization of the 0 Am A model for a nonideal op amp that includes some of the linear static nonidealities ideal Op Amp Fig 110705 where Rid differential input resistance Cid differential input capacitance Ricm common mode input resistance V05 input offset voltage 131 and 132 differential input bias currents 105 input offset current 105 131 132 CMRR common mode rejection ratio 6 voltage noise spectral density mean square voltsHertz 11 current noise spectral density mean square ampsHertz ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 110 7 Intro and Characterization of the Op Amp 12802 Page 1107 Linear and Dynamic Characteristics of the Op Amp Differential and common mode frequency response V1 sV2s Vows AvsV1s V2sl i Ads 2 Differential frequency response A AvO Avo p1p2p3 VG i 1 L Di 1 5 PlXS PZXS 173 P1 P P where p1 p2 p3 are the poles of the differential frequency response ignoring zeros Avjm dB Asymptotic 2010g104w c Magnitude Actual Mannitu e 6dBOCL OdB m1 18dBoct Fig 110706 ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 110 7 Intro and Characterization of the Op Amp 12802 Page 11078 Other Characteristics of the Op Amp Power supply rejection ratio PSRR Volvin Vdd O Volvod 0 Input common mode range ICMR ICMR the voltage range over which the input common mode signal can vary without in uence the differential performance AVDD PSRR AVOUT Avs Slew rate SR SR output voltage rate limit of the op amp Settling time TS VOL 70 1 Final Value c v Upper Tolerance e t vOUT Final Value A V Av V J IN Final Value S i E Lower Tolerance l lt Settling Time gt O 0 Tor Fig 1100 7 ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 110 7 Intro and Characterization of the Op Amp 12802 Page 1109 Classification of CMOS Op Amps Categorization of op amps Conversion Hierarchy Voltage Classic Differential Modified Differential I to Current Ampli er Amplifier I I First g Voltage Current Differential to single ended SourceSink MOS Diode Stage to Voltage Load Current Mirror Current Loads Load V V Current VOItage Transconductance Transconductance Sta 6 to Current Grounded Gate Grounded Source I I Second 0 0 Voltage Current Class A Source Class B Stage to Voltage or Sink Load Push Pull ECE 6412 7 Analog Integrated Circuits and Systems 11 Table 1 1001 PE Allen 7 2002 Lecture 110 7 Intro and Characterization of the Op Amp 12802 Page 110710 TwoSta e0 Am Architecture Simple two stage op amp broken into voltage to current and current to Voltage stages VgtI ECE 6412 7 Analog Integrated Circuits and Systems 11 IgtV 1 Fig 110708 PE Allen 7 2002 Lecture 080 7 1 Stage Frequency Response 711 11002 Page 08071 LECTURE 080 SINGLESTAGE FREQUENCY RESPONSE II READING GHLM 504516 Objective The objective of this presentation is l Illustrate the frequency analysis of single stage amplifiers 2 Introduce the Miller technique and the approximate method of solving for two poles Outline Differential and Common Frequency Response of the Differential Amplifier EmitterSource Follower Frequency Response Common BaseGate Frequency Response Summary ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 080 7 1 Stage Frequency Response 711 11002 Page 08072 Emitter Follower Input Impedance VCC Fig 080701 r71 If we let z then Vi Vi Vb ImUb Zn 1m ngnImRL gt Z1 E rb Zn 1 ngnRL r gmr 39 W ZirblSCirn 115Cirri RLrb SCI L Z 1ngLrn R R R 1 R irb sCi Lrbm L OB A gerquot l1ngLt lngLrL Z i gt where R 1ngLr and C Cil l39ngL Cu 39 39 RL 1 ngL T Fig 08002 ECE 6412 7 Analog Integrated Circuits and Systems 11 RE Allen 7 2002 Lecture 080 7 1 Stage Frequency Response 711 11002 Page 08073 Emitter Follower Output Impedance From the previous model or from the impedance transformation aspect of a BIT we can write r71 Vm z R rb z Rf 1SCir RI r RfsCir Rf Zn In 1ng 1ngn mm 01sCir 1sClr Multiplying top and bottom by ll o gives L E C a R 8m 30 H We 1 R1 sLR2 Z0 Rf R2 SL assuming 30 gtgt1 R1 sCirEE Equivalent output circuit VOW Fig 08003 ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 080 7 1 Stage Frequency Response 711 11002 Page 08074 Source Follower Freauencv From the previous lecture for the MOSFET r 0 rb 0 and R L 1gSRL 39 39 S S VOW ng L Z 1 5 Vaut ng39L 1 5 Wz R W S gt Wlngi S 1 ng39L l39 r 177 1 117 1 gm 1 RIR39L 1 where 21 C gs P1 39 Rngs and R11ngiz 5 Example Calculate the transfer function for a source follower with Cgs733pF K WLlOOmAV2 RL2kQ RI 19OQ and ID4mA Let gmbsz O ng O Cgb O and Cbs 0 Solution v 2822 gm 21004 mAV 282mAV 1 2822 0983VV g quot 9 w IZ1 OT cgs 385X10 radss R11ngtL112822 3829 1012 p1 7357x109 radss ng Cgb and Cbs cause two poles 1 zero ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 080 7 1 Stage Frequency Response 711 11002 Page 08075 Source Follower Output Impedance The output impedance of the source follower can be found from the previous general analysis or from the following model Fig 080704 Summing currents at the output Vn M In gmvgs SCgngs gmbsvnut and Vgs 39 ngSRI1 V0 I 0 g SC M In gmbsvnut gmSCgsngs 1 gt VOW gmbS39l39 lSCgSRI V0 1ngSR 1 t 1ngSR U In gm39l39gmbs 5CgsRIgmbs1 gm39l39gmbsL1 RIgmbs39l391 g gm39l39gmbs ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 080 7 1 Stage Frequency Response 711 11002 Page 08076 Identification of the Output Impedance Find the value of R1 R2 and L in the equivalent output impedance model shown for the source follower Note that VOL R1 4 Z0 R2R1SL R2R1SL R2 Zn R1R2sL e R2sL 1f R1ltlt R2 L The best way to solve this problem is to use the limits of Zn T Fig 08005 1 M where R1ltlt R2 R1R2 lzm Z0 5 O mz R1 RI lzm Z0 s gt co R2 W Cgs1RIgmbs CgsRIRl gm39l39gmbs R2 If one includes C gd in parallet with the equivalent circuit the potential for resonance of l 1 the output impedance will occur roughly at Lng previous example with gmbs 01gm and ng 05 pf gives R1 3229 R2 12379 and L 733pF1909322912379 0362nH gt fasc 118GHZ if R1 is small Using the values of the ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 080 7 1 Stage Frequency Response 711 11002 Page 08077 Frequency Response of Current Buffers Current buffers include the common base and common gate configurations ForM OS rb0 and r m Fig 080704 Summing the currents at the input node neglecting R1 2 r L z Z gmvl z 0 where z 1SCir gt 1i 7v1gm r SC The short circuit output current gain can be found as in gmr 39 l l v gt 39 0 gm 1 ll 1gmr r l 51gmr Ci ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 080 7 1 Stage Frequency Response 711 11002 Page 08078 CommonBase Amplifier Frequency Response Replace C with C 7 gives in gm 1 30 1 Ti 1gmr r z 30 C 1fl30gtgt1 where 30 gmr 1 WC 1 s m 71 gm 1 8 Low frequency gain 7 060 and a pole at p1 C r z 760T If the output current flows through RL then the current gain has another pole due to C LU gmr 1 1 I30 1 L 1 ii 1gmr r 1SRLCJ z130 C71 15ch Ai 11 Hi 1 Wc l Sg m P1 p2 Example If C 1mA 30 100 C 10pF C 05pF CCS 1pf and RL 2kg evaluate the CB amplifier gm 126 mS 1 Ai 099 p1 726x1012 rads and p2 7m 70333x109 rads ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 120 7 Compensation of Op Ampsel 13002 Page 12071 LECTURE 120 COlVlPENSATION 0F 0P AlVlPS I READING GHLM 425434 and 624638 AH 249260 INTRODUCTION The objective of this presentation is to present the principles of compensating two stage op amps Outline Compensation of Op Amps General principles Miller Nulling Miller Self compensation Feedforw ard Summary ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 120 7 Compensation of Op Ampsel 13002 Page 12072 GENERAL PRINCIPLES OF OP AMP COMPENSATION Objective Objective of compensation is to achieve stable operation when negative feedback is applied around the op amp Types of Compensation 1 Miller Use of a capacitor feeding back around a high gain inverting stage Miller capacitor only Miller capacitor with an unity gain buffer to block the forward path through the compensation capacitor Can eliminate the RHP zero Miller with a nulling resistor Similar to Miller but with an added series resistance to gain control over the RHP zero 2 Feedforward Bypassing a positive gain amplifier resulting in phase lead Gain can be less than unity 3 Self compensating Load capacitor compensates the op amp ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 120 7 Compensation of Op Ampsel 13002 Page 12073 SingleLoop Negative Feedback Systems Block diagram As differential mode voltage gain of the op amp F s feedback transfer function from the output of op amp back to the input De nitions Open loop gain Ls ASFs Closed loop gain M amp inS 1ASFS Stability Requirements The requirements for stability for a single loop negative feedback system is IAOw0 F39w0 l Liw0 l lt 1 where woe is defined as AfglAOwooW 1000 ArglLOwOOH 00 Another convenient way to express this requirement is AfglAUdeBWUdeBH AfglLUdeB gt 0 where deB is defined as IAUdeBFiw0dBI ILOdeBI 1 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Vin VOL5 Fig 12001 Lecture 120 7 Compensation of Op Ampsel 13002 Page 12074 Illustration of the Stabilitv Requirement using Bode Plots A 20dBdecade AcoFool OdB 40dBdecac1ev i 00 O c I O 0 La i l J ArglAOCOWOOJH 31 EMT 0 co deB F F 12002 Frequency radssec lg39 lg39 39 A measure of stability is given by the phase when AjaFal 1 This phase is called phase margin Phase margin PM ArgIAOdeBW 139600dBl ArgL39w0dBl ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 120 7 Compensation of Op Ampsel 13002 Page 12075 Why Do We Want Good Stability Consider the step response of second order system which closely models the closed loop gain of the op amp I JV 5 10 15 Fig 120 03 not uni see A good step response is one that quickly reaches its final value Therefore we see that phase margin should be at least 450 and preferably 600 or larger A rule of thumb for satisfactory stability is that there should be less than three rings ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 120 7 Compensation of Op Ampsel 13002 Page 1206 IT Freauencv 0f TwoStage Op Amps Two Stage Op Amps Small Signal Model D1 D3 C1 C3 C3 Ii Vout Fig 12005 Note that this model neglects the base collector and gate drain capacitances for purposes of simpli cation ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 120 7 Compensation of Op Ampsel 13002 Page 12077 1 Freauencv of TwoStage OD Amps Continued For the MOS two stage op amp 1 1 R1 3 gm rds3rds1 3 gm R2 rdsz rds4 and R3 mm mm C1 Cgs3Cgs4delde3 C2 Cgs6de2de4 and C3 CL de6de7 For the B T two stage op amp 1 1 R1 g llr gllrmllrog z 8 R2 r 6ll r02 r04 2 r756 and R3 r06 r07 C1 C7r3C7E4CcslCcs3 C2 C 6Ccs2Ccs4 and C3 CLCcs6Ccs7 Assuming the pole due to C1 is much greater than the poles due to C2 and C3 gives o I C 11 Vout I I 39 a Fig 120706 The locations for the two poles are given by the following equations 1 l p 1 Z RICI and p 2 Z RIICH where R1 R11 is the resistance to ground seen from the output of the first second stage and C1CH is the capacitance to ground seen from the output of the first second stage ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 120 7 Compensation of Op Ampsel 13002 Page 1208 IT Freauencv of an OD Amn Avd0 dB 20dB decade E o S OdB 10g10m Phase Shift 40dBdecade 1 e o F To 2 10g100 39PZI mOdB Fig 120707 If we assume that F s 1 this is the worst case for stability considerations then the above plot is the same as the loop gain Note that the phase margin is much less than 450 Therefore the op amp must be compensated before using it in a closed loop configuration ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 120 7 Compensation of Op Amps7l 13002 Page 12079 MILLER COMPENSATION TwoStage Op Amp VEE Fig 12008 The various capacitors are C c accomplishes the Miller compensation CM capacitance associated with the first stage mirror mirror pole C1 output capacitance to ground of the first stage C11 output capacitance to ground of the second stage ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 120 7 Compensation of Op Amps7l 13002 Page 120710 Com ensated TwoStage SmallSignal Freauencv Model Simpli ed Use the CMOS op amp to illustrate 1 Assume that gmg gtgt gds3 gdsl 8amp3 2 Assume that CM gtgt GB Therefore Cc V1 v2 I II l l 1 2 C i gmzvi C 8 6V2 mullahs M gm3 2 gm4V1 1 rdyzllrgm m msllrtk CL T u Cc 1 t 1 Vi gmlvin 0 l rmnrm gmsvz ltgtmy6nrds7 C T Vow Fig 120709 Same circuit holds for the B T op amp with different component relationships ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 120 7 Compensation of Op Amps7l 13002 Page 120711 General TwoStage Freauencv Analvsis Cc where 0 V2 J lt gm gml gmzy R1 rdszllrds4 C1 C1 lt m ngV CITRI ltgt mHV2 R11 CIT Vofquot and Fig120710 ngI gm R11 rds6rds7v C11 C2 CL Nodal Equations ngVm GI SCI CcV2 SCcV0ut and O ngI SCcV2 G11 SCI SCcV0ut Solving using Cramer s rule gives V0uts ngI r SCc VinS G1G11S GIIC1CHquotGICIICcgmICcSZCICIICCCICCCII A01 S 15 RlClCIIRIIC2CcngIR1RHCcSZRIRIICICII39l39CcCI39l39CcCII Where A0 gmlngIRIRII I 1D 71111 1iii D lii fllll 1 genera S 771 772 395 171 171172 gt 5 39p1ptp2 1 P2 gtgtP1 1 E 171 RIC1CIIRIICIICcngIR1RIICc ngIRIRIICc Z Cc R1C1C11R11C11CcngIRIRIICc ngICc ng1 2 R1R11C1C11CcC1CcCII C1C11CcC1CcC11 C11 C gt CC gt C1 ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 120 7 Compensation of Op Amps7l 13002 Page 120712 Summarv of Results for Miller C inn 0f the TwoStage OD Amn There are three roots of importance 1 Right half plane zero ngI gm6 Z1 Cc Cc This root is very undesirable it boosts the magnitude while decreasing the phase 2 Dominant left half plane pole the Miller pole 1 gds2gds4gds6gds7 1 1 ngIRIRIICc gm6Cc This root accomplishes the desired compensation 3 Left half plane output pole M m P2 2 C11 2 CL This pole must be 2 unity gainbandwidth or the phase margin will not be satisfied Root locus plot of the Miller compensation Closed7loop poles CL 0 jm 0 who oles pe CF81 9lt gt 6 P2 P2 P1 P1 21 Fig 120711 ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 LectuIe 120 7 Compensation of Op Amps71 13002 Page 120713 F OpenLoon Frequencv of the TwoStage On Amn R Avd0 13 x Uncompensated g quot 720dBdecade LA 8 o E 10164100 740dBdecade OdB Phase Shift 45 decade Phase Margin 10g1003 Fig 12012 Arg AjoaFjoal 00 Note that the unity gainbandwidth GB is ng gml gm2 1 GB Avd0P1 gmlgmIIRIRIIg mHRIRHCC Cc Cc C0 ECE 6412 7 Analog IntegIated Circuit Design 711 PE Allen 7 2002 LectuIe 120 7 Compensation of Op Amps71 13002 Page 120714 Conceptually where do these roots come from 1 The Miller pole VDD C RH RI 39 39539quot Wm 39Pl39 3 R1ltgm6RHCJ Ms vI gm6RnCcI T Fig120713 2 The left half plane output pole VDD VDD Cc R11 R11 p2 z gc M6 vom zo M6 VOW H CH cgt C11 T I T T Fig 120714 3 Right half plane zero Zeros always arise from multiple paths from the input to output RH gmG t guRHascm r RH 1 Vow L RII 1ch JV RH 1ch V RII 1ch V Where V V V T T T Fig120715 ECE 6412 7 Analog IntegIated Circuit Design 711 PE Allen 7 2002 Lecture 120 7 Compensation of Op Ampsel 13002 Page 120715 In uence of the Mirror Pole Up to this point we have neglected the in uence of the pole p3 associated with the current mirror of the input stage A small signal model for the input stage that includes C3 is shown below 39 lt lt l3 lt lt M lt lt lt gszm lt V01 2 ltgt lt 71 2 i gt ltgt rdsl rds3 gm3 C3 3 r4152 rds4 V Fig12016 The transfer function from the input to the output voltage of the first stage V01s can be written as V010 gm1 gm3gds1gds3 1 VinS 2gds2gds4 gm3 gds1gds3sC3 We see that there is a pole and a zero given as gm1 lsC3 28ml 2gds2gds4 t sC3 gmsj 2gm3 gm3 P3c 3 andZ3c 3 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 120 7 Compensation of Op Ampsel 13002 Page 120716 In uence of the Mirror Pole Continued Fortunately the presence of the zero tends to negate the effect of the pole Generally the pole and zero due to C3 is greater than GB and will have very little in uence on the stability of the two stage op amp A F 1 The plot shown rllustrates Avd0 dB Cc 0 the case where these roots are 6dBoctave less than GB and even then they have little effect on stability Cc 0 In fact they actually GB increase the phase margin OdB p gt 10g100 slightly because GB is Ma nitude in uence of C decreased Phase Shift g 3 3912dBOctaVe A Oo Cc 0 t 450 45 decac e A 39 C 0 900 V M 45 decade 135 Cc 0 C 0 239 5 Phase margi Phase margin due to C3 7gtI Algnormg C3 18no r 10g100 39Pr39 IP339 Z3 l 239 Fig 12017 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 410 7 IIigh7Speed Comparators 4802 Page 41071 LECTURE 410 HIGHSPEED CONIPARATORS READING AH 483488 Objective The objective of this presentation is 1 Show how to achieve high speed comparators Outline Concepts of high speed comparators Amplifier latch comparators Summary ECE 6412 7 Analog Integrated Circuit Design 7 II PE Allen 7 2002 Lecture 410 7 IIigh7Speed Comparators 4802 Page 41072 Conce tual Illustration of a Cascaded Com arator How does a cascaded high speed comparator work I 4 If sT1 sT1 sT1 sT1 sT1 sT 1 T T T T T T Linear Linear Linear Large Large Large small small amp large signal signal signal signal signal signal small C bigger C big C Fig 864 Assuming a small overdrive 1 The initial stage build the driving capability 2 The latter stages swing rail to rail and build the ability to quickly charge and discharge capacitance ECE 6412 7 Analog Integrated Circuit Design 7 II PE Allen 7 2002 Lecture 410 7 Hi ghAS peed Comparators 4802 Page 41073 quot 39 39 39 the P1 quot Delav Time in Cnmnarators Fact The input signal is equal to Vinmin for worst case Amplifiers have a step response with a negative argument in the exponential Latches have a step response with a positive argument in the exponential Result Use a cascade of linear amplifier to quickly build up the signal level and apply this amplified signal level to a latch for quick transition to the full binary output swing Illustration of a preamplifier and latch cascade VOW Minimization of IP Q If the preamplifer consists of n stages of gain A having a single pole response what is the value of n and A that gives minimum propagation delay time A n 6 andA 262 but this is a I very broad minimum and n is Fig 864 usually 3 andA 2 6 7 to save area ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 410 7 Hi ghAS peed Comparators 4802 Page 41074 Full Differential ThreeSta e Am lifier and Latch Com arator Circuit FB FB Reset Cvl C v3 Cv Reset 2 Reset CV4 Reset CV FB FB C1 CV vm Fig 863 Comments Autozero and reset phase followed by comparison phase More switches are needed to accomplish the reset and autozero of all preamplifiers simultaneously Can run as high as lOOMsps ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 410 e HigheSpeed Comparators 4802 Page 4105 Preamplifier and Latch Circuits Gain VDD A gm1 glz KN W1L1 M l l m V 39 gm3 39 gm4 39 Kp W3L3 Dominant Pole FB Reset Q 8amp3 8amp4 39 H IPdominantl C C n n Q where C is the capacitance seen from the quot39 Md output nodes to ground If WlL1W3L3 100 and the Enable bias current is IOOHA then A 385 Preamplifier and the bandwidth is 159MHZ if C 05pF VBias o Comments Fig 864 If a buffer is used to reduce the output capacitance one must take into account the loss of the buffer The use of a preamplifier before the latch reduces the latch offset by the gain of the preamplifier so that the offset is due to the preamplifier only ECE 6412 e Analog Integrated Circuit Design e 11 PE Allen e 2002 Lecture 410 e HigheSpeed Comparators 4802 Page 4106 An Improved Preamplifier Circuit VDD VBiasP VBiasp 0 M3 V14 I O Vout39 M5 6 WMquot M12 FB Vinquot Fig 865 Gain A gm1 IKN W1L111 IKN W1L1 1 15 v gmg ij W3L313 Kp ltW3L3 13 If 15 2413 the gain is increased by a factor of 5 ECE 6412 e Analog Integrated Circuit Design e 11 PE Allen e 2002 Lecture 410 7 Hi ghAS peed Comparators 4802 Page 41077 Charge Transfer Preamplifier The preamplifier can be replaced by the charge transfer circuit shown Vin VREF Q PR Vin VREF VPR Vin VREFAV 82 VREF Vrl AV Vin VT Vom Vom VPR 39ClAV S l Vom C0 cm or CT cw CT Co Charge transfer amplifier Precharge phase Amplification phase F 8 6 6 1g Comments Only positive values of voltage will be ampli ed Large offset voltages result as a function of the subthreshold current ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 410 7 HigheSpeed Comparators 4802 Page 41078 A CMOS Char e Transfer Pream lifier Circuit VDD VDD V PR CT 31 M2 82 S3 Vom v o I S3 M1 l CO CT 81 Fig 867 Comments NMOS and PMOS allow both polarities of input CMOS switches along with dummy switches reduce the charge injection Switch S3 prevents the subthreshold current in uence Used as a preamplifier in a comparator with 8 bit resolution at 20Msps and a power dissipation of less than SuW ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 170 7 1 Stage Frequency Response 11002 Page 17071 LECTURE 170 INTUITIVE ANALYSIS OF ANALOG CIRCUITS READING AH 191193 Objective The objective of this presentation is l Illustrate how to perform a small signal midband analysis from the schematic 2 Introduce the Miller technique and the approximate method of solving for two poles Outline Key concepts in CMOS analog IC circuit analysis Intuitive approach Examples Summary ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 170 7 1 Stage Frequency Response 11002 Page 17072 IMPORTANT RELATIONSHIPS FOR CMOS ANALOG IC DESIGN 1 Square law relationship K W lD 2L Vcs VT2 2 Small signal transconductance formula 2K WID gm L 3 Small signal simpli cation gm 108mm z 1OOgds 4 Saturation relationship 21D VDSsat m ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 170 7 1 Stage Frequency Response 11002 Page 17073 An Intuitive Method of Small Signal Analysis Small signal analysis is used so often in analog circuit design that it becomes desirable to nd faster ways of performin g this important analysis Intuitive Analysis or Schematic Analysis Technique 1 Identify the transistors that convert the input voltage to current these transistors are called transconductance transistors 2 Trace the currents to where they ow into an equivalent resistance to ground 3 Multiply this resistance by the current to get the voltage at this node to ground 4 Repeat this process until the output is reached Simple Example DD M2 V01 ngVUIT VOW T Fig 5210C V01 8m lVin R1 9 Vout gm2V01R2 a Vout 8m 1R18m2R2Vin ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 170 7 1 Stage Frequency Response 11002 Page 17074 Intuitive Anal sis of the CurrentMirror Load Differential Am lifier M1 gmlvzd ngVzd M2 2 2 Jaw 39 VBmi Fig52711 1 i1 05g le and i2 705gm2vid 2 i3 i1 058m1Vid 3 i4 i3 058m1Vid 1 gdsZ gds4 glein ngVin Vout gml 539 Vow O39nglvid O39ng2Vid mm gds2gds4 gds2gds4 2 Vin gds2gds4 4 The resistance at the output node ram is rdszllrds4 or ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 170 7 1 Stage Frequency Response 11002 Page 17075 Some Concepts to Help Extend the Intuitive Method of SmallSignal Analysis 1 Approximate the output resistance of any cascode circuit as Rout z ngrdSZrdsl where M1 is a transistor cascoded by M2 2 If there is a resistance R in series with the source of the transconductance transistor let the effective transconductance be 8 m g m e 1 gm R Proof gmemvml gmmmvml ngVgSZ 1W E M V1sz Small7signal model T T Fig52711A Vin VgsZ VgZ V52 Vin gm2rd51Vg52 gt VgsZ 1gm2rdsl ngVirt Thus lout 1gm21 d51 gm26 m Vin ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 170 7 1 Stage Frequency Response 11002 Page 17076 Miller TwoStage Op Amp VDD M3 M4 CC Vout M1 M2 Vin Assume proper NP common mode 39 I I M7 input voltage VBias F l I VSS Fig 170 01 ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 170 7 1 Stage Frequency Response 11002 Page 17077 Miller TwoStage Op Amp VDD M6 M3 Vout Ml Assume proper NF 5 common mode l M7 input voltage VBias L1 VSS Fig 170 01 ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 170 7 1 Stage Frequency Response 11002 Page 17078 Miller TwoStage Op Amp VDD M6 M3 v g m anl 0m 2 M1 Assume proper NF 5 common mode l M7 input voltage VBias F1 VSS Fig 170 01 ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 170 7 1 Stage Frequency Response 11002 Page 17079 Miller TwoStage Op Amp gleinl 2 gleinl 2 M6 M3 Vout I Assume proper NF 5 common mode 39 39 I input voltage VBias L1 IM7 SS f gl70 01 ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 170 7 1 Stage Frequency Response 11002 Page 170710 Miller TwoStage Op Amp gleinl 2 M3 gleinl 2 Vout n Assume proper NF 5 common mode 39 39 I input voltage VBias F1 IM7 VSS Fig 17001 ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Page 17071 1 Lecture 170 7 1 Stage Frequency Response 11002 Miller TwoStage Op Amp g m anl 2 M3 lgm6val v g m anl U w R autzrds6 Irds7 M 1 Assume proper NI common mode 39 M7 input voltage VB jag Fig 170 01 VSS Vaut gml H quotgm6 i quotgmlgm6 Vin Lgds2gds4i igds6gds7i gds2gds4gds6gds7 PE Allen 7 2002 ECE 6412 7 Analog Integrated Circuit Design 7 11 Page 170712 Lecture 170 7 1 Stage Frequency Response 11002 FoldedCascode Op Amp VDD VBiaS M3 11 M2 V0141 M6 7 VBiaS VBiaS 4 M4 M5 VSS Fig 17002 PE Allen 7 2002 ECE 6412 7 Analog Integrated Circuit Design 7 11 Page 170713 Lecture 170 7 1 Stage Frequency Response 11002 FoldedCascode Op Amp VDD V Ml M3 M10 M11 Vin 171 7 2 1 M2 M8 M9 V0141 Vin 7M6 M7 VBias VBiaS 4 M4 M5 VSS Fig 17002 PE Allen 7 2002 ECE 6412 7 Analog Integrated Circuit Design 7 11 Page 170714 Lecture 170 7 1 Stage Frequency Response 11002 FoldedCascode Op Amp VDD VBiaS M3 M10 M11 Vm 2 2 11 M2 M8 M9 vm gmlvinT l ngVin V01 2 2 n M6 7 VBiaS VBiaS 4 M4 M5 VSS Fig 17002 PE Allen 7 2002 ECE 6412 7 Analog Integrated Circuit Design 7 11 Page 170715 Lecture 170 7 1 Stage Frequency Response 11002 FoldedCascode Op Amp Vin V 7 2 1 M2 39 gmlvin T l ngVin 2 n gmlvinl 2 VBiaS 4 M4 M5 VSS Fig 17002 PE Allen 7 2002 ECE 6412 7 Analog Integrated Circuit Design 7 11 Page 170716 Lecture 170 7 1 Stage Frequency Response 11002 FoldedCascode Op Amp VDD V MI M3 M10 Vin 7 2 11 M2 39 gmlvm M8 M9 V gmlvinT l ngVin 2 Val m 2 2 gt VBiaS ngVin 2 gmlvm TngVin 2 2 VBiaS 4 M4 M5 VSS Fig 17002 PE Allen 7 2002 ECE 6412 7 Analog Integrated Circuit Design 7 11 Page 170717 Lecture 170 7 1 Stage Frequency Response 11002 FoldedCascode Op Amp V MI M3 Vii Vin 2 11 M2 gmlvint l ngVin 2 2 V55 Fig 170 02 PE Allen 7 2002 ECE 6412 7 Analog Integrated Circuit Design 7 11 Lecture 170 7 1 Stage Frequency Response 11002 Page 170718 FoldedCascode Op Amp VDD VBias M3 gmlvin M l T 2 2 1 M2 Vout Rout gm9rds9rdsu gm7rds7r dszllr 155 VBias ngVin 2 gmlvm 1gm2vin 2 2 VBias 4 M4 M5 V55 Fig 17002 gml 2 Ramgm1gm9rds9rds11 gm7rds7rds2 rds5 Vaut Vin 2 ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 130 7 Compensation of Op Ampsell 12604 Page 13071 LECTURE 130 COlVlPENSATION 0F 0P AlVlPSII READING GHLM 638652 AH 260269 INTRODUCTION The objective of this presentation is to continue the ideas of the last lecture on compensation of op amps Outline Compensation of Op Amps General principles Miller Nulling Miller Self compensation Feedforward Summary ECE 6412 7 Analog Integrated Circuits Design 11 PE Allen 7 2002 Lecture 130 7 Compensation of Op Ampsell 12604 Page 13072 Conditions for Stability of the TwoStage Op Amp Assuming 232GB 1 Unity gainbandwith is given as ngngIRIRI gmI gmlgmzR 1R2 G3 Avlt0quotP139 ngIRIRIICc Cc ngRlRZCc Cc The requirement for 450 phase margin is w w a 1800 ArgAF 1800 tan1W tan1a tan4 450 Let a GB and assume that z 2 10GB therefore we get 0 12 1 Q 1 Q 0 i180 tan hull tan Ila tan Z J 45 GB 1350 z tan1AVO tan1GP tan1Ol 900 tan1GP 570 GB GB 3930 tan1a 2 W 0818 2 The requirement for 600 phase margin If 600 phase margin is required then the following relationships apply gm6 108ml gm6 228ml C c gt CC gt gm6gt10gm1 and C 2 gt CC gt Ccgt022C2 ECE 6412 7 Analog Integrated Circuits Design 11 PE Allen 7 2002 Lecture 130 7 Compensation of Op Amps7ll 12604 Page 13073 Controlling the RightHalf Plane Zero Why is the RHP zero a problem Because it boosts the magnitude but lags the phase the worst possible combination for stability Fig 43001 Solution of the problem If zeros are caused by two paths to the output then eliminate one of the paths ECE 6412 7 Analog Integrated Circuits Design 11 PE Allen 7 2002 Lecture 130 7 Compensation of Op Amps7ll 12604 Page 13074 Use of Buffer to Eliminate the Feedforward Path throu h the Miller Ca acitor Model V CC 0 l V39 v C1 R Vt V I LquotngVm T I OH nglVI R CIT fm 1 Fig 430701 The transfer function is given by the following equation VaS gm1gm11RIRII VinS 1 SRICI RIICII RICE ngIRIRIICc S2RIRIICIICI Cc Using the technique as before to approximate p1 and p2 results in the following pl 5 RICI RIICII RICC ngIRIRIICc E ngIRIRIICc and ngICC 172 E CIICI Cc Comments Poles are approximately what they were before with the zero removed For 450 phase margin Ipzl must be greater than GB For 600 phase margin Ipzl must be greater than 173GB ECE 6412 7 Analog Integrated Circuits Design 11 PE Allen 7 2002 Lecture 130 7 Compensation of Op Ampsell 12604 Page 13075 Use of Buffer with Finite Out ut Resistance to Eliminate the RHP Zero Assume that the unity gain buffer has an output resistance of R0 Model 0 V1 C6 W D Vingmzvm CITRI R R0 V R11 01 quot VOW 39 ngI I l Fig 43003 It can be shown that if the output resistance of the buffer amplifier R0 is not neglected that another pole occurs at 1 1 4 E R0CICcCI Cc and a LHP zero at 1 22 E RUCC Closer examination shows that if a resistor called a nulling resistor is placed in series with C0 that the RHP zero can be eliminated or moved to the LHP ECE 6412 7 Analog Integrated Circuits Design 11 PE Allen 7 2002 Lecture 130 7 Compensation of Op Ampsell 12604 Page 13076 Use of Nullin Resistor to Eliminate the RHP Zero 0139 turn it into a LHP zero l V CC R2 r W v V C R Van UT I3 imngVm IT 1 gmHV RH Carr 7 Fig 430704 Nodal equations SCC 1 SCCRZ V1 Vow 0 VI gszm R7 SCsz SCC 1 SCCRZ Vom VI O V0 ngIVI R H SCIIVom Solution Vams a1 SCcgm11 Rchl Vins 1 75 632 133 where a ngngIRIRII b CH CcRII C1 CcRI ngIRIRIICc Rch C RIRIICICII CCCI CcCII RchRICI RIICII d RIRIIRZCICIICC WJ Parrish llAn Ion Implanted CMOS Amplifier for High Performance Active Filtersquot PhD Dissertation 1976 Univ of CA Santa Barbara ECE 6412 7 Analog Integrated Circuits Design II PE Allen 7 2002 Lecture 130 7 Compensation of Op Amps7II 12604 Page 13077 Use of Nulling Resistor to Eliminate the RHP Continued If RZ is assumed to be less than R or R11 and the poles widely spaced then the roots of the above transfer function can be approximated as 1 1 pl 5 1 ngIRIIRICc E ngIRIIRICc ngICc ngI 172 E CICII CCCI CCCII 5 CH 1 p4 m p3 has been used previously for the mirror pole so we choose p4 for the nulling resistor pole and 1 Z1 CC1ngI RZ Note that the zero can be placed anywhere on the real axis ECE 6412 7 Analog Integrated Circuits Design 11 PE Allen 7 2002 Lecture 130 7 Compensation of Op Amps7II 12604 Page 13078 Conce tual Illustration of the Nullin Resistor A roach T Fig Fig 430 05 The output voltage VW can be written as L gm6RI R2 SCC RH quotRI gm6Rz sCC 39 1 V0 1 V V 1 V RHRZE RHRZE RHRZE when V V V Setting the numerator equal to zero and assuming gm ngI gives 1 Z1 CC1ngI Rz ECE 6412 7 Analog Integrated Circuits Design II PE Allen 7 2002 Lecture 130 7 Compensation of Op Amps7II 12604 Page 13079 A Design Procedure that Allows the RHP Zero to Cancel the Output Pole Q2 We desire that Z1 p2 in terms of the previous notation Therefore 1 CC1ngI Rz CH x A A I C 3 The value of RZ can be found as quotP4 39P2 39P1 Z1 Fig 43006 CC CH Rz T 1ngI With p2 canceled the remaining roots are p1 and p4the pole due to R2 For unity gain stability all that is required is that Av0 gm 17439 gt AVOPl ngIRIIRICc To and 1RZC1 gtgm1CC GB Substituting RZ into the above inequality and assuming C11 gtgt CC results in ng Cc gt CICII This procedure gives excellent stability for a xed value of C11 C L Unfortunately as C L changes p2 changes and the zero must be readjusted to cancel p2 ECE 6412 7 Analog Integrated Circuits Design 11 PE Allen 7 2002 Lecture 130 7 Compensation of Op Amps7II 12604 Page 130710 Increasin the Ma nitude of the Out ut PoleT The magnitude of the output pole p2 can be increased by introducing gain in the Miller capacitor feedback path For example VDD Cc 711153 I I M7 l J VOW I3 1m R1 V1 Vs8 R2 C2 Vout 8m8VS8 gm6V1 T a Ignore rdsg Cc M6 M1 1m R1 V1 8 VS8 R2 C2 Vow gm8Vs8 gm6V1 Vss Fig 430707 The resistors R1 and R2 are defined as 1 1 gdsz gds4 gds9 8m gm where transistors M2 and M4 are the output transistors of the first stage Nodal equations R1 andR2 ngSCc in Givi39gmsvss lel39 gmg 5C6 ngS 6 V0 and O gm6V1 G2SC2 gm8SCC V0 BK Ahuja An Improved Frequency Compensation Technique for CMOS Operational Amplifiers IEEE J of SolidState Circuits Vol SC718 No 6 Dec 1983 pp 6297633 ECE 6412 7 Analog Integrated Circuits Design II PE Allen 7 2002 Lecture 130 7 Compensation of Op Amps7ll 12604 Page 130711 Increasing the Magnitude of the Output Pole Continued Solving for the transfer function VowIi gives SCC Vaut 39gm6 1 gm8 1m Ger 1 g 2 g gm6Cc 2 CCCZ 5 gm8G2G2 Ger 5 ngGZ Using the approximate method of solving for the roots of the denominator gives 71 171 CC g 2 gm6CC zgm6rds2CC ng G2 G2 Ger and gm6rds2CC ngrdszGZ gm6 ngrds P2 CCCz C2 3 Ipzl ngGZ where all the various channel resistance have been assumed to equal rds and p2 is the output pole for normal Miller compensation Result Dominant pole is approximately the same and the output pole is increased by z gmrds ECE 6412 7 Analog Integrated Circuits Design 11 PE Allen 7 2002 Lecture 130 7 Compensation of Op Amps7ll 12604 Page 130712 Conce tBehind the Increasin of the Ma nitude of the Out ut Pole VDD VDD gt M6 C11 i Fig Fig 43008 3 gm gmsrdss z gm gmsrdss Therefore the output pole is approximately gm6gm8rds8 IPZI z 3CH Besides the common gate amplifier stops the feedforward path preventing the RHP zero Rout rds7 ECE 6412 7 Analog Integrated Circuits Design 11 PE Allen 7 2002 Lecture 130 7 Compensation of Op Amps7ll 12604 Page 130713 FEEDFORWARD COMPENSATION Use two parallel paths to achieve a LHP zero for lead compensation purposes LHPZero C5 LHPZero using Follower A High Gain CH RHE Amplifier g Fig43009 VowS AC6 S ngIACC V1110quot Cc CH S 1RIICc CID To use the LHP zero for compensation a compromise must be observed Placing the zero below GB will lead to boosting of the loop gain that could deteriorate the phase margin Placing the zero above GB will have less in uence on the leading phase caused by the zero Note that a source follower is a good candidate for the use of feedforward compensation ECE 6412 7 Analog Integrated Circuits Design 11 PE Allen 7 2002 Lecture 130 7 Compensation of Op Amps7ll 12604 Page 130714 SELFCOMPENSATED OP AMPS Self compensation occurs when the load capacitor is the compensation capacitor can never be unstable for resistive feedback I BI Rommust be large Av0 dB39 Fig 430710 OdB Voltage gain Vout W Av0 GmRout Dominant pole 71 p1 RowCL Unity gainbandwidth Gm GB Av039lpl c L Stability Large load capacitors simply reduce GB but the phase is still 900 at GB ECE 6412 7 Analog Integrated Circuits Design 11 PE Allen 7 2002 Lecture 050 7 CE and CS Output Stages 123101 Page 05071 LECTURE 050 CONINION SOURCE AND EMITTER OUTPUT STAGES READING GHLM 384398 AH 218221 Objective The objective of this presentation is Show how to design stages that 1 Provide sufficient output power in the form of voltage or current 2 Avoid signal distortion 3 Be efficient 4 Provide protection from abnormal conditions short circuit over temperature etc Outline Common source stage Common emitter stage Summary ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 050 7 CE and CS Output Stages 123101 Page 05072 COMMON SOURCE OUTPUT STAGE Current source load inverter VDDV55 l VOUT RL 2 85 R L dominates i 5 as the load line D m IR 1 V I V VDD V55 7777777777777 77 IQ A Class A circuit has current ow in the MOSFETs during the entire period of a sinusoidal signal Characteristics of Class A ampli ers Unsymmetrical sinking and sourcing Linear Poor efficiency VOUrtpeak2 VOUnpeak2 PRL ZRL ZRL V0Ujfp63k2 Ef Clency PSuppy VDD VSS1 Q VDDV53 L VDD VSS J VDD VSSTJ Maximum efficiency occurs when VOU peak VDD IVSSI which gives 25 ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 050 7 CE and CS Output Stages 123101 Page 05073 Specifying the Performance of a Common Source Amplifier Output resistance 1 l W gds1 gdsz AH131D Current Maximum sinking current is 1W1 IOUTTVDD VSS VT12IQ Maximum sourcing currentis K 2W2 IOUTWVDD V002 V7202 S 1Q Requirements Want rout ltlt RL 39 IIOU gt CLSR VOU peak 39 IIOUll gt RL The maximum current will be determined by both the current required to provide the necessary slew rate C L and the current required to provide a voltage across the load resistor RL ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 050 7 CE and CS Output Stages 123101 Page 05074 SmallSi nal Performance of the Class A Am lifier Although we have considered the small signal performance of the Class A amplifier as the current source load inverter let us include the in uence of the load The modified small signal model I C1 I c t gt gt gt I v lt lt lt m gmlvm rds1ltgt rds2 ltgt RL ltgt C2 Vout quot 3 Fig 050 02 The small signal voltage gain is Vout 8 m 1 Vin gdslgdSZGL The small signal frequency response includes A zero at gml Z ngr and a pole at gds1gds2GL P ng1ng2delde2CL ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 050 7 CE and CS Output Stages 123101 Page 05075 Example 551 Design of a Simple ClassA Output Stage Use the values ofKN 110tIAV2 K p 50tIAV2 V7N07V and VTP 07V and design the WL ratios of M1 and M2 so that a voltage swing of i2 volts and a slew rate of El voltus is achieved if RL 20 k and CL 1000 pF Assume that VDD IVSSI 3 volts and VGGZ 0 volts Let the channel lengths be 2 pm and assume that ngl 100fF Solution Let us first consider the effects of RL and C L iOU peak 1000A and CLSR 109106 IOOOHA Since the slew rate current gtgt the current for RL we can safely assume that all of the current supplied by the inverter is available to charge CL Using a value of i1 mA 210UTIQ 4000 a L1 KN VDDIVSSI VTN2 110532 2pm and ZIOUT 2000 15 0111 L2 Kp VDD Veez IVTPI2 50232 2H1 The small signal performance of this amplifier is AV 821 VV includes RL 2019 ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 050 7 CE and CS Output Stages 123101 Page 05076 Broadband Harmonic Distortion The linearity of an amplifier can be characterized by its in uence on a pure sinusoidal input signal Assume the input is Vin0 Vp sin0t The output of an amplifier with distortion will be Vautw ale sin wt anp sin 2cot aan sinncut Harmonic distortion HD for the ith harmonic can be defined as the ratio of the magnitude of the ith harmonic to the magnitude of the fundamental For example second harmonic distortion would be given as a2 HDZ a Total harmonic distortion THD is de ned as the square root of the ratio of the sum of all of the second and higher harmonics to the magnitude of the first or fundamental harmonic Thus THD can be expressed as 2 2 2 a2 a3 an12 THD T The distortion of the class A amplifier is good for small signals and becomes poor at maximum output swings because of the nonlinearity of the voltage transfer curve for large signal swing ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 050 7 CE and CS Output Stages 123101 Page 05077 COMMON EMITTER OUTPUT STAGE Common Emitter Class A Output Stage V0 RLi l3 0 VIN RL2ltRL1 K t f 1ltsa gt Fig 050 03 Large signal characteristic lOUT 1Q 1C1 VOUT 10UT RL and 1C1 Isiexp v M VOUT RL Isiexp v IQ ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 050 7 CE and CS Output Stages 123101 Page 05078 Harmonic Distortion in the Common Emitter Output Stage Assume the input signal is VIN VBE1 Vin Substituting this in the expression on the last slide gives VIN VBE1 Islexp Vt IQ RL Islexp Vt exp Vt IQ IQ RL exp VI 71 Using the expansion of expx z 1 x x22 x36 gives VOUT RL V11 1amp2 1 2 3 VOUT 71QR Vt 2 Vt 6 Vt a1vina2vin a3vin where IQ RL IQ RL IQ RL 01 V 7 2 2Vl2 and a3 6W3 Suppose Vina Vpsincot then VOUjU a1 Vpsincot anP2 sinzat a3VP3 sin3cot a2V2 a3V3 alesincut 7L 1 c0s2cut 4L 3mm sin3cut 2 3 2 HD 11 1 lP d HD 11 1 LLYE 2 2 alVP 2a1 4Vt an 3 4 alVP 4a1 24 V For VP 05V HD2 125 and HD3 z 1 ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 290 7 Feedback Analysis using Return Ratio 32204 Page 29071 LECTURE 290 FEEDBACK CIRCUIT ANALYSIS USING RETURN RATIO READING GHLM 599613 Objective The objective of this presentation is 1 Illustrate the method of using return ratio to analyze feedback circuits 2 Demonstrate using examples Outline Concept of return ratio Closed loop gain using return ratio Closed loop impedance using return ratio Summary ECE 6412 7 Analog Integrated Circuit Design 7 II PE Allen 7 2002 Lecture 290 7 Feedback Analysis using Return Ratio 32204 Page 29072 Concept of Return Ratio Instead of using two port analysis return ratio takes advantage of signal flow graph theory The return ratio for a dependent source in a feedback loop is found as follows 1 Set all independent sources to zero 2 Change the dependent source to an independent source and define the controlling variable as sr and the source variable as st 3 Calculate the return ratio designated as RR srst Rest of feedback amplifier Rest of feedback ampli er Fig 290701 ECE 6412 7 Analog Integrated Circuit Design 7 II RE Allen 7 2002 Lecture 290 7 Feedback Analysis using Return Ratio 32204 Page 2903 Example 1 Calculation of Return Ratio Find the return ratio of the op amp with feedback shown if the input resistance of the op amp is ri the output resistance is r0 and the voltage gain is av Rs RF Vs 15g 290702 T Solution dvvrRs ri avRSri Vrr0RFRSIIri a RR vt rURFRSIIri ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 290 7 Feedback Analysis using Return Ratio 32204 Page 29074 ClosedLoo Gain Usin Return Ratio Consider the following general feedback amplifier Sr soc Soul gt o Sm Ste E kSic SOC Sou 39i 39 5 Rest of feedback amplifier Fig 29003 Note that sac kslC Assume the amplifier is linear and express sic and sum as linear functions of the two sources sin and sac Sic Bl Sin HSUC Saut d Sin BZSUC where Bl Bz and H are defined as B I I B Saut d H Sic 1 Sin soc0 Sin k0 2 SOC sm0 an SOC sm0 ECE 6412 7 Analog Integrated Circuit Design 7 11 RE Allen 7 2002 Lecture 290 7 Feedback Analysis using Return Ratio 32204 Page 29075 ClosedLoop Gain Using Return Ratio Continued Interpretation BI is the transfer function from the input to the controlling signal with k O Bz is the transfer function from the controlling signal to the output with Sm O H is the transfer function from the output of the dependent source to the controlling signal with Sm O and multiplied times a 1 d is defined as I I Sin soc0 Sin k0 d is the direct signal feedthrough when the controlled source in A is set to zero kO Closed loop gain sumSm can be found as Bl SiCBlsmHSUCBlsmkHSiC a Sin1kH Blsz Saut dsin BZSUC d Sin kBZSiC dsin 1 kH Sin M 31632 31632 g 2 A Sm 1kHd 1RRd 1RRd where RRkH andgBlsz gain from sin to sautifHOanddO ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 290 7 Feedback Analysis using Return Ratio 32204 Page 29076 ClosedLoop Gain Using Return Ratio Continued Further simplification i dJRR g gd1RR gdRR d RR d A1RRd 1RR 1RR1RR 1RR 1RR Defme i AwRRd RR d 30 AAoo 1RR 1RR Note that as RR 9 00 that A A00 A00 is the closed loop gain when the feedback circuit is ideal ie RR9 00 or k a 00 Block diagram of the new formulation Note that b RRAOO is called the effective gain of the feedback amplifier Fig 290 04 ECE 6412 7 Analog Integrated Circuit Design 7 11 RE Allen 7 2002 Lecture 290 7 Feedback Analysis using Return Ratio 32204 Page 2907 Exam le 2 Use of Return Ratio A roach to Calculate the ClosedLoo Gain Find the closed loop gain and the effective gain of the transistor feedback ampli er shown using the previous formulas Assume that the BJT gm 40mS r 5kg and r0 1M9 Solution The small signal model suitable 1F A1113 for calculating v v v A d d lm A ltgt gt gt DO an ls Sin 4 rnltgtvbe5lc r0 ltgt RCltgt V0Sout gt gt gt shown ngbe kSic Fig 29006 M I V0 I r a 1 Ace sin km im gmzm Remember thatA 1af a f as a a 00 V0 I l f EWFO R F Therefore Aw RF 20kg Sam I Va r71 Sin k0 agm0 r RFrUIIRC rallRC 5kg mlt1MQII10kmL42k9 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 290 7 Feedback Analysis using Return Ratio 32204 Page 2908 Example 2 Continued What is left is to calculate the RR A small signal model for this is shown below R A AFR a v v v 1 ltgt ltgt ltgt r vbevr hi RCgt V0 gmvbe ngt I Fig 29007 rUIIRC vr rallRC vr ngI r RFrURC 7r a Vt quotgmrn r RFrUIIRC r0 RC amp rn39l39RF l39rallRC 200 5k920k91M 2l10kQ 5674 Now the closed loop gain is found to be Vr RR w gmr RR d 5674 14m A Am 1 RR 1 R 20k9 1 5674 1 5674 496 The effective gain is given as b RRAOO 5674 20k 2 ll35kQ ECE 6412 7 Analog Integrated Circuit Design 7 11 RE Allen 7 2002 Lecture 290 7 Feedback Analysis using Return Ratio 32204 Page 29079 ClosedLoo Im edance Formula usin the Return Ratio Blackman s Formula Consider the following linear feedback circuit where the impedance at port X is to be calculated Rest of feedback amplifier Fig 29008 Expressing the signals vx and sic as linear functions of the signals ix and sy gives vx alix azsy Sic a3ix a4sy The impedance looking into port X when k O is Z k 0 E E part ix k0 ix Sy0 ECE 6412 7 Analog Integrated Circuit Design 7 II PE Allen 7 2002 Lecture 290 7 Feedback Analysis using Return Ratio 32204 Page 290710 ClosedLoop Impedance Formula using the Return Ratio Continued Next compute the RR for the controlled source k under two different conditions 1 The first condition is when port X is open ix O Sic a45y a45t Also 5 r Sr ksic sr M45 9 RRport open S7 M4 2 The second condition is when port X is shorted vx O dz 02 lx asyast a2a3 614 T Sic a31x 045 S The return signal is 0203 Sr ksic ka4 7 3 The port impedance can be found as Blackman s formula a2a3 E 1 39 k 4 39 a1 1 RRport shorted 4 Zport ix a1 1 a4 gt ZPOIT ZPOITkOi l RRport open Sr a2a3 s a RRport shorted S7 lta4 a1 ECE 6412 7 Analog Integrated Circuit Design 7 II RE Allen 7 2002 Lecture 290 7 Feedback Analysis using Return Ratio 32204 Page 290711 Example 3 Application of Blackman s Formula Use Blackman s formula to calculate the output resistance of Example 2 Solution RF We must calculate three quantities They are NV 0 Rautgm0 RRoutput port shorted and ltgt ltgt RRoutput port open Use the following r V552 r0ltgt RCltgt V0 model for calculations gmvbe gmvl Rautgm0 rUIIRCIIrnRF 70918 Fig 29007 RRoutput port shorted 0 because vr O RRoutput port open RR of Example 2 5674 1 RRport shorted 1 Ram Raur8m0 1 RRport open 1 709k9 15674 1299 ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 290 7 Feedback Analysis using Return Ratio 32204 Page 290712 Exam le 4 Out ut Resistance of a Su erSource Follower Find an expression for the small signal output resistance of the circuit shown Solution The appropriate small signal model is shown where gmz k V2 gt V ngVZ ltgt V outDVm rdsl quot out V1 vr gm2V1 rm 39 39 gm2Vt 39 Fig 290710 Rautgm20 rdsz and RRoutput port shorted 0 because V 0 Sr Vr RRoutput port open S7 V t Vr Vout gmlv2rdsl Vout gmlrds139vout Vout1 gmlrdsl Vout 39 ngrdSZVt a Vr quot1 gmlrdslgm2rds2vt Vr RR0utput port Open VI 1 gmirds1gm2rds2 1 RRport shorted 10 1 RUMIRUWgm2O1 1 RMPOrt Open J rdSZL11 gm1rds1gm2rdszJ z gmlrdslng ECE 6412 7 Analog Integrated Circuit Design 711 PE Allen 7 2002 Lecture 190 7 Cascode Op Amps 7 I 21802 Page 19071 LECTURE 190 CASCODE 0P AMPS I READING GHLM 443453 AH 293309 Objective The objective of this presentation is 1 Develop cascode op amp architectures 2 Show how to design with the cascode op amps Outline Op amps with cascoding in the first stage Op amps with cascoding in the second stage Folded cascode op amp Summary ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 190 7 Cascode Op Amps 7 I 21802 Page 19072 Why Cascode Op Amps Control of the frequency behavior Can get more gain by increasing the output resistance of a stage In the past section PSRR of the two stage op amp was insufficient for many applications A two stage op amp can become unstable for large load capacitors if nulling resistor is not used We will see in future sections that the cascode op amp leads to wider ICMR andor smaller power supply requirements WM First stage Good noise performance Requires level translation to second stage Degrades the Miller compensation Second stage Self compensating Increases the efficiency of the Miller compensation Increases PSRR ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 190 7 Cascode Op Amps 7 I 21802 Page 19073 Use of Cascodin in the First Sta e of the TwoSta e 0 Am Implementation of the VDD oating voltage VBiaS Rout 0f the first stage is R1 ngZrdSCZrds2lIng4rdsC4rds4 V 1 Voltage gain gm1R1 The gain is increased by approximately 05gMCrdSC As a single stage op amp the compensation capacitor becomes the load capacitor ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 190 7 Cascode Op Amps 7 I 21802 Page 19074 Example 1 SingleStage Cascode Op Amp Performance Assume that all WL ratios are 10 urnl Mm and that IDSl IDSZ 50 MA of single stage op amp Find the voltage gain of this op amp and the value of C if GB 10 MHZ Use the model parameters of Table 31 2 Solution The device transconductances are gml ng ng 3317 tus ngZ 3317115 ng4 2236 MS The output resistance of the NMOS and PMOS devices is 05 M9 and 04 M9 respectively R1 25 M9 AV0 8290 VN For a unity gain bandwidth of 10 MHZ the value of C1 is 528 pF What happens if a 100pF capacitor is attached to this op amp GB goes from lOMHz to 053MHZ ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 190 7 Cascode Op Amps 7 I 21802 Page 19075 TwoStage Op Amp with a Cascoded FirstStage VBias Fig 6572 MT1 and MT2 are required for level shifting from jm the first stage to the second The PSRR is improved by the presence of MT1 13 m m Internal loop pole at the gate of M6 may cause the Miller compensation to fail The voltage gain of this op amp could easily be lO0000VV Z1 Fig 552 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 190 7 Cascode Op Amps 7 I 21802 Page 19076 TwoStage Op Amp with a Cascode SecondStage Fig 6573 Av ngngIRIRII Where ng gmr ng ngI gm67 l 2 R1 m m and RH ng6rdsC6rds6llng7rdsC7rds7 Comments The second stage gain has greatly increased improving the Miller compensation The overall gain is approximately gmrds3 or very large Output pole p2 is approximately the same if CC is constant The RHP is the same if Cc is constant ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 190 7 Cascode Op Amps 7 I 21802 Page 19077 ABalanced TwoSta eO Am usin aCascode Out ut Sta e gmlgm8Vzl gm28m6Vzl gm3 2 gm4 2 ml gm2 R11 Voul 77 kVin R11 gm1kRH Vin where R11 gm7rds7rds6gm12rds12rds11 and w 816 gm3 gm4 Note that this op amp is balanced because the drain to ground loads for M1 and M2 are identical Fig 654 TABLE 1 Pertinent Design Relationships for Balanced Cascode Output Stage Op Amp out gmlgm8 1 gmlgMS gngm6 Slew rate CL gm3CL Av 2 gt3 gm4 H 15 12 15 1a mmax VDD B IVT03maX Vnm1n mm1n V55 VDSS B Vnm1n ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 190 7 Cascode Op Amps 7 I 21802 Page 19078 Wv39mm39n 2 Design of C Output Stage OD Amn The balanced cascoded output stage op amp is a useful alternative to the two stage op amp Its design will be illustrated by this example The pertinent design equations for the op amp were given above The specifications of the design are as follows VDD VSS 25 V Slew rate 5 Vys with a 50 pF load GB 10 MHz with a 10 pF load AV 2 5000 Input CMR 1V to 15 V Output swing 15 V Use the parameters of Table 31 2 and let all device lengths be 1 tan Solution While numerous approaches can be taken we shall follow one based on the above specifications The steps will be numbered to help illustrate the procedure 1 The first step will be to find the maximum sourcesink current This is found from the slew rate sourcesink C L x slew rate 50 pF5 VMs 250 MA 2 Next some WL constraints based on the maximum output sourcesink current are developed Under dynamic conditions all of 15 will flow in M4 thus we can write Max outsource S6S4I5 and Max 10msink SgS3I5 The maximum output sinking current is equal to the maximum output sourcing current if S3 54 S6 58 and 510 511 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 190 7 Cascode Op Amps 7 I 21802 Page 19079 Example 2 Continued 3 Choose 5 as 100 MA This current which can be changed later gives S6 2554 and Sg 2553 Note that Sg could equal S3 if S11 25510 This would minimize the power dissipation 4 Next design for 15 V output capability We shall assume that the output must source or sink the 250MA at the peak values of output First consider the negative output peak Since there is 1 V difference between V55 and the minimum output let VD511sat VD512sat 05 V we continue to ignore the bulk effects Under the maximum negative peak assume that 11 112 250 MA Therefore 2111 2112 SOOMA 0 5 K39N511 K39N512 HOtAVZ511 which gives S11 S12 182 and 9 S10 182 For the positive peak we get 216 217 500 MA 05 K39ps6 K39ps7 50 MAV2S6 which gives S6 S7 Sg 40 and S3 S4 4025 16 5 Next the values of R1 and R2 are designed For the resistor of the self biased cascode we can write R1 VD512sat250pA 2kg and R2 VSD7sat250uA 2kg ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 190 7 Cascode Op Amps 7 I 21802 Page 190710 Example 2 Continued Using this value of R1 R2 will cause M11 to slightly be in the active region under quiescent conditions One could redesign R1 to avoid this but the minimum output voltage under maximum sinking current would not be realized 6 Now we must consider the possibility of con ict among the specifications First consider the input CMR S3 has already been designed as 16 Using ICMR relationship we find that S3 should be at least 41 A larger value of S3 will give a higher value of Vmmax so that we continue to use S3 16 which gives Vmmax 195V Next check to see if the larger WL causes a pole below the gainbandwidth Assuming a CM of 04fF1Im2 gives the first stage pole of gm3 2K PS313 p3 cgs3CgS8 0667W3L3W8L8C0x 3315X109 radssec 01 5275GHZ which is much greater than 10GB 7 Next we find gm1 gmz There are two ways of calculating gm1 a The first is from the AV specification The gain is Av gm128m4gm6 ng RH Note a current gain of k could be introduced by making 5654 5853 51153 equal to k git gm11 2KP S616 k gm4 gm3 2KP S414 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 190 4 Cascode Op Amps 7 I 21802 Page 190711 Example 2 Continued Calculating the various transconductances we get gm4 2824 MS gm6 gm7 gmg 707 MS gmll gmlz 707 MS mm M7 016 M9 and rdsll rdslz 02 M9 Assuming that the gain AV must be greater than 5000 and k 25 gives gml gt 7243 MS b The second method of finding gml is from the GB specifications Multiplying the gain by the dominant pole lCHRH gives gm1gm6 ng 2gm4CL Assuming that C L 10 pF and using the specified GB gives gml 251 MS GB Since this is greater than 7243uS we choose gml gmz 251uS Knowing 15 gives 51 52 1145 12 8 The next step is to check that 51 and 52 are large enough to meet the 1V input CMR specification Use the saturation formula we find that VDS5 is 05248 V This gives S5 66 7 The gain becomes AV 6925VV and GB 10 MHZ for a 10 pF load We shall assume that exceeding the specifications in this area is not detrimental to the performance of the op amp 9 With S5 7 then we can design 513 from the relationship 113 125nA 513 15 55100nA 875 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 190 4 Cascode Op Amps 7 I 21802 Page 190712 Example 2 Continued 10 Finally we need to design the value of VBlas which can be done with the values of S5 and 15 known However M5 is usually biased from a current source owing into a MOS diode in parallel with the gate source of M5 The value of the current source compared with 15 would define the WL ratio of the MOS diode Table 2 summarizes the values of WL that resulted from this design procedure The power dissipation for this design is seen to be 2 mW The next step would be begin simulation Table 2 Summary of WL Ratios for Example 2 S1S212 S3S416 S57 565758 SlASls4O SQ SIOSHSIZ 182 S13875 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 190 7 Cascode Op Amps 7 I 21802 Page 190713 T 39 39 39 39 quot quot of the Cascade Configuration A Bo C o I L D p substratewell Fig 6575 If a double poly CMOS process is available internode parasitics can be minimized As an alternative one should keep the drainsource between the transistors to a minimum area Minimum Poly A B o B separation W a 00 1 p substratewell ECE 6412 7 Analog Integrated Circuit Design 7 11 Fig 655A Lecture 190 7 Cascode Op Amps 7 I 21802 In PE Allen 7 2002 ut Common Mode Ran e for Two T Page 190714 es of Differential Am lifier Loads VDDVSD3VIN VDD Vss T Differential ampli er with a current mirror load Vss Differential ampli er with current source loads Fig 656 In order to improve the ICMR it is desirable to use current source sink loads without losing half the gain The resulting solution is the folded cascode op amp ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 190 7 Cascode Op Amps 7 I 21802 Page 190715 The Folded Cascode Op Amp We have examined the small signal performance and the frequency response in an earlier lecture ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 190 7 Cascode Op Amps 7 I 21802 Page 190716 PSRR of the Folded Cascode 0 Am Consider the following circuit used to model the PSRRz Vout VGSG Fig 6579A This model assumes that gate source and drain of M11 and the gate and source of M9 all vary with VSS We shall examine VowV33 rather than PSRR Small VowV will lead to large PSRR The transfer function of VowV can be found as Vaut Sng9R t nu Vss z SCUMIRUMI1 for ngg lt Com The approximate PSRR39 is sketched on the next page ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 190 7 Cascode Op Amps 7 I 21802 Page 190717 Frequency Response of the PSRR of the Folded Cascode Op Amp IPSRRI lT uu 39 10g1000 C 849 1 GB Cont Fig 6510A Other sources of Vss injection ie rdsg We see that the PSRR of the cascode op amp is much better than the two stage op amp ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 190 7 Cascode Op Amps 7 I 21802 Page 190718 Design Approach for the FoldedCascode Op Amp zero Maximum output VSDsSat VSD7sat voltage vom max KP KP Let 84 8 14 8 5 amp 05VDDV0mrr1in S13Sc3S7 Minimum output VD59sat VDSHSat voltage vougmjn 511 KNV 7 59 KNV Let 10 11 amp 05V0mrninIVSSI GB Minimum input CM Of Maximum iIlpllt CM exceed the value in step 3 Differential Voltage Gain ngRom Power ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 190 7 Cascode Op Amps 7 I 21802 Page 190719 Example 3 Design of a FoldedCascode Op Amp Follow the procedure given to design the folded cascode op amp when the slew rate is IOVus the load capacitor is IOpF the maximum and minimum output voltages are iZV for 25V power supplies the GB is IOMHZ the minimum input common mode voltage is 715V and the maximum input common mode voltage is 25V The differential voltage gain should be greater than 5000VV and the power dissipation should be less than SmW Use channel lengths of lum Solution Following the approach outlined above we obtain the following results 13 SRCL10x1061O 11100uA Select 14 15 125uA Next we see that the value of 05VDD V0mmax is 05V2 or 025V Thus 2125uA 212516 S4 55 S14 SOuAVZO25V2 50 8 and assuming worst case currents in M6 and M7 gives 2125uA 212516 56 57 513 SOuAV2O25V2 50 80 The value of 05V0utmin IVSSI is also 025V which gives the value of S8 S9 S10 and S11 23918 2125 as Sg 59 510 SH KN VDSgZ 3636 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 190 7 Cascode Op Amps 7 I 21802 Page 190720 Example 3 Continued The value of R1 and R2 is equal to 025V125uA or 2kg In step 6 the value of GB gives S1 and S 2 as GBZCL2 2075x1062lO112 51Szwm359 The minimum input common mode voltage defines S3 as 213 200x10 6 S3 20 I3 2 6 100 2 KN Vinmmvsy m VT1 110x10 1525 110359 7075 We need to check that the values of S4 and S5 are large enough to satisfy the maximum input common mode voltage The maximum input common mode voltage of 25 requires 214 2125uA S4 55 Z KP VDD VmmaxVT1 SOxlO6uAV2O7V2 102 which is much less than 80 In fact with S4 S5 80 the maximum input common mode voltage is 3V Finally S12 is given as 125 512 m S3 25 The power dissipation is found to be Pdiss 5V125uA125uA125uA1875mW ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 190 7 Cascode Op Amps 7 I 21802 Page 190721 Example 3 Continued The small signal voltage gain requires the following values to evaluate S4 55 513 514 gm 21255080 rooops and gds 125x106O05 625uS S6 57 gm 275508O 7746uS and gds 75x106O05 375115 Sg 59 510 Sn gm I2751103636 7746uS and gds 75x106OO4 3118 5152 gm 250110359 628uS and gds 50x10 6004 2115 Thus 1 1 RH z gmgrdsgrdsll 7746pS 8607MQ 1 1 Ram z 8607MQII7746HSWW 194OMQ k RIIgds2gds4 8607MQ2HS625uS375pS HS gm7rds7 7746 The small signal differential input voltage gain is 2k 234375 Avd ngRm 0628x103194Ox106 7464 VV The gain is larger than required by the specifications which should be okay 34375 ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002 Lecture 190 7 Cascode Op Amps 7 I 21802 Page 190722 Comments on Folded Cascode Op Amps Good PSRR Good ICMR Self compensated Can cascade an output stage to get extremely high gain with lower output resistance use Miller compensation in this case Need first stage gain for good noise performance Widely used in telecommunication circuits Where large dynamic range is required ECE 6412 7 Analog Integrated Circuit Design 7 11 PE Allen 7 2002

### BOOM! Enjoy Your Free Notes!

We've added these Notes to your profile, click here to view them now.

### You're already Subscribed!

Looks like you've already subscribed to StudySoup, you won't need to purchase another subscription to get this material. To access this material simply click 'View Full Document'

## Why people love StudySoup

#### "Knowing I can count on the Elite Notetaker in my class allows me to focus on what the professor is saying instead of just scribbling notes the whole time and falling behind."

#### "Selling my MCAT study guides and notes has been a great source of side revenue while I'm in school. Some months I'm making over $500! Plus, it makes me happy knowing that I'm helping future med students with their MCAT."

#### "There's no way I would have passed my Organic Chemistry class this semester without the notes and study guides I got from StudySoup."

#### "It's a great way for students to improve their educational experience and it seemed like a product that everybody wants, so all the people participating are winning."

### Refund Policy

#### STUDYSOUP CANCELLATION POLICY

All subscriptions to StudySoup are paid in full at the time of subscribing. To change your credit card information or to cancel your subscription, go to "Edit Settings". All credit card information will be available there. If you should decide to cancel your subscription, it will continue to be valid until the next payment period, as all payments for the current period were made in advance. For special circumstances, please email support@studysoup.com

#### STUDYSOUP REFUND POLICY

StudySoup has more than 1 million course-specific study resources to help students study smarter. If you’re having trouble finding what you’re looking for, our customer support team can help you find what you need! Feel free to contact them here: support@studysoup.com

Recurring Subscriptions: If you have canceled your recurring subscription on the day of renewal and have not downloaded any documents, you may request a refund by submitting an email to support@studysoup.com

Satisfaction Guarantee: If you’re not satisfied with your subscription, you can contact us for further help. Contact must be made within 3 business days of your subscription purchase and your refund request will be subject for review.

Please Note: Refunds can never be provided more than 30 days after the initial purchase date regardless of your activity on the site.