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# Analog Integra Circuits ECE 4430

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This 0 page Class Notes was uploaded by Cassidy Effertz on Monday November 2, 2015. The Class Notes belongs to ECE 4430 at Georgia Institute of Technology - Main Campus taught by Staff in Fall. Since its upload, it has received 114 views. For similar materials see /class/233922/ece-4430-georgia-institute-of-technology-main-campus in ELECTRICAL AND COMPUTER ENGINEERING at Georgia Institute of Technology - Main Campus.

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Lecture 030 7 ECE4430 Review 111 122901 Page 03071 LECTURE 030 ECE 4430 REVIEW III READING GHLM Chaps 3 and 4 Objective The objective of this presentation is 1 Identify the prerequisite material as taught in ECE 4430 2 Insure that the students of ECE 6412 are adequately prepared Outline 0 Models for Integrated Circuit Active Devices Bipolar MOS and BiCMOS IC Technology Sin gle Transistor and Multiple Transistor Amplifiers Transistor Current Sources and Active Loads ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 030 7 ECE4430 Review 111 122901 Page 03072 SINGLETRANSISTOR AND MULTIPLETRANSISTOR AMPLIFIERS Characterization of Amplifiers Amplifiers will be characterized by the following properties Large signal voltage transfer characteristics DC Large signal voltage swing limitations DC and TRAN Small signal frequency independent performance TF Gain TF Input resistance TF Output resistance TF Small signal frequency response AC Other properties TEMP FOUR etc Noise NOISE Power dissipation OP Slew rate TRAN Etc ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 030 7 ECE4430 Review 111 122901 Page 03073 Tvnes of Single Transistor Amplifiers VCC VCC VCC VCC RC v R C R C IN VOUT VOUT VOUT VOUT VIN VIN RE T RE VIN Common Emitter Common Base Common Collector Emitter Degeneration VDD VDD VDD VDD VIN RD v RD RD OUT VOUT VOUT VOUT VIN VIN 0 1 LI RS T RS VIN Common Source Common Gate Common Drain Source Degeneration Fig 03001 ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 030 7 ECE4430 Review III 122901 Page 03074 Si nal Flow in Transistors It is important to recognize that ac signals can only ow into and out of certain transistor terminals Illustration C D W 1800 B 0 G o I 0 A R E S Fig 030 02 Rules The collector or drain can never be an input terminal The base or gate can never be an output terminal In addition it is important to note polarity reversals on these signal paths The base collector or gate drain path inverts All other paths are noninverting This of course assumes that there are no reactive elements causing phase shifts ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 030 7 ECE4430 Review 111 122901 Page 03075 Common Emitter Amplifer39 Large Signal ic V0 T VCC VCC VCC Forward RC i Active VOUT RC T Region VIN IB VIN E 393 Saturation vCEsat Region T Common Emitter Va 0 39 u U 39 o VCC 0 05V 10V P13030703 Small Signal Rm i 1 Ram in out B 039 o C I V C d A Vm Vout gm Vt an r 0 1C E o o E Fig 030704 B0 roRC Vout gm ro RC lam Bo ro Rln r gm7 Rout r0RC7 Vin r0RC and r0RC One should also consider the case of a source resistance RS in series with the input ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 030 7 ECE4430 Review 111 122901 Page 03076 Common Source Am lifier39 Large Signal v V V lD DS I GS T VOUT Cutoff Region VDD VDD Saturation RD VOUT VIN Region 0 1 Fig030705 U 390 VT VDD 1 Small Signal R v R m lin lom lam Go 3 D 4quot ltgt R ltgt Vin ngm rdsgt D gt Vom gt gt S c S Fig 030055 rdsRD Voul gm rds RD lam Rm 7 R01 rds RD Vin rds RD and iin ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Page 03077 Lecture 030 7 ECE4430 Review 111 122901 Summary of Single B IT Transistor Amplifiers Small Signal Common Common Common Collector Perfonnance Emitter Base Input Resistance r75 r77 r 13 R Low 0 E Medlum 1 30 High Rs Output Res1stance 0 ro1 o L ngh Very high 130 Very low Voltage Gain 7ngL ngL 1 Current Gain 30 a 1 0 ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 LectuIe 030 7ECE4430 Review III 122901 Page 03078 Summary of Single MOSFET Transistor Amplifiers SmallSignal Common Common Common PCTfOImaHCC Source Gate Drain Input Resistance 00 rdS l39RD Do 1quot39gmrds Output Resistance rdsRD rdsRD RS rds RD rdsR D 1ngS Voltage Gain gm rds RD ng D 08 rds RD Current Gain 0 71 x ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 030 7 ECE4430 Review 111 122901 Page 03079 B IT Cascode Amplifer Circuit and small signal model Va Vom i C1 E2 r02 3 C2 1 gt gt gt r01gt VagtVTEZ Vout jgt RL rm gszrcz T E 132 Fig 03006 If 31 z 32 and r0 can be neglected then Rm rm Rant B2r 02 Voul Voul Va 3 Bol W 7 a ngRL TB r l z gmzRL 1 ngRL iom ii 06231 The advantage of the cascode is that the gain of Q1 is 71 and therefore the Miller capacitor C 39u is not translated to the base emitter as a large capacitor ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 030 7 ECE4430 Review 111 122901 Page 030710 MOS Cascode Amplifier C1rcu1t and small vow gmzvgsz 78mm s1gnal model M2 G1 0 Small s1gnal Vin L D V performance M1 VBias v0 V s1 gmlv s1 1 g g SlG2G3 assuming a load T T Fig 030707 resistance in the drain of RL Rin Using nodal analysis we can write gdsr gdsz gmzlvr gdsZVout 39glein and gds2 gmzlvr gdsz GLVout 0 Solving for VOWVin yields M gmlgds2 ng Vin gdsrgdsz gderL gdszGL GLgmz Note that unlike the BJT cascode the voltage gain v1vin is greater than 71 V1 A H rds2RL rds2RL 1 RL Vin quotgm 132 1gm2rds2 rdsz quot rds2 The small signal output resistance is romrds1 rdsZ gm2rds1rds21RLERL ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 398 1 E a Z39gmlRL RL lt rdsz for the gain to be 71 Lecture 030 7 ECE4430 Review 111 122901 Page 030711 Tl Characteristic of the BJT Differential Amplifier Consider the following NPN BJT differential amplifier i i sometimes called an emitter coupled pair iC1 l licz Large Signal Analysis 1 Input loop eq V11 VBE1VBE2 V12 VIl VIZ VBEl VBE2 VID39VBEl39l39VBEZ 0 2 Forward active region VEE Fig 0303908 lC1 lC2 VBE1 V 111 1 and VBE2 V 111 S2 12 mm VID 3 If 51 152 then i 2 exp VI exp VI 1 4 Nodal current equation at the emitters 7iE1iE2 I EE a F ic1 iCZ FIEE FIEE 5 Combmmg the above equatlons gives 1C1 VID and 1C2 VID 1 expTlJ 1 exp ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 030 7ECE4430 Review 111 122901 Page 030712 Differential and Commonmode SmallSignal B IT Ampli er Performance The small signal performance of a differential amplifier can be separated into a differential mode and common mode analysis This separation allows us to take advantage of the following simpli cations HalfCircuit Concept Fig03009 Note The half circuit concept is valid as long as the resistance seen looking into each emitter is approximately the same ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 030 7 ECE4430 Review III 122901 Page 030713 Tl Performance of the Differential Amplifier Consider the following n channel differential amplifier 1 VDD M1 39liDl l39DZlI M2 VGZ VGSZ I ijulk T Fig 03010 Where should bulk be connected Consider a p well CMOS technology D1 G1 Sl S2 G2 D2 VDD la uh w t 39 39 r39 Fig 030711 1 Bulks connected to the well No modulation of VT but large common mode parasitic capacitance 2 Bulks connected to ground Smaller common mode parasitic capacitors but modulation of VT If the technology is n well CMOS the bulks must be connected to ground ECE 6412 7 Analog Integrated Circuits and Systems II PE Allen 7 2002 Lecture 030 7 ECE4430 Review III 122901 Page 030714 Tl Performance of the Differential Ampli er Continued Defining equations Assume that the MOSFETs are in saturation 21131 12 2iD2 12 VID VGSI VGSZ T T3 and SS lD1 lD2 Solution i ISSISS 31215 31V4iD12 and l ISSISS VDBi D2 D1 2 2 155 4115 D2 2 2 SS 4 SS which are valid for VID lt 2ISS 12 Illustration of the result quot 39 39 I l 139 r VID 20 1414 1414 20 ISS 05Fig 03012 ECE 6412 7 Analog Integrated Circuits and Systems II PE Allen 7 2002 Lecture 030 7 ECE4430 Review III 122901 Page 030715 Differential and Commonmode SmallSi nal Performance The small signal performance of a differential amplifier can be separated into a differential mode and common mode analysis This separation allows us to take advantage of the following simpli cations HalfCircuit Concept VDD lt lt gt RD gt gtRD Vi gt e wl i 0865 99 93W ldl l lzdz ode A V01 V02 3 a V111 i Mi Vil Vg1 T T Vg2 Viz Iss RSS Vss s Vs Fig030713 Note The half circuit concept is valid as long as the resistance seen looking into each source is approximately the same ECE 6412 7 Analog Integrated Circuits and Systems II PE Allen 7 2002 Lecture 030 7 ECE4430 Review III 122901 Page 030716 Other Characteristics of the Differential Am lifier Common mode rejection ratio Input common mode range Slew rate BJT I CMR The maximum and minimum input common mode range is vicmax VCC 051EERC vCE1satVBE1 Vicmin VEEVCE3SatVBE1 SR The differential amplifier has a slew rate limit of I EE Ceq where Ceq is the capacitance seen to ground from either collector MOSFET I CMR The maximum and minimum input common mode range is Vicmax VDD OSISSRD VT1 Vicmin VssVDs3SatVGsr SR The differential amplifier has a slew rate limit of 155 Ceq where Ceq is the equivalent capacitance seen from either of the drains to ground ECE 6412 7 Analog Integrated Circuits and Systems II PE Allen 7 2002 Lecture 030 7 ECE4430 Review 111 122901 Page 030717 TRANSISTOR CURRENT SOURCES AND ACTIVE LOADS Summary of Current Sinks and Sources Cascode Current Sink Current SinkSource rOUT VMIN Sim le MOS Current Sink l p rdS m VDS530 VON Simple B T Current Sink VA r0 F VCEsat 2 02V Cascode z gmzrdszrdsl Cascode BJT z Fro 2VCESat Minimum VMIN Cascode z gmzrdszrdsl 2V0N Current Sink 11113th CaSCOde Current 3 rds3gm3rdszgm4rds4llrdss z VT V0N in M39 39 V R l t d mmum MIN egu a e z rds3gm3rdszgm4rds4llrdss VON ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 030 iECE4430 Review 111 122901 Page 030718 Summary of MOS Current Mirrors Current Accuracy Output Input Minimum Minimum Mirror Resistance Resistance Output Input Voltage Voltage Simple Poor rds gi VON VT VON m Cascode Excellent gm rdSZ gi VT2 VON 2VT VON m Wide Output Excellent g rd 2 L 2V0N V1V0N Swing m S gm Cascode Self biased Excellent gm rdsz R L 2V0 N V12V0 N Cascode gm Wilson Poor gm rdSZ gi 2VT VON VT2 VON m Regulated Good gmzrd53 L VTQVQN VON Cascode Excellent gm mm ls mm is VON 2V0N ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 030 7 ECE4430 Review 111 122901 Page 030719 Summar of B T Current Mirrors Current Accuracy Output Input Minimum Minimum Mirror Resistance Resistance Output Input Voltage Voltage Simple Poor r 0 8L VCE330 VBE m Cascode Excellent FrO VCE330VBE 2VBE m Wide Output Excellent 31 L 2VCEsat VBE Swing gm Cascode Self biased Excellent FrO R L 2VCEsat VCEsatVBE Cascode gm Wilson Poor FrO 8i VCE330VBE VCE530VBE m Regulated Good BFr 0 L or 16 S S VCEsat VCEsat Cascode Excellent gm One can design the regulated cascode so that effectively the minimum value of VMIN out is just VCEsat ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 030 7 ECE4430 Review 111 122901 Page 030720 Active Load Amplifiers What is an active load amplifier GD i 39 MOS39Loaris 39 Bias Bias I I 11 I 0 1 I o VT o o ZVONI O I O I II I I I I vequ 1 I MOS Transconductors BIT Transconductors Fig 03014 It is a combination of any of the above transconductors and loads to form an amplifier Remember that the above are only some of the examples of transconductors and loads ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 030 7 ECE4430 Review 111 122901 Page 030721 B IT Differential Amplifier with a Current Mirror Load Design Considerations Constraints Speci cations Power supply Small signal gain Technology Frequency response C L Temperature ICMR Slew rate C L Power dissipation Relationships Av gmlRoul w 3dB 1R0utCL Fig 030715 5V wdmax VCC VBE3 VCE1Sat VBE1 z VCC VCE1Sat VICmin VEE VCE5Sat VBE1 SR I 1515 C L Pdiss VCCIVEEIA11 dc currents owing from VCC or to VEE ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 030 7 ECE4430 Review 111 122901 Page 030722 CMOS Differential Ampli er with a Current Mirror Load Design Considerations Constraints Speci cations Power supply Small signal gain Technology Frequency response C L Temperature ICMR Slew rate C L Power dissipation Relationships Av gmlRoul w 3dB 1R0utCL VICmaX VDD VSG3 VTN1 T VSS Fig 030716 VICmi VDssSat VGSl V0356 VGsz SR I 55 C L Pdiss VDDVsslAll dc currents owing from VDD or to VSS ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 030 7 ECE4430 Review 111 1904 Page 0301 LECTURE 030 ECE 4430 REVIEW III READING GHLM Chaps 3 and 4 Objective The objective of this presentation is 1 Identify the prerequisite material as taught in ECE 4430 2 Insure that the students of ECE 6412 are adequately prepared Outline 0 Models for IntegratedCircuit Active Devices Bipolar MOS and BiCMOS 1C Technology 0 SingleTransistor and MultipleTransistor Ampli ers Transistor Current Sources and Active Loads ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 030 7 ECE4430 Review 111 1904 Page 0302 SINGLETRANSISTOR AND MULTIPLETRANSISTOR AMPLIFIERS Characterization of Ampli ers Ampli ers will be characterized by the following properties 0 Largesignal voltage transfer characteristics DC 0 Largesignal voltage swing limitations DC and TRAN Smallsignal frequency independent performance TF 0 Gain TF 0 Input resistance TF 0 Output resistance TF Smallsignal frequency response AC 0 Other properties TEMP FOUR etc 0 Noise NOISE 0 Power dissipation OP 0 Slew rate TRAN Etc ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 030 7 ECE4430 Review 111 1904 Types of Single Transistor Ampli ers VCC RC V0 UT VIN Co mmon Emitter VDD RD V0 UT VIN Common Source VCC RC VOUT VIN Common Base VDD RD VOUT JII VIN Common Gate ECE 6412 Analog Integrated Circuits and Systems 11 VIN VOUT RE Common Collector VDD VIN V0 UT RS Common Drain Page 03 03 V0 UT VIN RE Emitter Degeneration VDD VOUT VIN RS Source Degeneration Fig 03001 PE Allen 2002 Lecture 030 7 ECE4430 Review III 1904 Page 0304 Si nal Flow in Transistors It is important to recognize that ac signals can only ow into and out of certain transistor terminals Illustration D 0 G o I 0 A S Fig 030 02 Rules The collector or drain can never be an input terminal The base or gate can never be an output terminal In addition it is important to note polarity reversals on these signal paths The basecollector or gatedrain path inverts All other paths are noninverting This of course assumes that there are no reactive elements causing phase shifts ECE 6412 Analog Integrated Circuits and Systems II PE Allen 2002 Lecture 030 7 ECE4430 Review 111 1904 Page 03 0 5 Common Emitter Amplifer LargeSignal VCC RC VOUT VIN Common Emitter SmallSignal 1C ngVZ 30 Rm 2 r gm iC VOUT A VCC Vg iortuvard RC RC live eglon TVINJB I1 Saturatlon vCEsat Region 4 0 I VCE 0 I 1ylv 0 VCC 0 05V N Fig 03003 iom lout C V d A 7 0 RC Vout an 70 o E Fig 03004 R VORC Vout 39gm ro39RC d loul 3070 an f out Vol RC Vm Vol RC lm Vol RC One should also consider the case of a source resistance R5 in series With the input ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 030 7 ECE4430 Review 111 1904 Page 0306 Common Source Am li er LargeSignal V V 1D VDS GS T VOUT Cutoff Region VDD VDD Saturation Region 1 RD V2 VOUT RD E lVIN 43 Triode VIN I3 393 E Region I i z I I T x v D 1 Fig 03005 0 I 0 VDD DS 0 I0 VT VDD VIN SmallSignal Rm Rout lm 1out I G D 4 Vin gmvin rds RD Vout S 6 5 S Fig 030055 rdsRD Vout 39gm Vds39RD loul Rm 00 Rom Va s RD Vin Vds RD an iiil ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 030 7 ECE4430 Review 111 1904 Page 0307 Summary of Single BJ T Transistor Ampli ers SmallSignal Common Common Common Collector Performance Emitter Base Input Resistance 7 r V 13 RE Medium 130 LOW Hig 39 7 0 Foal 30 PVC RS Output Res1stance High Very high HID Very low Voltage Gain ngL ngL 1 Current Gain 30 06 PF30 ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 030 7 ECE4430 Review 111 1904 Page 03 0 8 Summary of Single MOSFET Transistor Ampli ers SmallSignal Common Common Common Performance Source Gate Drain Input Resistance 00 w 00 1gm7 ds Output Resistance rdSRD rdSRD i rds RD rdSRD 1ngS Voltage Gain 39gm Vds RD ngD 0 8 rds RD Current Gain 00 1 00 ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 030 7 ECE4430 Review 111 1904 Page 0309 BJT Cascode Amplifer Circuit and smallsignal model Va Vout Q2 C1 E2 r02 Loicz 73901 Va V3172 Vout RL 52 gmzvnz c 39 T E12132 Fig 03006 If 31 z 32 and r0 can be neglected then Rm rarl Rout z 3 2r02 not including R L m m Va VH2 301 Vin Va Vin 2 ngRL 130239 r l ngRL 391 Z 39 ngRL iour 1m 06231 The advantage of the cascode is that the gain of Q1 is l and therefore the Miller capacitor C is not translated to the baseemitter as a large capacitor ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 030 7 ECE4430 Review 111 1904 Page 03010 MOS Cascode Ampli er Circuit and small signal model ngVgSZ 39ngVl Gl D l 82 D2D3 I rdsl I 5 Vin v 1 RL V t Vgsl gmlvgsl rd 1 0 S SlG2G3 Fig 03007 Smallsignal performance assuming a load resistance in the drain of RL Rm 2 00 Using nodal analysis we can write gdsl gdsz gm2V1 39 gdSZVout 39glein and 39gdsz gm2lvl gdSZ GLVout 0 Solving for Vowan yields Voul gmlgds2 gm2 gm1 R vm gdslgdsz gdslGL gdszGL GLgmz CL 39gm1 L Note that unlike the B T cascode the voltage gain vlvm is greater than 1 V1 Vds2RL rds2RL RL Vin gml 70151 1gm27 ds2 z 7ds2 1 ds2 The smallsignal output resistance is rout rdsl rdsz gmzrdslrdsz RL 5 RL assuming that RL is small RL lt r0152 for the gain to be 1 ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 030 7 ECE4430 Review 111 1904 Page 03011 Transconductance Characteristic of the BJT Differential Ampli er Consider the following NPN BJ T differential ampli er i i sometimes called an emittercoupled pair I39C1 l licz LargeSignal Analysis 1 Input loop eq V11VBE1VBE2V12 V11V12VBE1VBE2 VIDVBE1VBE2 0 2 Forwardactive region VEE Fig 03008 I39C1 z vBE1 V In and VBE2 V In 5 2 l39C1 V11V12 VID 3 If151 152 then 1C2 exp VI exp VI 1 4 Nodal current equation at the emitters iE1iE2 IEE a F 1C1 1C2 aFIEE O FIEE 5 Comblnlng the above equatlons glves 1C1 VID and 1C2 VID leXp VZ 16ngZ ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 030 7 ECE4430 Review 111 1904 Page 03012 Differential and Commonmode SmallSignal BJ T Ampli er Performance The smallsignal performance of a differential ampli er can be separated into a differential mode and common mode analysis This separation allows us to take advantage of the following simpli cations HalfCircuit Concept as amp VEE VEE Fig 030 09 Note The halfcircuit concept is valid as long as the resistance seen looking into each emitter is approximately the same ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 030 7 ECE4430 Review 111 1904 Page 03013 Transconductance Performance of the Differential Ampli er Consider the following n channel differential ampli er 1 VDD v 1 w M I 39 I V lIBias VID Q VGSI IVGSQJF M4 M3 1155 quot EVBulk T 00 Fig 03010 Where should bulk be connected Consider a pwell CMOS technology 1 1 s1 s2 2 2 VD 39 nsubistrfatei 3 39 39 Fig03011 l Bulks connected to the well No modulation of VT but large common mode parasitic capacitance 2 Bulks connected to ground Smaller common mode parasitic capacitors but modulation of VT If the technology is nwell CMOS the bulks must be connected to ground ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 030 7 ECE4430 Review 111 1904 Page 03014 Transconductance Performance of the Differential Ampli er Continued De ning equations Assume that the MOSFETs are in saturation 21191 12 2lD2 12 VID VGS1 VGSZ B and SS lD1 102 Solution 2 4 2 4 SS 1553VID 32VIDJ12 d SS 155 3VID 32VID 12 ID1 an ID2 2 2 Iss 413 2 2 Iss 4123 which are valid for VID lt 2155 312 Illustration of the result iD ISS s 0g ii 04 1 x 1 0 0 VID 20 1414 1414 20 ass9905 Fig mm ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 030 7 ECE4430 Review 111 1904 Page 03015 Differential and Commonmode SmallSi 1121 Performance The smallsignal performance of a differential ampli er can be separated into a differential mode and common mode analysis This separation allows us to take advantage of the following simpli cations HalfCircuit Concept VDD RD D i 60 3 V17 035 e 335 zdl l lidz VXon 3 V11 Vgsl Vgs2 V12 39 39 Co 0 V55 V55 Modejflob 8631 V10 Vic Fig 030 13 Note The halfcircuit concept is valid as long as the resistance seen looking into each source 1s approx1mately the same ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 030 7 ECE4430 Review 111 1904 Page 03016 Other Characteristics of the Differential Ampli er Commonmode rejection ratio 0 Input commonmode range Slew rate B T ICMR The maximum and minimum input common mode range is VicmaX VCC 051EERC VCE1SatVBE1 Vicmin VEEVCE3SatVBE1 SR The differential ampli er has a slew rate limit of I EECeq where Ceq is the capacitance seen to ground from either collector MOSFET ICMR The maximum and minimum input common mode range is vicmax VDD 05155131 VT1 vicmin VSSVDS3sat V051 SR The differential ampli er has a slew rate limit of 155 Ceq where Ceq is the equivalent capacitance seen from either of the drains to ground ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 030 7 ECE4430 Review 111 1904 Page 03017 TRANSISTOR CURRENT SOURCES AND ACTIVE LOADS Summary of Current Sinks and Sources Current Sink Source rOUT VMIN Sim le MOS Current Sink l P W m VDsltsatgt VON Sim le BJT Current Sink V p 70 Z VCEsat z 02V Cascode MOS z gmzrdszl dsl VT ZVON Cascode B T z 311770 2 VCESat Minimum VMIN Cascode z gmzrdsgrdsl 2 VON Current Sink Regulated Cascode Current z rds3gm3rd32gm4rds4lrds5 z VTV0N Sink Minimum VMIN Regulated z Vds3gm37 ds2gm40 ds4llrdSS zVON Cascode Current S1nk ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 030 7 ECE4430 Review III 1904 Summary of MOS Current Mirrors Page 03018 Current Accuracy Output Input Minimum Minimum Mirror Resistance Resistance Output Input Voltage Voltage Simple Poor Vols g VON VTJFVON m Cascode Excellent gmrdSZ g2 VT2 VON 2 VTJF VON m Wide Output Excellent gmrdsz 1 2 VON VT VON Swing gm Cascode Selfbiased Excellent gmrdsz R L 2 VON VT2 VON Cascode gm Wilson Poor gmrdSZ gi 2 VT VON VT2 VON m Regulated Good gm2rds3 L VT VON VON Cascode Excellent gm mm 13 mm 13 VON 2 VON ECE 6412 Analog Integrated Circuits and Systems II PE Allen 2002 Lecture 030 7 ECE4430 Review III 1904 Summary of BJT Current Mirrors Page 03019 Current Accuracy Output Input Minimum Minimum Mirror Resistance Resistance Output Input Voltage Voltage Simple Poor 7 0 g VCESat VBE m Cascode Excellent 3F 0 g2 VCESa Jr VBE 2 VBE m Wide Output Excellent 3170 1 2 VCEsat VB E Swing gm Cascode Selfbiased Excellent 3170 R L 2 VCEsat VCEsat VB E Cascode gm Wilson Poor J Fro gi VCESat VBE VCESat VBE m Regulated Good 3170 or less VCEsat VCEsat Cascode Excellent gm One can design the regulated cascode so that effectively the minimum value of VMIN out is just VCEsat ECE 6412 Analog Integrated Circuits and Systems II PE Allen 2002 Lecture 030 7 ECE4430 Review 111 1904 Page 03020 Active Load Ampli ers What is an active load ampli er VDD VCC H404 H39 ww H 45 2 I I 39 1 w r4 r4 ME 1 MOS Transconductors BJ T Transconductors 1 Fig 03014 It is a combination of any of the above transconductors and loads to form an ampli er Remember that the above are only some of the examples of transconductors and loads ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 030 7 ECE4430 Review 111 1904 Page 03021 BJ T Differential Am li er with a Current Mirror Load Design Considerations Constraints Speci cations Power supply Smallsignal gain Technology Frequency response C L Temperature ICMR Slew rate C L Power dissipation Relationships Av gm lRouZ 603 dB 2 1 RoulCL Fig 030 15 VICmaX VCC VBE3 VCE1sat VBEI z VCC VCE1sat V1Cmin VEE VCE5sat VBEI SR 1 EE C L Pdiss VCC VEEDAll dc currents owing from VCC or to VEE ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 030 7 ECE4430 Review 111 1904 Page 03022 CMOS Differential Ampli er with a Current Mirror Load Design Considerations Constraints Speci cations Power supply Smallsignal gain Technology Frequency response C L Temperature ICMR Slew rate C L Power dissipation Relationships Av gm lRouZ 603 dB 2 1 RoulCL VICmaX Z VDD 39 VSG3 VTNi T Vss Fig 03016 VICmin VDS5Sat VGSi Z VDS5Sat VGSZ SR 155 C L Pdiss VDD VSSDAll dc currents owing from VDD or to V55 ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 030 7 ECE4430 Review 111 1904 Page 03023 Summary of Active Load Ampli ers 0 Active load ampli er consists of a transconductor and a load There are a large number of combinations of loads and transconductors possible We have not considered the many cascoded possibilities and other con gurations The B T ampli er generally has more gain and wider signal swing than the MOS ampli er The voltage gain of the MOS transconductor with a current source or current mirror load is inversely proportional to the square root of the bias current The current mirror load differential ampli er is a widely used input stage The frequency response is generally determined by the dominant pole which is found at points in the circuit that are high impedance to ac ground and large capacitance The active load ampli er is the primary gain stage in operational ampli ers and other applications and will be a fundamental building block in more complex circuits Performance not considered include slew rate and noise ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 160A 7 Bipolar Technology 62204 Page 16071 LECTURE 160 BIPOLAR TECHNOLOGY READING TextSec 24 25 INTRODUCTION Objective The objective of this presentation is l Illustrate the fabrication sequence for a typical bipolar junction transistor 2 Show the physical aspects of the BJT Outline npn BJT technology Compatible pnp BJTs Modifications to the standard npn BJT technology Advanced BJT technology Summary ECE 4430 7 Analog Integrated Circuits and Systems PE Allen 7 2004 Lecture 160A 7 Bipolar Technology 62204 Page 16072 npn BIPOLAR JUNCTION TRANSISTOR TECHNOLOGY Major Processing Steps for a Iunction Isolated B IT Technology Start with a p substrate Implantation of the buried n layer Growth of the epitaxial layer p isolation diffusion Base p type diffusion Emitter n diffusion p ohmic contact Contact etching Metal deposition and etching Passivation and bond pad opening DWNQF 11PWN1 ECE 4430 7 Analog Integrated Circuits and Systems PE Allen 7 2004 Lecture 160A 7 Bipolar Technology 62204 Page 16073 Implantation of the Buried Layer Mask Step 1 llector resistance Objective of the buried layer is to reduce the co n implantation for buried layer SIDE VIEW 12 substrate p p 17 n n n n Metal Fig160701 ECE 4430 eAnalog Integrated Circuits and Systems RE Allen 7 2004 Lecture 160A 7 Bipolar Technology 62204 Page 16074 Epitaxial Layer 1N0 Mask Required The objective is to provide the proper n type doping in which to build the npn B T Epitaxial Region p p p n n n n Metal Fig16002 ECE 4430 7 Analog Integrated Circuits and Systems RE Allen 7 2004 Lecture 160A 7 Bipolar Technology 62204 Page 16075 p isolation diffusion Mask Step 2 The objective of this step is to surround isolate the npn BJT by a 17 diffusion These regions also permit contact to the substrate from the surface I g 7 TOP VIEW j I 17 l isolation E SIDE VIEW n buried layer 17 17 p n n n n Metal Fig3916003 ECE 4430 eAnalog Integrated Circuits and Systems PE Allen 7 2004 Lecture 160A 7 Bipolar Technology 62204 Page 16076 Base t e diffusion Mask Ste 3 The step providesthe p type bashe npn BJT n buiie tl layer 17 17 p n n n n Metal Fig39 004 ECE 4430 7 Analog Integrated Circuits and Systems PE Allen 7 2004 Lecture 160A 7 Bipolar Technology 62204 Page 16077 Emitter n diffusion Mask Step 4 This step implements the n emitter of the npn BJT and the collector ohmic contact n buried l39 39 39 17 P 17 Hi n n m Metal Fig16005 ECE 4430 iAnalog Integrated Circuits and Systems RE Allen 7 2004 Lecture 160A 7 Bipolar Technology 62204 Page 16078 g ohmic contact Mask Step 5 This step permits ohmic contact to the base region if it is not doped sufficiently high SIDE VIEW n buiie tl layer 17 P 17 n n n m Metal Fig160706 ECE 4430 7 Analog Integrated Circuits and Systems RE Allen 7 2004 Lecture 160A 7 Bipolar Technology 62204 Page 16079 Contact etchin Mask Ste 6 This step opens up the areas in the dielectric area which metal will contact Dielectric Layer 39 n buiie d layer p p p n n n n Metal Fig 0 07 ECE 4430 7 Analog Integrated Circuits and Systems PE Allen 7 2004 Lecture 160A 7 Bipolar Technology 62204 Page 160710 Metal de osition and etchin Mask Ste 7 In this step the metal is deposited over the entire wafer and removed where it is not wanted 4 1 TOP VIEW4 r V f 4 V m V w 11 emitter V I7 V p base A QED j 39 11 buried layer i p substrate Fig160708 ECE 4430 7 Analog Integrated Circuits and Systems PE Allen 7 2004 Lecture 160A 7 Bipolar Technology 62204 Page 160711 Passivation Mask Step 8 Covering the entire wafer with glass and opening the area over bond pads which requires another mask TOP VIEWt Passivation n buried layer Flg 16009 ECE 4430 7 Analog Integrated Circuits and Systems PE Allen 7 2004 Lecture 160A 7 Bipolar Technology 62204 Page 160712 T ical Im urit Concentration Profile for the n n B T Taken along the line from the surface indicated in the last slide 1k 1021 p r lt 11 4 lt7 n4gtlt7 p4 A 1020 7 a 1019 Substrate Doping Level E 1018 a g 1017 II Eprtaxral I l g l collector II 8 1016 II doping level 39 gtx 39 I I 1015 II I a 10m nl In I I39 I I nl I I xv Depth 39111 the H 1 2 3 4 5 6 7 8 9 10 11 12 surface mlcrons 1013 7 Base Collector Buried Layer Substrate Fig 16010 1012 L ECE 4430 7 Analog Integrated Circuits and Systems PE Allen 7 2004 Lecture 160A 7 Bipolar Technology 62204 Page 160713 COMPATIBLE pnp BJTS Substrate n B T Collector is always connected to the substrate potential which is the most negative DC potential x p p p n39I n n n Metal Fig39l 39o u ECE 4430 iAnalog Integrated Circuits and Systems RE Allen 7 2004 Lecture 160A 7 Bipolar Technology 62204 Page 160714 Lateral n B T Collector is not constrained to a fixed dc potential n buiie tl layer p substrate 17 17 p n n n n Metal Fig16042 ECE 4430 7 Analog Integrated Circuits and Systems RE Allen 7 2004 Lecture 160A 7 Bipolar Technology 62204 Page 160715 MODIFICATIONS TO THE STANDARD npn TECHNOLOGY Types of Modifications 1 Dielectric isolation Isolation of the transistor from the substrate using an oxide layer 2 Double diffusion A second deeper n emitter diffusion is used to create JFETs 3 Ion implanted JFETs Use of an ion implantation to create the upper gate of a p channel JFET 4 Superbeta transistors Use of a very thin base width to achieve higher values of SF 5 Double diffused pnp BJT Double diffusion is used to build a vertical pnp transistor whose performance more closely approaches that of the npn B T ECE 4430 iAnalog Integrated Circuits and Systems PE Allen 7 2004 Lecture 160A 7 Bipolar Technology 62204 Page 160716 ADVANCED BIPOLAR IC TECHNOLOGY Objective Newer BJT technologies use polysilicon to form a self aligned emitter resulting in higher frequency response capability These technologies attempt to keep the surface of the integrated circuit as at as possible Process 1 Buried layer and epitaxial growth i SiOz IllillllliliIIH 7V I 7 7 ll o 1 p 1 mil X l I I sumde Polytide Metil 04062203 ECE 4430 7 Analog Integrated Circuits and Systems PE Allen 7 2004 Lecture 160A 7 Bipolar Technology 62204 Page 160717 Process Continued 2 Etching of epitaxial layer SiOz pretype substrate Salicitle Polycitle Metal 040622704 3 Growth of thick SiOz pretype substrate quotquot Illlquot39lquot 1 mi p p p Poly Salititle fUlylee Metal 04062209 ECE 4430 Analog Integrated Circuits and Systems PE Allen 7 2004 Lecture 160A 7 Bipolar Technology 62204 Page 160718 Process Continued 4 Base diffusion and collector sinker n diffusion 7 base layer 5 retype substrate Salicitle Polycitle Metal 040622705 5 n polysilicon emitter 71 polysilicon emitter I 7 base layer 510 Si02 Si02 retype substrate 11 Salicitle Polycide Metal 04062206 ECE 4430 e A alog I tegrated Circuits and Systems PE Allen 7 2004 Lecture 215 7 Chapter 2 7 Review Problems 121601 Page 21571 LECTURE 215 CHAPTER 2 REVIEW PROBLEMS READING TextChapter 2 Chapter 2 Topics Integrated Circuit Technology Bipolar Technology Passive Components in Bipolar Technology CMOS Technology CMOS Technology Compatible Devices BiCMOS Technology ECE 4430 7 Analog Integrated Circuits and Systems PE Allen 7 2001 Lecture 215 7 Chapter 2 7 Review Problems 121601 Page 21572 Problem 1 a Sketch the approximate side View of a NMOS transistor in a p substrate Identify each region and identify the connections at the top surface of the integrated circuit for the source drain gate and bulksubstrate Solution BulkSubstrate Source Gate Drain Thin Oxide 10 100nm 10014 100013 Polysilicon 31 p substrate Heavily Lightly Intrinsic Lightly Heavily Metal Doped p Doped p Doping Doped n Doped n Fig3l01 ECE 4430 7 Analog Integrated Circuits and Systems PE Allen 7 2001 Lecture 215 7 Chapter 2 7 Review Problems 121601 Page 21573 Problem 1 Continued b Sketch the approximate side View of a NPN vertical transistor in an n epitaxial region which is on top of a p substrate Identify each region including the n buried layer and identify the connection at the top surface of the integrated circuit for the base emitter collector and substrate Solution Substrate COHBCtOT Base Emitter 11 emitter V p p p39 mi 11 n n Metal SuOOEZS4B ECE 4430 7 Analog Integrated Circuits and Systems PE Allen 7 2001 Lecture 215 7 Chapter 2 7 Review Problems 121601 Page 21574 Problem 2 A la out of a NMOS transistor is y Blue Black RBd White White shown a Find the values of RD and RS I in the schematic shown if the 11 Metal POIY coma P39subsm te sheet resistance of the n is 35 Qsq and the resistance of a single contact is 19 b Find the values of CBD and R CBS assuming the transistor is External L cutoff and the drain and source Gage I T are at ground potential if C and CJSW for an NMOS RS CBS T transistor are 77OxlO6 Fm2 Emma and 380x1012Fm Assume Source the capacitors are lumped and appear on the sourcedrain side of the bulk resistors in part Each square is lumx lum Fig F00E2p1 c What is the W and L of this transistor d If the overlap capacitorunit length is 220x1012Fm what is C GD ECE 4430 7 Analog Integrated Circuits and Systems PE Allen 7 2001 External Drain CBD Lecture 215 7 Chapter 2 7 Review Problems 121601 Page 21575 Problem 2 Continued Solution lue Black Red White White a The area between the edge of the i contacts to the polysilicon is 5pm by 11 Meta1 Poly Contact psubstrate 22pm This represents a bulk resistance of 522x35 Qsq 7959 Adding 5 contacts in parallel gives Esta RD RS 7959o29 8159 r1 CED b The area or the source and drain are 132 equal and are 9pm by 22pm or 198pm2 o I T The perimeter of the source and drain are 29um22pm or 62pm Therefore E R51 CBS 39 xtema C B DC BS 77Ox10396Fm2x198103912m2 Source 380x103912Fm x 62x10396m CMLCE 152fF 24fF 176fF c The W 22m and the L 215m d The overlap capacitor is CE 220x1012Fm x 22x106m 48fF Each square is lnm x lnm Fig100E2p1 ECE 4430 7 Analog Integrated Circuits and Systems PE Allen 7 2001 Lecture 215 7 Chapter 2 7 Review Problems 121601 Page 2156 Problem 3 A simple first order lter shown is to be built with a polysilicon resistor and a MOS capacitor The polysilicon resistor has a sheet resistance of SOQsq i 30 and is 5pm wide The MOS capacitor is 2fFum2 i 10 The 3dB frequency of the lowpass lter is 1MHZ a Choose the Vin size of the resistor the number of squares N to minimize CMoil the total area of the lter including both the resistor and the capacitor Find the area of the resistor and the capacitor in 39 7 1300132132 pm2 and their values b Using the worst case tolerance of the resistor and capacitor nd the maximum and minimum 3dB frequencies Rpoly v0 Solution a Value ofR SOQsqxN sq SON 9 Value of C 2fFpm2xAC m2 2AC fF Area of C AC Area ofR AR 25pm2xN 25N umz Total Area AT 25N AC pm2 We know that the RC product is given as 1 1 ECE 4430 7 Analog Integrated Circuits and Systems PE Allen 7 2001 Lecture 215 7 Chapter 2 7 Review Problems 121601 Page 21577 Problem 3 Continued Thus AT 251V 2nx10397N dN 25 39 2nx10397N2 O 1 39 N 252 gt An 957x95um2 6308m2 and Ar 6308m2 5075x10397 7 Also 5M R 252x509 126k9 and 9405 6308um2x2fFum2 12621 b 1 Max1mum 3dB frequency 16MHz 1 Mlnlmum 3dB frequency 07MHz ECE 4430 7 Analog Integrated Circuits and Systems PE Allen 7 2001 Lecture 215 7 Chapter 2 7 Review Problems 121601 Page 21578 Problem 4 A CMOS ampli er is shown along with the top View of the circuit layout assuming a p well CMOS technology Find the values of the capacitors shown in the circuit if Type P Channel N Channel Units Blue Gmquot Black Red Orange Whine CGDO CGSO 220 x 10 12 220 x 10 12 Fm I D CGBO 700 X 10 12 700 X 10 12 FIII 17 Metal Poly p7well n7substrate C 560 x 10 6 770 x 10 6 Fm2 CJSW 350 x 10 12 380 x 10 12 Fm M 05 05 MJSW 035 038 2 F 07 08 V Based on an oxide thickness of 140 or Cox247 x 104 Fmz Solution ng1 220 X 10 121010 6 gg 22fF ngz 220 X 10 122010 6 gg 44fF FOOFEPlA ECE 4430 7 Analog Integrated Circuits and Systems PE Allen 7 2001 Lecture 215 7 Chapter 2 7 Review Problems 121601 Page 21579 Problem 4 Continued Next we must nd the area and perimeter of each drain AD1 60pm2 amp PD1 32pm AD2 120um2 amp PD2 52pm CJAD1 CJSWPD1 770x1066Ox1012 380x101232x106 del 2 5V 2 5V 2 5V 2 5V 39 5 1 l Z W M 1 l Z FIMJSW 1 W 0 1 08 0 38 CE 2275fF 710fF 2984fF CJAD2 CJSWPD2 560x106120x103912 350x1o1252x106 25V 25V 25V 25V 05 035 1 2 F M 1 l Z FIMJSW 1 L7 1 07 CE 3143fF 1069fF 4212fF dez ECE 4430 7 Analog Integrated Circuits and Systems PE Allen 7 2001 Lecture 215 7 Chapter 2 7 Review Problems 121601 Page 215710 Problem 5 A CMOS circuit is shown Assume a p well CMOS technology and draw the complete layout for the NMOS and PMOS transistors that 5V has minimum rectangular area for the source and drain diffusions 20 In Some pertinent design rules are listed below DRl distance from the square contact to diffusion from polysilicon 2m Vin M VOW DR2 all contacts are to be square with a dimension of 2m by 10mm 2pm 2pm DR3 the overlap of the contact by the diffusion or poly 2m DR4 min separation between n diffusion and p well 2m F9399E1p1A DRS minimum overlap of contact by metal 1 pm DR6 poly must overlap the channel by lum All metal widths are to be 4m Put as many contacts between the metal and diffusions as possible Show the metal connections between transistors and indicate where metal goes for connections from transistors to external connections vin and v0 must be in metal Use the indicated scheme below for identifying the various regions If you wish to use colored pencil use the scheme below or indicate which colors pertain to which region ECE 4430 7 Analog Integrated Circuits and Systems PE Allen 7 2001 Lecture 215 7 Chapter 2 7 Review Problems 121601 Page 215711 Problem 5 Solution Continued e Green Black I P Metal Red Poly Orange White p well n substrate ECE 4430 7 Analog Integrated Circuits and Systems Fig F99ElSlB PE Allen 7 2001 Lecture 215 7 Chapter 2 7 Review Problems 121601 Page 215712 Problem 6 This problem consists of a number of short questions 1 What is the resistance of the drain if the sheet resistance of 11 diffusion is logsq What is the drain bulk capacitance Mata assuming VBD OV if bottom capacitance is 033pFum2 and the sidewall capacitance is 09fFpm 8 Rn 109sqx 7 1143Q Rn 1143Q CBD 033pFum2x70pm2 09fFpmx34pm 231fF306fF 537fF C BD 537fF 2 Why are contacts normally square and minimum size They are square because that is minimum area and they are minimum size because different size contacts do not etch evenly so small contacts are chosen for contact area Larger contacts are done by repeated use of minimum size contacts 3 What is the function of the field oxide FOX in a CMOS technology The function of field oxide is to isolate the substrate from conductors on the surface ECE 4430 7 Analog Integrated Circuits and Systems F99E1P3A PE Allen 7 2001 Lecture 215 7 Chapter 2 7 Review Problems 121601 Page 215713 Problem 6 Continued 4 How are two BJT transistors fabricated in the same substrate electrically isolated from each other Each BJT is fabricated in its own n epitaxial region surrounded on all sides by p material This pn junction is reversed biased to electrically isolate the two transistors 5 Assume that a le resistance of an IC process has a voltage coefficient of 71000ppmV What is the resistance value if the average voltage across the resistor is increased from O to 5V R5V ROV SVXIOOOQ 10009 59 9959 6 List the 5 capacitances associated with the MOSFET operating in the saturation region and tell whether this capacitance is depletion or parallel plate or both 1 Gate 7drain which is parallel plate 2 Gate source which is both parallel plate and depletion 3 Bulk drain which is depletion 4 Bulk source which is depletion 5 Gate bulk which is parallel plate ECE 4430 7 Analog Integrated Circuits and Systems PE Allen 7 2001 Lecture 215 7 Chapter 2 7 Review Problems 121601 Page 215714 Problem 7 A top view of a CMOS push pull ampli er is shown Find the numerical value of all capacitances shown on the schematic Assume that the dc value of the output is 25V and the M and M SW is 05 for both transistors Blue Green Black Red Orange White 7 V a I n p Meta Poly pwell nsubstrate F99FEP2B ECE 4430 7 Analog Integrated Circuits and Systems PE Allen 7 2001 Lecture 215 7 Chapter 2 7 Review Problems 121601 Page 215715 Problem 7 Continued Solution M1 W110pm L1 2pm AS AD1 6x10 60um2 PSI PD1 32pm CGDI 10pm045pm07fFpm2 315fF 6Opm2O33fFm232pm09fFpm Clng 2 5 2138fF 1 CGS1 lOpmO45pmO7fFpm2 O6720pm207fFm2 1248fF M2 W2 20pm L2 2m A52 AD2 6x20 12011119 P52 PD2 52pm CGD2 20um06pm07fFpm2 84fF 120 2O38fFm252 lfF 1 CGS2 20pm06pm07fFpm2 O6740um207fFm2 27fF ECE 4430 7 Analog Integrated Circuits and Systems PE Allen 7 2001 Lecture 215 7 Chapter 2 7 Review Problems 121601 Page 215716 Problem 8 This problem consists of a number of short questions 1 List three functions of polysilicon 1 Gate Of a MOS transistor 2 Ohmic connection between two points 3 Resistor 4 Capacitor plate 2 In a CMOS technology list three functions for the n or p diffusions 1 They can form the source or drain of a MOSFET 2 They are used to make an ohmic contact with metal 3 They can be used as a resistor 4 Capacitor plate Nitride is only used to define the active areas of transistors True or False X 4 How are two NMOS transistors fabricated in the same substrate electrically isolated from each other They are fabricated in an oppositely doped substrate so that they can be reverse biased and thus isolated from the substrate and from each other 5 What is the purpose of masks in an integrated circuit fabrication process TO allow selective 39m m essino of an area of a wafer P ECE 4430 7 Analog Integrated Circuits and Systems PE Allen 7 2001 Lecture 010 ECE4430 Review I 122901 Page 010 1 LECTURE 010 ECE 4430 REVIEW I READING GHLM Chap 1 Objective The objective of this presentation is 1 Identify the prerequisite material as taught in ECE 4430 2 Insure that the students of ECE 6412 are adequately prepared Outline Models for IntegratedCircuit Active Devices Bipolar MOS and BiCMOS IC Technology SingleTransistor and MultipleTransistor Ampli ers Transistor Current Sources and Active Loads ECE 6412 Analog Integrated Circuits and Systems II PE Allen 2002 Lecture 010 ECE4430 Review I 122901 Page 010 2 MODELS FOR INTEGRATEDCIRCUIT ACTIVE DEVICES PN Junctions Step Junction Barrier potential kT NAND NAND 120 714 Vt ln m2 Depletion region Widths 2 si1JoVDND W1 qNANAND W 1 2 si1JoVDNA 0C N W2 I qNDNAND Depletion capacitance gsinAND 1 GO QA 2NAND lw0vD 1 VD I3 NN UTll39l SLZQD Fig 01001 ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 010 ECE4430 Review I 122901 Page 010 3 PNlunctions Graded Junction Graded junction ND X 39NA Fig 010 02 Above expressions become Depletion region Widths 3 28si1JoVDND m W161NDNANDJ 1 m 2395 2 si1JoVDNA m W 0 2 W2 2 qNDNAND 15 Depletion capacitance J 1 SsiCINAN D m 1 Cjo 05 Cj A2NAND moVD quot 12 0 1 WC 0 2 where 033 sm s 05 Fig 01003 ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 010 ECE4430 Review I 122901 Large Signal Model for the BJT in the Forward Active Region Largesignal model for a npn transistor iB gt B o C VBE JL B FlB E E E Assumes vBEisa IS BE constant and 13 is 1B B F exp determined externally Fig010 04 Largesignal model for a pnp transistor iB B 2 C C VBE 1r 5FiB I3 E E E Assumes VBE is a E I VBE constant and i3 is lB 39 3 2 CXPE Z determined externally Fig010 05 Early Voltage VCE VBE Modl ed large s1gnal model becomes 1C I S 1 VA exp Vl ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 010 ECE4430 Review I 122901 Page 010 5 The EbersMoll Equations The reciprocity condition allows us to write O FIEF aRICR IS Substituting into a previous form of the EbersMoll equations gives VBE IS VBC zCIS exp Vt 1 exp Vt 1 and IS VBE VBC 1E a F exp Vt 1 15 exp Vt 1 These equations are valid for all four regions of operation of the B T Also 0 Dependence of 31 as a function of collector current The temperature coef cient of 31 is 1 aJ F O TCF E W z 7 OOOppm C ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 010 ECE4430 Review I 122901 Page 010 6 Sim le Small Si 113 B T Model Implementing the above relationships ic gmvi govce and vi r ib into a schematic model gives C B 2 C C B I Vi 7 ngi 0 Vce tl B 39c a E E E Fig 01006 Note that the small signal model is the same for either a npn or a pnp BJT Example Find the small signal input resistance Rm the output resistance Row and the voltage gain of the common emitter BJT if the BJT is unloaded RL 00 VowVin the dc collector current is 1mA the Early voltage is 100V and 30 100 at room temperature IC lmA 1 30 gm W m E mhos or Siemans Rm rat E 100 26 26kg VA 100v Vout Rom r0 E MA IOOkQ Vin gm r0 26mS100kQ 2600VN ECE 6412 Analog Integrated Circuits and Systems II PE Allen 2002 Lecture 010 ECE4430 Review I 122901 Complete Small Signal BIT Model Page 010 7 m C OB A 217 B39 IM A 26quot Co J quot J CST T r75 V1 gmvl r0 CCSI rex E E C 0 Fig 010 07 The capacitance C at consists of the sum of C jg and Cb C at Cje Cb ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 010 ECE4430 Review I 122901 Page 010 8 Example 1 Derive the complete small signal equivalent circuit for a BJT at C 1mA VCB 3V and VCS 5V The device parameters are CjeO 10fF ne 05 1106 09V C 10fF nc 03 1106 05V Ccso 20fF ns 03 1103 065V 30 100 IF 10ps VA 20V rb 3009 rc 509 rex 59 and r 1030r0 Solution Because C jg is dif cult to determine and usually an insigni cant part of C at let us approximate it as 2C 13960 Cje20 3 C CW IOfF 56fF and C C630 20 105fF Hgne 1E5JO393 CS HEW 1f jo393 OC WOS 1C lmA gm W m 38mAN Cb 17F gm 10ps38mAN 038pF C Cb CJe 038pF 002pF 04pF 3 VA 20V r j 100269 26kQ r0 E m 20k9 and m 103 or0 20M9 ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 010 ECE4430 Review I 122901 Page 010 9 Transition Frequency t1 fTis the frequency Where the magnitude of the shortcircuit commonemitter current 1 Circuit and model lt 17 CM re 1 quot 1M I ii C7 T 775 V1 ng1 Q 70 CCST Tia T Fig010 08 Assume that re z 0 As a result r0 and Ccs have no effect I 717 1000 gm 717 30 Vie 1r c cys 1i and Ioengl 3 11060 CJ C uS CJ C uS lgmr gm O gm 10060 30 NOW W 1100 Cy CyN39w 1 g gm At high frequencies L 3i L 3i 3003 zjw Cj cy 2 When I 3 co 1 then CUT C cy 0f fT 2 C Cy ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 010 ECE4430 Review I 122901 Page 010 10 IFET Large Signal Model Large signal model G D o 2 VGS IDSS1 yg VP c o S S Fig 010 09 Incorporating the channel modulation effect V032 1D IDss 1 V p 1WDS VDS Z VGsVp Signs for the JFET variables Type Of JFET Vp IDSS VGS pChannel Positive Negative Normally positive nChannel Negative Positive Normally negative ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 010 ECE4430 Review I 122901 Page 010 11 Fre uenc Inde endent FET Small Si 113 Model Schematic D id D O G I Vgs nggs r0 Vds 3 G lt3 5 S Fig010 1O S Parameters dip I 21055 V65 V65 gmdngQ Vp 1Vp 8m01Vp Where 21055 gm039 Vp dip I VGS2 1 rfmg MDss1v p em Typical values of I D55 and Vp for a pchannel JFET are 1mA and 2V respectively With A 002V1 and ID 1mA we get gm 1mAN 0r 1mS and r0 50kg ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 010 ECE4430 Review I 122901 Page 010 12 Fre uenc De endent FET Small Si 113 Model Complete small signal model ng D H C C G I gssf ngJ gs gr ng s S Fig010 l 1 All capacitors are reverse biased depletion capacitors given as S S 13 capacitance from source to top and bottom gates 0 C ngo 861 1 VGD C s0 C83 VG 1 13 capacitance from drain to top and bottom gates 0 C 0 C gss W capacitance from the gate pbase to substrate 1 0 1 gm fT rm 30MHZ 1f gm HAN and CgsngCgss SPF ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 010 ECE4430 Review I 122901 Page 010 13 Simple Large Signal MOSFET Model N channel reference convention Nonsaturation Wyocox VDS2 ID L V05 39 VTVDS 39 T 1 WDS 0 lt VDS lt VGS VT Saturation W 0C0x V 82102 ID 39UL sz VTVDssat DST 1 AVDS WHOCOJC VGS VT 2 A39VDS7 0 lt VGS 39 VT lt VDS where ya zero eld mobility cmZvoltsec Cox gate oxide capacitance per unit area Fcm2 A channellength modulation parameter volts1 VT VTo IVle VTo zero bias threshold voltage 3 bulk threshold parameter volts05 2km strong inversion surface potential volts Fig 01012 For pchannel MOSFETs use nchannel equations with pchannel parameters and invert current ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 010 ECE4430 Review I 122901 Page 010 14 MOSFET SmallSi 1131 Model Complete schematic model id D D Go Bo D S S S c Fig 010 13 where mp diD MD gm 5 M Q 3VGS39VT IZb ID gds E dvDS Q 1 LVDS z MD 07LD l dip avg 31D WT 8m and gmbs Q avT Q 2 Simpli ed schematic model D D Gg D GOIg Clolg Vgs oz Vds nggs s s s 39 5 Fig 42 2 Extremely important assumption l gm z 10gmbs z 100gds l ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 010 ECE4430 Review I 122901 Page 010 15 MOSFET De letion Ca acitors C JLdC Model CJAS CJSWPS CBS M MJSW V35 5 FCPB v35 VBS 1 W 1 Polysilicon gate and CJAS VBS CBS W 1 1MJFC MJ J 1 F C CJSWPS V35 Fig 010 14 1MJSW l 1MJSWFC MJSWWJ Dram bottom ABCD 1 F C Drain sidewall ABFE BCGF DCGH ADHE VBSgt FCB CBS I where 5439 AS area of the source BS 2 FCPB PS perimeter of the source VBS S FCPB PB CJS W zero bias bulk source sidewall capacitance I VBS MJSW bulksource sidewall grading coef cient For the bulkdrain depletion capacitance replace quotSquot by quotDquot in the above equations ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 010 ECE4430 Review I 122901 Page 010 16 MOSFET Intrinsic Capacitors CQLQ and Cg Cutoff Region CGBC22C5C0xltWeVVgtltLeVVgt 2CGB0ltLeVVgt 0 VS 0 VG VT VD 0 C05 C 1 e C0xLDWeff CGSOWeff CGD C3 C0xLDWeff CGDOWeff Saturation Region CGB 2C5 CGBOa eff Saturated CGS C 123C2 C0xLD067LeffWeff V30 VS0 VGVT VDgtVG39VT CGSOWeff 067C0xWeffLeff CGD C3 C0xLDWeff CGDOWeff quot Active Region CGB 2 C 5 2CGBOLeff Active 2 0 VS 0 VGgtVT VD ltVGVT CGS C 1 05C2 C0xLD05LeffWeff 39 H CGD CGSO 05C0xLeffWeff CGD C3 05C2 C0xLD05LeffWeff CGDO 05C0xLeffWeff P39 Substrate mvmwmgion Fig 010 1 ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 010 ECE4430 Review I 122901 Page 010 17 SmallSignal Frequency Dependent Model The depletion capacitors are found by evaluating the large signal capacitors at the DC operating point Gc d i The charge storage capac1tors are Vgs Cgs rds vds constant for a speci c region of T W gmbsvbs operation Cgb quot Sc Vs Gainbandwidth of the MOSFET W T Cbs Assume VSB 0 and the MOSFET Cg II is in saturation B Fig 01017 L 3m L 3 1 fT 2n Cgs ng 221 C83 Recalling that 2 W Cgs 3 CoxWL and g m Uocoxf VGS39 VT gives 1 L0 fT 471 L2 VGS39VT ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 010 ECE4430 Review I 122901 Page 010 18 Subthreshold MOSFET Model Weak inversion operation occurs when the applied gate voltage is below VT and pertains to when the surface of the substrate beneath the gate is weakly inverted VGS II Diffusion Current p substratewell Fig 010 18 Regions of operation according to the surface potential pg 55 lt ltsz Substrate not inverted Flt 55 lt 2P Channel is weakly inverted diffusion current 2 lt 55 Strong inversion drift current Drift current versus diffusion current in a MOSFET 10 Y iD Diffusion Current M Current 106 1 7 39 39 1017 quoti 0 VT Fig 010 19VGS ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 010 ECE4430 Review I 122901 Page 010 19 LargeSignal Model for Subthreshold Model W ip Kx f emsquotV41 eVDseri LVDS where Kx is dependent on process parameters and the bulksource voltage n 15 3 and kT 0 VI 7 111A VGS VT If vDS gt 0 then W ip Kxf emsquotVt 1 LVDS szltvT Smallsignal model aiD 611D 0 0 iv VDS gm ves Q nkT Fig 03920 8139 D ID 3613 8vDsQ V A ECE 6412 Analog Integrated Circuits and Systems 11 PE Allen 2002 Lecture 010 7 ECE4430 Review I 122901 Page 01071 LECTURE 010 ECE 4430 REVIEW I READING GHLM Chap 1 Objective The objective of this presentation is 1 Identify the prerequisite material as taught in ECE 4430 2 Insure that the students of ECE 6412 are adequately prepared Outline Models for Integrated Circuit Active Devices Bipolar MOS and BiCMOS IC Technology Sin gle Transistor and Multiple Transistor Amplifiers 39 Transistor Current Sources and Active Loads ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 010 7 ECE4430 Review I 122901 Page 01072 MODELS FOR INTEGRATEDCIRCUIT ACTIVE DEVICES PN unctions Ste unction Barrier potential kT N N N N N N wt 71n 212 D V ln 212 D UT ln 212 D Depletion region widths 23si1po VDND W1 qNANAND W i zssi1poVDNA N W2 qNDNAND C Depletion capacitance J EsinAND 1 C0 CPA MM 4 VD 393 C10 0 0 VD Fig 010 01 ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 010 7 ECE4430 Review I 122901 Page 01073 PN lunctions Graded lunction Graded junction o x NA Fig 010 02 Above expressions become Depletion region widths 2 si1JoVDND M W qNDNAND m zesiopo VDWA m W 0 1V W2 39qNDltNAN D Depletion capacitance C A EsinAND m l CjO J 12NAND weVD VD m 1 1p 0 0 10 8 6 4 2 0 2 VD 39 where 033 sm 5 05 F g3901003 ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 010 7 ECE4430 Review I 122901 Page 01074 Large Signal Model for the B IT in the Forward Active Region Large signal model for a npn transistor 13913 B C VBE 1ng 393 E E Assumes VBE is a I BE constant and i3 is 39 S lB 57 6XP determined externally Fig010704 E Large signal model for a pnp transistor 1393 B C VBE WEEE 393 E E Assumes VB is a I constant and i3 is l3919 IT exp determined externally Fig010705 Early Voltage VCE VBE Modi ed large signal model becomes 1C S l W exp Tl ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 010 7 ECE4430 Review I 122901 Page 01075 The EbersMoll Equations The reciprocity condition allows us to write ocFIEF ocRICR Is Substituting into the previous form of the Ebers Moll equations gives VBE Is VBC 1C 15 expTl 1 a R exle 1 and Is VBE VBC 1E a F eXpTl 1 15 exle 1 These equations are valid for all four regions of operation of the BJT Also Dependence of 7 as a function of collector current The temperature coefficient of 7 is 1 a F O TCF 235W z 7000ppm C ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 010 7 ECE4430 Review I 122901 Page 01076 Sim le Small Si nalB TModel Implementing the above relationships ic gmvi govce and vi r ib into a schematic model gives C B 2 C C B I Vi 397 ngi Vce CI B 39 E E E E Fig 01006 Note that the small signal model is the same for either a npn or a pnp BJT Example Find the small signal input resistance Rm the output resistance Ram and the voltage gain of the common emitter BJT if the BJT is unloaded RL 00 vowVin the dc collector current is 1mA the Early voltage is 100V and 7 0 at room temperature IC 1mA 1 g gm Vt m mhos or Siemans Rm r g m 10026 26k9 VA 100v Voul Rom r0 F m 100m gm r0 26mS100kQ 2600VV Vin ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 010 7 ECE4430 Review I 122901 Page 01077 Complete Small Signal B IT Model Fig 010 07 The capacitance C 71 consists of the sum of C je and C b C n C je C b ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 010 7 ECE4430 Review I 122901 Page 01078 Example 1 Derive the complete small signal equivalent circuit for a BJT at IC 1mA VCB 3V and VCS 5V The device parameters are CjeO 10fF ne 05 woe 09V CH0 10fF nc 03 we 05V C630 20fF ns 03 11103 065V 30 100 IF 10ps VA 20V rb 3009 rc 509 rex 59 and r39u 10 0r0 Solution Because C je is dif cult to determine and usually an insigni cant part of C let us approximate it as 2Cj60 Cje20fF C o 10fF C 0 20fF CH V39u T56fF and Ccsf105 i 1 CBne mp3 1 csns mp3 W00 1P0s IC 1111A gm W m 38mAV Cb 1F gm 10ps38mAV 038pF C Cb Cje 038pF 002pF 04pF 5 VA 20v r 100269 26k9 r0 E m 20kg and r IO Oro ZOMQ ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 010 7 ECE4430 Review I 122901 Page 01079 Transition Frequency 1 fT is the frequency where the magnitude of the short circuit common emitter current 1 Circuit and model 11 rb CH rc 393 ii CE rm v1 gmvl r0 Cm Tia z T T Fig010708 Assume that rc 0 As a result r0 and Ccs have no effect 71 1000 gmrn n Vlz lrnCnCHs 1i and Iong1 gt Iiw CnCHs Camps gmrn gm 0 gm 100w r NOW 150w Iiw Cncujw 1 fa gm At high frequencies gm gm L 8m 3001 zj w CWFCH gt When I Lu 1 then CUT CnCH 0r fT 27 CWFCH ECE 6412 7 Analog Integrated Circuits and Systems II PE Allen 7 2002 Lecture 010 iECE4430 Reviewl 122901 Page 010710 IFET Large Signal Model Large signal model ygsz V S S Fig 01009 Incorporating the channel modulation effect VGS 2 1D IDSS 1 VP 1WDS VDS Z VGsVp Signs for the IFET variables Type Of IFET VP I DSS VGS p ch annel Positive Negative Normally positive n ch annel Negative Positive Normally negative ECE 6412 7 Analog Integrated Circuits and Systems II PE Allen 7 2002 Lecture 010 7 ECE4430 Review I 122901 Page 010711 Freauencv JFET Small Signal Model Schematic D D o 1 I3 Vgs nggs c G S Fig01010 S Parameters diD I 2loss VGS VGS gmdvGSQ VP 1 VP ng 1 VP where ZIDSS ng VP diD I V032 L r0dVDSQ M055139Vp MD Typical values of I D55 and VP for a p channel JFET are lmA and 2V respectively With A 002V391 and ID lmA we get gm lmAV or lmS and r0 50kg ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 010 7ECE4430 Reviewl 122901 Page 010712 Fre uenc De endent FET Small Si nal Model Complete small signal model Gv IQ All capacitors are reverse biased depletion capacitors given as CG Fig010711 S Cgs 13 capacitance from source to top and bottom gates W C d0 ng VGD 13 capac1tance from drain to top and bottom gates 1 W C ssO Cgss 1 VGSS 12 capac1tance from the gate p base to substrate 110 1 gm fT Em 3OMHz if gm lmAV and CgsngCgss 5pF ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 010 7 ECE4430 Review I 122901 Page 010713 Simple Large Signal MOSFET Model N channel reference convention Non saturation 1D W OCOX V 2 i0 u VGS VTVDS 1 WDS O lt VDS lt VGs VT GZr I B VDS VGS VBS Saturation WHoCox vDssat2 S Fig 010712 10 L VGS VTVDsSa 2 l AVDs WHOCOX 2L VGs VT 2 l AVDs O lt VGs VT lt VDs where u zero field mobility cm2voltsec Cox gate oxide capacitance per unit area FcmZ A channel length modulation parameter voltsl VT VTo 11le VTo zero bias threshold voltage y bulk threshold parameter volts705 2 strong inversion surface potential volts For p channel MOSFETs use n channel equations with p channel parameters and invert current ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 010 7 ECE4430 Review I 122901 Page 010714 MOSFET SmallSi nal Model Complete schematic model D D G2 133 D G Il IltIB GO I B Vgs Vbs ginng MEWS rds vs S S S Fig3010713 where gmsjvl GDS VasVTW gdssddvl flTeDs MD WT deS gm mp aiDHasz dip Q Q 2 2 F7VBS ngm and gm WBS Q W03 W35 W T Simplified schematic model id D D Gg D G oI G oI Vgs 0 Vds grilng s s s S Fig 422 Extremely important assumption gm z IOgmbS z IOOgdS ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 010 7ECE4430 Reviewl 122901 Page 010715 MOSFET Depletion Capacitors CE and CBD Model CJAS CJSWPS CBS MV W VBS s FCPB 1 Polysilicon gate and C CMS 1 1 MDFC M V W BS l FC PB CJSWPS V33 Fig 010714 W l 1MJSVVFC MJSWW DrainbottomABCD 1 F C Drain sidewall ABFE BCGF DCGH ADHE VBsgt CBS where AS area of the source PS perimeter of the source CJSW zero bias bulk source sidewall capacitance MJSW bulk source sidewall grading coefficient For the bulk drain depletion capacitance replace quotSquot by D in the above equations VBSS FCPB 4 VBS FCPB Fig 01015 ECE 6412 7 Analog Integrated Circuits and Systems II PE Allen 7 2002 Lecture 010 7ECE4430 Reviewl 122901 Page 010716 MOSFET Intrinsic C quot s C and C Cutoff Region CGBC22C5CoxltWeioltLeio 2CGBOLeff VB 0 Vs 0 Va VT VD o CGS C1 CoxLDWeff CGSOWeff A CGD C3 CoxLDWeff CGDOWeff I Saturation Region CGB 2C5 CGBOLeff Samath C65 C123C2 C0xLD067LeffWeff V80 Vs 0 VGVT VDgtVG39VT CGSOWeff O67C0xWeffLeff CGD C3 CoxLDWeff CGDOWeff Active Region CGB 2 C 5 2CGBOLeff CGS C1 05C2 C0xLDO5LeffWeff Cuto p substrate Active CGSO 05C0xLeiiWeii CGD C3 05C2 C0xLDO5LeffWeff 39 I CGDO 05C0xLeffWeff P substrate mvwemgmn Fig 01071 ECE 6412 7 Analog Integrated Circuits and Systems II PE Allen 7 2002 Lecture 010 7 ECE4430 Review I 122901 Page 010717 SmallSignal Frequency 1 Model The depletion capacitors are found by evaluating the large signal ng capacitors at the DC operating point G D The charge storage capacitors are i Vgs J Cgs rds vds constant for a specific region of operation gb i Clad Gainbandwidth of the MOSFET T W T Cl T Assume VSB O and the MOSFET B l is in saturation Lgm Lgm fT 2n Cgs ng 2n Cgs Recalling that Fig 010717 2 W Cgs g COXWL and gm uoCoxT VGsVT gives 1 0 fT 4 L2 VGsVT ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 010 iECE4430 Reviewl 122901 Page 010718 Subthreshold MOSFET Model Weak inversion operation occurs when the applied gate voltage is below VT and pertains to when the surface of the substrate beneath the gate is weakly inverted VGS Diffusion Current psubstratewell Fig010718 Regions of operation according to the surface potential p3 pg lt pp Substrate not inverted Flt pg lt 2 Channel is weakly inverted diffusion current 2 lt pg Strong inversion drift current Drift current versus diffusion current in a MOSFET 10 lb Diffusion Current 5 Drift Current 1076 77777777777 fzr ww 10712 0 VT Fig 010719VGS ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 010 7 ECE4430 Review I 122901 Page 01071 LECTURE 010 ECE 4430 REVIEW I READING GHLM Chap 1 Objective The objective of this presentation is 1 Identify the prerequisite material as taught in ECE 4430 2 Insure that the students of ECE 6412 are adequately prepared Outline Models for Integrated Circuit Active Devices Bipolar MOS and BiCMOS IC Technology Sin gle Transistor and Multiple Transistor Amplifiers 39 Transistor Current Sources and Active Loads ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 010 7 ECE4430 Review I 122901 Page 01072 MODELS FOR INTEGRATEDCIRCUIT ACTIVE DEVICES PN unctions Ste unction Barrier potential kT N N N N N N wt 71n 212 D V ln 212 D UT ln 212 D Depletion region widths 23si1po VDND W1 qNANAND W i zssi1poVDNA N W2 qNDNAND C Depletion capacitance J EsinAND 1 C0 CPA MM 4 VD 393 C10 0 0 VD Fig 010 01 ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 010 7 ECE4430 Review I 122901 Page 01073 PN lunctions Graded lunction Graded junction o x NA Fig 010 02 Above expressions become Depletion region widths 2 si1JoVDND M W qNDNAND m zesiopo VDWA m W 0 1V W2 39qNDltNAN D Depletion capacitance C A EsinAND m l CjO J 12NAND weVD VD m 1 1p 0 0 10 8 6 4 2 0 2 VD 39 where 033 sm 5 05 F g3901003 ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 010 7 ECE4430 Review I 122901 Page 01074 Large Signal Model for the B IT in the Forward Active Region Large signal model for a npn transistor 13913 B C VBE 1ng 393 E E Assumes VBE is a I BE constant and i3 is 39 S lB 57 6XP determined externally Fig010704 E Large signal model for a pnp transistor 1393 B C VBE WEEE 393 E E Assumes VB is a I constant and i3 is l3919 IT exp determined externally Fig010705 Early Voltage VCE VBE Modi ed large signal model becomes 1C 15 l W exp Vt ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 010 7 ECE4430 Review I 122901 Page 01075 The EbersMoll Equations The reciprocity condition allows us to write ocFIEF ocRICR Is Substituting into a previous form of the Ebers Moll equations gives VBE Is VBC 1C 15 expTl 1 a R exle 1 and Is VBE VBC 1E a F eXpTl 1 15 exle 1 These equations are valid for all four regions of operation of the BJT Also Dependence of 7 as a function of collector current The temperature coefficient of 7 is 1 a F O TCF 235W z 7000ppm C ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 010 7 ECE4430 Review I 122901 Page 01076 Sim le Small Si nalB TModel Implementing the above relationships ic gmvi govce and vi r ib into a schematic model gives C B 2 C C B I Vi 397 ngi Vce CI B 39 E E E E Fig 01006 Note that the small signal model is the same for either a npn or a pnp BJT Example Find the small signal input resistance Rm the output resistance Ram and the voltage gain of the common emitter BJT if the BJT is unloaded RL 00 vowVin the dc collector current is 1mA the Early voltage is 100V and 7 0 100 at room temperature IC 1mA 1 g gm Vt m mhos or Siemans Rm r g m 10026 26k9 VA 100v Voul Rom r0 F m 100m gm r0 26mS100kQ 2600VV Vin ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 010 7 ECE4430 Review I 122901 Page 01077 Complete Small Signal B IT Model Fig 010 07 The capacitance C 71 consists of the sum of C je and C b C n C je C b ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 010 7 ECE4430 Review I 122901 Page 01078 Example 1 Derive the complete small signal equivalent circuit for a BJT at IC 1mA VCB 3V and VCS 5V The device parameters are CjeO 10fF ne 05 woe 09V CH0 10fF nc 03 we 05V C630 20fF ns 03 11103 065V 30 100 IF 10ps VA 20V rb 3009 rc 509 rex 59 and r39u 10 0r0 Solution Because C je is dif cult to determine and usually an insigni cant part of C let us approximate it as 2Cj60 Cje20fF C o 10fF C 0 20fF CH V39u T56fF and Ccsf105 i 1 CBne mp3 1 csns mp3 W00 1P0s IC 1111A gm W m 38mAV Cb 1F gm 10ps38mAV 038pF C Cb Cje 038pF 002pF 04pF 5 VA 20v r 100269 26k9 r0 E m 20kg and r IO Oro ZOMQ ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 010 7 ECE4430 Review I 122901 Page 01079 Transition Frequency 1 fT is the frequency where the magnitude of the short circuit common emitter current 1 Circuit and model 11 rb CH rc 393 ii CE rm v1 gmvl r0 Cm Tia z T T Fig010708 Assume that rc 0 As a result r0 and Ccs have no effect 71 1000 gmrn n Vlz lrnCnCHs 1i and Iong1 gt Iiw CnCHs CmCH gmrn gm 0 gm 100w r NOW 150w Iiw Cncujw 1 fa gm At high frequencies gm gm L 8m 3001 zj w CWFCH gt When I Lu 1 then CUT CnCH 0r fT 27 CWFCH ECE 6412 7 Analog Integrated Circuits and Systems II PE Allen 7 2002 Lecture 010 iECE4430 Reviewl 122901 Page 010710 IFET Large Signal Model Large signal model ygsz V s S Fig 01009 Incorporating the channel modulation effect V 2 lD IDSS 1 VP 1WDS VDS Z VGsVp Signs for the IFET variables Type Of IFET Vp IDSS VGS p ch annel Positive Negative Normally positive n ch annel Negative Positive Normally negative ECE 6412 7 Analog Integrated Circuits and Systems II PE Allen 7 2002 Lecture 010 7 ECE4430 Review I 122901 Page 010711 Freauencv JFET Small Signal Model Schematic D D o 1 D Vgs nggs c G S Fig01010 S Parameters diD I 2IDSS VGS VGS gmdvGSQ V 1vp 8m01vp where 2IDSS gm039 Vp diD I VG52 L radvDSQ MDSS1 VI MD Typical values of I D55 and VP for a p channel JFET are lmA and 2V respectively With A 002V391 and ID lmA we get gm lmAV or lmS and r0 50kg ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 010 7ECE4430 Reviewl 122901 Page 010712 Fre uenc De endent FET Small Si nal Model Complete small signal model Gv IQ All capacitors are reverse biased depletion capacitors given as CG Fig010711 S Cgs 13 capacitance from source to top and bottom gates W C d0 ng VGD 13 capac1tance from drain to top and bottom gates 1 W C ssO Cgss 1 VGSS 12 capac1tance from the gate p base to substrate 110 1 gm fT Em 3OMHz if gm lmAV and CgsngCgss 5pF ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 010 7 ECE4430 Review I 122901 Page 010713 Simple Large Signal MOSFET Model N channel reference convention Non saturation 1D W OCOX V 2 i0 u VGS VTVDS 1 WDS O lt VDS lt VGs VT GZr I B VDS VGS VBS Saturation WHoCox vDssat2 S Fig 010712 10 L VGS VTVDsSa 2 l AVDs WHOCOX 2L VGs VT 2 l AVDs O lt VGs VT lt VDs where u zero field mobility cm2voltsec Cox gate oxide capacitance per unit area FcmZ A channel length modulation parameter voltsl VT VTo 11le VTo zero bias threshold voltage y bulk threshold parameter volts705 2 strong inversion surface potential volts For p channel MOSFETs use n channel equations with p channel parameters and invert current ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 010 7 ECE4430 Review I 122901 Page 010714 MOSFET SmallSi nal Model Complete schematic model D D G2 133 D G Il IltIB GO I B Vgs Vbs ginng MEWS rds vs S S S Fig3010713 where gmsjvl GDS VasVTW gdssddvl flTeDs MD WT deS gm mp aiDHasz dip Q Q 2 2 F7VBS ngm and gm WBS Q W03 W35 W T Simplified schematic model id D D Gg D G oI G oI Vgs 0 Vds grilng s s s S Fig 422 Extremely important assumption gm z IOgmbS z IOOgdS ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 010 iECE4430 Review I 122901 Page 010715 MOSFET Depletion Capacitors CE and CBD Model CJAS CJSWPS CBS MJ W was s FCPB BS 1 1in 3 Polysilicon gate and CJAS VBS CBS W 1 1MJFC Mf lt1 F61 CJSW39PS 1 1 MJSWFC MJSW V W 1 F C PB VBSgt F C PB where AS area of the source PS perimeter of the source CJSW zero bias bulk source sidewall capacitance MJSW bulk source sidewall grading coefficient For the bulk drain depletion capacitance replace quotSquot by D in the above equations Fig 010714 Drain bottom ABCD Drain sidewall ABFE BCGF DCGH ADHE VBSS FCPB 4 VBS FCPB Fig 01015 ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 010 e ECE4430 Review 1 122901 Page 010716 MOSFET Intrinsic C quot s C and C Cutoff Region Cutoff CGBC22C5CoxWeffLeff 2CGBOLeff VB 0 VS 0 VG VT VD o CGS C1 CoxLDWeff CGSOWeff CGD C3 CoxLDWeff CGDOWeff Saturation Region CGB 2C5 CGBOL ff Saturated ch C123C2 CoxLD067LeiiltWeii VB 0 VS 0 VGVT VDgtVG39VT g 395 CGD C3 CoxLDWeff CGDOWeff quot Active Region p substrate CGB 2 C 5 2CGBOLeff CGS C1 05C2 C0xLDO5LeffWeff Active CGSO 05 CoxLeff Weff cam CGD C3 05C2 C0xLDO5LeffWeff 39 I CGDO 05C0xLeffWeff P substrate mvwemgmn Fig 010711 ECE 6412 7 Analog Integrated Circuits and Systems 11 RE Allen 7 2002 Lecture 010 7 ECE4430 Review I 122901 Page 010717 SmallSignal Frequency 1 Model The depletion capacitors are found by evaluating the large signal ng capacitors at the DC operating point G D The charge storage capacitors are i Vgs J Cgs rds vds constant for a specific region of operation gb i Clad Gainbandwidth of the MOSFET T W T Cl T Assume VSB O and the MOSFET B l is in saturation Lgm Lgm fT 2n Cgs ng 2n Cgs Recalling that Fig 010717 2 W Cgs g COXWL and gm uoCoxT VGsVT gives 1 0 fT 4 L2 VGsVT ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 010 iECE4430 Reviewl 122901 Page 010718 Subthreshold MOSFET Model Weak inversion operation occurs when the applied gate voltage is below VT and pertains to when the surface of the substrate beneath the gate is weakly inverted VGS Diffusion Current psubstratewell Fig010718 Regions of operation according to the surface potential p3 pg lt pp Substrate not inverted Flt pg lt 2 Channel is weakly inverted diffusion current 2 lt pg Strong inversion drift current Drift current versus diffusion current in a MOSFET 10 lb Diffusion Current 5 Drift Current 1076 77777777777 fzr ww 10712 0 VT Fig 010719VGS ECE 6412 7 Analog Integrated Circuits and Systems 11 PE Allen 7 2002 Lecture 200 7 BiCMOS Technology 121201 Page 20071 LECTURE 200 BICMOS TECHNOLOGY READING TextSec 211 INTRODUCTION Objective Illustrate BiCMOS technology Outline Introduction Physical process illustration Summary ECE 4430 7 Analog Integrated Circuits and Systems PE Allen 7 2001 Lecture 200 7 BiCMOS Technology 121201 Page 20072 Typical BiCMOS Technology The following pages describe a 05um BiCMOS process Masking Sequence 1 Buried 11 layer 13 PMOS lightly doped drain 2 Buried p layer 14 11 sourcedrain 3 Collector tub 15 p sourcedrain 4 Active area 16 Silicide protection 5 Collector sinker 17 Contacts 6 n well l8 Metall 7 p well 19 Via l 8 Emitter window 20 Metal 2 9 Base oxideimplant 21 Via2 10 Emitter implant 22 Metal 3 11 Poly 1 23 Nitride passivation l2 NMOS lightly doped drain Notation BSPG Boron and Phosphorus doped Silicate Glass oxide Kooi Nitride A thin layer of silicon nitride on the silicon surface as a result of the reaction of silicon with the HN3 generated during the field oxidation TEOS Tetro Ethyl Ortho Silicate A chemical compound used to deposit conformal oxide films ECE 4430 7 Analog Integrated Circuits and Systems PE Allen 7 2001 Lecture 200 7 BiCMOS Technology 121201 Page 20073 n and 12 Buried Layers Starting Substrate psubstrate lnm BiCMOSAOI lt Sum b 11 and p Buried Layers I I I I I I k NPN Transistor gt 5 PMOS Transistor gt 4 NM0s Transistor gt I psubstrate BiCMosroz 4 5pm ECE 4430 7 Analog Integrated Circuits and Systems PE Allen 7 2001 Lecture 200 7 BiCMOS Technology 121201 Page 20074 Epitaxial Growth I I I k NPN Transistor gt 5 PMOS Transistor gt1 NMOS Transistor gt p well ptype Epitaxial I I I I I I I I I E Silicon I i I I I I I I I I BiCM OS 703 Comment As the epi layer grows vertically it assumes the doping level of the substrate beneath it In addition the high temperature of the epitaxial process causes the buried layers to diffuse upward and downward ECE 4430 7 Analog Integrated Circuits and Systems PE Allen 7 2001 Lecture 200 7 BiCMOS Technology 121201 Page 20075 Collector Tub I I F NPN Transmtor quot i1 PMOS Transistor gt1 NMOS Transistor h Original Area of CollectorTub Implant psubstrate lnm BiCM0s704 lt 5mm Comment The collector area is developed by an initial implant followed by a drive in diffusion to form the collector tub ECE 4430 7 Analog Integrated Circuits and Systems PE Allen 7 2001 Lecture 200 7 BiCMOS Technology 121201 Page 20076 Active Area Definition I I I I k NPN Transistor gt 51 PMOS Transistor gt1 NMOS Transistor gtt psubstrate 1 pm BiCMosros lt 5 uni p Comment The silicon nitride is use to impede the growth of the thick oxide which allows contact to the substrate OLSlllCOIl is used for stress relief and to minimize the bird s beak encroachment ECE 4430 7 Analog Integrated Circuits and Systems PE Allen 7 2001 Lecture 200 7 BiCMOS Technology 121201 Page 20077 Field Oxide I I 51 PMOS Transistor gt 4 NM0S Transistor n I I ielid Oxide Field beide I I vquot Pf VP I BiCMOSVOG lt 5 pm I i4 NPN Transistor h I Field Oxide Comments The field oxide is used to isolate surface structures ie metal from the substrate ECE 4430 iAnalog Integrated Circuits and Systems PE Allen 7 2001 Lecture 200 7 BiCMOS Technology 121201 Page 20078 Collector Sink and nWell and Well Definitions Transistor D Collector Sink PMOS Transistor gtlt NMOS Transistor gt AntiPunch Through AntiPunch Through 39 Threshld Adjus Threshld Adjust 4 NPN I I I I Field Oxide E ield Oxide I A Field xide I I H I BiCMOSrO7 lt SpunD ECE 4430 7 Analog Integrated Circuits and Systems PE Allen 7 2001 Lecture 200 7 BiCMOS Technology 121201 Page 20079 Base De nition I I I I I i1 NPN Transistor gtE 51 PMOS Transistor gtElt NMOS Transistor gtE I I I l I E Field Oxide ie1d Oxide mu m 61 H I Field Ibxide I I E p substrate BiCMoseos 4 5pm ECE 4430 eAnalog Integrated Circuits and Systems PE Allen 7 2001 Lecture 200 7 BiCMOS Technology 121201 Page 200710 Definition of the Emitter Window and SubCollector Im lant I I I h 51 PMOS Transistor gt lt NMOS Transistor gti I I l l Field Oxide i ield Oxide Field Ibxide I lullquot BiCMOSeOQ 4 Sum gt ECE 4430 7 Analog Integrated Circuits and Systems PE Allen 7 2001 Lecture 200 7 BiCMOS Technology 121201 Page 200711 Emitter Implant F NPN Transistor gt39 lant I I 51 PMOS Transistor gtE4 NMOS Transistor gti I I I I r I I 5 Field Oxide Field beide I BiCMOSdO 4 5pm Comments The polysilicon above the base is implanted with n type carriers ECE 4430 iAnalog Integrated Circuits and Systems PE Allen 7 2001 Lecture 200 7 BiCMOS Technology 121201 Page 200712 Emitter Diffusion I l id NPN Transistor gt 51 PMOS Transistor gt 4 NM0S Transistor n I I I Field Oxide Fielld Oxide Field beide I p substrate BiCMosin 5pm Comments The polysilicon not over the emitter Window is removed and the n type carriers diffuse into the base forming the emitter ECE 4430 7 Analog Integrated Circuits and Systems PE Allen 7 2001 Lecture 200 7 BiCMOS Technology 121201 Page 200713 Formation of the MOS Gates and LD DrainsSources I I I I i1 NPN Transistor h 51 PMOS Transistor gtElt NMOS Transistor gtE I r I I m Fielde1de E a Field de6 m P YPe m1 H Field Oxide BiCMosilz 4 5pm Comments The surface of the region where the MOSFETs are to be built is cleared and a thin gate oxide is deposited with a polysilicon layer on top of the thin oxide The polysilicon is removed over the source and drain areas A light sourcedrain diffusion is done for the NMOS and PMOS separately ECE 4430 7 Analog Integrated Circuits and Systems PE Allen 7 2001 Lecture 200 7 BiCMOS Technology 121201 Page 200714 Heavil D0 ed SourceDrain I l id NPN Transistor gt 51 PMOS Transistor gt 4 NM0s Transistor gtt I I Field OXide Fielde1de 139 1 g C 7 Field Xide psub strate BiCMosii3 5pm Comments The sidewall spacers prevent the heavy sourcedrain doping from being near the channel of the MOSFET ECE 4430 7 Analog Integrated Circuits and Systems PE Allen 7 2001 Lecture 200 7 BiCMOS Technology 121201 Page 200715 Siliciding k NPN Transistor h i1 PMOS Transistor gtk NMOS Transistor I E ilicide TiSi 39 s1 39ci e TiSiz Silicide Tis39lz I I I I I I Field Ox1de 39 FE I M a 2 Field Ox1de n a Fieldb de BiCMOS714 45w11 gt Comments Siliciding is used to reduce the resistance of the polysilicon and to provide ohmic contacts to the base emitter collector sources and drains ECE 4430 7 Analog Integrated Circuits and Systems PE Allen 7 2001 Lecture 200 7 BiCMOS Technology 121201 Page 200716 Contacts Tungsten Plugs TungSten Plugs Tungsten Plugs n TEOSBPSGSOG Field Oxide F psub strate BiCMOS715 5pm Comments A dielectric is deposited over the entire wafer One of the purposes of the dielectric is to smooth out the surface Tungsten plugs are used to make electrical contact between the transistors and metall ECE 4430 7 Analog Integrated Circuits and Systems PE Allen 7 2001 Lecture 200 7 BiCMOS Technology 121201 Page 200717 Metall Metall Metall Metall TEOSBPSGSOG EO IBPSGSOG TEOSBPSGSOG F1eld Ox1de a E Field Ox1de C F1eld Ox1de In i gt n 39 pjtype p sub strate BiCMOSJG 4 Spun p ECE 4430 iAnalog Integrated Circuits and Systems PE Allen 7 2001 Lecture 200 7 BiCMOS Technology 121201 Page 200718 MetallMeta12 Vias Tungsten Plugs r r Oxide F TEOSBPSGSOG 39 TEOSBPSGSOG F1eld Ox1de quot HE Field Ox1de T quotl p sub strate BiCMOSrl7 lm ECE 4430 7 Analog Integrated Circuits and Systems PE Allen 7 2001 Lecture 200 7 BiCMOS Technology 121201 Page 200719 Meta12 TEOSBPSGSOG quot TEOSBPSGSOG TEOSBPSGSOG Field Oxide 7 Field Oxide Field Oxide 9 I a E In El m p substrate 1WD BiCMOS718 4 5pm ECE 4430 7 Analog Integrated Circuits and Systems PE Allen 7 2001 Lecture 200 7 BiCMOS Technology 121201 Page 200720 MetalZMetalS Vias TEOSBPSGSOG TEOSBPSGSOG TEO BPSG OG p pe F1eld Ox1de FE Field Ox1de g E F1e1d Ox1de m quot ty p sub strate BiCMOS719 4 5pm Comments The metalZ metal3 Vias will be lled with metal3 as opposed to tungsten plugs ECE 4430 7 Analog Integrated Circuits and Systems PE Allen 7 2001 Switched Capacitor Circuits 101 lOO SWITCHED CAPACITOR CIRCUITS INTRODUCTION Objective The objective of these notes is to provide an elementary background about switched capacitor circuits Outline Introduction Resistance emulation Switches Amplifiers Integrators Firstorder circuits Summary ECE4430 Analog Integrated Circuit Design Page 1 P W A Switched Capacitor Circuits 101 lOO RESISTOR EMULATION Switched Capacitors are Not New James ClerkMaxwell used switches and a capacitor to measure the equivalent resistance of a galvanometer in the 1860 s arallel Switched Ca acitor E uivalent Resistor Page 2 RESISTORS 1j52 w R w VC C V VI a b Figure 911 a Parallel switched capacitor equivalent resistor b Continuous time resistor of value R TwoPhase Nonoverlapping Clock II VI 22 1 V T2 ECE4430 Analog Integrated Circuit Design T 3T 2 2T Figure 912 Waveforms of a typical twophase nonoverlapping clock scheme rt Switched Capacitor Circuits 101 lOO Page 3 EOUIVALENT RESISTANCE OF A SWITCHED CAPACITOR CIRCUIT Assume that v1t and v2t are changing slowly with respect to the clock period The average current is T T2 il i2t i1average lffil lt fi10dt 39 I 2 0 Charge and current are related as Vlm d I Mr 19 Substituting this in the above gives T2 l T2 0 CV T2Cv O 11averagedeqltq1 72q1 2 r 72 A 0 However vCT2 v1T2 and vCO v20 Therefore i1average C V T239VZ0 z C V7 V2 For the continuous time circuit MRM R gt 139 avera e VI 1 g R For v1t z V1 and v2t z V2 the signal frequency must be much less than ECE4430 Analog Integrated Circuit Design J Switched Capacitor Circuits 101 lOO EXAMPLE 91 DESIGN OF A PARALLEL SWITCHED CAPACITOR RESISTOR EMULATION If the clock frequency of parallel switched capacitor equivalent resistor is lOOkHz find the value of the capacitor C that will emulate a 1M9 resistor Solution The period of a lOOkHz clock waveform is lousec Therefore using the previous relationship we get that l 0395 C 6 lOpF We know from previous considerations that the area required for lOpF capacitor is much less than for a 1M9 resistor when implemented in CMOS technology Page 4 ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101 lOO Page 5 POWER DISSIPATION IN THE RESISTANCE EMULATION If the switched capacitor circuit is an equivalent resistance how is the power dissipated 521w R w a b Figure 911 a Parallel switched capacitor equivalent resistor b Continuous time resistor of value R Continuous Time Resistor P V1 39 V22 ower R Discrete Time Resistor Emulation Assume the switches have an ON resistance of R0quot The power dissipated per clock cycle is T V1 39V2 f MR C Power 11averV1V2 where 11 aver W 0e an dt T Vi39Vz2 VI39V22 VI39VZ 2 2 tR TR c z Power TRon e Orzth TC e an 1 W0 1f Tgtgt RonC Thus if R TC then the power dissipation is identical in the continuous time and discrete time realizations ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101 lOO Page 6 OTHER SWITCHED CAPACITOR EQUIVALENT RESISTANCE CIRCUITS 1 2 1W 513362 EU VCU 2 IS Series SeriesParallel Bilinear SeriesParallel The current i1t that ows during both the 1 and 2 clocks is T2 T T i1average fi1tdt fi1tdt fi1tdt 772T 0 W 0 0 T2 Therefore i1average can be written as ilmverage C2 VmT239V 2O C1 VmTVmT2 The sequence of switches causevcz0 V2 vC2T2 V1 vClT2 0 and vClT V1 V2 Applying these results gives Clel39Vzl C1V1Vz 0 C1CzV139V2 T T T i1average T Equatlng the average current to the cont1nuous time c1rcu1t glves R W 1 2 ECE4430 Analog Integrated Circuit Design Switched Ca acitor Circuits 10 llOO Pa e7 P g EXAMPLE 912 DESIGN OF A SERIESPARALLEL SWITCHED CAPACITOR RESISTOR EMULATION If C1 C2 C find the value of C that will emulate a 1M9 resistor if the clock frequency is 250kHz Solution The period of the clock waveform is 4usec Using above relationship we find that C is given Therefore C1 C2 C 2pF ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101 lOO SUMMARY OF THE FOUR SWITCHED CAPACITOR RESISTANCE CIRCUITS SWItChed capacm Rimsmr Schematic Equivalent Resistance Emulation C1rcu1t 1 2 2 Parallel v1 C V2 E C 1 2 o S T W W I g M C 0 0 1 2 W13 SeriesParallel T V v t 1 C1 2 2 C1 C2 9151 52 Bilinear CI 1 t v t v10 2 1 2 0 0 0 Page 8 ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101 lOO Page 9 ACCURACY OF SWITCHED CAPACITOR CIRCUITS Consider the following continuous time firstorder low pass circuit The transfer function of this simple circuit is LEM 1 1 Vja j39leC2 1 jamquot1 1 where 11 RC2 is the time constant of the circuit and determines the accuracy Continuous Time Accuracy Let 11 TC The accuracy of 1C can be expressed as Hja d dR dC 41 F2 gt 5 to 20 dependlng on the s1ze of the components 1 2 TC Discrete Time Accuracy Q T 1 Let 11 ID 2 C2 The accuracy of 1D can be expressed as d 71 gt 01 to l dependlng on the Size of components 1 c eason for the success of switched capacitor circuits in CMOS technology 12amp T D C2 The above is the primary ml 1 ECE4430 Analog Integrated Circuit Design J Switched Capacitor Circuits 101 lOO Page 10 SWITCHED CAPACITOR CIRCUITS kTC NOISE Switched capacitors generate an inherent thermal noise given by kTC This noise is verified as follows An equivalent circuit for a switched capacitor Ran H Vin C Vaut Vin C Vaut a Figure 9311 a Simple switched capacitor circuit b Approximation of a The noise voltage spectral density of Fig 931 lb is given as 2 2kTR0n eRon 4kTR0n VoltsZHz VoltZRad sec 1 The rms noise voltage is found by integrating this spectral density from 0 to co to give 00 2 2kTR wzdw 2kTR mo V J 1 0 1E TVOltSrms2 2 on TC a 2w2 7t 2 l where 601 lRanC Note that the switch has an effective noise bandwidth of l Hz 3 fsw 4R0nC which is found by dividing Eq 2 by Eq 1 ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101 lOO Page 11 SWITCHES MOS TRANSISTOR AS A SWITCH Symbol Bulk A B A B SD I DS CG F1g4l2 On Characteristics of a MOS Switch Assume operation in active region VDs lt VGs VT and VDs small 1D L VGS VT Tms e L VGs VTVDs V S 1 Thus RON z XW 0 L VGs 39 VT OFF Characteristics of a MOS Switch If VGs lt VT then i1 1011 0 when VDs z 0V If VDs gt 0 then ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101 lOO Page 12 MOS SWITCH VOLTAGE RANGES If a MOS switch is used to connect two circuits that can have analog signal that vary from 0 to 5V what must be the value of the bulk and gate voltages for the switch to work properly Bulk 0 to 5V LL 0 to 5V Circuit 57D D75 Circuit 1 139 2 Gate II 439 Fig4l3 To insure that the bulksource and bulkdrain pn junctions are reverse biased the bulk voltage must be less than the minimum analog signal for a NMOS switch To insure that the switch is on the gate voltage must be greater than the maximum analog signal plus the threshold for a NMOS switch Therefore VBulk S 0V and VGate gt 5V VT Also VGateoft S 0V Unfortunately the large value of reverse bias bulk voltage causes the threshold voltage to increase ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101100 Page 13 CURRENTVOLTAGE CHARACTERISTICS OF A NMOS SWITCH The following simulated output characteristics correspond to triode operation of the MOSFET 0V 100uA 1V 0I6V F1g 41 3 SPICE Inpm F116 VGS 2 0 DC 00 MOS Sw1tch On Characteristics VBS 3 0 DC 5 0 M11203MNMOSW3UL3U DC VDS llleGSZ 101 MODEL MNMOS NMOS VT0075 KP25U 39PRINT D39C ID M1 LAMBDA001 GAMMA08 PHI06 39 PROBE VDS 1 0 DC 00 END ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101100 Page 14 MOS SWITCH ON RESISTANCE AS A FUNCTION OF GATESOURCE VOLTAGE 1 10kQ MOS Switch On Resistance 1009 10V 15V 20V 25V 30V 35V 40V 45V 50V GateSource Voltage Fig 415 SPICE Input File LAMBDA001 GAMMA08 PHI06 MOS Switch On Resistance as a fWL VDS 1 0 DC 0001V M1 1 2 0 0 MNMOS W3U L3U VGS 2 0 DC 00 M212 0 0 MNMOS W15U L3U DC VGS 15 01 M3 1 2 0 0 MNMOS w30U L3U PRINT DC 1DM1 1DM2 1DM3 1DM4 M4 1 2 0 0 MNMOS W150U L3U PROBE MODEL MNMOS NMOS VTO075 KP25U END ECE4430 Analog Integrated Circuit Design INFLUENCE OF THE ON RESISTANCE ON MOS SWITCHES Finite ON Resistance ng 0 VC C VG r C vin25V 5 oa e Vmgto f RON TFig 416 Example Initially assume the capacitor is uncharged If VGateON is 5V and is high for 01 us find the WL of the MOSFET switch that will charge a capacitance of lOpF in five time constants KN 110uAV2 and VTN 07V Solution The time constant must be equal to 102m 20ns Therefore RON must be less than 128 2kg The on resistance of the MOSFET for small VDS is R gt Z 1 1 l 06 ON KN WLVGsVT L RON39KN VGsVT ZkQl 10uAV243 39 Comments It is relatively easy to charge on chip capacitors with minimum size switches Switch resistance is really not constant during switching and the problem is more complex than above Switched Capacitor Circuits 10 l lOO Page 15 ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101100 Page 16 INCLUDING THE INFLUENCE OF THE VARYING ON RESISTANCE Gatesource Constant K W gONU L VGStVT VDSI 1 M gONaver39 VONaver N 2 K W K WVDS0 K W 2L VGS39VT39 2L 2L VGS39VT K W K WVDs0 Z L VGS39VT 39 2L Gatesource Vaging ID VGfsv VGate VIN C vC0 0 VGf5VVIN vb 5 DS Fig 418 K W K WVDS0 K W g0N 2 VGS0VT 2L TL VGS 39VIN39VT ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101 lOO Page 17 SWITCH ON RESISTANCE EXAMPLE Assume that at t 0 the gate of the switch shown is taken to 5V Design the WL value of the switch to discharge the C1 capacitor to within 1 of its initial charge in 10ns Use the MOSFET parameters of Table 312 0V Vaula T T T Fig4l9 Solution Note that the source of the NMOS is on the right and is always at ground potential so there is no bulk effect as long as the voltage across C1 is positive The voltage across C1 can be expressed as t v t Sex Cl PRONC1 At lOns Va is 5100 or 005V Therefore 8 3 005 56xp 5exp gt expGON103 100 gt GONzlJ ln 100 RON 103 000468 K W K WVDS 110x1065 W W 00046 TVGSVT T 110x10643 T f 198X10396f Thus w 232 z 23 198x106 ECE4430 Analog Integrated Circuit Design J Switched Capacitor Circuits 101 lOO Page 18 INFLUENCE OF THE OFF STATE ON MOS SWITCHES The OFF state in uence is primarily in any current that ows from the terminals of the switch to ground An example might be Vaut T j T Fig 4140 Typically no problems occur unless capacitance voltages are held for a long time For example Vow VCHl e39tRBulkCH IfRBulk z 1099 and CH lOpF the time constant is 109103911 001seconds ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101 lOO Page 19 INFLUENCE OF PARASITIC CAPACITANCES The parasitic capacitors have two in uences Parasitics to ground at the switch terminals C B D and C B S add to the value of the desired capacitors This problem is solved by the use of strayinsensitive switched capacitor circuits Parasitics from gate to source and drain cause charge injection onto or off the desired capacitors This problem can be minimized but not eliminated Model for studying charge injection A simple switch circuit useful A distributed model of A lumped model of for studying charge injection the transistor switch the transistor switch Fig 4111 ECE4430 Analog Integrated Circuit Design CHARGE INJECTION CLOCK FEEDTHROUGH CHARGE FEEDTHROUGH Charge injection is a complex analysis which is better suited for computer analysis Here we will attempt to develop an understanding sufficient to show ways of reducing the effect of charge injection What is Charge Injection 1 When the voltages change across the gatedrain and gatesource d capac1tors a current w1ll flow because 139 C d 4213quot 1 r 2 When the switch is off charge injection will appear on the external quot39 I I quot39 capacitors C L connected to the switch terminals causing their voltages Fig 4112 to change There are two cases of charge injection depending upon the transition rate when the switch turns off 1 Slow transition time 2 Fast transition time Switched Capacitor Circuits 10 l lOO Page 20 ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101 lOO Page 21 SLOW TRANSITION TIME Consider the following switch circuit A T Fig 4113 1 During the on tooff transition time from A to B the charge injection is absorbed by the low impedance source viquot 2 The switch turns off when the gate voltage is vm VT point B 3 From B to C the switch is off but the gate voltage is changing As a result charge injection occurs to C L ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101100 Page 22 FAST TRANSITION TIME For the fast transition time the rate of transition is faster than the channel time constant so that some of the charge during the region from point A to point B is injected onto C L even though the transistor switch has not yet turned off Fig 4114 ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101 lOO Page 23 APPROXIMATE ANALYSIS OF FEEDTHROUGH The model for this case is given as A Charge injection V V D S 1 CL C1rcu1t at the V L instant gate reaches VSVT Vin zVs zVD T Fig 4116 The switch decrease from B to C is modeled as a negative step of magnitude VSVT VL The output voltage on the capacitor after opening the switch is CL COL COL COL v V V VV V zVV2V V CL COLCL S COLCL T s T L COLCL s s T L CL if C O L lt C L Therefore the error voltage is COL COL Verror z 39VS 2VT 39 VL 2 quotVin ZVT VL CL ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101 lOO Page 24 SOLUTIONS TO CHARGE INJECTION 1 Use minimum size switches to reduce the overlap capacitances and0r increaseCL 2 Use a dummy compensating transistor Xx if T T T Fig 41 19 Requires complementary clocks Complete cancellation is difficult and may in fact may make the feedthrough worse 3 Use complementary switches transmission gates 4 Use differential implementation of switched capacitor circuits probably the best solution ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101 lOO Page 25 INPUTDEPENDENT CHARGE INJECTION Examination of the error voltage reveals that Error voltage Component independent of the input Component dependent on the input This only occurs for switches that are oating and is due to the fact that the input in uences the voltage at which the transistor switches vm z VS z VD Leads to spurious responses and other undesired results Solution Use delayed clocks to remove the inputdependence by breaking the current path for injection from the oating switches H H Vin 1d Cs 12 D21 39 1 I H I s4 vout H H l S 1 2 24 4 CL quot HHW gt I Clock Delay Fig 4120 Assume that C S is charged to Vm both 1 and 1d are high 1 1 opens no inputdependent feedthrough because switch terminals S3 are at ground potential 2 1d opens no feedthrough occurs because there is no current path except through small parasitic capacitors ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101100 CMOS SWITCHES TRANSMISSION GATE IClock I Clock Feedthrough somewhat diminished Advantages Larger dynamic range Lower ON resistance Disadvantages Requires a complementary clock Requires more area ECE4430 Analog Integrated Circuit Design Clock A I B Clock Fig 4121 Page 26 Switched Capacitor Circuits 101 lOO Page 27 DYNAMIC RANGE OF THE CMOS SWITCH The dynamic range of a switch is the range of voltages at the switch terminals VA z VB VA B over which the ON resistance stays reasonably small fDD 3kg M1 25kQ ZkQ 15kQ le tch 0 Resistance I Fig 41 22 05kg Splce File I I 0kg Slmulatlon of the re51stance of a CMOS 0V 1V 2V 3V 4V transmission switch VAB Common mode voltage M1 1 3 2 0 MNMOS L2U W50U M2 1 0 2 3 MPMOS L2U W50U MODEL MNMOS NMOS VTO075 KP25ULAMBDA001 GAWA05 PHI05 MODEL MPMOS PMOS VTO075 KP10ULAMBDA001 GAWIA05 PHI05 VDD 3 0 VAB l 0 IA 2 0 DC lU DC VAB 0 5 002 VDD 4 5 05 PRINT DC V12 END Result Low on resistance over a wide voltage range becomes very difficult as the power supply decreases W1 S 5V ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101100 Page 28 CMOS SWITCH WITH TWINWELL SWITCHING VControl fr M1 VDD M m Analog 39 Analog Signal O 39 Signal Input Output M4 M5 Vss 111 39 M2 VControl C1rcu1t when VCOmml 1s 1n 1ts high state C1rcu1t when VCOmml 1s 1n 1ts low state High State LOW State M1 M1 Analog Analog Amlog Analog 39 S1gnal Slgnal S1gnal Slgnal In ut ou ut Input Output p tp M2 1 M2 Low State ngh State ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101 lOO Page 29 CHARGE PUMPS FOR SWITCHES WITH LOW POWER SUPPLY VOLTAGES As power supply voltages decrease below 3V it becomes difficult to keep the switch on at a low value of on resistance over the range of the power supply Consequently charge pumps are used Charge pump circuit V 33V DD Prevents latchup Vsubihi gale M11 0V NMOS C1 CZJ i J L SWItdlxhizsv CL 33V 1M NJ Li C2 2V hl DD CgateNMOS switch C2 CL V ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101 lOO Page 30 CHARGE PUMP CONTINUED High voltage generator for the well of M1 VDD 33V 66V Vsubihi 1W l C Storage 0V Prevents latchup of M1 by providing a high bulk bias 66V Use a separate clock driver for each switch to avoid crosstalk through the gate clock lines Area for layout can be small ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101100 Page 31 SIMULATION OF THE CHARGE PUMP CIRCUIT Circuit VDD CLKout M1 MZ CLKout M5 E Em A I I I L 311 C1L J II I M4 CLKin M6FJ 2 0 I VSS Fig 4123 Simulation 30 20 E 10 00 10 20 30 40 50 60 70 80 90 100 Time us Fig 4124 ECE4430 Analog Integrated Circuit Design J Switched Capacitor Circuits 101 lOO Page 32 SUMMARY OF MOS SWITCHES Symmetrical switching characteristics High OFF resistance Moderate ON resistance OK for most applications Clock feedthrough is proportional to size of switch W and inversely proportional to switching capacitors Output offset due to clock feedthrough has 3 components Ideal Input dependent Input independent Complementary switches help increase dynamic range As power supply reduces switches become more difficult to fully turn on ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101 lOO ECE4430 Analog Integrated Circuit Design Page 33 AMPLIFIERS CONTINUOUS TIME AMPLIFIERS R1 R2 VOUT VIN R1 R2 VOUT VIN Noninverting Ampli er Inglerting Ampli er Gain and GB 00 La 2 Eli La 2 E Iir1 R1 Iin R1 Gain 75 co GB 00 A g 0 l R R 0 RIA 1 0 Luz AKALamp zJ R1Rz Luz Ri z ampRl z Vin 1 Avd0R1 R1 1 Avd0R1 Vin 1 Avd0R1 R1 Avd0R1 R1R2 R1R2 R1R R1R2 Gain 75 co GB 75 00 GB 39R1 GB 39R1 V R1Rz R1Rz R1Rz w V s ISL R1Rz EL w Vins R1 GB39Rl R1 SwH Vins R1 GB39Rl R1 SwH S R1R2 S R1R2 Switched Capacitor Circuits 101 l00 Page 34 EXAMPLE 921 ACCURACY LIMITATION OF VOLTAGE AMPLIFIERS DUE TO A FIN ITE VOLTAGE GAIN Assume that the noninverting and inverting voltage amplifiers have been designed for a voltage gain of 10 and 10 If Avd0 is 1000 find the actual voltage gains for each amplifier Solution For the noninverting amplifier the ratio of RzR1 is 9 1000 Avd0R1R1R2 W 100 V V0 10 j 9901 rather than 10 For the inverting amplifier the ratio of RzR1 is 10 Avd0R1 1000 R1R2 110 90909 Vaut 90909 V m 10m 9891 rather than 10 ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101 lOO Page 35 EXAMPLE 9223dB FRE UENCY OF VOLTAGE AMPLIFIERS DUE TO FINITE UNITYGAINBANDWIDTH Assume that the noninverting and inverting voltage amplifiers have been designed for a voltage gain of 1 and 1 If the unitygainbandwidth GB of the op amps are 21cMradssec find the upper 3dB frequency for each amplifier Solution In both cases the upper 3dB frequency is given by GB R1 H M For the noninverting amplifier with an ideal gain of 1 the value of RzR1 is zero 60H GB 2n Mradssec lMHz For the inverting amplifier with an ideal gain of l the value of RzR1 is one 60H 2 if GTE nMradssec SOOkHz ECE4430 Analog Integrated Circuit Design J Switched Ca acitor Circuits 10 llOO Pa e 36 P g CHARGE AMPLIFIERS C1 C2 V C1 C2 l 011T VIN i II n v V II n VOUT VIN Noninverting Charge Ampli er Inverting Charge Amplifier Gain and GB 00 Vaut C1C2 Vaut i Vin C2 Vin C2 Gain 75 co GB 00 Avd0C2 Avd0C2 Km 2 C C J C1C2 V Z C1C2 Im C2 1 Iin C2 1 C1C2 C1C2 Gain 75 co GB 75 00 GB 39C 2 GB 39C2 Km 2 C C C1C2 Km 9L C1C2 Vm C2 GBCZ Vm C2 GBCZ s s C1C2 C1C2 ECE4430 Analog Integrated Circuit Design J Switched Capacitor Circuits 101 lOO SWITCHED CAPACITOR AMPLIFIERS Parallel Switched Capacitor Amplifier 2 V 3 C1 quotC1 1 C2 IVCZ Vout Inverting Switched Capacitor Ampli er Analysis I Page 37 in Vout Modi cation to prevent openloop operation Assume that the switching frequency clock frequency fc 17 is much greater than the signal bandwidth Then Vow R2 TC2 C1 Vin R1 z TC1 C 2 If the oversampling assumption is not made then the transfer function becomes M 121 Vin C2 ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101 lOO FREQUENCY RESPONSE OF SWITCHED CAPACITOR AMPLIFIERS Replace z by eJ39wT Vouteja C 39 L 39coT2 H060 VinejaT CzjeJ and Vouteja C L 39m VinejmT 39CZJeJ T If C 1C 2 is equal to RzRl then the magnitude response is identical to inverting unity gain amplifier However the phase shift of H 09eJ39wT is ArgH efa 7 i180 COT2 and the phase shift of H 09eJ39wT is ArgH efa 7 i180 wT Comments The phase shift of the switched capacitor inverting amplifier has an excess linear phase delay When the frequency is equal to 05fc this delay is 90 One must be careful when using switched capacitor circuits in a feedback loop because of the excess phase delay ECE4430 Analog Integrated Circuit Design Page 38 Page 39 Switched Capacitor Circuits 101 lOO POSITIVE AND NEGATIVE TRAN SRESISTAN CE E UIVALENT CIRCUITS Transresistance circuits are twoport networks where the voltage across one port controls the current owing between the ports Typically one of the ports is at zero potential Virtual ground vcm 752 13920 gt Circuits no I gt 52 3d 2 C C v10 z 95 v10 7J2 915 Cpx CP Cp x ch Positive Transresistance Realization Negative Transresistance Realization Analysis Negative transresistance realization v 5322 1 RT 12t 12average If we assumev1t is approximately constant over one period of the clock then we can write T 12mm ge 2 fizmdt qzT qultT2gt Z CvcltTgt TCvcltT2gt Z 2v m Substituting this expression into the one above shows that RT TC Similarly it can be shown that the positive transresistance is TC Comments These results are only valid when f gtgtf These circuits are insensitive to the parasitic capacitances shown as dotted capacitors ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101100 Page 40 INVERTING STRAY INSENSITIVE SWITCHED CAPACITOR AMPLIFIER 1 vi 2 CIq 2 VC2 Vout C C 2 1 1 VCIU Inverting Switched Capacitor Voltage Ampli er Analysis Assume that the switching frequency clock frequency fc 17 is much greater than the signal bandwidth Then Vow R2 TC2 C1 ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101100 Page 41 N ONVERTIN G STRAY INSENSITIVE SWITCHED CAPACITOR AMPLIFIER Use the negative transresistor switched capacitor circuit at the input to get 9151 V 1 VCII 2 V02 z C1 I 1 V mt C2 Noninverting Switched Capacitor Voltage Ampli er Analysis Assume that the switching frequency clock frequency fc 17 is much greater than the signal bandwidth Then V out V 111 R2 TC2 C1 R1 z 39 TC1 C2 ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101 lOO Page 42 EXAMPLE 923 DESIGN OF A SWITCHED CAPACITOR SUMMING AMPLIFIER Design a switched capacitor summing amplifier using the circuits in stray insensitive transresistance circuits which gives the output voltage during the 2 phase period that is equal to 10v1 5v2 where v1 and v2 are held constant during a 2 1 period and then resampled for the next period Solution Based on the previous examples a solution is proposed below 10C V1 1 2 1 2 1 V0 J J 5C V2 2 2 1 1 It easy to show that if the oversampling assumption is true that V0z10V1 5V2 ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101 l00 Page 43 N ONIDEAL 0P AMPS FINITE GAIN Consider the inverting switched capacitor amplifier during 2 C1 C2 Voemnl2T I I v5mn 12T Avd0 v2n1T Op amp with nite value of Avd0 Fig 9241 The output during 2 can be written as e C a C C v0n l2T L IZ vomn l2T CZ vinn lT C2 J Mm Converting this to the zdomain and solving for the H 092 transfer function gives V6 Hoez00LZ 9L 212 1 I Vinltzgt C2 1 31 C2 39 Zvd0Cz Comments The phase response is unaffected by the finite gain A gain of 1000 gives a magnitude of 0998 rather than 10 ECE4430 Analog Integrated Circuit Design J Switched Capacitor Circuits 101 lOO Page 44 NONIDEAL 0P AMPS FINITE BANDWIDTH AND SLEW RATE Finite GB In general the analysis is complicated We will provide more detail for integrators The clock period T should be equal to or less that lOGB The settling time of the op amp must be less that T2 Slew Rate The slew rate of the op amp should be large enough so that the op amp can make a full swing within T 2 ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101100 CONTINUOUS TIME IN TE GRATORS Vin R1 C2 0 R R Vout Vin R 1 C2 Vtmt Inverter a b a Noninverting and b inverting continuous time integ rators Ideal Performance Noninverting Inverting EMM2LLwr M 391 LjwL IwR1C2 Iw a IwR1C2 J39w 60 Frequency Response VomUm Vz39nl390 ArgVoml39DVmf0 AL A s 40 dB 20 dB 0 dB 20 dB 40 dB log 1701 b ECE4430 Analog Integrated Circuit Design Page 45 Switched Capacitor Circuits 101 lOO Page 46 NONINVERTING SWITCHED CAPACITOR INTEGRATOR Approximate analysis v t v Assume that the switching frequency clock frequency Viquot I C10 2 C2 V0 fc lT is much greater than the signal bandwidth Then 31 C1 S4 C2 2 S3 V0 1sC2 1sC2 C1 60 1 Vm quot Rl z39TC1sTC2T T 7 Where Noninverting stray insensitive integrator CI a I T C 2 Exact analysis VOW 9L 2 9L 1 Vinz C2 lz391 C2 zl Exact frequency response replace 2 by el39wT to get M Q wT C IwTZ 6W2 VmejaT C2 12s1naT2 COT COTC2 smaT2 1 IdealxMagnitude errorxPhase error where 601 2 gt Ideal 2 ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101100 Page 47 EXAMPLE 932 COMPARISON OF A CONTINUOUS TIME AND SWITCHED CAPACITOR INTEGRATOR Assume that 001 is equal to 0100C and plot the magnitude and phase response of the noninverting continuous time and switched capacitor integrator from 0 to 001 Solution Letting 001 be 0100C gives 1 00 wT 1 rma ch How1039wwc and H 6 10jaa6 sin7rwwcej Plots 0 50 HG 1 m 1 02 04 00060 08 1 ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101 lOO Page 48 IN VERTIN G SWITCHED CAPACITOR IN TE GRAT OR Analysis Approximate analysis V 2 1010 2 ch V t m 01 Assume that the switching frequency clock S1 C 34 C2 frequency fc lT is much greater than the signal S21 S3 bandwidth Then 3 1 VOW ISCZ z ISCZ C1 Inverting stray insensitive integrator Vm R1 TCl sTC2 s where CI 60 I T C 2 Exact analysis Voutz C l C Z m2 2 Vmz Z 39 1 21 2 39 Exact frequency response replace 2 by el39wT to get V0ut6wT E eij2 wT J C wT2 ijz 1ng C2 12 smmm wT 39 39wTC2 sinaT2 e In Same as noninverting integrator except for phase error Consequently the magnitude response is identical but the phase response is given as T ArgHe 1 25 7 ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101100 Page 49 A SIGN MULTIPLEXER A circuit that changes the 1 and 2 of the leftmost switches of the stray insensitive switched capacitor integrator I 2 0 0 To switch connected x to the input signal S 1 II T r VC x v VC v n II T 0 2 I L 1 T To the left most switch y connected to ground S2 T T Fig 938 This circuit steers the 1 and 2 clocks to the input switch S1 and the leftmost switch connected to ground S2 as a function of whether V6 is high or low ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101 lOO Page 50 FIRSTORDER SWITCHED CAPACITOR CIRCUITS GENERAL FIRSTORDER TRANSFER FUNCTIONS A general firstorder transfer function in the sdomain a1 0 gt Low pass a0 0 gt High Pass a0 75 0 and a1 75 0 gt All pass Note that the zero can be in the RHP or LHP The following continuous time circuit is capable of realizing most of the various forms above Vin R1 R2 Vaut C1 T Fig950 V sR2C21 Vout m R1 ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101 lOO Page 51 NONINVERTING FIRSTORDER LOW PASS CIRCUIT a Figure 951 a Noninverting firstorder low pass circuit b Equivalent circuit of Fig 95la Transfer function Noting that C1 of the general circuit is zero gives Vout R2 1 1 390 1 quotXIT Vin lev S R2 C2l N X2 STXZ 1 ST 052 S Equating the above to the H s of the general firstorder transfer function gives a0 1 0 ala0TJTc anda2b0TJTc ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101 lOO Page 52 INVERTING FIRSTORDER LOW PASS CIRCUIT An inverting low pass circuit can be obtained by reversing the phases of the leftmost two switches in Fig 95la 062C1 Z 1 11 D2 4 061C1 2 2 Via 1 In 4 L Iriverting firstorder low pass circuit It can be shown that Vout Rf 1 0 1 1 0 1 051 T Vm R1 s R2 C21 z 072 sTocz 1 2 sT a2 2 s aZT Equating the above to the H s of a general first order transfer function gives the design equations as 10 b0 ala0TJTc anda2b0TJTc ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101 l00 Page 53 EXAMPLE 951 DESIGN OF A SWITCHED CAPACITOR FIRSTORDER CIRCUIT Design a switched capacitor firstorder circuit that has a low frequency gain of 10 and a 3dB frequency of lkHz Give the value of the capacitor ratios 061 and 062 Use a clock frequency of lOOkHz Solution Assume that the clock frequency fc is much larger than the 3dB frequency In this example the clock frequency is 100 times larger so this assumption should be valid Therefore we can write Vouts 0 1 05105 V s N 062 sTl sToc2 m 60 Setting this equation equal to the specifications gives 061 10062 and 062 EdB C 062 6283100000 00628 and 061 06283 The above represent capacitor ratios and should preferably be close to unity for small area ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101 lOO Page 54 FIRSTORDER HIGH PASS CIRCUIT a b Figure 953 a Switchedcapacitor high pass circuit b Version of Fig 953a that constrains the charging of C1 to the 2 phase Transfer function It can be shown that Vout S R2 C1 STal Sal Vm 39 s R2 C21 z 39 sTCaZC 1 2 39 sTa2 1 2 39 sT a2 2 39 s aZT Equating the above to the general firstorder H s gives the design equations as a1 a1 and aZT b0 Solving for 061 and 062 gives 1 0 051 11 and 062 boT 7 C ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101100 Page 55 FIRSTORDER ALLPASS CIRCUIT 13C Pg BIC 2 viU D2 1 T i 4 b Figure 955 a High or low frequency boost circuit b Modi cation of a to simplify the zdomain modeling Transfer function Summing the currents owing into the inverting input of the op amp gives Vout cchaa J scchaaC11 0533 Vm R1 s R2 C21 Z 39 sTa21 Z 39 s aZT 0 2 Therefore X3 11 allT200 and 0 Of 10 1 0 11 X3 061200ng and 062 ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101 lOO Page 56 EXAMPLE 952 DESIGN OF A SWITCHED CAPACITOR BASS BOOST CIRCUIT Find the values of the capacitor ratiosocl 062 and 063 using a lOOkHz clock for Fig 955 that will realize the asymptotic frequency response shown in Fig 957 A 20 dB 0 lOHz lOOHz lkHz lOkHz Frequency Figure 957 Bass boost response for EX 952 Solution From the previous results we can write the allpass transfer function approximately as sToc3 a1 a1 sTw3Jc1 I HSz sToc2 39a2 sTa21 From Fig 957 we see that the desired response has a dc gain of 10 a righthalf plane zero at 21 kHz and a pole at 2001c Hz Thus we see that the following relationships must hold 0 1 0 1 0 2 10 20001quot and 2001 a2 T063 T From these relationships we get the desired values as a 220001 a 22001 and a 1 1 fc 2 f6 3 ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101 lOO PRACTICAL IMPLEMENTATIONS OF THE FIRSTORDER CIRCUITS Most practical implementations of switched capacitor circuits are fully differential as shown below T 1 1 1 JT12 2C q 1 20ch 2 CBC 1 2 WC 2 OLlC OLlC 2 1 2 2 1 d C1 OLlC w 2 1 gt V00 D Van 2 1 I OLlCl 1 2 2 1 2 00 00 OLlC CL C d V 0L1C 2 C q V F62 2 0L2 0L3C J1 11 1 11 J1 b T T Figure 958 Differential implementations of a Fig 951 b Fig 953 and c Fig 955 Comments Differential operation reduces clock feedthrough common mode noise sources and enhances the signal swing Differential operation requires op amps or OTAs with differential outputs which in turn requires a means of stabilizing the output common mode voltage ECE4430 Analog Integrated Circuit Design Page 57 Switched Capacitor Circuits 101 lOO ANTIALIASING IN SWITCHED CAPACITOR FILTERS A characteristic of circuits that sample the signal switched capacitor circuits is that the signal passbands occur at each harmonic of the clock frequency including the fundamental T010 AntiAliasing Filter T00 Tau 0 lgsML ti 4 f mcmp3 2DcDP l L Ai 39 DPB DPB Dc Figure 9728 Spectrum of a discretetime lter and a continuoustime antialiasing lter Page 58 The primary problem of aliasing is that there are undesired passbands that contribute to the noise in the desired baseband ECE4430 Analog Integrated Circuit Design Switched Capacitor Circuits 101 lOO Page 59 NOISE ALIASIN G IN SWITCHED CAPACITOR CIRCUITS In all switched capacitor circuits a noise aliasing occurs from the passbands that occur at the clock frequency and each harmonic of the clock frequency Magnitude From hi her bands Al Vise 377 arequot quot N f Baseband fcfsw f fsw A B 0 fswa 032 fc fB f fcmff Figure 9731 Illustration of noise aliasing in switched capacitor circuits It can be shown that the aliasing enhances the baseband noise voltage spectral density by a factor of Z w Therefore the baseband noise voltage spectral density is 2 eBN2 kTCamp 2kT VOltSZHZ fsw fc ch Multiplying this equation by 2L gives the baseband noise voltage in voltsrms2 Therefore the baseband noise voltage is MT 2kT2fi3 2kT C VBN2 fcC B C K OSR voltsrms2 where OSR is the oversampling ratio ECE4430 Analog Integrated Circuit Design Lecture 194 7 CMOS Passive Components 7 11 71002 Page 19471 LECTURE 194 CMOS PASSIVE CONIPONENTS II READING TextSec 210 Objective The objective of this presentation is 1 Examine the passive components that are compatible with CMOS technology 2 Physical in uence on passive components Outline 39 Capacitors Resistors Summary ECE 4430 7 Analog Integrated Circuit Designl PE Allen 7 2002 Lecture 194 7 CMOS Passive Components 7 11 71002 Page 19472 Capacitor Errors 1 Oxide gradients 2 Edge effects 3 Parasitics 4 Voltage dependence 5 Temperature dependence ECE 4430 7 Analog Integrated Circuit Designl PE Allen 7 2002 Lecture I94 7 CMOS Passive Components 7 II 71002 Page 19473 Ca acitor Errors Oxide Gradients Error due to a variation in oxide thickness across the wafer l i i No common a n lt centroid layout i Common 03 4 centroid layout X1 x2 X3 Fig 192701 Only good for one dimensional errors An alternate approach is to layout numerous repetitions and connect them randomly to achieve a statistical error balanced over the entire area of interest Fig 194702 02 matching of poly resistors was achieved using an array of 50 unit resistors ECE 4430 7 Analog Integrated Circuit Design I PE Allen 7 2002 Lecture I94 7 CMOS Passive Components 7 II 71002 Page 19474 Capacitor Errors Edge Effects There will always be a randomness on the definition of the edge However etching can be in uenced by the presence of adjacent structures For example Matching of A and B are disturbed by the presence of C Improved matching achieved by balancing the adjacent material a a Fig 19403 ECE 4430 7 Analog Integrated Circuit Designl PE Allen 7 2002 Lecture 194 7 CMOS Passive Components 7 11 71002 Page 19475 Capacitor Errors AreaPeriphery Ratio The best match between two structures occurs when their area to periphery ratios are identical Let C l C1 AC1 and C Z C2 AC2 where C the actual capacitance C the desired capacitance which is proportional to area AC edge uncertainty which is proportional to the periphery Solve for the ratio of C 2C 1 C 2 CziACZ C21 739C 2 C2 AC2 AC1 C2 AC2 AC1 C 1C1iAC171 AC1 CliTziiltC 1 E1iC 2Tl iC l AC2 C 2 g If C 2C 1then C1 Therefore the best matching results are obtained when the areaperiphery ratio of C2 is equal to the areaperiphery ratio of C1 ECE 4430 7 Analog Integrated Circuit Designl PE Allen 7 2002 Lecture 194 7 CMOS Passive Components 7 11 71002 Page 19476 Capacitor Errors Relative Accuracy Capacitor relative accuracy is proportional to the area of the capacitors and inversely proportional to the difference in values between the two capacitors For example 004 Unit Capacitance 05pF 0 O U I Unit Capacitance lpF Relative Accuracy 0 o N Q Q t Unit Capacitance 4pF 03900 2 4 8 16 32 64 Ratio of Capacitors Fig 19204 This result will change if the unit capacitor consists of two or more unit capacitors ECE 4430 7 Analog Integrated Circuit Designl PE Allen 7 2002 Lecture 194 7 CMOS Passive Components 7 11 71002 Page 19477 Capacitor Errors Parasitics Parasitics are normally from the top and bottom plate to ac ground which is typically the substrate Top Plate r 1 Top Desired 391 plat Capacitor 2quot para51t1c I 39 39 Bottom BottomPlate 3 plate i parasitic Fig 194 05 11 Top plate parasitic is 001 to 0001 of Cdesired Bottom plate parasitic is 005 to 02 Cdesjred ECE 4430 7 Analog Integrated Circuit Designl PE Allen 7 2002 Lecture 194 7 CMOS Passive Components 7 11 71002 Page 19478 Other Considerations on Capacitor Accuracy Decreasing Sensitivity to Edge Variation A A39 A B B39 B 1339 Sensitive to edge variation in Sensitive to edge varation in both upper andlower plates upper plate only Fig 19406 A structure that minimizes the ratio of perimeter to area circle is best Top Plate of Capacitor Bottom plate of capacitor Fig 19407 ECE 4430 7 Analog Integrated Circuit Designl PE Allen 7 2002 Lecture 194 CMOS Passive Components 7 II 71002 Page 19479 C quot Errors Temnerature and Voltage I Polysilicon Oxide Semiconductor Capacitors Absolute accuracy z i10 Relative accuracy z i02 Temperature coef cient 25 ppmCO Voltage coefficient 50ppmV Polysilicon Oxide Polysilicon Capacitors Absolute accuracy z i10 Relative accuracy z i02 Temperature coef cient 25 ppmCO Voltage coefficient 20ppmV Accuracies depend upon the size of the capacitors Accuracy 0 1Area2 ECE 4430 7 Analog Integrated Circuit Designl PE Allen 7 2002 Lecture 194 CMOS Passive Components 7 II 71002 Page 194710 RESISTORS MOS Resistors SourceDrain Resistor pr substrate Fig 194708 Diffusion Ion Implanted 10100 Ohmssquare 500 2000 ohmssquare Absolute accuracy 3570 Absolute accuracy 15 RelatiVe accuracy 2 5WD 02 50 Relative accuracy 2 5 pm 015 H111 50 pm Temperature COCf CiCnt 1500 PPmOC Temperature coef cient 400 ppm0C VOHage COCf Ciem z 200 PPmV Voltage coef cient 800 ppmV Comments Parasitic capacitance to substrate is voltage dependent Piezoresistance effects occur due to chip strain from mounting ECE 4430 7 Analog Integrated Circuit Designl PE Allen 7 2002 Lecture 194 7 CMOS Passive Components 7 11 71002 Page 194711 Polysilicon Resistor Metal Polysilioon resistor p7 substrate Fig 194 09 30 100 ohmssquare unshielded 100 500 ohmssquare shielded Absolute accuracy i30 Relative accuracy 2 5 pm Temperature coefficient 500 1000 ppm0C Voltage coef cient 100 ppmV Comments Used for fuzes and laser trimming Good general resistor with low parasitics ECE 4430 7 Analog Integrated Circuit DesignI PE Allen 7 2002 Lecture 194 7 CMOS Passive Components 7 11 71002 Page 194712 Nwell Resistor p7 substrate Fig 194 10 1000 5000 ohmssquare Absolute accuracy i40 Relative accuracy z 5 Temperature coefficient 4000 ppm0C Voltage coefficient is large z 8000 ppmV Comments Good when large values of resistance are needed Parasitics are large and resistance is voltage dependent ECE 4430 7 Analog Integrated Circuit DesignI PE Allen 7 2002 Lecture 194 7 CMOS Passive Components 7 II 71002 Page 194713 MOS Passive C Performance v Component Range of Absolute Relative Temperature Voltage Type Values Accuracy Accuracy Coefficient Coef cient Poly oxide O 3 5 0 5 10 01 20ppmOC i20ppmV semiconductor fFum2 Capacitor Poly Poly 03 0 4 fFum2 20 01 25ppmOC iSOppmV Capacitor Diffused 10 1 OO Qsq 35 2 lSOOppmOC 200ppmV Resistor Ion Implanted 05 2 kQsq 15 2 400ppm C 800ppmV Resistor poly Resistor 30 200 Qsq 30 2 lSOOppmOC lOOppmV n well Resistor l l 0 k9 sq 40 5 8OOOppmOC lOkppmV The electrical performance of all passive components greatly depends on the geometry and physical aspects of the layout ECE 4430 7 Analog Integrated Circuit Designl PE Allen 7 2002 Lecture 194 7 CMOS Passive Components 7 II 71002 Page 194714 INDUCTORS Inductors What is the range of values for on chip inductors 12 Inductor area is too large 1 0 XXXXXX quotE 8 8 g 6 00L 509 5 a 4 5 Interconnect parasitics 2 t l are 00 arge 0 1 10 20 30 40 Frequency GHZ Fig 65 Consider an inductor used to resonate with SpF at lOOOMHZ 1 1 4n2f02C 2n10925x103912 Note Off chip connections will result in inductance as well L 5nH ECE 4430 7 Analog Integrated Circuit Designl PE Allen 7 2002 Lecture 194 7 CMOS Passive Components 7 11 71002 Page 194715 C quot for39 sin CMOS technolo vare 1 Bond wires 2 Spiral inductors 3 Multi level spiral 4 Solenoid Bond wire Inductors Fig676 Function of the pad distance d and the bond angle 3 Typical value is lnHmm which gives 2nH to 5nH in typical packages Series loss is 02 Qmm for 1 mil diameter aluminum wire Q 60 at 2 GHZ ECE 4430 7 Analog Integrated Circuit Designl PE Allen 7 2002 Lecture 194 7 CMOS Passive Components 7 11 71002 Page 194716 Planar Spiral Inductors Spiral Inductors on a Lossy Substrate L R C1 C2 R1 R2 Fig 167 Design Parameters InductanceL 2Lself Lmumal wL Quality factor Q f l Self resonant frequency fself V7 Trade off exists between the Q and self resonant frequency Typical values are L l 8nH and Q 3 6 at 2GHZ ECE 4430 7 Analog Integrated Circuit Designl PE Allen 7 2002 Lecture 194 7 CMOS Passive Components 7 II 71002 Page 194717 Planar Spiral Inductors Continued Inductor Design Fig 59 Nmms 25 Typically 3 lt Ntums lt 5 and S Smin for the given current Select the OD Ntums and W so that ID allows sufficient magnetic flux to flow through the center Loss Mechanisms Skin effect Capacitive substrate losses Eddy currents in the silicon ECE 4430 7 Analog Integrated Circuit Designl PE Allen 7 2002 Lecture 194 7 CMOS Passive Components 7 II 71002 Page 194718 Planar Spiral Inductors Continued In uence of a Lossy Substrate L R WT C1 C2 Clo d a 121 1 Fig 122713 where L is the desired inductance R is the series resistance C1 and C2 are the capacitance from the inductor to the ground plane R1 and R2 are the eddy current losses in the silicon Guidelines for using spiral inductors on chip Lossy substrate degrades Q at frequencies close to fself To achieve an inductor one must select frequencies less than fself The Q of the capacitors associated with the inductor should be very high ECE 4430 7 Analog Integrated Circuit Designl PE Allen 7 2002 Lecture 194 7 CM05 Passive Components 7 n 71 002 Page194719 Comments concerning implementation 1 Put ametal ground shield between the inductor and the silicon to reduce the capacitance Should be patterned so ux goes through but electric field is grounded Metal strips should be orthogonal to the spiral to avoid induced loop current The resistance of the shield should be low to terminate the electric field 2 Avoid contact resistance wherever possible to keep the series resistance low 3 Use the metal with the lowest resistance and furtherest away from the substrate 4 Parallel metal strips if other metal levels are available to reduce the resistance Example mg 2542 ECE 4430 7 Analog negated Cucmt Design P E Allen 7 1001 Lecture 194 7 CM05 Passive Componean r H 71001 Page194710 MultiLevel Spiral Inductors Use of more than one level of metal to make the inductor Can get more inductance per area Can increase the interwire capacitance so the different levels are often offset to get minimum overlap Multielevel spiral inductors suffer from contact resistance must have many parallel contacts to re uce the contact resistance Metal especially designed for inductors is top level approximately 4pm thick Metal 8 Marat 3 MW 5 7 C1 Metal 3 T Substrate I j Sub iraie quot x 1 39 Substrate Q 576f5R 30740GHz Q 10711 fSR ng30GHzl Good for high Lin small area ECE 4430 7 Analog Intagated Clrcmt Destgnl o P E Allen 7 2002 Lecture 194 r CMOS Passive Components 7 11 71002 Page194r21 Inductors Continued Self resonance as a function of inductance Outer dimension of inductors SR Outer GHz Dimension 140 l m 130 12 12 Single 110 stacked Layer 100 100 so 80 BO 70 e 6 MS Ma 5 MB M5 M2 50 40 40 30 Single M8M5M2 20 Layer 20 10 f 1 I 10 20 30 40 50 L 10 20 30 40 50 L nH nH ECE 4430 7 Analog Integrated Circuit DesignI RE Allen 7 2002 Lecture 194 r CMOS Passive Components 7 11 71002 Page 194722 Transformers Transformer structures are easily obtained using stacked inductors as shown below for a 12 transformer Method of reducing the if inter winding capacitances Secondary Primary Ms M E 4 turns 8 turns 08 15 C 15 L E 5 5 5 506 a g 1 g cLG 5 39 3 gt g 39 gt0 05 I M quot395 cL1 pF 5 2 4 s a 1 4 s a 1n Frequency em ECE 4430 7 Analog Integrated Circuit DesignI 0 Ln mm 2W2

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