Digital Integ Circuits
Digital Integ Circuits ECE 4420
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This 0 page Class Notes was uploaded by Cassidy Effertz on Monday November 2, 2015. The Class Notes belongs to ECE 4420 at Georgia Institute of Technology - Main Campus taught by Staff in Fall. Since its upload, it has received 10 views. For similar materials see /class/233916/ece-4420-georgia-institute-of-technology-main-campus in ELECTRICAL AND COMPUTER ENGINEERING at Georgia Institute of Technology - Main Campus.
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Date Created: 11/02/15
Fabrication of CMOS ICs ECE4420 Jeff Davis Images taken from textbook J Uymura Introduction to VLSI Circuits and Systems John Wiley and Sons 2002 Outline Overview of Silicon Processing Material Growth and Deposition Lithography CMOS Process Flow Integrated Circuits created on Silicon Wafers 100 300mm Diameter Wafer Die sites Flat The water Is SHD ECIECI many Inulvmual processmg steps to make each ICE Fabrication Yield YEgtlt1OO N T NG Number of good working die NT Total number of die sites Yield enhancement is complex and time consuming Wafer Costs are approximately constant Diameter Example AMD vs Intel AMD Athlon XP 180nm 129mm2 200mm wafers Intel s P4 180nm 217mm2 200mm wafers Wafer AMD Athlon XP 130nm 80mm2 200mm wafers Intel s P4 130nm 116mm2 300mm wafers Die sites Flat Smaller Dies Less cost Outline Overview of Silicon Processing Material Growth and Deposition Lithography CMOS Process Flow Thermal Oxide Growth O 2 Flow x51 Si02 layer i I xox surfacev T T Silicon wafer Silicon wafer a Growth phase b Final structure X S z 046XOX thermal oxide SiO Si Wafer Si Wafer 503931 above original surface 5039 below original sun ace Dry VS Wet Oxidation Dry Oxidation Slow but high quality Heat accelerates reaction 8 02 a 802 Wet Oxidation Fast but high quality Heat accelerates reaction Si H20 a 802 2H2 WetDry Combo Example START 100 ptype 10 ohm cm wafers CLEAN in H2SO4H202 piranha etch 2 min Clean rinse dry RINSE 1 4 min RINSE 2 4 min DRY OXIDIZE 1 hr at 1000 C in Wet Oxygen place wafers in quartz oxidation boat insert into furnace anteChamber push at 12quot per sec at 800 C in Oxygen ramp to 1000 C 10 Cmin 20 min turn on steam 60 min ramp down to 800 C in Oxygen pull at 12quot per sec unload into plastic carriers CVD Oxide Process Deposited 102 on a surface Where no Si is present Si02 molecules 0 0 0 ca 0 0009 3 O 0600 0000 000000 009 Substrate Silane SiH4 gas 202 gas a SiO2 soid 2H20gas LTO Low Temperature Oxides Silicon Nitride Si3N4 0 Often called nitride only 0 Strong barrier to most items 0 Use as an overglass layer to protect chip 38iH4gas 4NH3 gas a Si3N4solid 12H2gas l Silane Ammonia Silicon Nitride Polysilicon Silicon Depositing silicon on Silicon Dioxide produces small crystallites areas Called poly for short Used for gate eletrotrode in FETs Even heavily doped this has high sheet resistance 0 Refractory metals such Ti coating on poly to decrease sheet resistance this is called a silicide SLH4 a Si 2H2 5006oooc Silane Metals Aluminum vs Copper 0 aluminum bulk resistivity 286e 6 Q Cm 0 copper bulk resistivity 167e 6 Q Cm Electromigration Current ow displace metal ions in metals dent High current density Electromi gration Hillocks current density Doping Silicon Layers selective doping is very important Ion Implantation Ion source Magnetic Accelerator Mass som Trimurme an Ion Implantation magnet Inn Snurce 39 wafer target The Ion Stopping Process 7 OIon energies control depth OK Silicon nuclei Can penetrate thin oxide layers 0 101r1 Kev 4 electron Clouds Silicon wafer Damage can resultbut is xed With an moderate heated ie annealing l gt x 0 Physics 101 One electron volt is equal to the amount of energy gained by an electron dropping through a potential difference of one volt which is 16 10 19 joules Gaussian Implant Pro le 1XRp2 2 AR NP IionXIVpe p N ionpd Straggle PrOJECIeu nan5n Chemical Mechanical Polish CMP Deposited oxide a After oxide deposition b After CMP Epitaxial Layer Growth EPI Tri TCS 10001180 C HCl 0 1 SinGz O Suuvce mm semmunducm amech cummummy edmun 15 15 Mama 5 pm Outline Overview of Silicon Processing Material Growth and Deposition Lithography CMOS Process Flow Photo 2 light EXCimer Laser Sources 0 250 130nmKrypton Fluoride KrF 248nm 90nm Argon Fluoride ArF 193nm 65nm Fluorine F2 157nm Reticle or Mask De nition A Glass Pattern on underside Remember During Layout using CAD tools this is what you are designing Photoresist Application U Photoresist coating Photoresist spray I Spinning wafer 39 9 Vacuum chuck a Resist application b Coated wafer Edge bead Edge bead Flat resist Wafer c Beading Exposure Step Reticle I Projection I I optics ll not shown resistcoated wafer surface Characteristics of positive photoresist MMH 14 Reticle lay r f Transmitted HM fingm J lt Resist Wafer Wafer a Exposure pattern b After development and rinsing Negative photoresist works in opposite way Etching an Oxide Layer Hardened resist layer Patterned oxide layer WWWe W M layer l Substrate J l Substrate a Initial patterning of resist b After etching process Reactive Ion Etching RF 3 5 6 ma lt plusnu MHZ wafers RIE Etching uses both ion bombardment and chemical reaction etching39quot A Hracqu maunonFIGuq u mu r on pm 1 SGEBa Sillcuu hm Ru Iimin 3 E MSource wwwatechsystemcokrcustomriepdf Reactive Ion Etch RIE Anisotropic Etch No undercut Source wwwatechsystemcokrcustomriapdf Ion Implantation of Doped Si Patterns Arsenic ions 3C 0 LC on o eh gt Substrate a Incoming ion beam b Doped n type regions note lateral doping Step and Repeat Process D die site quot 33 test site I 3 I v i I u I v I I t quotI a v I a I v I u Ila I I I I I v I I i u v 39 I v v II masking steps Clean Room De nitions Use HEPA lters that are 9997 effective of removing particles that are 05micr0ns or larger Class X clean rooms means that there are less than X particles per cubic foot With diameter greater than 05 micron OTypical clean room facilities have various class levels 0e g TSMC Fab 6 190000sqft 32000 wafer per month Class 100 ballroom has Class 01 SMIF minienviroments Outline Overview of Silicon Processing Material Growth and Deposition Lithography CMOS Process Flow nWell and Active Area Masking Steps p epitaxial layer p substrate a Starting wafer with epitaxial layer p Na n Well I MaSK b Creation of n Well in p epitaxial layer nFET and pFET will eventually go here Nitride Active Area Mask C Active area definition using nitride oxide Needed to define oxide electrical isolation between devices Field Oxide FOX growth d Silicon etch FOX FOX a m p Na e Field oxide growth f Surface preparation FiEld quotHue Ileeueu to Menu unlue eleuulual IaUIauuu nelweell ueViCES Self Aligned Gate Process GateDrainSource Regions are automatically aligned m p Na n Well a Gate oxide growth p01y 39 Poly Mask p Na nWell b Poly gate deposition and patterning Self Aligned Gate Process p gate electrode boron implant pSelect Mask p implants c pSelect mask and implant n gate electrode arsemc implant nSelect Mask n implants d nSelect mask and implant SourceDrain Contacts I 17 39quotquotquotI jquot 11 p nvwell 7 p Na a After anneal and CVD oxide tive Contact Mask Poly Contact b After CVD oxide active contact W plugs Mask Metal Masking Steps etal 1 Mask c M ta11 coating and patterning Via Mask Metal 2 Mask Bonding Pad Structure H To package pin Metal pad Overglass cut To silicon a Top View b Side View Lightly Doped Drain LDD nFET n implant n implant n implant spacers no additional mask needed d Heavy donor implant Lightly Doped Drain LDD nFET n implant n implant n implant spacers no additional mask needed d Heavy donor implant Sthldes oDefined as a refractory metaleg TiTaPt etc coated over silicon or polysilicon oReduce sheet resistance of gate from 25 2 to 10s mm P39type p type a LDD FET structure b Silicide formation Silicide reduces contact resistance of Tungsten Contact Copper Interconnect Damascene Oxide trenches for cu copper patterns I I I X I I 7 Iquot X 393 If R If x a x a x r quot 39 i quot I 39 3quot quot quot39 39 39 192 e Wafer Wafer C After planarization Copper needs a barrier layer eg TiN to block diffusion to Si02
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