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# Analog Integra Circuits ECE 4430

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This 0 page Class Notes was uploaded by Cassidy Effertz on Monday November 2, 2015. The Class Notes belongs to ECE 4430 at Georgia Institute of Technology - Main Campus taught by Staff in Fall. Since its upload, it has received 58 views. For similar materials see /class/233922/ece-4430-georgia-institute-of-technology-main-campus in ELECTRICAL AND COMPUTER ENGINEERING at Georgia Institute of Technology - Main Campus.

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BJT Differential Ampli ers 62400 Page 1 34 BJT DIFFERENTIAL AMPLIFIERS INTRODUCTION Objective The objective of this presentation is 1 Define and characterize the differential amplifier 2 Show the largesignal and smallsignal performance 3 Show alternate implementations of the differential amplifier Outline Characterization and definitions Largesignal transconductance Largesignal voltage transfer Smallsignal performance Other characteristics of the differential amplifier Summary k ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 BJT Differential Ampli ers 62400 Page 2 CHARACTERIZATION AND DEFINITIONS What is a Differential Amplifier A differential amplifier is an amplifier that amplifies the difference between two voltages and rejects the average or common mode value of the two voltages Symbol for a differential amplifier V 1 V2 VOUT IT Fig 521A Differential and common mode voltages v1 and v2 are called singleended voltages They are voltages referenced to ac ground The differentialmode input voltage v 1D is the voltage difference between v1 and v2 The commonmode input voltage v 1C is the average value of VI and v2 v1v2 VID v1 v2 and VIC 2 gt v1 VIC 05le and v2 VIC 05va v1 v2 VOUT AVDVID i AVCVIC AVDV1 39 V2 i AVC 2 where VOUT AVD differentialmode voltage gain T Fig 521B AVC commonmode voltage gain k ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 BJT Differential Ampli ers 62400 Page 3 Differential Amplifier Definitions Common mode rejection rate CMRR A VD CMRR AVC CMRR is a measure of how well the differential amplifier rejects the commonmode input voltage in favor of the differentialinput voltage Input commonmode range ICMR The input commonmode range is the range of commonmode voltages over which the differential amplifier continues to sense and amplify the difference signal with the same gain Typically the CMR is defined by the commonmode voltage range over which all MOSFETs remain in the saturation region and all BJ Ts remain in the active region Output offset voltage VOSout The output offset voltage is the voltage which appears at the output of the differential amplifier when the input terminals are connected together Input offset voltage VOSin VOS The input offset voltage is equal to the output offset voltage divided by the differential voltage gain Vos0ut V03 2 AVD k ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 BJT Differential Ampli ers 62400 Page 4 LARGESIGNAL TRANSC ONDUCTANCE Transconductance Characteristic of the Differential Am lifier Consider the following NPN BJ T differential amplifier sometimes called an emittercoupled pair i i 1C1 1 llcz VEE BJTDAOI LargeSignal Analysis 11nput 1001 e411 V11 39 VBEi VBE2 39 V12 2 V11 39 V12 39 VBEi VBE2 VID 39 VBEi VBE2 0 2 Foward active re ion39 v V In and v V In g BEl t SI BE2 t 1S2 iCl V1139V12 V11 3 If 1 then eX eX S1 32 1C2 P Vt J th 1 4 Nodal current equatlon at the emltters iE1iE2 IEE a iCl iCZ F FIEE FIEE 5 Combmmg the above equatlons gives iCl and iC2 1 VID 1 v2 exp Vt exp Vt k ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 BJT Differential Ampli ers 62400 Page 5 Transconductance Characteristic of the Differential Am lifier Continued Plotting the collect current as a function of VIDI l 08 06 1C WEE 04 02 0 5 4 3 2 1 0 1 2 3 4 5 LD BJTDAOO VI Transconductance I CV 1 when V 0 gm 3le Q 39VID 12 4Vt 2Vt ID Llexp TJ Vt t aiCZ l 39O FIEE 39O FIEE 39ICZ when V Z 0 gm 8le Q VID 2 4V 2V ID leXp 7 Vt L t J L ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 BJT Differential Ampli ers 62400 Page 6 VOLTAGE TRANSFER CHARACTERISTICS Lar eSi nal Volta e Transfer Function Assume load resistors as shown VEE BJTDA03 39 VOD 2 V0139V02 VCC39iClRC 39 VCC iCZRC RCiC239iC1 1 Substituting in the previous expressions and using hyperbolic trig identities gives 05 vD VOD vOD aFIEERC tauh2 Vt XFIEERC 0 Illustration gt 0 5 l 5 4 3 2 l 0 l 2 3 4 5 VI BJTDA04 ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 BJT Differential Ampli ers 62400 Page 7 Emitter De eneration 0f the BJT Differential Am lifier Increases the range over which the emittercoupled pair behaves as a linear amplifier with lower gain at the cost of lower gain VOD XFIEERC Increasing 05 RE I I I I I I I I I I m 25 20 15 10 5 10 15 20 25 VI W 05 RE0 l BJTDAOS We know that 1D lCl 1C2 OCFIEE ta z OCFIEE Solving for I39D gives I39D iCl iC2 E Ig t E EE dip FIEE FIEEyZ Vt gmmc 61le 2Vt REIEE 1 REIEEZVt k ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 BJT Differential Ampli ers 62400 Page 8 SMALLSIGNAL PERFORMANCE Differential and Commonmode SmallSi nal Performance The smallsignal performance of a differential amplifier can be separated into a differential mode and common mode analysis This separation allows us to take advantage of the following simplifications HalfCircuit Concept lt amp D lt amp D VEE VEE BJTDA06 Note The halfcircuit concept is valid as long as the resistance seen looking into each emitter is the same k ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 BJT Differential Ampli ers 62400 Page 9 SMALLSIGNAL PERFORMANCE Differential and Commonmode SmallSi nal Performance The smallsignal performance of a differential amplifier can be separated into a differential mode and common mode analysis This separation allows us to take advantage of the following simplifications HalfCircuit Concept lt amp D lt amp D VEE VEE BJTDA06 Note The halfcircuit concept is valid as long as the resistance seen looking into each emitter is the same k ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 Dage 10 BJT Differential Ampli ers 62400 SmallSi nal Common Mode Performance of the BJT Differential Am lifier Circuit and smallsignal model Rm Ram I I LB 4 gt VT V75 ngrc Va gt Vic Rc i Vaul ZREBE v BJTBAOS Halfcircuit performance l 3012REE l V01 BolRC R1711 r71 1l3012REE Routl Vol ZREErn1J 2REEHVm a and Z 39 rn1l 012REE Common mode performance V n11 ol2REE R 1 OIZREE 1 2R H d Voc 301RC r r an 2 06 0L ZREEV n1 EE 1 Vic V n11l3012REE ic Where gml gmz V7271 772 and B01 302 PE Allen 2000 k ECE 4430 Analog Integrated Circuits and Systems BJT Differential Ampli ers 62400 Dage ll Common Mode Rejection Ratio CMRRl The common mode rejection ratio is a measure of the differential amplifier s ability to reject the common mode signal and amplify the differential mode signal A gmlRC I R v v CNIRR Adm 01 1d 2 2 ngIREE EE EE cm Vol Vic BolRC 2Vt r7z11l3012REE Thus the larger the input transconductance or REE the larger the common mode rejection ratio x ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 BJT Differential Ampli ers 62400 Dage 12 OTHER CHARACTERISTICS OF THE DIFFERENTIAL AMPLIFIER Input Common Mode Voltage Range The input common mode voltage range IClVlR is the range of common mode input voltages over which the differential amplifier amplifies the differential signal without significant change Consider the following BJTDA03 Maximum Input Common Mode Voltage Minimum Input Common Mode Voltage vlCmaX VCE1SatVBE1 vicmin VEEVCE3SatVBE1 k ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 BJT Differential Ampli ers 62400 Dage l3 Slew Rate of the BJT Differential Am lifier Slew rate is a voltage rate limit due to the fact that the current available to charge a capacitor is constant dVC iC Slew rate SR 7 6 where iC and vC are the current through and voltage across a capacitor C A differential amplifier that has a capacitive load will experience slew rate which is seen as follows f VCC f VCC R ltgt ltgt LE ltgtRc R 21113 Cltgt VOD ltgtRC z39CS 2 ltgt VOD cs 0 Cltgt 2 z39Cs Situation at VC1 39 VCZ 39 gt Cs J ZCI l C l CZ Cs J VOD 39 0 Cs J ZCI 01 C0 iCo 11C271EEJ Cs I 0 I I I Q1 Q2 Q1 Q2 39 Vi1ltlto VBE1 VBE2 Vi2gtgt0 Vi1ltlt0 VBE1 VBE2 Vi2gtgt0 T IEE T T IEE VEE VEE BITDA09A Note that the current in Q1 is 0 and Q2 is IEE Therefore the initial value of iCO is iCO 051EE iCS dv dv o Cl OD Z COCS 1e dt 05 dt 051EE 1C 1C If we define the slew rate across Co as SR C 0 then iCS 05SRCS O IEE 0 IEE iCs IEE SR39Cs Cs IEE SREC O2C 2C0 gt SR1 2C0 E gt SR 2 C005CS Z 2C0CS k ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 eurrent Mirrors 51100 Pasu 1 CURRENT MIRRORS INTRODUCTION Objective The objective of this presentation is 1 Introduce and characterize the current mirrors 2 Show how to improve the performance of the current mirrors 3 Demonstrate the design of current mirrors Outline Simple MOS current mirrors Simple BJ T current mirrors Cascode current mirrors Wilson current mirrors Regulatedcascode current mirrors Summary Kl5 E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r eurrent Mirrors 51100 SIMPLE MOS CURRENT MIRRORS Characterization of Current Mirrors A current mirror is basically nothing more than a current amplifier The ideal characteristics of a current amplifier are A z39 Output current linearly related to the input current 139 out l m Input resistance is zero Output resistance is infinity In addition we have the characteristic VMIN which applies not only to the output but also the input VMINin is the range of input voltage over which the input resistance is not small VMINout is the range of the output voltage over which the output resistance is not large Graphically lIin lHour Slope lRin 14139 l m i l V 1in lHaul gt O C Current Vm Vaut M1rror 7 r m 39 VMIN in Input Characteristics Therefore we will focus on Rout Rm Transfer Characteristics VMINout VMINin and Al to characterize the current mirror Page 2 lIaut Slope lRam L1 r um 39VMiN0ut Output Characteristics Fig 441 PE Allen 2009 K156E 4430 Analog Integrated Circuits and Systems eurrent Mirrors 51100 Pasu 3 Simple MOS Current Mirror M1 M2 VDSl VDSZ VG S Fig 44 2 Assume that VDS2 gt VGS VD then 1392 L1W2 VGS39VTZ 1 AVDSz 1391 W1L2 VGS39VTI 1 lVDSl K1 If the transistors are matched then K1 K2 and V VD to give i0 LIWZ l lVDS2 i WILZ 1VDS1 If VDSI VDS2 then 1390 L1W2 139 W1L2 Therefore the sources of error are l vDSli VDS2 and 2 M1 and M2 are not matched Kl5 E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r eurrent Mirrors 51100 Pasu 4 In uence of the Channel Modulation Parameter 7t If the transistors are matched and the WL ratios are equal then i0 1 AVDSZ i1 l lVDSl assuming that the channel modulation parameter is the same for both transistors L1 L2 Ratio error versus drain voltage difference 80 1002 e E 8 70 j Rario Error va vm1 volts x 60 10015 50 L a a 7 5 5 ltlt ltlt 40 1001 7 g 30 i 5 t m E 20 L 1 M 1390 vm1 20 volt 00 7iiii iHi iiii HH iiii i H HH HH HH HH 00 10 20 30 40 50 vavm1 volts Flg 443 Note that one could use this effect to measure 2 Measure VDSIVDSZ 139 and i0 and solve the above equation for the channel modulation parameter 2 Kl5 E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r eurrent Mirrors 51100 Page 5 In uence of Mismatched Transistors Assume that VDSI VDS2 and that K 1 75 K2 and V at VTZ Therefore we have 12 K2 VGS 39 V722 1 K1 VGS39 VTi2 How do you analyze the mismatch Use plus and minus worst case approach Define AK K 2 K l K 05K2 Kl AVT VTZ VTI and VT 05VT1VT2 Kl K 05AK K2 K 05AK VT1 VT 05AVT and VB VT05AVT Substituting these terms into the above equation gives AK AVT i0 K 05AK VGS VT 05AVT2 1 Jr 1 Z K 05AK VGS VT 05AVT2 AK AVT 39fll 2ltvas VT Assuming that the terms added to or subtracted from 1 are smaller than unity gives 1390 AK AK AVT AVT 1 A l 2K 1 2K 1 2VGSVT l 2VGSVT Uses the appr0X1mat10n ll8 2 le Retaining only first order products gives 1390 AK ZAVT 4 l l K VGs VT Assume AKVK i5 and AVTVGSVT i10 39 iOi 2 l i 005 i020 l i 025 gt i15 error in gain iftolerances are correlated K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 eurrent Mirrors 51100 Illustration of the Offset Volta e Error In uence Assume that VTl 07V and K WL llOuAVZ 5101 41gtlt100 i13uA 0 x I i SuA Ratio Error m o i110uA i1100uA iiiWm iii WWii mm Wm mwm 00 10 20 30 40 50 60 70 80 90 10 AVTmV Fig 444 Key Make the part of VGS that causes the current to ow VON more significant than VT Kl5 E 4430 Analog Integrated Circuits and Systems Page 6 PE Allen 2009 r eurrent Mirrors 51100 In uence of Error in As ect Ratio of the Transistors Example 1 Aspect Ratio Errors in Current Mirrors W125 i0l um andW220i0l um Solution consequently the gain of the current amplifier is 01 li J O io20i01 iI Wl 20 5 H U19 p A error is 15 of the desired current ratio or gain l39l I I I I I I ll k I l Page 7 Figure 444 shows the layout of a onetofour current amplifier Assume that the lengths are identical L1 2 L2 and find the ratio error if W1 2 5 i 01 gm The actual widths of the two transistors are We note that the tolerance is not multiplied by the nominal gain factor of 4 The ratio of W2 to W1 and 01 0l 01 04 441i 1 441i 4006 20 20 where we have assumed that the variations would both have the same sign correlated It is seen that this ratio K156E 4430 Analog Integrated Circuits and Systems Fig 445 PE Allen 2009 r eurrent Mirrors 51100 Page 8 In uence of Error in As ect Ratio 0fthe TransistorsContinued Example 2 Reduction of the Aspect Ratio Errors in Current Mirrors Use the layout technique illustrated in Fig 445 and calculate the ratio error of a current amplifier having the specifications of the previous example Solutions The actual Widths of M1 and M2 are W1 5 i 01 um and W2 45 i 01me The ratio of W2 to W1 and consequently the current gain is given below and is for all practical purposes independent of layout error i04 5i0124 i 5i0l Fig 446 K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 eurrent Mirrors 51100 Page 9 Summa 0f the Sim 1e MOS Current MirrorAm li er Minimum input voltage is VMlN n VTVON Okay but could be reduced to VON Principle Fig 44 7 Will deal with later in low voltage op amps Minimum output voltage is VMINout VON 1 Output resistance is Rout f D 1 39 Input res1stance 1s Rm 2 g m Current gain accuracy is poor because VDSI 7t VDS2 K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 eurrent Mirrors 51100 Fuse 10 SIMPLE BJT CURRENT MIRRORS Characterization of a Sim 1e BJT Current Mirror Rout r02 C2 quot gm1 1C1 VMIN0ut vCEsat 2 02V VBE 2 t0 and 2 Al L 1f the trans1st0rs are matched and 3 00 sl K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 eurrent Mirrors 51100 Page 11 Sim 1e BJT Current Mirror Matchin Circuit i 139C1 39lic2i2 11 1C1IB1132 1E1132 a le F1 VCE1 Q2 VCE2 v2 1C1 1 VAl Sl eXpvBEVt and CMll VCE2 1C2 12 1 ES2 eXpvBEVt Now VCE1 Isl iCZ 1392 139am V2 i eX V i andi 2 2 2 1 I eX V 1 VA 1 Ian P BE t 32 32 gm I VAZ 32 P BE t 0512 V1 Isl Lam V2 139 1 1 eX v V 1 VAlIaFl 09172 VA2 s2 P BE t K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 eurrent Mirrors 51100 Page 12 Sim le BJT Current Mirror Matchin Continued Using a Taylor series expansion and ignoring the secondorder terms we have i2 132 1 11 v2 1s1 lt1390 F2gt VAl V142 aFl an S2 For large 3F 06F 22 1 2 1s 2 1391 2 v1 v2 VA1 VA2 SI Again using Taylorseries expansion 1392 1s2 V1 V2 22 1 l1 Is1 VA1 VA2 Let AIS 132 Isl and IS 2213123 132 L2 1 l 12 i1 Is quotVA1 VA2 A For v1 VBE 07V v2 5V S 002 VA 50 s L2 11 a 111 gt 11 error due primarily to mismatch in Rout v1 and v2 K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 eurrent Mirrors 51100 Page 13 Geometrical In uence on BJT Matchin If everything is ideal F co and VCEI VCEZ the Collector Emitter Area matching of the currents is determined by the matching of the Contact 1 Base saturation currents I which is given as K I Coma 3 CM18 Emitter Contact I 477121 A 417121 A S NAWBVCB E QBVCB E Therefore the transistor matching directly depends on how well the emitter areas are matched If a current gain greater than 1 is required the emitter areas should be implemented as follows Metal 2 C1 Metal 1 C2 CM19 B1 Current gain of the above structure is 15 K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r eurrent Mirrors 51100 Page 14 Rules for Matchin ofNPN BJT Transistorsr Use identical emitter geometries The emitter diameter should equal 210 times the minimum allowed diameter Maximize the emitter areatoperiphery ratio circle the best square okay Place matched transistors in close proximity Keep the layout of matched transistors as compact as possible Construct ratioed pairs and quads using even integer ratios between 41 and 161 Place matched transistors far away from power devices 00lOUIJgtUJN Place matched transistor in lowstress areas thermal and physical O P1ace moderately or precisely matched transistors on axes of symmetry of the die A O Do not allow the buried 1ayer shadow to intersect matched emitters must overlay the emitter area 11 Place emitters far enough apart to avoid interactions A J Increase the base overlap of moderately or precisely matched emitters 13 Operate matched transistors on the at portion of the beta curve 14 The contact geometry should match the emitter geometry circular contact for circular structure square contact for square structure etc 15 Consider using emitter degeneration 1 Alan Hastings The Art of Analog Layout Chapter 9 1998 Unpublished text VRGlmsgticom K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r eurrent Mirrors 51100 Page 15 Rules for Matchin Lateral PNP Transistors Use identical emitter and collector geometries Use minimumsize emitters for matched transistors Field plate the base region of mateched lateral PNP transistors Splitcollector lateral PNP transistors can achieve moderate matching Place matched transistors in close proximity If possible avoid constructing VPTAT circuits from ratioed lateral PNP transistors Place matched transistors far away from power deVices oouoxmgwww Place matched transistor in lowstress areas thermal and physical 9 Place moderately or precisely matched transistors on axes of symmetry of the die 10 Do not allow the buried layer shadow to intersect matched emitters must overlay the emitter area 11 Operate matched lateral PNP transistors near peak beta 12 The contact geometry should match the emitter geometry circular contact for circular structure square contact for square structure etc 13 Consider using emitter degeneration Kl5 E 4430 Analog Integrated Circuits and Systems PE Allen 2009 eurrent Mirrors 51100 Fuse 16 Sim le BJT Current Mirror for Finite Circuit If the transistors are matched and vCEl VCEZ then iCl iC2 but 2 211 If 3F is small then appreciable error is introduced into the current gain Solutions to this problem K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 eurrent Mirrors 51100 Fuse 17 BaseCurrent Cancellation In a BiCMOS process base current cancellation is possible and using the following technique VDD CM13 If Q1 and Q2 are matched then Cl 2 1C2 and Bl 2 132 The cascode current mirror is used to make sure that I Bl 132 Kl5 E 4430 Analog Integrated Circuits and Systems PE Allen 2009 l l R r r a m gm3 ds3 gml dsl VMIMOUO VT VMIMin 2VT V0N l l 2 Q gml gm3 gm Current gain match Excellent since vDSl VDS2 K156E 4430 Analog Integrated Circuits and Systems eurrent Mirrors 51100 Fuse 18 CASCODE CURRENT MIRRORS MOS Cascode Current Mirror Improving the output resistance D4 139 11 110 gm4Vgs4 M3 M4 Vaul lHour gt ltgt Ml M2 ngVgSZ Fig 448 Rout Vout rds4iout39gm4vgs4 rd32iout39gm2vg32 But iiquot 0 SO V1 V3 0 2 Vgs4 VS4 i0utrdS2 and Vgsz 0 Vout lIoutlrals4 rds2 gm4rd32rds4 2 rdslgm4rds4 Rm PE Allen 2009 eurrent Mirrors 51100 Fuse 19 Lar e Out ut Swin Cascode Current Mirror A VVV gt ltgtVS5 r Fig 44 9 39 Rout 2 gm2rd32rdsl 39 Rm 2 Vin rds5iin 39 ngVgSS V35 rds5iin gm5vs5 V35 rdSSiin 1gm5rd35V35 BUt V35 rds3iin 39 gm3vin Vin rdSSiin 1gm5rd35rds3im 39 gm3rds31gm5rds5vm 39 VMIMOUO 39 VMIMin VT VON Current gain is excellent because vDSl VDS3 K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r eurrent Mirrors 51100 Fuse 20 SelfBiased Cascode Current Mirror VDD 12 lIaut M4 Vin I M1 M2 lt rem Selfbiased cascode current mirror Smallsignal model to calculate Rm Fig 4410 39 Rm 2 Vin lIz39nR rds3iin39gm3vgs3 rdsliin39gmlvgsl BUt Vgsl Vin 39 lIz39nR and Vgs3 Vin 39 rdsliin39gmlvgsl Vin 39 rdsliin gmlrdslvin39iinR Vin lIz39nR rds3iin 39 gm3rds3lvin 39 rdsliin gmlrdslvin39iinR rdslliin 39 gmlviniinR Vinll gm3rds3 gmlrdslgm3rds3 gmlrdsl 1ian rdsl rds3 gm3rds3rdsl gmlrdslgm3rds3R R rdsl rds3 gm3rds3rdsl gmlrdslgm3rds3R 1 R A R m 1gm3rds3 gmlrdslgm3rds3 gmlrdsl gml 39 Rout 2 gm4rds4rds2 VMINin VT ZVON VMN0ut ZVON Current gain matching is excellent K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 eurrent Mirrors 51100 Page 21 BJT Cascode Current Mirror Advantages Because VCE1 VCEZ this mirror will have very good matching if 3F is very large Output resistance large because of cascoded output Rout 2 F4r02 Disadvantages VMIN0ut VBEl VCE4Sat VMJNOH VBEi VBE3 2VBE K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r eurrent Mirrors 51100 Fuse 22 Im rovin the Matchin 0f the BJT Cascode Current Mirror liOUT Q4 Q2 CM15 Achieves the desired base current Achieves the desired base current cancellation cancellation using only two stacked However there are three transistors stacked translstors at the output which will cause a large VMIN VMIN VBE VCEsat K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 eurrent Mirrors 51100 Improving VMINofthe BJT Cascode Current Mirror Page 23 Use the trick of freeing the voltage at the bases of the cascode transistors to get Q3 VBE BE VCESat VCESat JVBE j T CM16 Advantages VMINout ZVCEsat Rout a BFVO VMINOn VBE lowest possible without using extreme methods Disadvantages Screwed up the current mismatch Okay if 3F is large or you can use another transistor but VMlN n will increase Requires a battery of VBE vCEsat K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 eurrent Mirrors 51100 v sat Design R so thatR Comments K156E 4430 Analog Integrated Circuits and Systems SelfBiasedaVMIndout BJT Cascode Current Mirror Can eliminate the battery using the selfbiased concept as illustrated below 1391 1 VCEsat R Minimum VMINout can be obtained ZVCEsat The VMINin is equal to VBE vCEsat Page 24 Still have current mismatch if 3F is not large can use two more transistors to eliminate the mismatch PE Allen 2009 r eurrent Mirrors 51100 Page 25 WILSON CURRENT MIRROR BJT Wilson Current Mirror E E L L ic1 lll 112 12ZB3 lC2lBl 132 gt 121BF lC21BF BF Q3 iCll 1 1 2 F 1 1 1 llcz 2 C2 13F C21 F Q1 Q2 T CMZO ov1ng or 1C2 gives 1C2 2 F 2 1392 Substituting for iCl iC2 into 1391 iCliB3 iClB gives F 1I3F i2 1BFL BF22BF1 i2 B F 11 BF lz BF 12 23 2 23 B F i 1 BF 22l3F 1 How does the Wilson current source work Negative feedback lf 1392 increases because VOUT increases then the voltage at the base of Q1 increases The increase of voltage at the base of Q1 appears as a decrease at the base of Q3 Therefore the original increase in 1392 is opposed It can be shown that Rout 2 05 Fr0 however VMIN out VBEVCEsat and VMINOn ZVBE Wilson current mirror suffers from poor matching vCE1 ZVCEZ Kl5 E 4430 Analog Integrated Circuits and Systems PE Allen 2009 eurrent Mirrors 51100 Fuse 26 Wilson MOS Current Mirror lHour 11 110 M3 gm3Vgs3 me E Vgs3 Vaul M1 M2 gt gt 7 Vin glegsl rd51gtgm2vgs2 VdsZ gtV8527V851 Fig 44 11 Uses negative series feedback to achieve higher output resistance 39 Rout 117120 Vout rd32lout 39 gm3vgs3 VgsZ lHour rdSZiout v 2 and v g r v v lg r v gsZ gm2gd32 1gm2rdS2 gs3 m1 dsl gsZ gsZ m1 dsl gsZ 1gm3rd32gmlrdslgm3rds3 39 Vout rds210ut gm3rd321gmlrdslvg32 tout rds3rd52 1 ngVdSZ R 1gm3rd32gmlrdslgm3rds3 gmlrdslgm3rds3 out 6133 dSZL 1 gmzrdsz gmz Kl5 E 4430 Analog Integrated Circuits and Systems PE Allen 2009 eurrent Mirrors 51100 Wilson Current Mirror Continued 39 Rm 2 Vout 0 gmlgm3vgs3 gmlgm3vgs3 1 2 V 2 m gnu g gm2gd32gds3 gm2 gm 1gm3vgs3 V V V Z V gs3 m gsl m gmz gs3 gmlgm3 Vin Z gm2 gm3 l 2 m gm2 gm3 m gmlgm3 39 VMIMin 2VT VON 39 VMIMOUO VT Current gain matching poor vDSl 7t VDS2 Page 27 Vin gmlgm3 1 gm2 Kl5 E 4430 Analog Integrated Circuits and Systems PE Allen 2009 eurrent Mirrors 51100 Fuse 28 Evolution of the Re ulated Cascode Current Mirror from the Wilson Current Mirror ill lio M2 Wilson Current Mirror Redrawn Regulated Cascode Current sink Fig 44 12 Kl5 E 4430 Analog Integrated Circuits and Systems PE Allen 2009 eurrent Mirrors 51100 Page 29 REGULATED CASCODE CURRENT MIRROR MOS Re ulated Cascode Current Mirror 139 l BitIsl M4 M2 7 FIG 4413 2 3 Rout gm rds R g L m VMIN0ut VT2 VONCan be reduced to ZVON VMINin VTVON Can be reduced to VON Current gain matching good as long as VDS4 VDS2 K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r eurrent Mirrors 51100 Fuse 30 BiCMOS Re ulated Cascode Current Mirror Circuit VDD W11 Mll M15 MII 6JMII ZI i i i i i LO UT 1amp4 16 MS 141 c 171 Isl M3 Kw Mj M4 VOUT Q2 VCESat W 4 ch21 Constraints Let I 4 16 and 15 16 If the WL values of M4M7 are equal than these currents can be used to set the collectoremitter voltages of Q1 and Q2 gds7gdsl4gnlgn2 m z Rom 3 701gm3rds3gm50ds5Inks VMJMOUD VMJAm Vc sat gm lg m7g m8 and the current matching will be excellent PE Allen 2009 K156E 4430 Analog Integrated Circuits and Systems r eurrent Mirrors 51100 Page 31 SUMMARY Summa of MOS Current Mirrors Current Mirror Accuracy Output Input Minimum Minimum Input Resistance Resistance Output Voltage Voltage 1 Simple Poor Vds VON VT VON gm 2 Cascode Excellent gmrdsz g VT2 VON 2 VT VON m Wide Output Swing Excellent gmr 6132 i ZVON VTVON Cascode gm Selfbiased Excellent gmr 6132 R i ZVON VT2 VON Cascode gm 2 Wilson Poor gmrds2 g 2 VT VON VT2 VON m Regulated Cascode GoodExcellent g mz 5133 i VT2 VON VT VON gm min is ZVON min is VON K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r Temp Indep Biasing 71400 Pasu l 45 A43 TEMPERATURE INDEPENDENT BIASING BANDGAP INTRODUCTION Objective The objective of this presentation is 1 Introduce the concept of a bandgap reference 2 Show circuits that implement the bandgap reference 3 Show how to improve the performance of the bandgap reference Outline Introduction Development of the bandgap circuit Bandgap reference circuits Improved bandgap reference circuits Summary K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r Temp Indep Biasing 71400 Page 2 Temperature Stable References The previous reference circuits failed to provide small values of temperature coefficient although sufficient power supply independence was achieved This section introduces the bandgap voltage concept combined with power supply independence to create a very stable voltage reference in regard to both temperature and power supply variations Band a Volta eReference Princi 1e The principle of the bandgap voltage reference is to balance the negative temperature coefficient of a pn junction with the positive temperature coefficient of the thermal voltage Vt kTq Concept VBE 2mVquotC VREF VBE KV Fig 461 Result References with TC F s approaching 10 ppm C Kl5 E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r Temp Indep Biasing 71400 DEVELOPMENT OF THE BANDGAP REFERENCE CIRCUIT erivation of the Tem erature Coef cient of the BaseEmitter Volta e Pa5c3 D To achieve small TCF s we must know the TCF of VBE more precisely than approximately 2mV C 1 Start with the collector current density JC q D11 npO VBE Jc WB e p Vt where Jc IcArea collector current density D n average diffusion constant for electrons WB base width VBE baseemitter voltage kT Vt q k Boltzmann s constant 138X103923J K T Absolute temperature np0 niZNA equilibrium concentration of electrons in the base VG0 ni2 DT3 exp Vt 1ntr1ns1c concentratron of carr1ers D temperature independent constant VGQ bandgap voltage of silicon 1205V N A acceptor impurity concentration K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r Femp Indep Biasing 71400 Page 4 Derivation of the Tem erature Coef cient of the BaseEmitter Volta e Continued 2 Combine the above relationships into one q Dn VBE VGO VBE VGO 3 Y Jc NAWB DT exp Vt AT eXp Vt where y 3 3 The value of Jo at a reference temperature of T To is Jco AToY exp VBE Vow 0 while the value of Jo at a general temperature T is Jc ATY exp ff VBE VGo 4 The ratio of JcJco can be expressed as JC l V q VBEVGo VBEoVGo Jco To exp k T 39 T0 J C T T 1n E Y 1nT 0 qu VBE VGO T O VBEo Vow where VBEO is the value of VBE at T To 5 Solving for VBE from the above results gives T T XlgT T0 kT JC n VBET VGO1 To VBE0T0 q 1nT q 1 J00 Kl5 E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r Femp Indep Biasing 71400 Page 5 Derivation of the Tem erature Coef cient of the BaseEmitter Volta e Continued 6 Next assume Jc oc T06 and find BVBEBT VBE VGO l M mamp 1HltT0Tgt 1 m vaqkT 1nltJcJcogt JC T T quotTO39TO T0 q T T T qL T q Jco 7 Assume that T To which means Jc Jco Since BVGoBT 0 VBE l VGO VBEO Jr 1nToT kT lnJcJco T TTO T0 T0 q T q T 8 Note that m 1ltToTgt lT0 1 d macJoe Jco JCJco JC0 gJC j T To T To T2 Tan T Jc T Jc TJCO T Therefore VBE I E 3k 0ck VBE VBEoVGo g T TTo 39 T0 T0 39 q q or T TTo T0 aYq Typical values of 0a and y are l and 32 Therefore if VBEo 06V then at room temperature VBE l 061205 0026 06120501092 o T H0 300 032 300 300 1826mVC Derivation of the Temperature Coef cient of the Thermal Voltage ngq 1 Consider two identical pn junctions having different current densities Kl5 E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r Femp Indep Biasing 71400 Pasu 6 DD VDD 1C1 1C2 AEl AE2 T Fig 462 q J02 nJc1 J02 kT JC1 AVBE VBE1 VBE2 1u 2 Find 8AVBE8T ME JC1E T Tnchq K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r Femp Indep Biasing 71400 Page 7 Derivation of the Gain K for the Band 3 Volta e Reference 1 In order to achieve a zero temperature coefficient at T To the following equation must be satisfied VBE AVBE T l H 0 T TT0 K where Kquot is a constant that satisfies the equation 2 Therefore we get V J V V 06 V 0Kut0 mg BEO GO lt Y to T0 T0 J 3 Define K Kquot therefore C2 V V V 1 V to BEO G0 Y t0 OZKT o T0 T0 V V V OL 4 Solving for K gives K W Assuming that JClch AElAEZ 10 and VBEO 06V gives K 1205 06 92290262 25 469 0026 5 The output voltage of the bandgap voltage reference is found as VREF VBEo KVtO VBEo VGO VBEO YOCWto 0r VREF VGO YOOVto TT0 For the previous values VREF 1205 002622 1262V K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r Femp Indep Biasing 71400 Page 8 Variation ofthe Band 3 Reference Volta e with res ect to Tem erature The previous derivation is only valid at a given temperature To As the temperature changes away from To the value of BVREFBT is no longer zero Illustration VRE V t 1290 BVREF T0 400 K 3T 1280 2271f aVREF 0 T0 300 K BVREF 0 1250 BT 10 T0 200 K 1240 39 I I I I I I I I I I TOC 60 40 20 0 20 40 60 100 120 Fig 463 Bandgap Curvature Correction will be necessary for 10w ppmC bandgap references KI5 E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r Temp Indep Biasing 71400 6 Fig 464 Example K156E 4430 Analog Integrated Circuits and Systems BANDGAP REFERENCE CIRCUITS Classical Widlar Band a Volta e Referencel Operation VBEi VBE2 12R3 gives AVBE VBEi VBE2 12R3 But 11 12 111s2 AVBE Vt lu181 Vt ll 1182 Vt ll 112181 Assume VBE1 2 VBE3 we get I1R1 I2R2 Therefore 12 AVBE 1119 2 1nR21s2 R3 R3 121s1 R3 Rilsi Now we can express VREF as R2 R21s2 VREF 12R2 VBE3 R 3 Vt 1nm VBE3 KVt VBE Design R1 R2 Isl and I52 to get the desired K Let K 25 and I52 10151 and design R1 R2 and R3 Choose R2 10R1 lOkQ ln100 4602 Therefore R2R3 254602 or R3 R254287 1842kQ l RI Widlar New Developments in IC Voltage Regulators IEEE J afSalid Stale Circuits Vol SC 6 pp 27 February 1971 Page 9 PE Allen 2009 r Femp Indep Biasing 71400 Page 10 A CMOS Band 3 Reference usin PNP Lateral BJTs Bootstrapped Voltage Reference using PNP Laterals 113 V55 Fig 465 IVBE1VBE2 ln11 1n12 1 1s2 2amp1 AE2 2 R2 R2 Isl 1s2 R2 Isl R2 AE1 if 11 12 which is forced by the current mirror consisting of M1 and M2 V V IR V amp1 VV KV REF BEl 1 1 BEl R2 AEI t BEl t While an op amp could be used to make 11 12 it suffers from offset and noise and leads to deterioration of the bandgap temperature performance VREF is with respect to VDD and therefore is susceptible to changes on VDD Kl5 E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r Femp Indep Biasing 71400 A Fig 466 K156E 4430 Analog Integrated Circuits and Systems CMOS Band 3 Reference usin Substrate PNP BJTs Page 11 Operation The cascode mirror MSM8 keeps the currents in Q1 Q2 and Q3 identical Thus VBEi 12R VBE2 Of 12 E 1nn Therefore VREF VBE3 12kR VBE3 kVt 1nn Use k and n to design the desired value of K n is an integer greater than 1 PE Allen 2009 r Femp Indep Biasing 71400 Weak Inversion Band 3 Volta e Reference Circuit Fig 468 VBG2 IDi 1D2 1D0W2L2 6XP th Note that VBG2 VBG4 and V1334 VR1 Therefore 111 W2L2 Vin ID3 W4L4 exp Vt where W1W4L2L3 KE E 4430 Analog Integrated Circuits and Systems J and ID3 ID4 1D0W4L46Xpn Vt Page 12 Analysis For the p channel transistors VBG VBS 39VBD ID IDOWL exp th Iexp Vt exp Vt where Vt kT q BG VBs 1 1Vt Vt 39 V 1f VBD gtgt Vt then ID ID0WL 6XP The various transistor currents can be expressed as VBG4 VBs4 Vt V Vl d l m R1 tnL1L4W2W3 an RlR1 PE Allen 2009 r Femp Indep Biasing 71400 Page 13 Weak Inversion Band 3 Volta e Reference Continued The reference voltage can be expressed as VREF R216 VBES However I W6L3 W6L3 E W1W4L2L3 6 L6W3 R1 L6W3 R1 n L1L4W2W3 Substituting 16 and the previously derived expression for VBET in VREF gives W6L3 R2 W1W4L2L3 T T TO VREF L6W3 R1 Vt lnL1L4W2W3 Vgol TOJ VBEO T0 3Vt lr1T J To achieve BVREFBT 0 at T To we get VREF E amp W6L3 1n W1W4LzL3 VGO VBE0 3 T q R1 L6W3 L1L4W2W3 T0 T0 q Therefore R2W6L3 W1W4L2L3 i i R1L6W3 L1L4W2W3 kTo VGO VBEO 3 Under the above constraint VREF has an approximate zero value of temperature coefficient at T To and has a value of 3kT To 3kT VREFVGO q 11n T VG0 q Practical values of BVREFBT for the weak inversion bandgap are less than 100 ppm C KE E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r Femp Indep Biasing 71400 Fuse 14 IMPROVEMENT OF THE BANDGAP REFERENCE CIRCUIT Curvature Correction Techni ues Squared PTAT Correction 1311 VPTAT I x r z x 4 O zquot on If I m I z 4 a gt 3 a x gt r 2 VPTAT x a Temperature Fig 469 Temperature coefficient 2 l2O ppm C VBE loop M Gunaway et al A CurvatureCorrected LowVoltage Bandgap Reference IEEE Journal of Solid State Circuits V01 28 no 6 pp 667670 June 1993 compensation 1 Lee et al Exponential CurvatureCompensated BiCMOS Bandgap References IEEE Journal of SolidState Circuits V01 29 no 11 pp 13961403 NOV 1994 Nonlinear cancellation GM Meijer et al A New CurvatureCorrected Bandgap Reference IEEE Journal of SolidState Circuits V01 17 no 6 pp 11391143 December 1982 PE Allen 2009 K156E 4430 Analog Integrated Circuits and Systems r Femp Indep Biasing 71400 ZBE Loo Curvature Correction Techni ue Circuit VDD l 3Output Current Mirror IVBEINL VDD VBEHNLL VDD VDD PTAT 1 f lt PTAT V gt BE R3 gtlINL VREF IPTAT 4 I C onstant 2 gt R lt 7 gt R2 X2 lt 1 J Fig 4610 where VI kTq Rx a resistor used to define I PTAT VBE Vt 2IPTAT VREF Z R R 1 I 2 3 NL constant IPTAT R1 Page 15 Operation INL VBE VBE2 g 3 3 ZIPTAT R3 nINLI Constant where I constant 2 INL IPTAT IVBE I E VBE NL Rx R2 In c1142 A1102 a quasitemperature independent current subject to the temperature coefficient of the resistors I cl and 162 are the collector currents of in and an respectively Temperature coefficient a 3 ppm C with a total quiescent current of 95 uA PE Allen 2009 K156E 4430 Analog Integrated Circuits and Systems r Femp Indep Biasing 71400 Fuse 16 2 Compensation Curvature Correction Technigue Circuit Operation VREF VBE ATR A VBE ATTR where BT A and B are constant T temperature VREF The temperature dependence of 3 is M cc rm 2 MT CelT Fig 4611 BTe lT 39 VREF AT C Not good for small values of Vm 14V Vin 2 VREF Vsat VGO Vsat K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r Femp Indep Biasing 71400 Nonlinear Cancellation Curvature Correction Techni ue Objective Eliminate nonlinear term from the baseemitter Result 05 ppm C from 25 C to 85 C Operation From above VREF VPTAT 4VBEUPTAT 39 3 VBEU Constant Note that IPTAT gt 16 cc T1 05 1 and I 0 constant 2 c x T Z 05 0 Previously we found T T V AV V V T aVln BIB T GO TO GO BElt 0 Y I To so that l l VBEUPTAT VGO T0 VGO 39VBET0 1Vt 1 T0 and l l VBKIConstant VGO 39 T0 VGO quotVBET0 quotWt In To Combining the above relationships gives T T VREFT VPTAT VGO FOWGO 39 VBET0l Y 4 Vt lnT0 lfyz 4 then T T VREFltD 4 VPTAT VGO1 39 F0 VBET0T0 Kl5 E 4430 Analog Integrated Circuits and Systems Page 17 Constant IPTAT V REF o 1 T2 IPTAT VBE VREF R12 VPTAT l Jquot Conventional Curvature Corrected Bandgap Reference Bandgap Reference Flg 4 6 l 2 PE Allen 2009 r Femp Indep Biasing 71400 Fuse 18 Other Characteristics of Band a Volta e References N0ise Voltage references for highresolution AD converters are particularly sensitive to noise Noise sources Op amp resistors switches etc Maximize the PSRR of the op amp t VCC Offset Voltages 1 Becomes a problem when op amps are used Q2 Q1 VBE2 VBE1 VR1 Vos VREF R1ltVR1V AV V V V V V l ICZAEI lt OS BE BE2 BEl R1 OS t 101 AEZ lczl ml iczR3 iC1R2 Vos ltgt gt or R3 gt R2jgt iC2 amp VOS amp VOS BGROl i V 101 R3 iC1R3 R3 iC1R2 EE Therefore R2AE1 V03 2 l VR1 V03 Vt luR3 5 E2 1 ICIRZJ VR1 R2 VREF VBE2 Vos 101R2 VBE2 VOS R1 12 V3132 Vos RT VRI R2 R2 RzAE1 VOS V V V 1 V1 1 REF BE2 OS R1 R1 t n R3AE2 ICIRZ Kl5 E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r Femp Indep Biasing 71400 Fuse 19 How do 0u et 3 Stable Reference Current from the Band 3 Assume that a temperature stable reference voltage is available ie bandgap reference and use the zero TC NMOS current sink The problem is that VREF may not be equal to the value of VGS that gives zero TC VDD 11 Current Mirror lt IRll Rl lIREF VREF l11 Current Mirrorl VGS T T T Fig 4614 VREF R2 VGS IR2R2 R2 R1 R1 VREF dT 2 R1 dT RldT39R12 dT 2R1 dT dT39 dT de dRz If the temperature coefficients of R1 and R2 are equal W W then dVGS R2 dVREF and VGS is proportional to the temperature dependence of VREF dT R1 dT If the MOSFET is biased at the zero TC point then the current should have the same dependence on temperature as VRE F PE Allen 2009 Kl5 E 4430 Analog Integrated Circuits and Systems r Femp Indep Biasing 71400 Fuse 20 Practical As ects 0fTem eratureInde endent and Su 1 Inde endent Biasin A temperatureindependent and supplyindependent current source and its distribution V DD M7 M8 M9 M5 M6 I I M10 quotnm L yoltage R4ltgt VBG 3 h I I I I I l quotquot T M11 M13 M15 M3 M4 h l l M1 l l M2 M12 M14 M16 lt PTATl 1 R2 REFl ltgt Q1 Q2 Q3 Rexl X71 1 Fig 4615 Constant current REF Rext Where VBG VBE3 IPTATR2 VBE3 R1 lnn R2 K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r Femp Indep Biasing 71400 Slave bias circuit From Master Bias 5 1 j K156E 4430 Analog Integrated Circuits and Systems Practical As ects of Bias Distribution Circuits Continued Distribution of the current avoids change in bias voltage due to IR drop in bias lines VDD gtVPBz39as1 gtVPBz39as2 T NBiasZ 7 NBiasl j L Fig 4616 Page 21 PE Allen 2009 r Femp Indep Biasing 71400 Page 22 SUMMARY OF BANDGAP REFERENCES Summa Bandgap voltage references can achieve temperature dependence less than 50 ppm C Bandgap voltage references are also independent of power supply Correction of secondorder effects in the bandgap voltage reference can achieve very stable 1 ppm C voltage references Watch out for secondorder effects such as noise when using the bandgap voltage reference in sensitive applications K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 IC Passive Components ll300 Page 1 l INTEGRATED CIRCUIT PASSIVE COMPONENTS INTRODUCTION Objective The objective of this presentation is 1 Show the passive components that are compatible with BJT and CMOS technologies 2 Modifications to the standard BJ T and CMOS processes 3 Physical in uence on passive components Outline Capacitors Resistors Inductors Modifications to the standard BJT and CMOS processes Diodes Summary k ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components 11300 Page 1 2 INTEGRATED CIRCUIT CAPACITORS PN Junction Concept Metallurgical Junction ptype semiconductor I Xp 6 n V X Doped atoms near the metallurgical junction lose their free carriers by diffusion As these fixed atoms lose their free carriers they build up an electric field which opposes the diffusion Jp A mechanism Equilibrium conditions are reached when Current due to difusion Current due to electric eld U PE Allen and JA Connelly 2000 k ECE 6421 Analog IC Design IC Passive Components 11300 PN Junction Characterization Cross section of an ideal pn junction Page 1 3 Impurity concentration cm393 k ECE 6421 Analog IC Design ND 0 x NA Depletion charge concentration cm393 9ND xp 0 xn x qNA Electric Field Vcri x E0 Potential V Po VD x Fig 232A 479 4b PE Allen and JA Connelly 2000 IC Passive Components 11300 Page 1 4 Summar of PN Junction Anal sis Barrier potential kT AND AN Depletion region widths 28sil039VDNA n qNDNAND X F X 28si oVDND N 1 qNDNAND Depletion capacitance lasinAND 1 CjO 5 C39 A J 12ltNANDgt OVD VD CJo 1 ltlgto 39 V Breakdown voltage Flg392393 3B 0 0 D 8siNAND 2 2qNAND max C ZIH x ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 Summary of PN Junction Analysis Continued Graded junction Impurity Concentration cm3 A ND t x 0 NA PCOO Above expressions become Depletion region widths 2 si oVDNA 3 n qNDNAND 1 25 X 2 si oVDND X N P qNDNAND 2 Depletion capacitance 1 5 1390 C asinAND 1 CjO 1 J 2NA ND 0VDm 1 V2 10 05 where 033 Sm S 05 Note that m MJ 0 IC Passive Components 11300 Page 1 5 ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components 11300 Page 1 6 S ummar of PN Junction Anal sis Continued CurrentVoltage Relationship 2 V D D n 39 V 1 Isexpvli l where Is qA Lug z KT3eXp 20 20 iD 15 Is 10 5 0 5 k ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components 11300 Page 1 7 CrossSection of an NPN BJT All passive components must be compatible with this structure substrate Collector Base Emitter O nepitaXial layer nJr buried la er p substrate Heavily Lightly Intrinsic Lightly Heavily Metal Doped p Doped p Doping Doped n Doped n BJTNPN L ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components 11300 Page 1 8 Collecto rBase Capacitance Cl Illustration Substrate Collector Base p substrate Model Sidewall contribution C CCB C B o n I Asidewall Pd 3 C 1 CS where T SUbStrate PCOZ P perimeter of the capacitor d depth of the diffusion Values Includes the bottom plus sidewall capacitance C I z ltFum2 dependent on the reverse bias voltage Can also have baseemitter capacitance and collectorsubstrate capacitance L ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components 11300 MOS Capacitors Polysilicon OXideChannel for Enhancement MOSFETs Bulk connected to VSS Page 1 9 VV DG GS gtV T Gate Substrate Bulk Comments Capacitance CGS z COXWL Channel must be formed therefore VGS gt VT With VGS gt VT and VDS 0 the transistor is in the active region k ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components 11300 Page 1 10 MOS Ca acitors Continued Bulk tuning of the polysilicon oxidechannel capacitor 035 pun CMOS CG 065V 06 Volts or pF CG ll 0 N I I I I I I I I I I Fig253 l5 l4 13 l2 ll l0 09 08 07 06 05 VB Volts CmaX Cmin z 4 PE Allen and JA Connelly 2000 x ECE 6421 Analog IC Design IC Passive Components 11300 Page 1 ll MOS Ca acitors Continued Bulk connected to SourceDrain 39 V V gtV T S l D s DG GS Gate Drain Bulkl Source 35 I I I t E 23 1 Substrate Bulk CGDS CGDs CGsOxide CGBdepletion Comments l V VGDs Capacitance 1s more constant as a functlon of VGD S T Still not a good capacitor for large voltage swings k ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 1C Passive Components ll300 Page 1 12 MOS Capacitors Continued AccumulationMode Capacitor I k 0 Source Substrate Fig 25 4 Comments i30 tuning range Tuned by the voltage across the capacitor terminals Q z 25 for 31pF at 18 GHZ optimization leads to Qs of 200 or greater 1 T Soorapanth et a1 Analysis and Optimization of AccumulationMode Varactor for RF 1Cs Proc 1998 Symposium on VLSI Circuits Digest of Papers pp 3233 1998 Z R Castello et a1 A i30 Tuning Range Varactor Compatible with future Scaled Technologies Proc 1998 Symposium on VLSI Circuits Digest afPapers pp 3435 1998 PE Allen and JA Connelly 2000 k ECE 6421 Analog IC Design IC Passive Components 11300 Page 1 l3 MOS Ca acitors Continued Pol siliconOxide DiffusionActive for Enhanced MOSFETs psubstrate Unit capacitance z 12 fFinn2 Voltage dependence CV z CO alV aZVZ where a1 z 0 and a2 z 210 ppmV2 Not as good linearity as polypoly capacitors k ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components 11300 Page 1 l4 MOS Ca acitors Continued PolVsiliconOXidePolVsilicon PolvPolv substrate Best possible capacitor for analog circuits Less parasitics Voltage independent Approach for increasing the voltage linearity Top Plate Top Plate Bottom Plate Bottom Plate k ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components 11300 Page 1 15 Im lementation of Ca acitors usin Available Metal and P01 Interconnect La ers M3 M2 Pol M1 D Z 1 G M2 M1 M2 I P01 m Mz M1 Fig 258 x ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components 11300 Page 1 16 Fractal Capacitors Capacitance between conductors on the same level and use lateral uX Fringing Capacitance 4 A j Top View of a Lateral Flux Capacitor PC10 These capacitors are called fractal capacitors because the fractal patterns are structures that enclose a finite area with an infinite perimeter In certain cases the capacitorarea can be increased by a factor of 10 over vertical flux capacitors k ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components ll300 Page 1 l7 Capacitor Errors 1 Oxide gradients 2 Edge effects 3 Parasitics 4 Voltage dependence 5 Temperature dependence PE Allen and JA Connelly 2000 x ECE 6421 Analog IC Design Page 1 18 IC Passive Components 11300 Ca acitor Errors Oxide Gradients Error due to a variation in oxide thickness across the wafer l l l A A No common centroid 1 2 layout 1 l 1 Common centroid A1 A2 layout Only good for onedimensional errors An alternate approach is to layout numerous repetitions and connect them randomly to achieve a statistical error balanced over the entire area of interest 02 matching of poly resistors was achieved using an array of 50 unit resistors PE Allen and JA Connelly 2000 k ECE 6421 Analog IC Design IC Passive Components 11300 Capacitor Errors Edge Effects For example A B k ECE 6421 Analog IC Design lll A B III There will always be a randomness on the definition of the edge However etching can be in uenced by the presence of adjacent structures Matching of A and B are disturbed by the presence of C Improved matching achieve by matching the surroundings of A and B PE Allen and JA Connelly 2000 Page 1 l9 IC Passive Components 11300 Page 1 20 Capacitor Errors AreaPeriphery Ratio The best match between two structures occurs when their areatoperiphery ratios are identical Let C 1 Cli AC1 and C 2 Czi AC2 where C the actual capacitance C the desired capacitance which is proportional to area AC edge uncertainty which is proportional to the periphery Solve for the ratio of C ZC 1 AC2 C 2C2iAC2C2 1 C 2 C 1C1iAC1C1 AC1 1i Cl C AC AC C AC AC 1 2 l l 2 l AC2AC1 C2 C2 fez Wen c fc l Therefore the best matching results are obtained when the areaperiphery ratio of C 2 is equal to the areaperiphery ratio of C1 k ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components 11300 Page 1 21 Ca acitor Errors Relative Accurac Capacitor relative accuracy is proportional to the area of the capacitors and inversely proportional to the difference in values between the two capacitors For example 004 Unit Capacitance 05pF 0 O U I Unit Capacitance lpF Relative Accuracy 0 O M Q C i Unit Capacitance 4pF 03900 2 4 8 16 32 64 Ratio of Capacitors k ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components 11300 Page 1 22 Capacitor Errors Parasitics Parasitics are normally from the top and bottom plate to ac ground which is typically the substrate Top Plate J TOP iDesired 391 Plate Capacitor J39 parasitic I 1 3939 5 Bottom Bottom Plate T plat para51t1c L Top plate parasitic is 001 to 0001 of Cdesired Bottom plate parasitic is 005 to 02 Cdesired x ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components 11300 Page 1 23 Other Considerations on Ca acitor Accurac Decreasing Sensitivity to Edge Variation A A A A B B39 B 1339 Sensitive to edge variation in Sensitive to edge varation in both upper andlower plates upper plate only Fig 2613 A structure that minimizes the ratio of perimeter to area circle is best Top Plate of Capacitor Bottom plate of capacitor Fig 2614 L ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components 11300 Page 1 24 Capacitor Errors Temperature and Voltage Dependence Polysilicon OxideSemiconductor Capacitors Absolute accuracy z i10 Relative accuracy z i02 Temperature coefficient z 25 ppmCo Voltage coefficient z 50ppmV PolysiliconOXidePolysilicon Capacitors Absolute accuracy z i10 Relative accuracy z i02 Temperature coefficient z 25 ppmCo Voltage coefficient z 20ppmV Accuracies depend upon the size of the capacitors x ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components 11300 Capacitor Layout Doublepolysilicon capacitor Met 1 Polysilicon 2 f Polysilicon gate Po Page 1 25 Triplelevel metal capacitor Metal 3 Metal 2 Metall 1 FOX l Substrate l Metal 3 Metal 2 Metal 1 Metal 3 lysilicon gate Fig 2617 x ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components 11300 Page 1 26 INTEGRATED CIRCUIT RESISTORS Resistor Layout Direction of current ow w i T Area A h L 4 Fig 2615 Resistance of a conductive sheet is expressed in terms of L L R p Q A where p resistivity in Qm Ohmssquare L L R W PSW Q where pS is a sheet resistivity and has the units of ohmssquare x ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components 11300 Page 1 27 Base and Emitter Diffused Resistors Crosssection of a Base Resistor Substrate Collector C I g I 3 Collector p substrate PC03 Comments Sheet resistance z 100 QD to 200 QD TCR 1500ppm C Note 1 Z 104 C C Emitter Resistor Sheet resistance z 52 QD to 10 QD Generally too small to make sufficient resistance in reasonable area TCR 600ppm C L ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components 11300 Page 1 28 Base Pinched Resistor Good for large value of sheet resistance Crosssection Substrate O IV Curves and Model Pinched o eration R P A AB B 0 JL VAB Collector PCOS Comments Sheet resistance is 5 to lSkQD Voltage across the resistor is limited to 6V or less because of breakdown TCR z 2500ppm C L ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components 11300 Epitaxial Pinched Resistors Cross section Substrate O p substrate Sheet resistance z 1 l OkQ D Top View Page 1 29 L ECE 6421 Analog IC Design PE Allen and 1A Connelly 2000 IC Passive Components 11300 Page 1 30 MOS Resistors SourceDrain Resistor Metal p substrate Fig 2516 Diffusion Ion Implanted 10100 ohmssquare 5002000 ohmssquare Absolute accuracy i3 5 Absolute accuracy 2 i15 Relatch accuracy 2 2 5 H111 02 50 H111 Relative accuracy 2 5 um 015 50 um Temperature eeef eiem 1500 PPmOC Temperature coefficient 400 ppm C Veltage eeef eiem z 39200 PPmV Voltage coefficient z 800 ppmV Comments Parasitic capacitance to well is voltage dependent Piezoresistance effects occur due to chip strain from mounting x ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components 11300 Page 1 3l Polysilicon Resistor Metal Polysilicon resistor p substrate Fig 25 17 30100 ohmssquare unshielded 100500 ohmssquare shielded Absolute accuracy i30 Relative accuracy 2 5 um Temperature coefficient 5001000 ppm C Voltage coefficient z 100 ppmV Comments Used for fuzes and laser trimming Good general resistor with low parasitics x ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components 11300 Page 1 32 NWell Resistor p substrate Fig 2518 10005000 ohmssquare Absolute accuracy i40 Relative accuracy z 5 Temperature coefficient 4000 ppm C Voltage coefficient is large z 8000 ppmV Comments Good when large values of resistance are needed Parasitics are large and resistance is voltage dependent x ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components 11300 Page 1 33 Example of Resistor Layouts Metal Substrate Substrate Active area diffusion Active area diffusion Well diffusion A t C t t W we area Well diffusion W 011 30 Active area or PolySlllcon Contact i f L i Metal 1 L T Metal 1 Diffusion or polysilicon resistor Well resistor Fig 2616 Corner COIICCthl lSI Fig 2616B k ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components 11300 Page 1 34 Example 261 Resistance Calculation Given a polysilicon resistor like that drawn above with W208ch and L20le calculate pS in QCI the number of squares of resistance and the resistance value Assume that p for polysilicon is 9 X 10394 2 cm and polysilicon is 3000 A thick Ignore any contact resistance Solution First calculate ps B 9 gtlt104 Qcm p5 T 3000x108 cm The number of squares of resistance N is l N W 08pm 25 giving the total resistance as RpsgtltN 30X25750 2 30 QCI x ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components ll300 Inte rated Circuit Passive Com 011th Performance Summar Page 1 35 Component Type Range of Values Absolute Relative Temperature Voltage Accuracy Accuracy Coefficient Coefficient Polyoxidesemicond 0 3 51 0 fF 1112 10 0 1 20ppm C i20ppm V uctor Capacitor PolyPoly Capacitor 0310 fFum2 20 01 25ppm C i50ppmV Base Diffused 1002002sq i20 02 1750ppm C Emitter Diffused 2 1 09 sq i20 i2 600ppm C Base Pinched 2k10kQsq i50 i10 2500ppm C Poor Epitaxial Pinched 2k5kQ sq in 50 i7 3000ppm C Poor SourceDrain Diffused 10100 Qs q 3 5 2 1500ppm C 200ppm V Ion Implanted Resistor 052 kQ sq 15 2 400ppm C 800ppmV P 01y Resistor 30200 Qsq 30 2 1500ppm C 100ppmV nwell Resistor 1 10 k9 sq 40 5 8000ppm C 1 Okppm V Thin Film 01k2kQsq i5i20 i02i2 i10 to i200ppm C k ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components 11300 Page 1 36 INDUCTORS Inductors What is the range of values for on chip inductors 12 Inductor area is too large 10 xxxxxxxxxxxxxxxxxxxxk E 8 8 g 6 0L 509 H O b 4 E Interconnect parasmcs 2 are too lar e 7 g A 0 10 20 30 40 5 Frequency GHz Fig 65 Consider an inductor used to resonate with SpF at lOOOMHz L 5nH 41c2f02C 2n10925X103912 Note Offchip connections will result in inductance as well x ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components 11300 Page 1 37 Candidates for inductors in CMOS technology are 1 Bond wires 2 Spiral inductors 3 Multilevel spiral 4 Solenoid Bond wire Inductors 1 d Fig66 Function of the pad distance d and the bond angle 3 Typical value is lnHmm which gives 2nH to SnH in typical packages Series loss is 02 mm for 1 mil diameter aluminum Wire Q 60 at 2 GHZ x ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components 11300 Page 1 38 Planar Spiral Inductors Spiral Inductors on a Lossy Substrate L R C1 C2 R1 R2 Fig 167 Design Parameters Inductance L 2Lself Lmutual Quality factor Q L 1 Selfresonant frequency fself f LC Tradeoff exists between the Q and selfresonant frequency Typical values are L l 8nH and Q 36 at 2GHZ L ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components 11300 Page 1 39 Planar Spiral Inductors Continued Inductor Design Silicon gt I Fig 6 9 Ntums 25 Typically 3ltNturns lt5 and S Smin for the given current Select the OD Nmms and W so that ID allows sufficient magnetic flux to ow through the center Loss Mechanisms Skin effect Capacitive substrate losses Eddy currents in the silicon L ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components 11300 Page 1 40 Planar Spiral Inductors Continued In uence of a Lossy Substrate L R TAM WT C1 C2 CLaad R1 R2 1 Fig 122 13 Where L is the desired inductance R is the series resistance C 1 and C 2 are the capacitance from the inductor to the ground plane R1 and R2 are the eddy current losses in the silicon Guidelines for using spiral inductors on chip Lossy substrate degrades Q at frequencies close to fself To achieve an inductor one must select frequencies less than fself The Q of the capacitors associated with the inductor should be very high x ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components 11300 Page 1 41 Planar Spiral Inductors Continued Comments concerning implementation 1 Put a metal ground shield between the inductor and the silicon to reduce the capacitance Should be patterned so ux goes through but electric field is grounded Metal strips should be orthogonal to the spiral to avoid induced loop current The resistance of the shield should be low to terminate the electric field 2 Avoid contact resistance wherever possible to keep the series resistance low 3 Use the metal with the lowest resistance and furtherest away from the substrate 4 Parallel metal strips if other metal levels are available to reduce the resistance Example Fig 610 PE Allen and JA Connelly 2000 L ECE 6421 Analog IC Design IC Passive Components 11300 Page 1 42 MultiLevel Spiral Inductors Use of more than one level of metal to make the inductor Can get more inductance per area Can increase the interwire capacitance so the different levels are often offset to get minimum overlap Multilevel spiral inductors suffer from contact resistance must have many parallel contacts to reduce the contact resistance x ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components 11300 Page 1 43 Solenoid Inductors Example Silicon Comments Magnetic ux is small due to planar structure Capacitive coupling to substrate is still present Potentially best with a ferromagnetic core ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components 11300 Page 1 44 OTHER CONSIDERATIONS OF CMOS TECHNOLOGY Lateral Bi olar Junction Transistor PWell Process NPN Lateral VDD Base Emitter Collector p well nsubstrate x ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components 11300 Page 1 45 Lateral Bi olar Junction Transistor Continued Fieldaided Lateral BF z 50 to 100 depending on the process Keep channel from forming VDD Base Emitter VGate Collector nsubstrate Good geometry matching Low lf noise if channel doesn t form Acts like a phototransistor with good responsitiVity k ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components 11300 Geometrv 0f the Lateral PNP BJT Minimum Size layout of a single emitter dot lateral PNP BJT p substrate diffusion p diffusion nwe11 contact nwell contact Base Lateral Collector Gate Emitter P0137 330pm gt k ECE 6421 Analog IC Design Page 1 46 40 emitter dot LPNP transistor total device area is 0006mm2 in a 12um CMOS process Lateral Collector 7 I I y 39 T Y i Bums a N Emitter N 39 t V ss 1 PE Allen and IA Connelly 2000 IC Passive Components 11300 Performance of the Lateral PNP BJT Schematic Emitter Gate Base Vertical L t 1 Collector a era Collector V SS BL vs ICL for the 40 emitter dot LPNP BJT 150 130 110 Lateral B 90 70 50 lnA lOnA lOOnA luA 10uA 100uA lmA Lateral Collector Current Lateral Efficiency Lateral efficiency versus IE for the 40 emitter dot LPNP BJ T 0 oo 0 ox 0 4 02 0 lnA 10 nA L ECE 6421 Analog IC Design Page 1 47 100nA luA IOuA IOOuA lmA Emitter Current PE Allen and IA Connelly 2000 IC Passive Components 11300 Performance of the Lateral PNP BJT Continued Typical Performance for the 40 emitter dot LPNP BJT Page 1 48 Transistor area 0006 mmZ Lateral B 90 Lateral efficiency 070 Base resistance 150 En5HZ 246nVx1Tz En midband 192 nV IH z fc En 32 Hz 1n5HZ 353pAJrTz In midband 061 pA VH Z fc In 162 Hz fT 85 MHz Early voltage 16 V k ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components 11300 Page 1 49 High Voltage MOS Transistor The well can be substituted for the drain giving a lower conductivity drain and therefore higher breakdown voltage NMOS in nwell example Source Gate Drain SUb Straw psubstrate Fig 267A Drainsubstratechannel can be as large as 20V or more x ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components 11300 Page 1 50 Latchup in CMOS Technology Latchup Mechanisms 1 SCR regenerative switching action 2 Secondary breakdown 3 Sustaining voltage breakdown Parasitic lateral PNP and vertical NPN BJTs in a pwell CMOS technology 3T1 ST ST n substrate Fig 268 Equivalent circuit of the SCR formed from the parasitic BJTs VDD A Vin mVss B Vout Vss Fig 269 L ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 j IC Passive Components 11300 Preventin LatchU in a PWell Technolo will lower the value of the BJT betas 2 Reduce the values of RN and RP This requires more current before latchup can occur 3 Make a p39 diffusion around the pwell This shorts the collector of Q1 to ground pchannel transistor nchannel transistor uard bars p guard bars 7 quot 7 Figure 2610 11 For more information see R Troutman CMOS Latchup Kluwer Academic Publishers 1 Keep the sourcedrain of the MOS device not in the well as far away from the well as possible This k ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components 11300 Electrostatic Discharge Protection QESDt Page 1 52 Objective To prevent large external voltages from destroying the gate oxide Electrical equivalent circuit VDD p to nwell diode To internal gates A A A vvv t n to psubstrate p mm or diode L VI VSS Implementation in CMOS technology Metal Bonding Pad psub strate x ECE 6421 Analog IC Design Fig 2611 PE Allen and JA Connelly 2000 IC Passive Components 11300 Tem erature Characteristics of Transistors Fractional Temperature Coefficient 1 8X TCF g Typically in ppm C MOS Transistor VT VT0 MTTO where 0c z 23mV C 200 K to 400 K H KHTlj BJT Transistor Reverse Current IS LBLS 1 L We IS 8T T T kTq Empirically IS doubles approximately every 5 C increase Forward Voltage vD aVD VGo 39 VD 3kT W T Tqz 2mV C at VD 06V x ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 Page 1 53 IC Passive Components 11300 Page 1 54 Noise in Transistors Shot Noise i2 2qIDAf amperesz where q charge of an electron ID dc value of iD Af bandwidth in Hz 12 Noise current spectral density Af amperesZHz Thermal Noise Resistor v2 4kTMf voltsz MOSFET SkTgmAf iD2 T ignoring bottom gate where k Boltzmann s constant R resistor or equivalent resistor in which the thermal noise is occurring gIn transconductance of the MOSFET x ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components 11300 Page 1 55 Noise in Transistors Continued Flicker 1 l Noise 17 KAf where Kf constant 103928 Faradamperes a constant 05 to 2 b constant zl Noise power spectral density lf 10gf Fig 2612 x ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components 11300 Page 1 56 Design Rules Design rules are geometrical constraints which guarantee the proper operation of a circuit implemented by a given CMOS process These rules are necessary to avoid problems such as device misalignment metal fracturing lack of continuity etc Design rules are expressed in terms of minimum dimensions such as minimum values of Widths Separations Extensions Overlaps Design rules typically use a minimum feature dimension called lambda Lambda is usually equal to the minimum channel length Minimum resolution of the design rules is typically half lambda In most processes lambda can be scaled or reduced as the process matures k ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components 11300 Page 1 57 D IODE S BJT Diode Different configurations Diode 5 f PCOSA PC0813 PCOSC PCOSD PCOSE PCOSF condition 0 IE 0 IE 0 0 VEB 0 0 no emitter Se s Vbb Vbb Froc Vbb Froc Vbb 713 Vbb 713 Vcc39 Vbb Re51stance VF IOmA 960mV 950mV 950mV 850mV 940mV 920mV Breakdown BVEBO BVCBO BVCBO BVEBO BVCBO BVEBO Voltage Storage Time z70ns zl 30ns zSOns z6ns z90ns z150ns PE Allen and JA Connelly 2000 k ECE 6421 Analog IC Design IC Passive Components 11300 Page 1 58 MOS Diode PC09 1D 3VD39VT2 L ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 IC Passive Components 11300 Page 1 59 Comparison of the BJT and MOS diodes Assume the IS lfA 30 99 and VD 065V for the BJT diodes and 3 300uAV2 and VT 05V for the MOS diode Find the dc current the static resistance and the dynamic resistance of the BJT diode in the first and fourth columns and the MOS diode IC0 diode I D 3 3 eXp0650026 19f 72x1010 0727 gA Rm c 893m 8139 I eXp0650026 I Lzaviz S 2 1 6 357142 rd D V430 Vt 357kQ VCB0 diode 133 m D IE ICIB a 30 ISeXp0650026 727 gA Rsmc 727M 893m Vt r 3579 d D MOS diode 65V 1 1 ID 300WV2065052 675uA Rsmc 60397W100k 2 111kQ rd z gm V2300675 k ECE 6421 Analog IC Design PE Allen and JA Connelly 2000 LargeSignal Behavior of BJTS 51200 Page 13l 13 LARGESIGNAL BEHAVIOR OF BJ TS INTRODUCTION Objective The objective of this presentation is 1 Understand how the bipolar junction transistor works 2 Develop large signal models for analysis and simulation Outline Largesignal models in the forwardactive region Effects of collector voltage on the largesignal model in the forwardactive region Saturation and inverse active regions Transistor breakdown voltages Dependence of transistor current gain on operation conditions k ECE 4430 Analog Integrated Circuits and Systems PE Allen LargeSignal Behavior of BJTs 51200 Page 132 Notational Difference from Gra and Me er These slides will use slightly different notation from the Gray and Meyer text The differences are 1 Total dc and ac variables Consider the collector current of a transistor iC E total collector current consisting of both the ac and dc C E dc collector current 139 c E ac collector current 2 The thermal voltage which is kTq and equal approximately to 26mV at room temperature will be given the symbol of Vt rather than VT which will be reserved for threshold of fieldeffect transistors x ECE 4430 Analog Integrated Circuits and Systems PE Allen LargeSignal Behavior of BJTS 51200 Page 133 LARGESIGNAL BEHAVIOR OF BJTS Bi olar Transistor S mbol and Si 11 Convention The bipolar junction transistor BJT is a threeterminal device whose symbol and sign convention according to Gray and Meyer is given below C C l l V36 1 VBC l 13 1393 B VBE 13 VBE VBE 39 VBE 39 1 1 E E npn Pnp Fig13l We will see that the names of the terminals of the transistor are descriptive of their function Emitter The emitter is the source of majority carriers that result in the gain mechanism of the BJT These carriers which are emitted into the base are electrons for the npn transistor and holes for the pnp transistor Base The base is a region which physically separates the emitter and collector and has an opposite doping holes for the npn and electrons for the pnp BJTS The word base comes from the way that the first transistors were constructed The base supported the whole structure Collector The collector serves to collect those carries injected from the emitter into the base and which reach the collector without recombination k ECE 4430 Analog Integrated Circuits and Systems PE Allen LargeSignal Behavior of BJTs 51200 Page 134 Ph sical As ects of an n n BJT A crosssection of an npn BJT is shown below E Depletion Depletion Region Region e u A l l F1gl3 2 Depletion Depletion Region Region Comments The emitterbase depeletion region is generally smaller in width because the doping level is higher and baseemitter junction is generally forwardbiased The next slide will examine the carrier concentrations see looking into the above AA crosssection k ECE 4430 Analog Integrated Circuits and Systems PE Allen LargeSignal Behavior of BJTs 51200 Carrier Concentrations of the n n BJT The carrier concentrations not to scale for the npn BJT are shown below Page 135 Comments collector junction is reverse biased Carrier Concentration Depletion Region quotquotE ppoc quotquotC A Depletion Region Ax np0 NA NA n x PnE0 gt p npWB v PnC x I V v A lt Emitter 74 4 Base gt 47 Collectorip A x 0 x WB Fig133 The above carrier concentrations assume that the baseemitter junction is forward biased and the base The above carrier concentration will be used to derive the large signal model on the next slide k ECE 4430 Analog Integrated Circuits and Systems PE Allen LargeSignal Behavior of BJTs 51200 Page 136 Derivation of the BJT Large Signal Model in the Foward Active Region 1 Carrier concentrations in the base on the emitter side The concentration of electrons in the base on the emitter side x 0 is VBE np0 npo eXpV t The concentration of electrons in the base on the collector side x W3 is W Vic 0 b 39 t39 d 1 np B npo exp Vt ecause VBC 1s nega 1ve an arge 2 If the recombination of electrons in the base is small then the minoritycarrier concentrations npx are straight lines and shown on the previous page From chargeneutrality requirements for the base NA npx ppx gt npx 39ppx NA 3 The collector current is produced by minoritycarrier electrons in the base diffusing in the direction of the concentration gradient and being swept across the collectorbase depletion region by the field existing there Therefore the diffusion current density due to electrons in the base is dn 2x x where Dquot is the diffusion constant for electrons From the previous page the derivative is the slope of the concentration profile in the base which gives 0 k ECE 4430 Analog Integrated Circuits and Systems PE Allen LargeSignal Behavior of BJTs 51200 Page 137 Derivation of the BJT Large Signal Model in the Foward Active Region Continued 3 Continued If the collector current is defined as positive owing into the collector terminal then n 0 qAD n VBE p 71 p0 Vt where A is the crosssectional area of the emitter The desired result is 39 I eXp VBE z C S Vt where the saturation current I S is I 2 S WB Since n2 npoNA we can rewrite IS as qADnrzl2 qADnrzl2 1 S WBNA QB where Q B is the number of doping atoms in the base per unit area of the emitter k ECE 4430 Analog Integrated Circuits and Systems PE Allen LargeSignal Behavior of BJTs 51200 Page 138 Derivation of the Forward Current Gain of the BJT 3E l The base current 139 3 consists of two major components These components are due to the recombination of holes and electrons in the base 13931 and the injection of holes from the base into the emitter 13932 It can be shown that ZlnpoWBquX E and I quDp ex VLE Bl 2 Tb p Vt 32 LP ND p Vt 2 Therefore the total base current is l quotpoWBqA qADp quot12 VIBE exp 13 2131 132 5 1b LP ND 7 3 Define the forward active current gain F as qADnnpo jg WB 1 F iB anoWBqA qADp W32 DpWBNA 2 1 LP ND 21b0 1 LP D Note that 3F is increased by decreasing WB and increasing N DN A k ECE 4430 Analog Integrated Circuits and Systems PE Allen LargeSignal Behavior of BJTs 51200 Page 139 Derivation of the Current Gain from Emitter to Collector in the Forward Active Re ion 1C l Emitter to collector current gain is designated as 06F E 2 Since sum of all currents owing into the transistor must be zero we can write that l39C 1 1C zE 1CzB 1C 5 1C 1E a F IF 1 BF 1 L W32 DP WB NA 05Ty 1 BF 2TbDn Dn p D where XT EBase Transport factor z W32 gt 1 1 zrbDn and 1 yEmztter Injectzon ef czency DP WB NA gt 1 n p D k ECE 4430 Analog Integrated Circuits and Systems PE Allen LargeSignal Behavior of BJTs 51200 Page 1310 Lar e Si nal Model for the BJT in the Foward Active Re ion Largesignal model for a npn transistor 13913 B C VBE BFI39 E E Assumes VBE is a I BE constant and 13 is 39 7 S B 7 I exp 1 determined externally F1gl34 Largesignal model for a pnp transistor 13913 B C VBE BFI39B E E Assumes VBE 1s a I VBE constant and 13 is 13 S eX BF Plt VI gt determined externally F1gl3 5 k ECE 4430 Analog Integrated Circuits and Systems PE Allen LargeSignal Behavior of BJTs 51200 Page l3ll COLLECTOR VOLTAGE INFLUENCE ON THE LARGE SIGNAL MODEL Base Width De endence 0n the CollectorEmitter Volta e The large signal model so far has the collector current as a function of only the baseemitter voltage However there is a weak dependence of the collector current on the collectoremitter voltage that is developed here In uence of the basecollector depletion region width Carrier Collector depletion Concentration region widens due to a h change in VCE AVCE 4 Initial Depletion 0 VBE Region np npa exp lt7 V I I 5 i i 39 x I I Emitter I 4 W3 Collector Base 396 39 F39 1 3 6 AWE 1g Note that the change of the collectoremitter voltage causes the amount of charge in the base to change slightly in uencing the collector current k ECE 4430 Analog Integrated Circuits and Systems PE Allen LargeSignal Behavior of BJTs 51200 Page 1312 The Early Voltage of BJTs Previously we saw that qADnniZ VBE i eX C QB p Vt Differentiation of iC with respect to vCE gives aiC qADnni2 VBE 3Q 1C aQB eXp aVCE Q32 Vt aVCE QB aVCE For a uniformbase transistor Q B WBNA so that the derivative becomes Bic 1C 8W3 1C aVCE a gt VA WB 8W3 aVCE WB aVCE where VA is called the Early voltage x ECE 4430 Analog Integrated Circuits and Systems PE Allen LargeSignal Behavior of BJTs 51200 I Volta e The output characteristics of an npn BJT lustration 0f the Earl Page 1313 Modified large signal model becomes 1352 E VA exp Vt K iC IS VCE Fig13 7 x ECE 4430 Analog Integrated Circuits and Systems PE Allen LargeSignal Behavior of BJTs 51200 Page l3l4 SATURATION AND INVERSE ACTIVE REGIONS Regions of Operation of the BJT If we consider the transistor as backtoback diodes we can clearly see the four regions of operation VBE Forward Active Region Saturation Region C C BE forward biased BE forward biased BC reverse biased BC forward biased VBC B z B Cutoff Region Inverse Active Region BE reverse biased BE reverse biased BC reverse biased BC forward biased E E Fig138 Note While the backtoback diode model is appropriate here it is not a suitable model for the BJT in general because it does not model the current gain mechanism of the BJ T Essentially the backtoback diode model has a very wide base region and all the injected carriers from the emitter recombine in the base F 0 k ECE 4430 Analog Integrated Circuits and Systems PE Allen LargeSignal Behavior of BJTs 51200 Page 1315 Saturation Region In the saturation region both the baseemitter and basecollector pn junctions are forward biased Consequently there is injection of electrons into the base from both the emitter and collector The carrier concentrations in saturation are Carrier Concentration AK Ppx I W nnC Electr g gtnpxi npWB M npmx x p C N PnE0 igt npz PnE 3 L Emitter Base Collector F 1g 1 39 A 7 k ECE 4430 Analog Integrated Circuits and Systems PE Allen LargeSignal Behavior of BJTs 51200 Page 1316 T ical Out ut Characteristics for an n n BJT CmA Forward Fig1310 k ECE 4430 Analog Integrated Circuits and Systems PE Allen LargeSignal Behavior of BJTs 51200 Page 1317 Lar e Si nal Model in Saturation In saturation both junctions are forward biased and the impedance levels looking into the emitter or collector is very low Simplified model Bo iL Jl oC Bo l i oC VBE0n VCESat VBE0n 1 TI VCESat E E E E quotPquot Pnp Fig13 ll where VBEon z 06 to 07V and VCEsat z 02V x ECE 4430 Analog Integrated Circuits and Systems PE Allen LargeSignal Behavior of BJTs 51200 Page 1318 The EbersMoll Large Signal Model Consider the saturation condition with both pn junctions forward biased l The emitter injected current in the base resulting from np1x is iEF IESeXpWE I t where I ES is a constant called saturation current no connection with I S 2 The collector injected current in the base resulting from np2x is VBC ZCR ICS EXP l t where CS is another constant called saturation current again no connection with I S 3 The total collector current iC is equal to iCR plus the amount A np0 h of 139 EF that reaches the collector VBE VBC 1C 1CR anEF aFIES exp l JCS eXth 1 Also we can write x VBE VBC iE iEF XRiCR ES XRICS CXPTI Base Flg39 3933911A R where 06R is the collector efficiency as an emitter and 3R W 39 R These two equations are the EbersMoll equations for the BJT k ECE 4430 Analog Integrated Circuits and Systems PE Allen LargeSignal Behavior of BJTs 51200 Page 1319 The EbersMoll Eguations Continued The reciprocity condition allows us to write FIEF RICR 2 IS Substituting into the previous form of the EbersMoll equations gives iC aISeXpVBE IJIi expol 1 VI R VI and S E VBC zE aF eXth 1 13 eXp Vt l These equations are valid for all four regions of operation of the BJ T x ECE 4430 Analog Integrated Circuits and Systems PE Allen LargeSignal Behavior of BJTs 51200 Page 1320 TRANSISTOR BREAKDOWN VOLTAGES CommonBase Transistor Breakdown Characteristics z39CmA A IEl5mA IEl0mA IE05mA IE0 l l l l V l T CBV Fig1312 0 20 40 60 80 100 BVCBO As the collectorbase voltage becomes large the collector current can be written as iC XFi EM where M 0 FiE 1 VCB B VCBO k ECE 4430 Analog Integrated Circuits and Systems PE Allen LargeSignal Behavior of BJTs 51200 Page 1321 CommonEmitter Transistor Breakdown Characteristics Assume that a constant base current 139 B is applied Using the previous result gives iC IC aF1EM gt 1E W 1 FM 1C1EIB gt 1Cl aFMIB gt 1C1aFM 13 where l M 1 VCB BVCBO Breakdown occurs when aFM 1 Assuming that vCE z VCB gives 21 Z BVCEO 1a lnBV BVCEO BVCBO F BF BVCBO Note that BVCEO is much less than BVCBO For 3F 100 and n 4 BVCEO z 05BVCBO x ECE 4430 Analog Integrated Circuits and Systems PE Allen LargeSignal Behavior of BJTs 51200 Page 1322 DEPENDENCE OF 3F ON OPERATING CONDITIONS Transistor 3E Dependence on Collector Current and Temperature Plot of BF as a function of iC BF A 400 7 lt Region I Region 1117 Reglon I Low current reglon where 3F T125quotC decreases as iC decreases Region II Midcurrent region where 3F is approximately constant Region III High current region Where 3F decreases as iC increases 0 If 0 HA lMA lOHA lOOMA lmA lOmA Fig1313 3F dependence on temperature The temperature coefficient of 3F is TCF z 7000ppm C ppm parts per million k ECE 4430 Analog Integrated Circuits and Systems PE Allen LargeSignal Behavior of BJTs 51200 Page 1323 Variation of Forward Beta with Collector Current Region II VBE IS VBE 1C I S exp7t and 13 z exp7t where BFM the maximum value of 3F Region I iC I S expvf and 139 B X I SX expilft due to recombination m z 2 B 2 11 ex 1 LIS 1392 1lt1mgt1 FL iBX ISX p Vrk m ISX Is for m 2 BFL 0C Regionlll VBE IS VBE 1C I SH exp2 Vt due to the high level ll ljeCUOl l and 13 z E exp7t IsH VLE JSHz 1 FH S BFeXP39 ZVI N S FM iC k ECE 4430 Analog Integrated Circuits and Systems PE Allen LargeSignal Behavior of BJTs 51200 Page 1324 Illustration of the Dependence of 3E on i lnz39 lnIS VBE Fig13l4 linear scale x ECE 4430 Analog Integrated Circuits and Systems PE Allen BJT Technology 53100 Page 1 24 BJT TECHNOLOGY INTRODUCTION Objective The objective of this presentation is 1 Illustrate the fabrication sequence for a typical bipolar junction transistor 2 Show the physical aspects of the BJT Outline npn BJT technology Compatible pnp BJTs Modifications to the standard npn BJT technology Summary x ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 Page 2 BJT Technology 53100 npn BIPOLAR JUNCTION TRANSISTOR TECHNOLOGY Maior Processino Steps for a Innrtinn I 39 J BJT TH hnnln V Start with a p substrate 1 Implantation of the buried n layer 2 Growth of the epitaxial layer 3 p isolation diffusion 4 Base ptype diffusion 5 Emitter n diffusion 6 p ohmic contact 7 Contact etching 8 Metal deposition and etching 9 Passivation and bond pad opening x ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 BJT Technology 53100 Page 3 Im lantation 0f the Buried La er Mask Ste 1 Objective of the buried layer is to reduce the collector resistance n implantation for buried layer SIDE i 39 VIEW p substrate 17 P 1quot I11 n 11 11 Metal Fig24l k ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 BJT Technology 53100 Page 4 Epitaxial Layer 1N0 Mask Required The objective is to provide the proper ntype doping in hich to build the npn BJT TOP VIEW A 4 w l Epitaxial SIDE Region VIEW nt buried layer pzsuhs tmte 17 p 1339 n1 n 11 11 Metal Fig39MZ k ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 BJT Technology 53100 Page 5 2 isolation diffusion Mask Step 21 The objective of this step is to surround isolate the npn BJT by a p diffusion These regions also permit r14r buried layer 13 P P ni n n n Metal Fig243 k ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 BJT Technology 53100 Page 6 Base t e diffusion Mask Ste 3 The step provides the ptype base for t BJT r14r buried layer 1 1fr p p39 ni n 11 nt Metal Fig23944 k ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 BJT Technology 53100 Page 7 Emitter n diffusion Mask Step 4 This step implements the n emitter of the npn BJT and the ohmic contact to the collector r14r buried layer 13 P 1339 n1 n 11 11 Metal Fig24 5 k ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 BJT Technology 53100 Page 8 p ohmic contact Mask Step 5 e base region if it is not doped sufficiently high n buried layer n39 n n Metal Fig392394396 k ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 A L C a m w mJ W M Vn m II mi mm mm t L p nw A P om Tw m he do 6 T um n ms B ns om rCT BJT Technology 53100 Dage 10 Metal de osition and etchin Mask Ste 7 In this step the metal is deposited over the entire wafer and removed where it is not wanted TOP VIEW 0 nt buried layer p substrate Fig248 L ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 BJT Technology 53100 Dage ll Passivation Mask Ste 8 Covering the entire wafer with glass and opening the area over bond pads which requires another mask Passivation 9 9 9 9 0 V 9 9 9 I39Q 939 I0 020202020 20202020202020 020202 quot0quot 0 0 0 0 0 0 0 202020202020 O C Q Q 9 Q Q Q Q V 0390 0 9 9 Vivi 02020202020202020202020 3902020202020 s 020202020201 020202020201 0 V k zgig 0 00 420 quot020 V 39 V VVVV VVV 020202020201 0202020202020202020201 020202020201 V V m Fig249 L ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 BJT Technology 53100 T ical Im urit A Concentration Profile for the n n BJT Taken along the line from the surface indicated in the last slide Dage 12 3c Depth from the k ECE 4430 Analog Integrated Circuits and Systems 1021 n H47 n4gtlt7p 4r A 1020 0 1019 Substrate Doping Level 9 1018 E 5 1017 39I Epitaxial lt1 I 39 I g l collector 39 I 8 1016 Il doping level i gt I II I 1015 I I m x quot x a 1014 I l I I I I I I I H 1 2 3 5 6 7 8 9 10 ll 12 1013 Base Collector Buried Layer Substrate 1012 m surface microns Fig 2410 PE Allen 2000 BJT Technology 53100 Dage l3 COMPATIBLE pnp BJTS Substrate Eng BJT Collector is always connected to the substrate potential which is the most negative DC potential p collector substrate p4r p p39 n1 n39 n r14r Metal Fig3923943911 k ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 BJT Technology 53100 Dage 14 Lateral Eng BJT Collector is not constrained to a fixed dc potential Fig24 12 p4r p 1139 n1 n 11 nt Metal L ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 BJT Technology 53100 Dage 15 MODIFICATIONS TO THE STANDARD npn TECHNOLOGY Types of Modifications 1 Dielectric isolation Isolation of the transistor from the substrate using an oxide layer 2 Double diffusion A second deeper n emitter diffusion is used to create JFETs 3 Ion implanted JFETs Use of an ion implantation to create the upper gate of a pchannel JF ET 4 Superbeta transistors Use of a very thin base width to achieve higher values of 3F 5 Double diffused pnp BJT Double diffusion is used to build a vertical pnp transistor whose performance more closely approaches that of the npn BJT k ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 Device MismatchinDiff Amps 7100 Page 1 36 DEVICE MISMATCH IN DIFFERENTIAL AMPLIFIERS INTRODUCTION Objective The objective of this presentation is l Characterize the dependence of bias circuits on the power supply 2 Introduce circuits that have various degrees of power supply independence Outline 0 Characterization of power supply dependence 0 Simple bias circuits 0 Bootstrapped bias circuits 0 Temperature characterization of bias circuits Objective The objective of this presentation is l Illustrate the method of analyzing mismatches 2 Analyze the input current and voltage offsets for differential amplifiers Outline 0 The general approach to analyzing mismatches 0 Input voltage and current offsets of BIT differential amplifiers 0 Input voltage offsem of MOS differential amplifiers 0 Summary LECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 Device Mismatch in Diff Amps 7100 Page 2 MISMATCH ANALYSIS METHODS General Method Suppose that two performances p1 and p2 can be written can be written as p1f1x1y1zl and p2f2x2y222 Ideally yl should be equal to y2 but in practice their difference could be expressed as Error ep1 p2 fx1y1 21 x2y2 22 Now assume that x1y1 21 and x2y2 22 can be expressed in terms of their difference and average values We illustrate only for x1 ande x1x2 Ax x1 x2 and x T We can solve for x1 ande in terms ofo and x as follows x1x05Ax and x2x 05Ax Now the error can be express as ep1 p2 fx05Ax x05Ax This expressing can generally be simplified by assuming that Ax ltltx and using the following approximations l 1 LS 18 or 18 15 and neglecting higher power values of s ie 2 ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 Device MismatchinDiff Amps 7100 Page 3 INPUT VOLTAGE AND CURRENT OFFSETS OF THE BJT DIFFERENTIAL AMPLIFIER Model for Innut Offset Voltage and Current where 101 Ic2 Ic1 152 V V V Vln Vln Vln OS BEl BEZ r 1x1 r 1J2 r 1C2 In How does I 5 depend upon the semiconductor parameters I Inian A 47an A d I 47an A 47an A an 1 NAWBlVCB 1 Q31VCB 1 2 NAWBZVCB 2 Q32VCB 2 where WBVCB is the base width as a function of VCB NA is the acceptor density in the base andA is the emitter area LECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 Device MismatchinDiff Amps 7100 Page 4 BJT Input Offset Voltage Continued In order for the output voltage to be zero it is required that Ic1 R02 I R I C1 c1 cchz 1C2 RC1 Combining these two relationships gives V V1 i C2 A2 QBlaCB l n OS RC1 V11 kQBZltVCBJ Making the following definitions R 1RC2 Afr12 Q31Q32 ARC RCI39RC2gt RC 2 gt M Al39A2gt A 2 gtAQB Q3139Q32gt 311ng 2 which gives AR AQ AQ c 0 AA AA B B Rc1Rc 7 Rc2Rc T A 114 7 A2A T QBIQB 7 and QBZQB 7 Substituting these values into the expression for VOS gives ARC AA AQB RC 39 A 39 QB F AR AQ l 7 2 2 2 c AA B Vosinln AR AA AQ V1n1 R 1 A 1 Q J c B c B l A 2 Q 2 K B 2 ifARC ltltRC AA ltltA and AQB ltlt QB Expanding the logarithm and neglecting higher order terms gives ARC AAAQBJ7 ARC AI t S V z V Where OS RC A QB RC 1 ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 Device MismatchinDiff Amps 7100 Page 5 Example 1 Calculation of Input Voltage Offset for a BJT Differential Amplifier Find the value of the input offset voltage for a B T differential amplifier at room temperature if the standard deviations of the resistor match and saturation current match are 1 and 5 respectively Assume that the standard deviations are correlated Repeat this example if the standard deviations are not correlated Solution For the correlated case we have ARC AIv VOS V E 0026001005 15mV Magnitude not sign is important since the polarity of the mismatch is not known When the variation in RC and I 5 are uncorrelated then we get AR AI VOS V 0026I00120052 00260051 13mv LECE 4430 Analog Integrated Circuits and Systems PE A en 2000 Device MismatchinDiff Amps 7100 Page 6 T 39 of the Input Offset Voltage The temperature dependence of VOS is found by examining the temperature dependence of V V A AA OS t k RC 1 J While Iv and RC have reasonably large 1 J J J the J J r J of their difference can be neglected Therefore assuming a value of VOS 2mV we get dVos Vos 2mV dT T W 667pV C Offset voltage can be cancelled using external circuitry but to cancel the temperature drift requires the external circuitry to have the same temperature dependence ECE 4430 Analog Integrated Circuits and Systems PE A en 2000 Device Mismatch in Diff Amps 7100 In Page 7 ut Offset Current of the BJT Differential Am lifie Consider the following model based on the previous circuit The input offset current of the B T differential amplifier can be Written as 131 IE 05105 and 132 IE 05105 Icz 101 10513239131 I 1 Defining AIC ICZICI 1C C12 C2 whichgives F1 F2 A F FZ39 Fb and F 2 AIC AIC F A F 1010 39Tgt ICZIC 7 F1 F 39 2 gt and n F 2 LECE 4430 Analog Integrated Circuits and Systems Device Mismatch in Diff Amps 7100 PE Allen 2000 In Page 8 ut Offset Current of the BJT Differential Am lifier Continued Combining the previous expressions into the function for 10S gives AIC AIC 10 1039 IcAlc 43F h N dA I z ltlt I ltlt OS A F A F 1c F W en C C an F F F 2 F 39 2 Recalling that for the output voltage to be zero that Ic1 RC2 then 102 RC1 1c ARC 139 E H 2RC AIC AIC ARC ARC AIC ARC 1 1 1 1 AIC RC 21C 21C 2RC 2RC 1C RC m 139 227 Therefore I ICARC IcA F IC ARC A F OS FRC F F F RC F Typically A F F is about 10 and ARCRC is about 1 giving 1c OS F 00101 01113 11pA assuming thatIB lOpA ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 Device MismatchinDiff Amps 7100 Page 9 INPUT VOLTAGE OFFSET OF MOS DIFFERENTIAL AMPLIFIER Model for In ut Offset Volta e where for viquot 0 21m 21m K W Vos VGSl39VGsz WVT1 39 l n Where T Define ID1ID2 z VT1VT2 AID ID1391D2gtID 2 gtA l39 2gt 2 gtAVT VTl39VTZ and VT 2 Gives AID AID A A AVT AVT ID1ID TgtID2ID 39Tgt 1 3 f VTl VT Jrde VTZ VT 397 LECE 4430 Analog Integrated Circuits and Systems PE Alen 2000 Device MismatchinDiff Amps 7100 D 10 INPUT VOLTAGE OFFSET OF MOS DIFFERENTIAL AMPLIFIER Model for In ut Offset Volta e VDD where for viquot 0 21m 21m K W Vos VGSl39VGSZ l 1VT139 2VT2 Where T Define ID1ID2 z VT1VT2 AID IDl39IDz ID 2 A l39 2gt 2 gtAVT VTl39VTZ and VT 2 Gives AID AID A A AVT AVT ID1 ID TgtID2 ID 397 l tag z 39 VTl VT Jrde VTZ VT 397 ECE 4430 Analog Integmted Circuits and Systems PE Alen 2000 Device MismatchinDiff Amps 7100 D 11 Example 2 Calculation of Input Voltage Offset for a MOS Differential Amplifier Find the value of the input offset voltage for a MOS differential amplifier at room temperature if the standard deviations of the the resistor match and beta match are 1 and 5 respectively Assume that the threshold voltage deviation is normalized to the value of VGSVT 15V and is 10 Assume that the standard deviations are correlated Repeat this example if the standard deviations are not correlated Solution For the correlated case we have Vos AVT 4RD 411 7010 001 005 7 2 VGSVT VGSVT 39 2RD 39 23 15 VOS 00367x15V 55mV 00367 When the variation in R D and VT are uncorrelated then we get V AV AR 00714 GS39 T GS39 T D VOS 00714x15V 107mV LECE 4430 Analog Integmted Circuits and Systems PE A en 2000 Device MismatchinDiff Amps 7100 D 12 T t 39 of the MOS Input Offset Voltage V AV 39 i211 MRD A OS T 2RD Z J While RD and VT have a strong 1 J J J the J J of there matching can be ignored The temperature dependence of is K TW T 15 d 153ToTTo391395 15 lto4LL ltTogtT O 31 T Was d w a 1412 1 4 a 1412 21244 A l dT d LZRD 23j 23 LZRD 23de 4T izRD 23j At room temperature and a current of lOOpA and 200 we get Was 13 001 005 dT FooiT T75 VC ECE 4430 Analog Integmted Circuits and Systems PE A en 2000 pn Junction 51100 Dage 12l 12 DEPLETION REGION OF A PN JUNCTION INTRODUCTION Objective Characterize and model the pn junction Outline Physical aspects of pn junctions Mathematical models of the pn junction Depletion capacitance Breakdown characteristics x ECE 4430 Analog Integrated Circuits and Systems PE Allen pn Junction 51100 Dage 122 PHYSICAL ASPECTS OF THE PN JUNCTION Abrupt Junction Fig 12 1 Doped atoms near the metallurgical junction lose their free carriers by diffusion As these fixed atoms lose their free carriers they build up an electric field which opposes the diffusion Jp A mechanism Equilibrium conditions are reached when U ll Current due to diffusion Current due to electric field PE Allen k ECE 4430 Analog Integrated Circuits and Systems pn Junction 51100 Dage 123 MATHEMATICAL CHARACTERIZATION OF THE PN JUNCTION Abrupt PN Junction Impurity concentration cm393 Cross section of an ideal pn junction ND Apply a reverse 0 x bias VD VR NA 393 Depletion charge concentration cm393 9ND WI 0 W2 x qNA S mbol of the 39unction y pn Electrlc F1eld Vcrn ID gt l H x I t 39 I I VD I I ID I E0 I I 0 Potentlal V VD Fig 121 4 I V2 4 Voir VR 4 V l x 1 796d 439 Fig 12 2 k ECE 4430 Analog Integrated Circuits and Systems PE Allen Dage 124 pn Junction 51100 Summar of the PN Junction Characterization Barrier potential kT AND AND Hal J Depletion region widths 28siVoVDND W1 qNDltNAND W V1 W 28siVoVDNA N 2 qNDNAND Depletion capacitance CZA gsinAND l Clo J V2NAND WOND 1 V2 a 10 V0 Fig 12 3 PE Allen x ECE 4430 Analog Integrated Circuits and Systems Dage l25 pn Junction 51100 Example 1 An abrupt pn junction in silicon has the doping densities of N A 1015 atomscm3 and N D 1016 atomscm3 calculate the junction builtin potential the depletionlayer widths the maximum field with 10V reverse bias and the depeletion capacitance with 10V reverse bias if C10 3pF Solution At room temperature kTq 26mV and the intrinsic concentration is 111 15X1010 cm393 Therefore the junction builtin potential is Ilo 0026 ln 0637V The depletion Width on the pside is 2104x10121064 4 2 W1 16x1019101511 355x Cm E The depletion width on the nside is 2104x10121064 4 2 W2 16X1019101611 035X10 cm 035 m The maximum field occurs for x 0 and is qN 19 15 4 8A W116X10 10 35X10 538X104Vcm max 39 104x1012 The depletion capacitance can be found as 3 F C P 0659F 10 l k ECE 4430 Analog Integrated Circuits and Systems PE Allen Dage 126 pn Junction 51100 Summar of the PN Junction Characterization Continued Breakdown voltage 8siNAND 2 1 R 2qNAND max N where E 2 is the maximum electric field before breakdown occurs usually due to avalanche maX breakdown Reverse leakage current The reverse current I R increases by a multiplication factor M as the reverse voltage increases and is IRA MIR where ID mA BV VR k Breakdown Fig 12 4 x ECE 4430 Analog Integrated Circuits and Systems PE Allen Dage 127 pn Junction 51100 Example 2 An abrupt pn junction has doping densities of N A 5X1015 atomscm3 and N D 1016 atomscm3 Calculate the breakdown voltage if E 3X105 Vcm crit Solution 8siNAND 2 R 2qNAND 104x101215x1015 88V max 216x10195x10151016 x ECE 4430 Analog Integrated Circuits and Systems PE Allen MOS Models 52300 18 MOSFET MODELS INTRODUCTION Objective The objective of this presentation is 1 Understand how the MOS transistor works 2 Understand and apply the simple large signal model 3 Understand and apply the smallsignal model Outline MOS Structure and Operation Large Signal Model SmallSignal Model Capacitance Short Channel Large Signal Model Subthreshold Large Signal Model Summary ECE 4430 Analog Integrated Circuits and Systems Page 1 Phillip E Allen 2000 MOS Models 52300 Page 2 MOS STRUCTURE AND OPERATION MetalOxideSemiconductor Structure BulldSubstrate Source Thin Oxide 10 100nm V1 Po1ysi1icon 3 r IOOA 1000A 5232323252325232323252325251 Gate Drain O O p substrate Heavily Lightly Intrinsic Lightly Heavily Metal Doped p Doped p Doping Doped n Dopedn Figl8 l Terminals Bulk Used to make an ohmic contact to the substrate Gate The gate voltage is applied in such a manner as to invert the doping of the material directly beneath the gate to form a channel between the source and drain Source Source of the carriers owing in the channel Drain Collects the carriers owing in the channel L ECE 4430 Analog Integrated Circuits and Systems Phillip E Allen 2000 MOS Models 52300 Formation of the Channel for an Enhancement MOS Transistor Subthreshold VgltVT VB 0 p substrate Threshold VGVT VB 0 p substrate Strong Threshold VggtVT VB 0 Vs 0 v mg Region p substrate Figl82 L ECE 4430 Analog Integrated Circuits and Systems Page 3 Phillip E Allen 2000 MOS Models 52300 Page 4 The MOSFET Threshold Voltage When the gate voltage reaches a value called the threshold voltage VT the substrate beneath the gate becomes inverted it changes from ptype to ntype Qb QSS VT gtMs2 F q q where MS Fsubstrate Fgate F Equilibrium electrostatic potential F emi potential kT FPMOS 7111NAni Vt lnNAnl kT FNMOS 7 lnNDnl Vt lnNDnl Qb z IquAssil392 FVSBl QSS undesired positive charge present in the interface between the oxide and the bulk silicon Rewriting the threshold voltage expression gives Q Q Q Q VT 2 gtMS 392 F w VTo 7Il2 F VSBl l2 F 0x where QbO QSS IzqssiNl Cox C and y Cox ECE 4430 Analog Integrated Circuits and Systems Phillip E Allen 2000 MOS Models 52300 Si us for the uantities in the Threshold Volta e EX ression Parameter N Channel P Channel Substrate gtMs Metal r1 Si Gate t Si Gate gtF QboaQb SS VSB 7 ECE 4430 Analog Integrated Circuits and Systems P39type n type Page 5 Phillip E Allen 2000 MOS Models 52300 Page 6 Example 1 Calculation of the Threshold Voltage Find the threshold voltage and body factor 7 for an n channel transistor with an n silicon gate if tax 2 200 A NA 3 X 1016 cm393 gate doping ND 2 4 X 1019 cm393 and if the positivelycharged ions at the oxidesilicon interface per area is 1010 cm392 Solution From above Fsubstrate is given as 3X 1016 Fsubstrate 00259 In 0377 V The equilibrium electrostatic potential for the n polysilicon gate is found from as 4 gtlt1019 145gtlt1010 0 563V Fgate 00259 ln Therefore the potential MS is found to be Fsubstrate Fgate 0940 V The oxide capacitance is given as 39 x 8854 gtlt103914 C saxtax 200 x 108 The fixed charge in the depletion region Qbo is given as 1727 x 107 FcmZ Qb0 2 x 16 x1019 x 117 x 8854 x1014 x 2 x 0377 x 3 gtlt101612 866 gtlt108 Ccm2 ECE 4430 Analog Integrated Circuits and Systems Phillip E Allen 2000 MOS Models 52300 Example 1 Continued Cox 1727 gtlt10397 VTO 0940 0754 The body factor is found as 1010gtlt 160 x1019 Dividing Qbo by Cox gives 0501 V Finally QSSCox is given as 93 gtlt10393 v Substituting these values for VTO gives 0501 93 X 10393 0306 V 12 2 x 16 x1019 x 117 x 8854 gtlt103914 x 3 x1016 ECE 4430 Analog Integrated Circuits and Systems 1727 x 10397 0577 v 2 Page 7 Phillip E Allen 2000 MOS Models 52300 Page 8 SIMPLE LARGE SIGNAL MOSFET MODEL Large Signal Model Derivation Derivation 1 Let the charge per unit area in the channel inversion layer be Q10 Coxvas v0 VT coulombscm2gt 2 Define sheet conductivity of the inversion layer per square as coulombs amRs l G s MOQM vsI cm2 volt Qsq 3 Ohm s Law for current in a sheet is lID dv iD iDdy JS W GSEy SSW gt dv GSW dy MOQIOMV gt 1D dy WMoQIydV 4 Integrating along the channel for 0 to L gives L VDS VDS fiDdy fWMOQIQMv nyoCoxszvyVT dv 0 0 0 5 Evaluating the limits gives WHoCox 2 VDS I39D TVGSVTVU 0 gt WM C VDS2 I39D VGSVTVDS 2 ECE 4430 Analog Integrated Circuits and Systems Phillip E Allen 2000 MOS Models 52300 Page 9 Saturation Voltage VD sat Interpretation of the large signal model iD VDs VGs VT Active Region The saturation voltage for MOSFETs is the value of drainsource voltage at the peak of the inverted parabolas ox dvDS L szVTgtvns10 9 Useful definitions MoCoxW K W L 713 ECE 4430 Analog Integrated Circuits and Systems Phillip E Allen 2000 MOS Models 52300 Complete Large Signal Model Regions of Operation of the MOS Transistor l Cutoff Region iDO vgsVTltO 2 Active Region MocoxW iD T2VGS VT VDS VDS 3 Saturation Region I MocoxW 1D Twas VT 2 Output Characteristics of the MOSFET Page 10 Ignores subthreshold currents 0ltVDSltVGSVT 0 ltVGSVTltVDS iDIDO VDs VGs VT 10 39quotquot 39 39 39 39 VGS39VT 10 V V d anye Saturation Region b GSO T eglon I VGSVT 7 7 0867 075 quotquotquotquotquot 39 39 VGSO VT Channel modulation effects VGS39VT 0707 5 39 39 39 quotVGsoVT I VGsVT 5 E VGso VT 025 VGsVT Cutoff Region VGSO VT 0 I II I I I gt VIDS 05 10 15 20 25 VGSO39VT ECE 4430 Analog Integrated Circuits and Systems Phillip E Allen 2000 MOS Models 52300 Page 11 In uence of VM on the Output Characteristics Channel modulation effect As the value of VD S increases it causes the effective L to decrease which causes the current to increase Illustration VGgt VT VD gt Vpssat Depletion Region p substrate F1gl83 Note that Leff L X d Therefore the model in saturation becomes K W v V 2 E ii 2Leff2 GS T dVDS Leff dVDS D K W dip i v V 2 gt D 2Leff GS T dvDS Therefore a good approximation to the in uence of vDS on 139 D is K W 2L VGS39VT2139VDS dlD iD z iDVDS0 dvDS VDS iDO DSZOXI lVDS L ECE 4430 Analog Integrated Circuits and Systems Phillip E Allen 2000 MOS Models 52300 Page 12 In uence of the Bulk Volta e on the Lar e Si nal MOSFET Model Illustration of the in uence of the bulk VSBO 0V1 Vs1300I Bulk Source 1 Ip 1 VSB1gt0V 1 Substrate Bulk V332 gt VSBiI VSB2 Bulk I Source I I 139 n ECE 4430 Analog Integrated Circuits and Systems Phillip E Allen 2000 MOS Models 52300 Page 13 In uence of the Bulk Voltage on the Large Signal MOSFET Model Continued BulkSource vBs in uence on the transconductance characteristics lD Decreasing values of bulksource voltage gt gt VGs VTo VT1 VT2 VT3 VBs VDS In general the simple model incorporates the bulk effect into VT by the following empirically developed equation VTVBS VTO 7V2 gtf1 IVle 7 2W1 ECE 4430 Analog Integrated Circuits and Systems Phillip E Allen 2000 MOS Models 52300 Page 14 MOSFET Schematic Symbols Enhancement VBS 720V VB 50V Simple D D D NMOS GHI B Go I Gp EI s s s D D D PMOS GO IEEAB Go l G s S S Figl8 4 L ECE 4430 Analog Integrated Circuits and Systems Phillip E Allen 2000 MOS Models 52300 Page 15 Summar 0f the Sim le Lar e Si nal MOSFET Model rig N channel reference convention Gg In gB sz VBS Nonsaturation quot I39D WMZ Coxvas VTVDS VDZSZ 1 lVDS Saturation iD WMZ VGS VTVDSSat VW 1 lVDS WMZO EOXWGS VT 2 1 lVDS where u0 zero field mobility cmZvoltsec Cox gate oxide capacitance per unit area F cm2 2 channellength modulation parameter volts39l VT VTO l2 fl IVle VTO zero bias threshold voltage 7 bulk threshold parameter volts05 2 f1 strong inversion surface potential volts For pchannel MOSFETs use nchannel equations with pchannel parameters and invert current ECE 4430 Analog Integrated Circuits and Systems Phillip E Allen 2000 MOSFET MOS Models 52300 Constants for Silicon Page 16 strong inversion Constant Symbol Constant Description Value Units VG Silicon bandgap 270C 1205 V k Boltzmann s constant 1381X1023 JK nl Intrinsic carrier concentration 270C 145X1010 cm393 80 PermittiVity of free space 8854XIO3914 fcm SSZ PermittiVity of silicon 117 90 Fcm sax PermittiVity of SiOZ 39 90 Fcm Model Parameters for a Typical CMOS Bulk Process 08um CMOS nwell Parameter Parameter Typical Parameter Value Symbol Description N Channel PChannel Units VTO Threshold Voltage 07 i 0 15 07 i 015 V VBs 0 K 39 Transconductance 1100 i 10 500 i 10 uAJV2 Parameter in saturation 7 Bulk threshold 04 057 V12 parameter a Channel length 004 L1 um 005 L 1 um 00391 modulation 001 L2 um 001 L 2 um parameter 2 F1 Surface potential at 07 08 V ECE 4430 Analog Integrated Circuits and Systems Phillip E Allen 2000 MOS Models 52300 MOSFET SMALL SIGNAL MODEL SmallSignal Model Complete schematic model D 4 1 G3 Bg gD G B G B Vdsltgt Vds H H Vgs Vb gmvgs gmbstS ltgt S 5 5 S S Fig 424 where ngWGSQ TGSVT 2HD gdsz Qm zllD d alD 81D avGSl M an gm aVBSQ aVGS aVBS Simplified schematic model D GOI Go I s S Extremely important assumption 32 Li 2 9 aVBS 2 2 F VBS gm S Fig42 2 gm z logmbs z loogds ECE 4430 Analog Integrated Circuits and Systems Page 17 Phillip E Allen 2000 Page 18 MOS Models 52300 Illustration of the SmallSignal Model Application 139 A lt7 AC Resistance lt7 DC Resistance DC resistor v V DC res1stance T I 1 I Useful for biasing creating current from voltage and ID 7777777 W Vice versa VT VDS Fig 4 223 SmallSlgnal Load AC res1stance D D 4 1 G3 Bg gD G B G B v vb rds ltgt vds H H gs S nggs gmbsts ltgt S 5 39 5 S S Fig 42 4 Vds 1 1 AC resistance 161 gm gals gm Phillip E Allen 2000 ECE 4430 Analog Integrated Circuits and Systems MOS Models 52300 Page 19 Example 2 SmallSignal Load Resistance Find the small signal resistance of the MOS diode VDD 5V shown using the parameters of Table 321 Assume that the WL ratio is 10 um 1 pm Solution 4rac If we are going to include the bulk effect we must first find the dc value of the bulksource voltage Unfortunately we do not know the threshold voltage because the bulksource voltage is unknown The best approach is to 100uA ignore the bulksource voltage find the gatesource voltage and then iterate if F 4 2 5 necessary T 1g39 39 39 21 2100 VGS VT0 39 m 07 1126V Thus let us guess at a gatesource voltage of 13V to account for the bulk effect and calculate the resulting gatesource voltage VT VTO 2 F 37 71 2 F 07 04V0737 04V07 120V gt VGS 163V Now refine our guess at VGS as 16V and repeat the above to get VT 1175V which gives VGS 160V Therefore VBS 34V ECE 4430 Analog Integrated Circuits and Systems Phillip E Allen 2000 MOS Models 52300 Page 20 Example 2 Continued The small signal model for this example is shown GDB 1d lt I l quot The ac mput res1stance is found by T gt V rdS gtVds Vgs Vac lac gdsvac 39 gmvgs 39 gmbsvbs gm gs gmbsvbs S v Vac gdsvac gmvs gmbsvs Vacgmgmbsgds 1110 Flg 426 Vac l 39 r ac lac gmgmbsgds Now we must find the parameters which are gm 12135 V211010100 us 469uS gds 004V391100uA 4ps and gmbs 6 00987469118 4633118 Finally 106 Vac 469 4633 4 If we had used the previous approximations of gm z lOgmbS z IOOgdS then we could have simply let 1 l raczg m E ZBZQ 19269 Probably the most important result of this approximation is that we would not have to nd VBS which took a lot of effort for little return ECE 4430 Analog Integrated Circuits and Systems Phillip E Allen 2000 MOS Models 52300 Page 21 SmallSignal Model for the Active Region 3quotD 2w K W gm aVGSQ L HMBS z VDS 81D K Wy VDS g b quot 9V3 2L2 gtFV3s 811 CW ID K W T VGS VT VDS1NDS m TWGS VT VDS Phillip E Allen 2000 ECE 4430 Analog Integrated Circuits and Systems MOS Models 52300 Page 22 MOSFET CAPACITANCES Types of Capacitance Physical Picture Fig185 MOSFET Capacitances consist of Depletion capacitance Charge storage or parallel plate capacitance ECE 4430 Analog Integrated Circuits and Systems Phillip E Allen 2000 MOS Models 52300 MOSFET Depletion Capacitors AS area of the source PS perimeter of the source CJSW zero bias bulk source sidewall capacitance MJSW bulksource sidewall grading coefficient ECE 4430 Analog Integrated Circuits and Systems Polysilicon gate Page 23 Sio2 Figl 8 6 Drain bottom ABCD Drain sidewall ABFE BCGF DCGH ADHE Model CBS CJAS J CJSWPiSW VBSSFCPB 1 Wis 1 VBS 39 PB 39 PB and CJAS VBS C33W 11MJFC MJ lFC V 11MJSWFC MJSWPLBS 1 FC v33gtFCPB where was s FCPB For the bulkdrain depletion capacitance replace quotSquot by quotDquot in the above BS FCPB Fig186B Phillip E Allen 2000 K MOS Models 52300 Page 24 Charge Storage Parallel Plate MOSFET Canacitances ClCC3 and Ci MaskLa Oxide encroachment i 77777 MLActuaI i l Len1 MaSk l Acmal 3 LD 1 W 1 WWeff L W J Gate Sourcegate overlap Dr aimgate OVerlap capacitance C GS C 1 capaCitance CGD C3 T GateChannel BulkChannelBulk Capacitance C 2 Capacitance C4 Fig187 Overlap capacitances C1 C3 LDWe Cox CGSO or CGDO LD z 0015 um for LDD structures Channel capacitances C2 gatetochannel CoxWe LZLD CoxWeffLeff C4 voltage dependent channelbulksubstrate capacitance ECE 4430 Analog Integrated Circuits and Systems Phillip E Allen 2000 MOS Models 52300 Page 25 Charge Storage Parallel Plate MOSFET Canacitances C View looking down the channel from source to drain Overlap OVerlaP Source Dram Figl8 8 C5 CGBO Capacitance values and coefficients based on an oxide thickness of 140 A or Cox247 X 10 4 FmZ Type PChannel NChannel Units CGSO 220 x 10 12 220 x 10 12 Ml CGDO 220 x 1012 220 x 1012 Ml CGBO 700 x 10 12 700 x 10 12 W31 CJ 560 x 10 6 770 x 10 6 Fm2 CJSW 350 gtlt10 12 380 gtlt10 12 Wm M 05 05 MJSW 035 038 ECE 4430 Analog Integrated Circuits and Systems Phillip E Allen 2000 MOS Models 52300 Page 26 Expressions for CG DCQL1CB Cutoff Region CutoiT CGB C2 2 C 5 CoxWeffLeff 2CGBOLeff C GS C1 z CoxLDWeff CGSOWeff CGD C3 z CoxLDWeif CGDOWeff Saturation Region CGB 2C5 CGBOLeff C GS C1 2 3C 2 CoxLDO67LeffWeff CGSO Weff 067C0xWe cLeff CGD C3 z CoxLDWeif CGDOWeff ll Plysilicon 39f 1 A EggE I Active Region CGB 2 C 5 2CGBOLeff CGS C1 05C2 C0xLD05LeffWe CGSO 05ioxLe VIeff 1quot Substrate mvmeanegion CGD C3 05C2 C0xLD05Le cWe c CGDO 05C0xLe cWeff Figl 89 L ECE 4430 Analog Integrated Circuits and Systems Phillip E Allen 2000 Page 27 MOS Models 52300 Illustration of C i and CGB Capacitance C2 2C5 C1 067C2 C1 0502 C1C3 C4 Large 205 o l C36 2C5 C2 C4 For VGSzO CGB zCz 2C5 For 0ltvGS VT CGB z 2C5 ECE 4430 Analog Integrated Circuits and Systems HOE Saturation lt7 VT Comments on the variation of C BG in the cutoff region VDSVT C4 is small because of the thicker inversion layer in strong inversion Non a S aturation Figl810 C4 is large because of the thin inversion layer in weak inversion where VGS is slightly less than VT Phillip E Allen 2000 MOS Models 52300 Page 28 SmallSignal Freguency Dependent Model ng id G c J c D vgs cgs Q Q rds Vds T nggs gmbsts Cg Squot J 38de Vbs Cbs T Bl Figl815 The depletion capacitors are found by evaluating the large signal capacitors at the DC operating point The charge storage capacitors are constant for a specific region of operation Gainbandwidth of the MOSFET Assume VSB 0 and the MOSFET is in saturation gmLgm fT 27thS ngNZrcCgS Recalling that 2 CgsngoxWL and W gm HoCoxf VGS39 VT gives 3 Iuo fr fzaGS39VT ECE 4430 Analog Integrated Circuits and Systems Phillip E Allen 2000 MOS Models 52300 Page 29 Summary of the MOSFET Large Signal Model JFD ltrD CGD ltgt CBD VBD IA lt39 1D lBD G VG VBS r3 o wv e wrv w 113s E Where CGS CBS VG rs VB and VB are ohmic and contact resistances VBD VBS iBDISexpT l andiBSISexp7 l CGB gt t t ltgtVS ls Phillip E Allen 2000 ECE 4430 Analog Integrated Circuits and Systems K MOS Models 52300 Page 30 SHORTCHANN EL MOSFET MODEL Velocity Saturation The most important shortchannel effect in MOSFETs is the velocity saturation of carriers in the channel A plot of electron drift velocity versus electric field is shown below A 105 7 5X104 2X104 104 5XlCQ t 105 106 107 Electric Field Vm Fig1811 Electron Drift Velocity ms An expression for the electron drift velocity as a function of the electric field is HnE W N 1 EEc Where vd electron drift velocity ins un lowfield mobility z 007m2Vs E c critical electrical field at which velocity saturation occurs ECE 4430 Analog Integrated Circuits and Systems Phillip E Allen 2000 MOS Models 52300 Page 31 Sho rtChannel Mo del Derivation As before 239 WQIO nE JD Js Q1ltygtvdltygt ip W Q1ltygtvdltygt W a iD1 WQmenE Replacing E by dvdy gives l d v dv 2D1 EC dy mommy Integrating along the channel gives L v l dv DS 1191 E 5 y fWQJCVMndV 0 C 0 The result of this integration is IunCox W K W L 2VGS 39 VTVDS 39 VDSZl 2H 9VGSVT L iD lVDS 21 EC L 2VGS 39 VTVDS 39 VDSZl Where 0 lLEC with dimensions of VI The saturation voltage has not changed so substituting for VD S by VGSVT gives K W 39 2 D 21 ewesm L VGS W Note that the transistor will enter the saturation region for VDS lt vGS VT in the presence of velocity saturation ECE 4430 Analog Integrated Circuits and Systems Phillip E Allen 2000 MOS Models 52300 Page 32 The In uence of Velocity Saturation on the Transconductance Characteristics The following plot was made for K llOHAV2 and WL l 1000 9 800 04 600 400 iDW uNum 200 0 05 l 15 2 25 3 VGS V Figl8 12 Note as the velocity saturation effect becomes stronger that the drain currentgate voltage relationship becomes linear L ECE 4430 Analog Integrated Circuits and Systems Phillip E Allen 2000 MOS Models 52300 Circuit Model for Velocitv Saturation A simple circuit model to include the in uence of velocity saturation is the following We know that Substituting VGS into the current relationship gives K W 1D 2L VGS 39 ZDRSX 39VT2 Solving for 139 D results in K j W K fRSXOGsVT W 1 L VGs VT2 Comparing with the previous result we see that W 9L 1 9 K LRSX gt RSX KW ECKW K W 2 1D 2L VGS 39VT and VGS VGS 11 RSX 0r VGS VGS39 ZDRXS Therefore for K 110uAV2 W 1m and EC 15x106Vm we get RXS 606142 Page 33 D G we l VGS39 VGS RSX s Figl8 13 ECE 4430 Analog Integrated Circuits and Systems Phillip E Allen 2000 MOS Models 52300 Page 34 Output Characteristics of ShortChannel MOSFETsl IBM 1998 t 35mm ox 800 l I l l l l PFET NFET VGS18V 700 7 Leff Leff A 008 m g 600 7 01le H 7 2 VGF14V 3500 7 7 E t 400 Vast18V 5 300 VG C10V 7 g VGF14V 81 Q 200 VGscIOV 7 100 7 V 706V 7 VGF06V Gf 0 l x l l l 18 12 06 00 06 12 18 Drain Voltage V Figl8l4 l Su L etal A High Performance Sub025pm CMOS Technology with Multiple Thresholds and Copper Interconnects 1998 Symposium on VLSI Technology Digest afTechnical Papers pp 1819 ECE 4430 Analog Integrated Circuits and Systems Phillip E Allen 2000 MOS Models 52300 Page 35 SUBTHRESHOLD MOSFET MODEL Weak inversion operation occurs when the applied gate voltage is below VT and pertains to when the surface of the substrate beneath the gate is weakly inverted Diffusion Current p sub strate well Regions of operation according to the surface potential 3 3 lt F Substrate not inverted F lt S lt 2 F Channel is weakly inverted diffusion current 2 F lt S Strong inversion drift current Drift current versus diffusion current in a MOSFET lo I z39 Diffusion Current 4 Drift Current 106 1 j 39 1017 Iquot 0 VT VGs L ECE 4430 Analog Integrated Circuits and Systems Phillip E Allen 2000 MOS Models 52300 Page 36 LargeSignal Model for Subthreshold Model iD KxgeVGsquotVt e39VDWle WDS where Kx is dependent on process parameters and the bulksource voltage n z 15 3 and 1D kT Vt 7 IMA VGSCVT If vDS gt 0 then W I39D KxfeVGSquotVt 1 VVDS VGSltVT Smallsignal model 0 0 1V VDS 31D I qID Figl818 gm 8VGS nkT 15D 2 gds BVDSQ VA ECE 4430 Analog Integrated Circuits and Systems Phillip E Allen 2000 MOS Models 52300 Page 37 SUBSTRATE CURRENT FLOW IN MOSFETS Impact Ionization Impact Ionization Occurs because high electric fields cause an impact which generates a holeelectron pair The electrons ow out the drain and the holes ow into the substrate causing a substrate current ow Illustration Depletion Ill T Region V n 11 1 e b t t 1quot S11 S ra e Figl8l6 L ECE 4430 Analog Integrated Circuits and Systems Phillip E Allen 2000 MOS Models 52300 Page 38 Model of Substrate Current Flow Substrate current iDB K1VDS vDSltsatiDe39KZVDS39VDSGaUH where K 1 and K2 are processdependent parameters typical values are K1 5V391 and K2 30V Schematic model D I39DB G B S Figl8 l7 Smallsignal model aiDB K DB gdb aquotDB 2 VDS 39 VDSSat This conductance will have a negative in uence on highoutput resistance current sinkssources ECE 4430 Analog Integrated Circuits and Systems Phillip E Allen 2000 Small Signal BJT Models 52100 Page 1 14 SMALL SIGNAL MODEL OF THE BJT INTRODUCTION Objective The objective of this presentation is 1 Concept of the small signal model 2 The small signal model for the BJT Outline Transconductance small signal model Input resistance output resistance of the common emitter model Extensions of the small signal BJ T model BJT frequency response x ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 Small Signal BJT Models 52100 Cate orization of Electrical Models TRANSCONDUCTANCE SMALL SIGNAL MODEL Time Dependence Time Independent Time Dependent Smallsignal midband Smallsignal frequency iD fVDVGVSVB OP Linear R A R response poles and Linearity 17quot V out zeros TF AC Nonlinear DC operating point Largesignal transient response Slew rate TRAN Based on the simulation capabilities of SPICE k ECE 4430 Analog Integrated Circuits and Systems Page 2 PE Allen 2000 Page 3 Small Signal BJT Models 52100 What is a Small Signal Model A small signal model is a linear model which is independent of amplitude It may or may not have time dependence ie capacitors The small signal model for a nonlinear component such as a BJT is a linear model about some nominal operating point The deviations from the operating point are small enough that it approximates the nonlinear component over a limited range of amplitudes Illustration of the pn diode S39 n I Small Signal ID J LvYf l 7 7 7 7 l gt yD Time nD r VD AT TATT TTTT 4 3amp7 7 7 lt5 Fig141 eunl A x ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 Small Signal BJT Models 52100 Page 4 BJT CommonEmitter ForwardActive Re ion Effect of a smallsignal input voltage applied to a BJT Carrier 1 I Emitter Concentration 1C 4g 16 Depletion V AQh 1393 B ib Region Collector Depletion V1 V II Region CC n 0 n ex BE Vbe p 70 P VI y AQe VBE ICiC 71170 npa exp I h I i C x Emitter i lt WB i Collector Base 39 Fig142 Vgt ib Zgti k ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 Small Signal BJT Models 52100 Page 5 Transconductance 0f the Small Si nal BJT Model The small signal transconductance is defined as diCI AiC 139 gmdeEQAvBE vbev Z lcgmvi The large signal model for iC is VBE d VBEl IS VBE IC zC ISeXth gt gm ISeXpV t 7t eXth Vt 1C gm 7t Another way to develop the small signal transconductance 139 1 eX VBEVi 1 eX Eex v iI eX v i1lv ili 11 C S p Vt S p Vt th C th C Vt 2 Vt 6 Vt iczlcic lcNCVt 2 Vt 6 Vt Vtvi gmvl But k ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 Small Signal BJT Models 52100 Page 6 k ECE 4430 Analog Integrated Circuits and Systems INPUT AND OUTPUT RESISTANCE SMALL SIGNAL MODEL Input Resistance of the Small Signal BJT Model In the forwardactive region we can write that 139C 13 E Small changes in 139 B and iC can be related as A L 13 61 BF 1C The small signal current gain 30 can be written as Therefore we define the small signal input resistance as Vi on39 amp rE 7 C gm 5 139 PE Allen 2000 Small Signal BJT Models 52100 Page 7 Out ut Resistance of the Small Si nal BJT Model In the forwardactive region we can write that the small signal output conductance g0 r0 lgo is diC I AiC ic I go dVCE Q AVCE Vce Z 16 govce The large signal model for iC including the in uence of vCE is 39 I 1vC E VBE lc S VA eXpV t diC I1 VBE 1C S g WWW x ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 Small Signal BJT Models 52100 Page 8 Sim 1e Small Si nal BJT Model Implementing the above relationships 139 c gmvi 139 c govce and v1 r ib into a schematic model gives C 1395 to C C gt B In Vi 7139 ngi 70 Vce CI B E E E E Fig 143 Note that the small signal model is the same for either a npn or a pnp BJT Example Find the small signal input resistance Rm the output resistance Rout and the voltage gain of the common emitter BJ T if the BJ T is unloaded R L 00 v tvm the dc collector current is lmA the Early voltage is 100V and 30 at room temperature ou 1c lmA 1 I30 gm Vt 26mV 26 mhos or Slemans Rm r g m 10026 26kQ VA 100v V Rom r0 g m 100m V0quot gm r0 26mS100kQ 2600VV m k ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 Small Signal BJT Models 52100 Page 9 EXTENSIONS OF THE SMALL SIGNAL BJT MODEL CollectorBase Resistance of the Small Si nal BJT Model Recall the in uence of V on the base width Carrier Collector depletion Concentration region widens due to a At change 1n VCE AVCE A l Initial Depletion 0 VBE Region np npa exp lt7 V I I l I I x Emitter I 4 W3 Collector Base 396 39 F39 1 3 6 AWE 1g We noted that an increase in vCE causes and increase in the depletion width and a decrease in the total minoritycarrier charge stored in the base and therefore a decrease in the base recombination current 13931 This in uence is modeled by a collectorbase resistor rlu defined as Av Av Ai Ai CE CE C C rlu Aim AiC Aim r0 Aim z Borg lower 11m1t 1f base current 1s all recombmatlon current In general rlu 2 10 Borg for the npn BJT and about 25 Borg for the lateral pnp BJT k ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 Small Signal BJT Models 52100 Dage 10 BaseChar in Ca acitance 0f the Small Si nal BJT Model Consider changes in basecarrier concentrations once again Carrier 1 1 1 Emitter Concentration C lt c Depletion F AQh iB 13 lb Region N Collector gt Depletion V I3 Region CC 71 0 n eX BEVbe p 70 P VI V AQe ICH39C I N I I VBE 71170 npa exp I l 1C x Emitter l 4 W3 E Collector Base 39 Fig142 The AVBE change causes a change in the minority carriers AQe qe which must be equal to the change in majority carriers AQh q h This charge can be related to the voltage across the base vi as W 7sz where Cb is the basecharging capacitor and is given as C 1h lg b vl V1 7FgmTFVt W32 The base trans1t time 1F 1s de ned as 2Dquot k ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 Small Signal BJT Models 52100 Dage ll Parasitic Elements of the BJT Small Si nal Model Typical crosssection of the npn BJT Collector Base Emitter nJr emitter i p isolation x 9 I i 739 r 1 p isolation Cos V p substrate I p4r p p n1 n n n Metal Fig 144 C 18 baseemitter depletion capacitance forward biased 0 C I collectorbase depletlon capacltance reverse blased C B T Resistances are all bulk ohmic resistances Of importance are rb rc and Vex Also rb is a function of 1C x ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 Dage 12 Small Signal BJT Models 52100 Com lete Small Si nal BJT Model B rb B V c C AVAVA n lt i CWT rn ivl gmv1 ra CCSI gt r lt exltgt E E The capacitance C n consists of the sum of C 18 and C b CZ C16 Cb PE Allen 2000 x ECE 4430 Analog Integrated Circuits and Systems Dage 13 Small Signal BJT Models 52100 Example Derive the complete small signal equivalent circuit for a BJT at C lmA VCB 3V and VCS 5V The deVice parameters are CjeO 10fF me 05 woe 09V Ciao 10fF nc 03 IIOC 05V C630 20fF nS 03 IIOS 065V 30 100 IF 10ps VA 20V rb 3009 rc 509 Vex 59 and rlu lOBOVO Solution Because C je is difficult to determine and usually an insignificant part of C n let us approximate it as ZCJeo Cje20rF C C C 0 z lofF 56fF and CcsiL IOS W 05 WOS 065 I gm 2 70 ggmAV Cb TFgm 10ps38mAV 038pF C Cb Cf 038pF002pF 04pF 3 V V g r 10026Q 26kQ r0 f 20m and r 10B0r0 1010020kQ ZOMQ k ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 Small Signal BJT Models 52100 Dage l4 FREQUENCY RESPONSE OF THE BJT Transition Frequency 1 fT is the frequency where the magnitude of the shortcircuit commonemitter current equal unity Circuit and model 1 Vb CI A13 J vv I3 ii C1 7139 V1 ng1 Q 70 Cos Tia ii T T T Fig1406 Assume that rc z 0 As a result Va and C CS have no effect 73972 Iogw gmrn 30 39 V I d I V 39 l N 1 VACECbs 139 an o N gm 1 2 1060 CnCbs CnCbs 1 gmrn gm 1 0 gm 10060 30 Now 31 60 Iiw CnCbjw 1 30 gm At high frequencies gm gm L gm Ksz gt WhenBQw 1thean Cncb or fT 2 CnCb k ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 Small Signal BJT Models 52100 Dage 15 Illustration of the BJT Transition Fre uenc 3 as a function of frequency lBO l AA 1000 100 DB 01mT DR 0log scale Fig147 Note that the product of the magnitude and frequency at any point on the 6dBoctaVe curve is equal to COT For example 01 COT X10 wT In measuring COT the value of Bfa is measured at some frequency less than COT say cox and COT is calculated by taking the product of 39ax and cox to get COT x ECE 4430 Analog Integrated Circuits and Systems PE Allen 2000 Single Transistor Ampli ers 6 1300 Page 1 32 SINGLE TRANSISTOR AMPLIFIERS INTRODUCTION Objective The objective of this presentation is 1 Show how to characterize an amplifier 2 Show the analysis of single transistor amplifiers using resistive loads 3 Build the amplifier concepts necessary to consider integrated circuit amplifiers Outline Characterizing an amplifer BJT Single transistor amplifiers MOS Single transistor amplifers Amplifiers with emitter source degeneration Summary k ECE 4430 Analog Integrated Circuits and Systems PE Aquot Page 2 Single Transistor Ampli ers 6 1300 CHARACTERIZING AMPLIFIERS Characterization of Amplifiers Amplifiers will be characterized by the following properties Largesignal voltage transfer characteristics DC Largesignal voltage swing limitations DC and TRAN Smallsignal frequency independent performance TF Gain TF Input resistance TF Output resistance TF Smallsignal frequency response AC Other properties TElVlP FOUR etc Noise NOISE Power dissipation OP Slew rate TRAN Etc x ECE 4430 Analog Integrated Circuits and Systems RE Aquot Single Transistor Ampli ers 6 1300 T es of Sin le Transistor Am lifiers VCC VCC V0 UT V0 UT VIN VIN Common Emitter Common Base VDD VDD RD RD vo UT VOUT V IN JIl VIN Common Source Common Gate VIN V0 UT RE Common Collector VDD VIN vo UT Rs Common Drain Page 3 Rs Source Degeneration STA01 RE Aquot x ECE 4430 Analog Integrated Circuits and Systems Single Transistor Ampli ers 6 1300 Page 4 Signal Flow in Transistors It is important to recognize that ac signals can only ow into and out of certain transistor terminals C D B 00 G o I 00 A A E S STA015 Illustration Rules The collector or drain can never be an input terminal The base or gate can never be an output terminal In addition it is important to note polarity reversals on these signal paths The basecollector or gatedrain path inverts All other paths are noninverting This of course assumes that there are no reactive elements causing phase shifts k ECE 4430 Analog Integrated Circuits and Systems PE Aquot Single Transistor Ampli ers 6 1300 Page 5 BJT SINGLE TRANSISTOR AMPLIFIERS Common Emitter Amplifer LargeSignal 1C VOUT V A CC VCC RC VCC Forward 11 1 Actlve VOUT T 1 p Region V I l VIN j IN E D i l Saturation VCEsat 1 Region T 7 7777777 7 71 7 7 Common Emitter 0 I 0 VCC r VCE 0 0 05V 1 0V SVT A102 SmallSignal 10 I law 3 C C d VA 44 gm Vt an r0 C r0 lt RC Vaul 391 E R B0 R roRC Vout quotgmro39RC d lIou Bo39ro r 2 2 2 an m n gm out ya RC Vin r0 RC 1in yo RC One should also consider the case of a source resistance RS in series with the input k ECE 4430 Analog Integrated Circuits and Systems PE Aquot Page 6 Single Transistor Ampli ers 6 1300 Exam le 1 Common Emitter BJT with Source Resistance Find the smallsignal input resistance Rm output resistance Rout voltage gain voulvm and current gain 139 outiiquot for the circuit shown Assume that 30 is 100 VA 100V and IS lOfA Solution Smallsignal model is Rm 1quot laut Ram Bo tAWj C i R8 gt gt gt gt41 vm 1 k9 ltgt 7 r0 ltgt RC ltgt RL ltgt VOL rnlt gmvn ltr ltr lt EC STAO9C E 1c lmA 1l30 101 VA 100V gm 2 ft m 3851113 77 E m 26219 and r0 g m100k9 Vout Vout V717 r717 262 V R mngom 385196 1566 VV gt 239dB 139 V g r IIR and O W LC r 7549mS262kQ 1978 AA in The maximum voltage gain RS gt 0 RC gt oo RL gt 00 is VAVt lOO0026 3846VV k ECE 4430 Analog Integrated Circuits and Systems PE Aquot LargeSignal Single Transistor Ampli ers 6 1300 Common Base Amplifer Page 7 k ECE 4430 Analog Integrated Circuits and Systems lb Vcc 1 RC Vg VOUT RL I3 lVIN II VI Saturation Region STA04 G gt VCB 0 VCC 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 if SmallSignal ngin in 1in 1out fiat gt 4 E c c C I I 41 gt E quotI quot I gt 39 R Vm Vngt r C gt Vaut B 5 5 B STAOS l l r727 Vout lout quotgm NeglectingrR z R zR zg R and 0 m gngm gm Bo1 out C Vin m C 1in gm g727 One should also consider the case of a source resistance RS in series with the input eJa RE Aquot Single Transistor Ampli ers 6 1300 Page 8 Common Collector Emitter Follower LargeSignal V0 UT 2 VIN 39VBE VOUT VIN l Forward Active Region RE STA06 0 I 0 VIN SmallSignal 0 E Vaul 5 C STA07 139 z 1 and t 1B0 l Vout ngE ou gm Vin 1ngE 139139 r Neglecting r0 again Rm r 1 0RE Rout o n One should also consider the case of a source resistance RS in series with the input x ECE 4430 Analog Integrated Circuits and Systems PE Aquot Single Transistor Ampli ers 6 1300 Page 9 MOS SINGLE TRANSISTOR AMPLIFIERS Common Source Amplifier LargeSignal v V V 1D DS 1 GS T VOUT Cutoff Region VDD VDD Saturation Region X 1 RD y y VOUT Q g Triode VIN Region STAIO 0 0 VT VDD VIN SmallSignal Rm iin iaut low gt Q Vm ngin V RD gt Vaut 5 5 S STAN R R rdSRD Vout quotgmrds39RD d iou 00 2 2 an 2 co m out 7613 RD Vin rds RD 1m RE Aquot k ECE 4430 Analog Integrated Circuits and Systems Single Transistor Ampli ers 6 1300 Page 10 Common Gate Amplifier LargeSignal 1D Cutoff VOUT VDD Region VDD RD Saturation VOUT VINGT Region T 7777 H V VIN 0 T STA12 VDG VIN 0 0 VDD SmallSignal g Vin R39 Im Hm I laut lam S c A D 4quot I n 39 Vin rc39l RD Vaul G L L G STA13 l Vout lout Neglectingr R z R zR zg R and l ds m gm out D Vin m D 11quot k ECE 4430 Analog Integrated Circuits and Systems PE Aquot j Page 11 Single Transistor Ampli ers 6 1300 Example 2 Find the values of R R 110uAV2 VT 07V 1N 004V391 WL 10um1um ID 200uA and RD 20kg Solution First find the model parameters ZKN WID gm L VZllOIOZOO 663118 ngin Using the smallsignal model shown we get Vin iin39gmvinrds l39z39nRD Rm W 172819 Compared to 15119 if we neglect rds Writing a nodal equation at the output gives Vout gmgds 6638 gmvin gdsvin39vout 39 GDVout gt gdSGD 850 Compared to 1326VV if we neglect rds Rout rdsRD 1724kQ Compared to 20k if we neglect rds k ECE 4430 Analog Integrated Circuits and Systems m out and VowVin of the common gate amplifier including rds Assume that K N RE Aquot Single Transistor Ampli ers 6 1300 Page 12 Common Drain Source Follower LargeSignal VOUT VIN 39 VGS VOUT VDD VIN I VO UT iSaturation a Region Rs STA15 U I 0 VIN SmallSignal Rm lHour Ram I Vgs 39 S I gt Vin ltgt Vaul D3 5 D STA16 Neglecung rdS gives Rm Rout RSlKlgm 39 and out m lt 1 1ng Vin 1JrngS x ECE 4430 Analog Integrated Circuits and Systems RE A j Single Transistor Ampli ers 6 1300 Common Emitter with Emitter De eneration AMPLIFIERS WITH EMITTERSOURCE DEGENERATION k ECE 4430 Analog Integrated Circuits and Systems Rin RB B CR6 A Ink QJ r75 jiv ngn 0 Vin E RC vam RE V STAI7 Rm RBrn1 oRE l BORE l Rout r01 RBRErnJ RERBrn z 1Boro M gmr ro oRC IE Vin rnRB N Vnl oRE N RE max gain RinLroRCREH 1l30 J Page 13 RE Aquot Single Transistor Ampli ers 6 1300 Page 14 Common Source with Source De eneration VDD R H513 G DREW RD OUT Li J I OUT gt I39IN Vgs nggs rdsjgt gt gt v 39 RG m S RDgt VOW VIN RS lt RS STA18 Rm Rout rdsu gm gmbsRS RS z rdsngS Vout ngD RD I vm N 1ngS RS max gain x ECE 4430 Analog Integrated Circuits and Systems PE Aquot r Introduction t0 Op Amps 71700 Pasu l 62 INTRODUCTION TO OP AMPS INTRODUCTION Objective The objective of this presentation is l Characterize the operational amplifier 2 Illustrate the analysis of both BJT and MOS op amps 3 Illustrate the design of both BJ T and MOS op amps Outline Introduction and Characterization of Op Amps Compensation of Op Amps General principles Miller Nulling Miller Selfcompensation Feedforward Simple Op Amps Twostage Foldedcascode Design of Op Amps Summary K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r htroduction to Op Amps 71700 Page 2 INTRODUCTION AND CHARACTERIZATION OF OP AMPS Hi hLevel View 0th of an 0 Am Block diagram of a general twostage op amp Compensation Circuitry V1 0 Differential High VOUT Output VOUT Transconductance gt Gain gt Buffer 0 V2 0 D Stage Stage T I T Fig 611 Differential transconductance stage Forms the input and sometimes provides the differentialtosingle ended conversion High gain stage Provides the voltage gain required by the op amp together with the input stage Output buffer Used if the op amp must drive a low resistance Compensation Necessary to keep the op amp stable when resistive negative feedback is applied K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r lntroduction to Op Amps 71700 Page 3 Ideal 09 Am Symbol V1 Vss V0 UT AvV1V2 V2 IT Fig 612 Null port If the differential gain of the op amp is large enough then input terminal pair becomes a null port A null port is a pair of terminals where the voltage is zero and the current is zero le v1 v2 v 0 and 1391 0 and 1392 0 Therefore ideal op amps can be analyzed by assuming the differential input voltage is zero and that no current ows into or out of the differential inputs Kl5 E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r lntroduction t0 Op Amps 71700 General Con uration 0fthe 0 Am as a Volta e Am li er Fig 613 KE E 4430 Analog Integrated Circuits and Systems Page 4 PE Allen 2009 r htroduction to Op Amps 71700 Page 5 Exam 1e 1 Sim li ed Anal sis of an 0 Am Circuit The circuit shown below is an inverting voltage amplifier using an op amp Find the voltage transfer function VoutVin39 R z 139 R l l 2 2 Vm Voul Vlrtual Ground Fig 614 Solution If the differential voltage gain AV is large enough then the negative feedback path through R2 will cause the voltage V and the current 139 1 shown on Fig 614 to both be zero Note that the null port becomes the familiar virtual ground if one of the op amp input terminals is on ground If this is the case then we can write that 1 1 and Vout 12 Since 139 l 0 then 1391 1392 0 giving the desired result as Vout amp v in R1 I K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r htroduction t0 Op Amps 71700 Pasu 6 Linear and Static Characterization of the 0 Am A model for a nonideal op amp that includes some of the linear static nonidealities V1 R ltgt CMRR lcm ltgtIBZ 712 v2 ltgt lt gt G Rout v I V05 12 Cid Ridi 0 v1 3 Ideal Op Amp Ricm 31 Fig 615 where Rid differential input resistance C id differential input capacitance Ricm common mode input resistance VOS inputoffset voltage I BI and 132 differential inputbias currents OS inputoffset current IOS Bl132 CMRR commonmode rejection ratio 2 e n voltagen01se spectral dens1ty meansquare voltsHertz 2 z n currentn01se spectral dens1ty meansquare ampsHertz K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r htroduction t0 Op Amps 71700 Page 7 Linear and D namic Characteristics 0fthe 0 Am Differential and commonmode frequency response V1SV2S Vouts AvsVls 39 V2sl iAcs T Differentialfrequency response A 2 Avo Av0P1P2P3 V s i 1 i 1 i 1 S P1S P2S 173 P1 P2 P3 where p1 p2 p3 are the poles of the differentialfrequency response lAviltDl dB AK Asymptotic 2010g10Av0 t Magnitude w 6dBoct Magnltuue 0dB 18dBoct Fig 616 K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r htroduction to Op Amps 71700 Page 8 Other Characteristics of the 0 Am Power supply rejection ratio PSRR AV V V V 0 PSRR DD Avs a 1n dd AVOUT VaVdd an 0 Input common mode range ICMR ICMR the voltage range over which the input commonmode signal can vary without in uence the differential performance Slew rate SR SR output voltage rate limit of the op amp Settling time TS TS time needed for the output of the op amp to reach a final value to with a predetermined tolerance when excited by a small signal SR is large signal excitation VOUT Final Value T016rance vOUT Final Value VIN J Final Value Lower T Settling 0 TS Fig 617 K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 Categorization of op amps r lntroduction to Op Amps 71700 Classi cation of CMOS 0 Am 5 Page 9 Kl5 E 4430 Analog Integrated Circuits and Systems Conversion Hierarchy VOItage Classic Differential Modi ed Differential I to Current Ampli er Ampli er I I F1rst g Vsotltage Current Differentialtosingle ended Source Sink MOS Diode age to Voltage Load Current Mirror Current Loads Load I I I l V Current VOItage Transconductance Transconductance Sta e to current Grounded Gate Grounded Source I Second Voltage Current Class A Source Stage to Voltage or Sink Load Table 61 PE Allen 2009 r htroduction t0 Op Amps 71700 TwoSta e 0 Am Architecture Simple twostage op amp broken into voltagetOcurrent and currentto Voltage stages VDD I I gtV K156E 4430 Analog Integrated Circuits and Systems V gtI Vaut w c Vaut 939 Vin o Page 10 Vaut o I gtV V gtI PE Allen 2009 r htroduction t0 Op Amps 71700 FoldedCascodeO Am Architecture VDD V MI M3 MlO M11 o 1M2 M8 1 9 Vin V0 0 cw M6 7 VBia H VBias M4 M T V SS 1 I gtV V gtI K156E 4430 Analog Integrated Circuits and Systems Simple foldedcascode op amp broken into voltagetOcurrent and currentto Voltage stages Page 11 VCC VBias Q 1 0 Q 1 0 Q1 Q2 Q8 Q Vin Vaul Vout 39 c quot 0 3 Q6 Q7 VBia VBic s 4 5 VEE Q Q V gtI 1 I gtV OAOIS PE Allen 2009 r htroduction to Op Amps 71700 Page 12 COMPENSATION OF 0P AMPS GENERAL PRINCIPLES Objective Objective of compensation is to achieve stable operation when negative feedback is applied around the op amp Types of Compensation 1 Miller Use of a capacitor feeding back around a highgain inverting stage Miller capacitor only Miller capacitor with an unitygain buffer to block the forward path through the compensation capacitor Can eliminate the RHP zero Miller with a nulling resistor Similar to Miller but with an added series resistance to gain control over the RHP zero 2 Feedforward Bypassing a positive gain amplifier resulting in phase lead Gain can be less than unity 3 Self compensating Load capacitor compensates the op amp K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r htroduction to Op Amps 71700 Page 13 Sin leL00 Ne ative FeedbackS stems Vow Fig 621 As amplifier gain normally the differentialmode voltage gain of the op amp F s transfer function of the external feedback from the output of the op amp back to the input Definitions Openloop gain Ls AsFs Vauts S Closedloop gain Vina 1AsFs Stability Requirements The requirements for stability for a singleloop negative feedback system is P40030 Ff030 ILO39woo lt 1 where 0300 is defined as Ara1406000 10300 ArgLI39600 l 0 Another convenient way to express this requirement is AfgAf030dBFI39030dBl AfgLI39030dBl gt 0 where OJOdB is defined as MOWERmedal ILUCOOdB 1 K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r lntroduction t0 Op Amps 71700 Illustration of the Stabilit Re uirement usin Bode Plots 5 0 3 20dBdecade g E GdB w 40dB decade 5 1805 s E 1350 8 g 900 7 F 450 7 a DMI X 00 0 Frequency rads sec DOdB Fig 622 A measure of stability is given by the phase when A39aFfa 1 This phase is called phase margin Phase margin 45M AfgAI39dBFI39dB ArgLfdB Kl5 E 4430 Analog Integrated Circuits and Systems Page 14 PE Allen 2009 r htroduction to Op Amps 71700 Page 15 Wh Do We Want Good Stabilit Consider the step response of secondorder system which closely models the closedloop gain of the op amp lt D 3 FR Cb 0 oo ll 0 15 Fig 623 5 10 not ont sec A good step response is one that quickly reaches its final value Therefore we see that phase margin should be at least 45 and preferably 60 or larger A good rule of thumb for satisfactory stability is that there should be less than three rings K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r htroduction to Op Amps 71700 Fuse 16 Uncom ensated Fre uenc Res onse 0fTWOSta e0 Am 5 TwoStage Op Amps Small Signal Model D1 D3 C1 C3 D2 D4 C2 C4 D6 D7 C6 C7 I I l I4 I I gt 439 ngVin gt 439 gt 1 g 1V39 R1ltgt C CV17 ltgt VZ R3ltgtC3 V0ul m m lt 1 2 gm4V1 R2lt C2 gm6V2 lt OA03 Note that this model neglects the basecollector and gatedrain capacitances for purposes of simplification K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r htroduction to Op Amps 71700 Page 17 Uncom ensated Fre uenc Res onse 0fTWOSta e0 Am sContinued For the MOS twostage op amp 1 R1 gm rds3llrdsl gm R2 2 ram rds4 and R3 Vdssll r5137 C1 Cgs3Cgs4delde3 C2 Cgs6de2de4 and C3 2 CL de6de7 For the BJT twostage op amp 1 1 R1 llrn3Vn4V03 4 R2 77276 r02H ro4 4 776 and R3 r06 r07 gm3 gm3 C1 C7273C7274CcslCcs3 C2 C7v6Ccs2Ccs4 and C3 2 CL Ccs6Ccs7 Assuming the pole due to C1 is much greater than the poles due to C2 and C3 gives l O O I4 I 39 39 l gmwm R C v2 R3C3 W I glez39n R C V1 Rigiciizx Vow 2 2 gm6V2 I 1 39 gmHVI The locations for the two poles are given by the following equations 1 l p 1 RICI and p 2 RIICII where RI RH is the resistance to ground seen from the output of the first second stage and C 1 CH is the capacitance to ground seen from the output of the first second stage K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r htroduction t0 Op Amps 71700 Page 18 Uncom ensated Fre uenc Res onse ofanO Am 20dB decade o E OdB 10g100 Phase Shift 40dBdecade l 5 o F F E 00 10g10lt0 lpl l lpzl deB Fig 625 If we assume that Fs 1 this is the worst case for stability considerations then the above plot is the same as the loop gain Note that the phase margin is much less than 45 Therefore the op amp must be compensated before using it in a closedloop configuration K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r htroduction to Op Amps 71700 Fuse 19 MILLER COMPENSATION TwoStage 09 Amp VDD Vss The various capacitors are C c accomplishes the Miller compensation CM capacitance associated with the firststage mirror mirror pole C I output capacitance to ground of the firststage C H output capacitance to ground of the secondstage K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r htroduction to Op Amps 71700 Fuse 20 Sim li cation 0fthe Com ensated TwoSta e SmallSi nalFre uenc Res onse Model Use the CMOS op amp to illustrate 1 Assume that gm3 gtgt gds3 gdsl gm3 2 Assume that C gtgt GB M Therefore Cc V1 V2 l c J quot J t glez39n lt llt g V lt lt v0 2 lt C 7lt m2 m C lt gm vz lt rdglllrdg3 M gm3 2 gm4V1 1 rdngrds4 rds Hrds CL T v Cc V2 I A i J quot J1 gt gt V39 lt lt C Vaul m gmlvm ITrdszllrds4ltgtgm6V2 rds llrds7ltgt H T V V Fig 625B Same circuit holds for the BJ T op amp with different component relationships PE Allen 2009 K156E 4430 Analog Integrated Circuits and Systems Ge 0 Vin A v r htroduction to Op Amps 71700 neralTwoSta eFre uenc Res onse Anal sis I A J ltgt quot 2 J ngVin R ltgt ltgtC Vaut CIT I gmHV2 RH 17quot Page 21 V2 Cc where gm 2 gm 2 gm2 R1 rds2llrds4 C1 C1 where Nodal Equations quotngVz39n SCI V2 SCc Vout Solving using Cramer s rule gives 1 1 2 Ingeneral Ds li lils s P1 P2 P1 P2 P1172 and Fig 63 6 gmH gm RH rds6llrds7 CH C2 CL and 0 SCC V2 SCI SCC Vout Vouts gm1gmH 39 SCC Vin G1G11S lG11ltCICHG1CHCCgmHCclS2C1C11CcC1CcCHl A0139 s Ccgm 15 R CICHRHC2CcgmHRJRHCcl52RIRIKCICHJFCcC CcCHH A0 gmlgmHRIRH 2 S S gt D Al if gtgt S 171 171172 le lD1 l l ngI A z p1 RlClCHRIICIICCgmHRJRIICc gmHRJRHCc Cc R1CICHR11CHCCgmHRJRIICcl 39gmHCc gm11 P2 RR C CCCC C CCCC C WhereCHgtCcgtCP I 11 1CH 6 I c H 1CH 6 I c H H K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r lntroduction to Op Amps 71700 Page 22 Summa of Results for Miller Com ensation 0f the TwoSta e 0 Am There are three roots of importance 1 Righthalf plane zero This root is very undesirable because it boosts the loop magnitude while decreasing the phase 2 Dominant lefthalf plane pole the Miller pole gmH gm6 Z 1 CC CC A l quotgds2gds4gds6gds7 p1 gmHRIRHCc gm6Cc This root accomplishes the desired compensation 3 Lefthalf plane output pole A 39ngI A 39gm6 p2 CH CL This pole must be beyond the unitygainbandwidth or the phase margin will not be satisfied Root locus plot of the Miller compensation Closedloop poles Cato jm O enloo oles P Cc8 P V hA 1 39gt 6 P2 117239 17139 171 21 Fig 627A K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r htroduction t0 Op Amps 71700 Page 23 Com ensated O enL00 Fre uenc Res onse 0fthe TwoSta e 0 Am M i Avd0 dB quotquot 39 quotx Uncompensated A p g x 20dBdecade 95 v Aq 390 Compensated E x GB OdB gt 10g100 Phase Shift 40dBdecade n Uncompensated E 180 45quotdeca de E 135 o A V 900 45quotdecade g 450 Compensated 4 Phase lt3 Mar in N0 phase margln sn 1 g 0O v 0glO 3 lpil lPl l PM M Fig 6MB Note that the unitygainbandwidth GB is 1 gm g ml g m2 GBA 039 RR vdlt lPJl gmlgmH I IIgmHRIRHCC Cc Cc Cc K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r htroduction t0 Op Amps 71700 Fuse 24 Conce tuall Where do these roots come from 1 The Miller pole VDD RH Ln IA 1 V r 01 1 R1gm6RHCc M6 T Fig 629 2 The lefthalf plane output pole VDD VDD R R Cc H H Vaut 1 39 39 39 Vaut gl6 M6 m M6 lpll CII I CH gt I CH T T T T Fig 6210 VDD 3 Righthalf plane zero Zeros always arise om multiple paths om RH the input to output g 6 Vaut RII 1 r RH U s G M6 vout L RH lSCC lSCC v RH lSCC v T Fig 62 11 wherevv v K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r htroduction to Op Amps 71700 Page 25 In uence of the Mirror Pole Up to this point we have neglected the in uence of the pole p3 associated with the current mirror of the input stage If p2 2 p3 we have problems in compensation This pole is given approximately as A quotgm3 P3 CM is F l 39D Closedloo oles J Avd0 dB Cc 0 p p h 6dBoctave p3 M x x x x 39 gt G V A p H4 p Z 2 Openloop poles 1 1 Cc 0 GB OdB log10o Phase Shift Ron Off due to p3 7 X1 12dB octave n 00 Cc o 450 45quotdecad 1 39 Cc 5 0 900 b 45quotdecade LC 0 vlt 13 5 Phase 0 073 A Margin 1800 Phase margm 71p TA logloan due to p3 p l pli 3 Excess Phase Fig 62llA due to p3 K156E 4430 Analog Integrated Circuits and Systems PE Allen 2009 r lntroduction t0 Op Amps 71700 Page 26 Summary of the Conditions for Stability of the TwoStage 09 Amp gAssuming 232GB Unitygainbandwith is given as 4 gmj 4 49quot GB Av0 LD1 nggmHRIRH gmHRIRHCCJ Cc gm1gm2R1R2 gmleRZCCJ Cc The requirement for 45 phase margin is a a a i180 Ar A i180 tan391 tan391 tan391 45 g F Lyn anl Let 60 GB and assume that z 2 10GB therefore we get GB GB GB 180o tan391 tan391 tan1 450 P1 LD2 Z 135 ztan391Av0 tan1 tan10l 90 tan1 57 393 tan 1 0818gt p8122GB 39 LD2 LD2 39 2 39 The requirement for 60 phase margin m a 22GB ifz a 10GB If 60 phase margin is required then the following relationships apply gm6 10gml gm6 22gml 76gt gt gm6gt10gm1 and C 2gtTc gt Ccgt022C2 Kl5 E 4430 Analog Integrated Circuits and Systems PE Allen 2009

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