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by: Alayna Veum
Alayna Veum

GPA 3.81

Sung Lim

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Sung Lim
Class Notes
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This 0 page Class Notes was uploaded by Alayna Veum on Monday November 2, 2015. The Class Notes belongs to CS 8803 at Georgia Institute of Technology - Main Campus taught by Sung Lim in Fall. Since its upload, it has received 7 views. For similar materials see /class/234010/cs-8803-georgia-institute-of-technology-main-campus in ComputerScienence at Georgia Institute of Technology - Main Campus.

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Date Created: 11/02/15
C88803 Advanced Digital Design for Embedded Hardware SWITC H D ESIGN SWITCH NETWORKS C HAPTE R quot6 SWITC H D ESIGN CMOS CMOS SWITCHES INPUT SELECTOR SWITCHES IN SERIES SWITCHES IN PARALLEL The idea is to use the series and parallel switch configurations to route signals in a desired fashion Unfortunately it is difficult to implement an ideal switch as given Complementary Metal Oxide Semiconductor CMOS devices give us some interesting components Lecture 1 CMOS Transistors and Layout IDEAL SWITCH nMOS transistor pMOS transistor INPUT DRAIN SOURCE Instructor Sung Kyu Lim limskecegatechedu SWITCH GATE GATE Website 39 an gamh 39 39 39 39 quotM OUTPUT SOURCE DRAIN J RM Darisereauvio SWITCH DESIGN SWITCH NETWORKS swTCH DESIGN SWITCH NETWORKS CHAPTER quot7 39 CMDS SWITCHES CHAPTER quot398 39c39 nsoS SWITCHES SWITCH DESIGN TRANSFER CHARACTERISTICS SWITCH DESIGN TRANSMISSION GATE 1 TRANSFER CHAR r N S quotMos S SWITCH nMOS when CLOSED IDEAL SWITCH INPUT oo OUTPUT S 3 0 OPEN Transmits logic level 0 well JL 1 CLOSED 39 39 Transmits logic level 1 poorly CMOS TRANSMISSION GATE SWITCH INPUT OUTPUT 7 pMoS S SWITCH t pMOS when CLOSED 3 o CLOSED Transmits logic level 1 well S quotMos pMos OUTPUT 1 OPEN Transmits logic level 0 poorly 0 OFF OFF Z INPUT OUTPUT 1 ON ON INPUT S J J RM Dansereau v I I RM Dansereau v I I SWITCH D ESIGN C HAPTE R quot9 SWITCH D ESIGN CMDS C SWITCHES TRANSMISSION GATE 2 39TRANSFER CHAR TRANSMISSIDN GATE SWITCH DESIGN CHAPTER quot10 SWITC H D ESIGN CMDS SWITCH NETWORKS was SWITCHES HIGH HVIPEDANCE Z 1 39TRANSFER CHAR TRANSMISSIDN GATE LOGIC0 AT INPUT SPLIT OF CURRENT ACROSS A TRANSMISSION GATE FOR LOGIC0 AND LOGIC1 INPUT LOGIC1 AT INPUT Logic0 Logic1 With switches we can considerthree states for an output High Impedance Z S 0 S 0 Path exists for Logic0 and Logic1 when the switch is CLOSED s 011 o u OUTPUT 01 0 o 1 1 High impedance is a state where the switch is OPEN 3 31 31 011 039o OUTPUTz J RM Dansereauwl RM Dansereauwl smTAggEDrfIf N SWITCH N ETWORKS 39286 smTAggEDrfgjgN SWITCH N ETWORKS 39286 SWITCH DESIGN Z HIGH IMPEDANCE Z SWITCH DESIGN HIGH IMPEDANCE Z r f Another way of thinking of switches is as follows Path exists for Logic0 and Logic1 when the switch is CLOSED meaning that the impedanceresistance is small enough to allow amply flow of current 1 CLOSED J SOURCEJ L mm Igt High impedance is a state where the switch is OPEN meaning that the impedanceresistance is very large allowing nearly no current flow 0 OPEN SOURCE II II DRAIN ltlt 10 K9 SOURCE 1W DRAIN gtgt100MQ lgt SOURCE JNr DRAIN Tag I I I AB AB I I 02 o1gt 10 1zI I I d gt o xcu This network inverts the binary input value RM Dansexeau v t u RM Dansexeau v t u SWITCH NETWORKS SWITCH DESIGN CMDS SWITCH DESIGN CHAPTERILB SWITCH NETWORKS mml gmgz CHAPTERHM SWITCH NETWORKS ml ERITEEDANCEZ SWITCH DESIGN INVERTER SWITCH DESIGN NAND NETWORK C A B VDD C AB VDD A I I TFGEISBOWNRULTTUPI EPULL39DOWN PULL39UP i I I A cABC ABC ABC B ABC ABC ABC 002 001 001 Cooz oo1oo1 o1z o11 gto11 3 B 1oz1o1 101 11011Z110 1 1 o 1 1 z 1 1 o L J J J RM Dansexeauw I 0 RM Dansexeauw I D SWITCH DESIGN SWITCH NETWORKS swTCH DESIGN SWITCH NETWORKS CHAPTERM SWITCH NETWORKS m w CHAPTERM SWITCH NETWORKS gamma SWITCH DESIGN NOR NETWORK SWITCH DESIGN AND NETWORK K f 1 NOR INVERTER c AB r I I I I l 39 c I I I I I I I I I I J J RM Dansexeau v I D RM Dansexeau v I D SWITCH DESIGN CHAPTER quot17 SWITCH NETWORKS SWITCH NETWORKS R SWITCH NETWORKS SWITCH DESIGN SWITCH NETWORKS CHAPTERII18 39 SWITCH DESIGN XOR NETWORK 32323quot SWITCH DESIGN XNOR NETWORK gtIIIIINE IVWDRK VDD VDD A44 rCl CABAB A44 VDD CABAB C ECI 54 3 4 1 C c o 0 AI A 1 BI BI Can th is be implemented without the extra T inverter at the output Answer Yes J 2 RM Dansexeau v I D RM Dansexeau v I D SWITCH D ESIGN C HAPTE R quot20 SWITCH D ESIGN SWITCH NETWORKS XNDR NETWORK FUNCTION IMPLEMENTATION FULLUFIFULLDDWN SWITCH NETWORKS XOR NETWORK SWITCH DESIGN CHAPTER quot21 SWITC H D ESIGN SWITCH N ETWORKS EXAMPLE PULLUP SWITCH NETWORKS XNOR NETWORK FULLUFIFULLDOW FUNC IMPLEMENTATION f Most Boolean functions can be easily implemented using switches The basic rules are as follows Pullup section of switch network Use complements for all literals in expression Use only pMOS devices Form series network for an AND operation Form parallel network for an OR operation Pulldown section of switch network Use complements for all literals in expression Use only nMOS devices Form parallel network for an AND operation Form series network for an OR operation RM Dansexeau v I D f To implement the Boolean function given below the following pullup network could be designed RM Dansexeau v I D SWITC H D ESIG N CHAPTER quot22 SWITC H D ESIG N SWITCH NETWORKS EXAMPLE PULLDOWN 39SWITCH NETWORKS PULLUPIPULLDOWN FUNC IMPLEMENTATION EXAMPLE PULLUP To complete the switch design the pulldown section forthe Boolean function must also be designed Notice how AND and OR become OR and AND circuits respectively RM Danseieaii v 1 u SWITCH NETWORKS COMPLETED EXAMPLE SWITCH DESIG N C HAPTER II23 SWITCH DESIG N Putting the pullup and pulldown pieces together gives the following CMOS switch implementation of the Boolean function PULLUP PULLDOWN R M Danseieaii v 1 o F EAD A 6 39SWITCH NETWORKS FUNC IMPLEMENTATION EXAMPLE PULLUP EXAMPLE PULLDOWN Fabrication Materials DIfferenpres cit tabncaticn matenais insulatucs J cmiuetm J Semicunductucs J High electrical resistance Used furlsulauun er devices e g sitich meme Luw e1ectnca1 resistance Used fur cunducung e g Gutd at aluminum Eiectncai cesistimty at mum temp Used fur ruimatiun er devices e g siiiccn MOS Subthreshold Region Subthreshold Region ds 2 O Vgs s V Gate p type substrate Subthreshold current is due to reverse bias leakage current of diode between diffusion and substrate ECE 3060 Lecture 2 3 MOS Linear Region MOS Linear Region The inversion layer channel is symmetric until Transverse electric field distorts the channel Gate V2 V2 ds d3 Ids BVgs VIN613 T OSVdSSVgS Vt Ids BVgs VIN 13 7 031613 Vgs Vt ECE3060 Lecturez 4 ECE 3060 Lecturez 5 MOS Saturation Region Photolithographic Process Channel is pinched off when Vgs VI 3 Vds Gate rllllllllll 15k gw vgz 0 s V5167 V Va Current is swept through depletion region electric field after leaving channel ECE3060 Lecture 2 6 Layout Example CMOS Inverter Layout Example CMOS Inverter Set Pitch place well and powerground busses ECE 3060 JCIIIIE A 3 Add Transistors active select and poly ECE 3060 JCIIIIE A A Layout Example CMOS Inverter Make Connections poly metal and cuts ECE 3060 11611175 A 5 Layout Example CMOS Inverter Add Substrate and Well Contacts ECE 3060 JCIIIIE A 6 Layout Example CMOS Inverter Design Rules Minimum Separation A lntralayer all layers A lnterlayer active to polywelllselect IE From Transistor Minimum Width all layers B C Minimum Overlap C Past Transistor poly active Around Contact Cut all contacted layers Around Active well select Exact Size contact cuts D D lt Add External erlng and ReSIze ECE 3060 Lecture4 7 ECE 3060 Lecture3 I3 WidthSpacing Design Rules A CMOS Inverter ECE 3060 Lecture 3 15 A CMOS NAND Gate I I I I A CMOS NOR Gate ECE 3060 Lecture 5 2 ECE 3060 Lecture 5 3 Complex Gates The gate function does not need to be primitive or symmetric Any fx may be implemented Algorithm put in form with only AND OR and literals use DeMorgans compute f using generalized DeMorgan s Theorem construct complimentary networks using transistors in series for AND and transistors in parallel for OR Note There are many correct networks due to commu tivity 9 ECE 3060 Lecture 5 5 Euler Paths Vdd r4 lire 34 Out c4 A B Mapping CMOS Circuits to Graphs Circuit Nodes Map to Graph Vertices Transistors Map to Graph Edges Complementary Circuit Networks Map to Dual Graphs ECE 3060 Lecture 5 6 Euler Paths om order B A C Finding Euler Paths Find All Euler Paths Find an n and a p Euler Path with Identical Labeling If No Identical Labeling Break the Path Minimally ECE 3060 Lecture 5 7 Describing an Euler Path While an ordered list of edges only suffice to denote an Euler path a complete description is an ordered list of nodes and edges For example Path Vdd A l1 B Out C Vdd This form is useful for layout purposes ECE 3060 Lecture 5 8 Euler Path to Layout Map Euler Paths to CMOS Layout Place Busses Place Transistors Complete Wiring ECE 3060 Lecture 5 9 Standard Cell Layout In general when laying out standard cells or other custom gate designs there may not exist a Euler Path 29 Standard cells for a particular process eg 35u HP CMOS need not follow lamda spacing rules There are companies whose sole purpose is the cre ation and maintenance of standard cell libraries Custom layout is very timeintensive and laborious for large chips therefore custom layout is typically done only for critical paths Read Chapters 3 4 and 7 of Wolf E05 3060 Lemma 5 10 Complex Gate vs Network of Gates O Complex gate implementation of F ab C d Complex Gate vs Network of Gates O Network ofNANDZINV implementation DOL pdllf ii F F nrdllf qnguni Basic Cells Basic Cells cont 1bit logic unit Bit Slice Basic Blocks 4 registers adder logic unit bitslice will be stacked 16 times 1 4x16bit registers 16bit adder 16bit logic unit Matrix Solver 20K Matrix Solver 20K Cadence Encounter placement 1 sec routing 12 sec 7 Area 72x72um 45nm library used 6 metal layers Matrix Solver 20K 32bit Processor 27M GDSII shots manufacturingready Placement took 739 sec routing took 4740 sec 7 Specify all intracell details 7 Area 1000x1000um used 10 metal layers


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