Systems and Networks
Systems and Networks CS 2200
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This 0 page Class Notes was uploaded by Alayna Veum on Monday November 2, 2015. The Class Notes belongs to CS 2200 at Georgia Institute of Technology - Main Campus taught by Ramachandran in Fall. Since its upload, it has received 8 views. For similar materials see /class/234062/cs-2200-georgia-institute-of-technology-main-campus in ComputerScienence at Georgia Institute of Technology - Main Campus.
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Date Created: 11/02/15
Datapath and Control Ch 5 Path from source to object source le c le compiler s le assembler 0 le linker stitch together individual modules object le aout le header text data relocation info symbol table debugging info loader from disk to memory memory layout LC99 Rtype add nand 1614 1311 108 73 20 I 0pc0de reg A reg B unused reg D Itype 1W SW beq 1614 1311 108 73 20 I 0pc0de reg A reg B 0ffset eld J type 1 alr 1614 1311 108 73 20 I 0pc0de reg A reg B unused Otype halt noop 1614 1311 108 16 20 lopcode unnuavu CPU organization Datapath and control how to decide the datapath What resources do we need in the datapath A simple datapath LC99 PC IR register le MUXes at address inputs to register le Why optional MUXes at ALU inputs Why ALU optional buffers at input and output of ALU optional buffers at outputs of register le CPU registers IR PC Where does each get its data input how do we use each of its contents control signals needed to actuate each 0 GPR or register le external interface internal logic data input load vs arithmetic instructions control signals needed Why do we need muxes at ALU input ALU arithmetic instructions Where are the operands in LC99 address calculations What instructions need this Where are the operands PC management What is involved in this Why buffer at output of register le Why buffer at output of ALU Busbased Datapath data bus address bus units electrically connected to the bus What does that mean how to ensure only one driving the bus at a time how to make better use of the address bus use it for both data and address eliminates need for buffering register file output introduces the need for latching ALU output Control Design What is involved in instruction execution fetch decode execute fetch operands store operands designing the control unit given instruction set and DP write owcharts this is no different from writing C code adopt a control regime hardwired FSM microprogrammed control gtgt stored program Hardwired Control What states do we need in the FSM Actions during instruction fetch ifetchl want to init fetch and increment PC PC to address bus how to effect this Read memory how to effect this increment PC how to effect this code snippet to simulate the above machinecontrolPCdriveAddr ON machinecontrolRdMem ON machinecontrol1atchALU ON machinecontrolALUop ADDop machinecontrolALUC ALUCone Actions during instruction fetch ifetch2 latch memory data instruction into IR how code snippet to simulate this machinecontrolEnableMem ON machinecontrollatchIR ON Actions during instruction fetch ifetch3 write the incremented value into PC how Why not in ifetch2 code snippet to simulate this machinecontrolALUdriveData ON machinecontrolPCWr ON Actions during instruction fetch ifetch3 contd Decode instruction how Code snippet to simulate this opcode machineinstReg gtgt 14 amp OX7 regA machineinstReg gtgt 11 amp OX7 regB machineinstReg gtgt 8 amp OX7 regD machineinstReg amp OX7 offsetValue machineinstReg amp OXff Now choose neXt state As you construct the states below try to share states among instructions when possible if opcode ADD What next 4 different FSM sequences depending on instruction type Rtype Itype J type Otype Rtype FSM select regA and regB from register le how ALU op ADD or NAND store result in ALUresult how write ALUOut into register le at regD how can all of the above be done in one cycle Where do we go from here Itype FSM loadstore address arithmetic regA plus offset result into ALUresult ALUresult to address bus load read memory onto data bus latch into regB store drive regB onto the data bus back to F1 ltype FSM BEQ subtract regA and regB if equal latch 0 into cond register if all ALU bits are 0 latch 1 into cond register if any ALU bit is a 1 if cond register is 0 then then PC0ffset t0 ALUresult Where did the 1 g0 ALUresult to PC else nothing back to F1 Jtype FSM JALR PC to register regB speci ed in IR contents of register regA in IR to PC back to F1