New User Special Price Expires in

Let's log you in.

Sign in with Facebook


Don't have a StudySoup account? Create one here!


Create a StudySoup account

Be part of our community, it's free to join!

Sign up with Facebook


Create your account
By creating an account you agree to StudySoup's terms and conditions and privacy policy

Already have a StudySoup account? Login here

Spec Prob

by: Alayna Veum
Alayna Veum

GPA 3.81


Almost Ready


These notes were just uploaded, and will be ready to view shortly.

Purchase these notes here, or revisit this page.

Either way, we'll remind you when they're ready :)

Preview These Notes for FREE

Get a free preview of these Notes, just enter your email below.

Unlock Preview
Unlock Preview

Preview these materials now for free

Why put in your email? Get access to more of this material and other relevant free materials for your school

View Preview

About this Document

Class Notes
25 ?




Popular in Course

Popular in ComputerScienence

This 0 page Class Notes was uploaded by Alayna Veum on Monday November 2, 2015. The Class Notes belongs to CS 4903 at Georgia Institute of Technology - Main Campus taught by Staff in Fall. Since its upload, it has received 7 views. For similar materials see /class/234096/cs-4903-georgia-institute-of-technology-main-campus in ComputerScienence at Georgia Institute of Technology - Main Campus.

Similar to CS 4903 at

Popular in ComputerScienence


Reviews for Spec Prob


Report this Material


What is Karma?


Karma is the currency of StudySoup.

You can buy or earn more Karma at anytime and redeem it for class notes, study guides, flashcards, and more!

Date Created: 11/02/15
Appendix C The Microarchitecture 0f the LC3b Basic Machine This appendix illustrates one example of a microarchitecture that implements the base machine of the LC3b ISA We have not included exception handling interrupt pro cessing or virtual memory We have used a very straightforward nonpipelinedversion Interrupts exceptions virtual memory pipelining they will all come later 7 before we part company in December C 1 Overview Figure C 1 shows the two main components of an ISA the data path which contains all the components that actually process the instructions and the control which contains all the components that generate the set of control signals that are needed to control the processing at each instant of time We say at each instant of time but we really mean during each clock cycle That is time is divided into clock cycles The cycle time of a microprocessor is the duration of a clock cycle A common cycle time for a microprocessor today is 033 nanoseconds which corresponds to 3 billion clock cycles each second We say that such a microprocessor is operating at a frequency of 3 Gigahertz At each instant of tim eior rather during each clock cycleithe 35 control signals as shown in Figure C 1 control both the processing in the data path and the generation of the control signals for the next clock cycle Processing in the data path is controlled by 26 bits and the generation of the control signals for the next clock cycle is controlled by nine bits Note that the hardware that determines which control signals are needed each clock cycle does not operate in a vacuum On the contrary the control signals needed in the next clock cycle depend on all of the following 1 What is going on in the current clock cycle 2 The LC 3b instruction that is being executed l ZAPPENDIX C THE MICROARCHITEC TURE OF THE LC 3B BASIC lVIACHlNE Memory 10 3 Data D ata Inst 1 6 16 Addr B EN i 6 Data Path 23 IR1511 Control J COND 1RD Figure C l Microarchitecture of the LC3b major components 3 If that LC3b instruction is a BK Whether the conditions for the branch have been met ie the state of the relevant condition codes 4 If a memory operation is in progress Whether it is completing during this cycle Figure Cl identi es the speci c information in our implementation of the LC3b that corresponds to these ve items They are respectively J50 COND1O and IRDi9 bits of control signals provided by the current clock cycle 19 inst1512 which identi es the opcode and instl l l l which differentiates J SR from JSRR ie the addressing mode for the target of the subroutine call L BEN to indicate Whether or not a BR should be taken C2 THE S TATE lVIACHINE 3 4 R to indicate the end of a memory operation C2 The State Machine The behavior of the LC 3b microarchitecture during a given clock cycle is completely determined by the 35 control signals combined with seven bits of additional inform a tion inst1511 BEN and R as shown in Figure C 1 We have said that during each clock cycle 26 of these control signals determine the processing of information in the data path and the other 9 control signals combine with the seven bits of additional in formation to determine which set of control signals will be required in the next clock cycle We say that these 35 control signals specify the slate of the control structure of the LC 3b microarchitecture We can completely describe the behavior of the LC 3b mi croarchitecture by means of a directed graph that consists of nodes one corresponding to each state and arcs showing the ow from each state to the ones it goes to next We call such a graph a state machine Figure C2 is the state machine for our implementation of the LC3b The state machine describes what happens during each clock cycle in which the computer is running Each state is active for exactly one clock cycle before control passes to the next state The state machine shows the stepbystep clock cycle by clock cycle process that each instruction goes through from the start of its FETCH phase to the end of that instruction Each node in the state machine corresponds to the activity that the processor will carry out during a single clock cycle The actual processing that is performed in the data path is contained inside the node The stepbystep ow is conveyed by the arcs that take the processor from each state to the next For example recall that the FETCH phase of every instruction cycle starts with a memory access to read the instruction at the address speci ed by the PC Note that in the state numbered 18 the MAR is loaded with the address contained in PC the PC is incremented by two in preparation for the FETCH of the next LC 3b instruction and the ow passes to the state numbered 33 The PC is incremented by two since each 16 bit instruction is stored in two consecutive byteaddressable memory locations Before we get into what happens during the clock cycle when the processor is in the state numbered 33 we should explain the numbering system 7 that is why 18 and 33 Recall from your knowledge of nite state machines each state must be uniquely speci ed and that this unique speci cation is accomplished by means of the state variables Our state machine that implements the base LC 3b microarchitecture requires 31 distinct states to describe the entire behavior of the LC3b base machine We will come into contact with all of them as we go through this Appendix Since k logical variables can uniquely identify 2 items ve state variables are suf cient to uniquely specify 31 states We have chosen six state variables to provide you with enough additional states to handle interrupts exceptions and virtual memory later in the semester The number next to each node in Figure C2 is the decimal equivalent of the values 0 or 1 of the six state variables for the corresponding state Thus the state numbered 18 has state variable values 010010 Now then back to what happens after the clock cycle in which the activity of 4APPENDIX C THE MICROARCHITEC TURE OF THE LC 3B BASIC lVIACHlNE state 18 has nished Again if no external device is requesting an interrupt the ow passes to state 33 In state 33 since the MAR contains the address of the instruction to be processed this instruction is read from memory and loaded into the MDR Since this memory access can take multiple cycles this state continues to execute until a ready signal from the memory R is asserted indicating that the memory access has completed Thus the MDR contains the valid contents of the memory location speci ed by MAR The state machine then moves on to state 35 Where the instruction is loaded into the instruction register IR completing the fetch phase of the instruction cycle Note that the arrow from the last state of each instruction cycle ie the state that completes the processing of that LC3b instruction takes us to state 18 to begin the instruction cycle of the next LC3b instruction C N THE S TATE NIACHINE 5 mu BENltIR11 ampN 1R10 amp z 1R9 amp P AD IR1512 T011 mm T010 0 1 XOR DRlt SR10P2 IMP TRAP 15R BEN 0 sm To 18 5 1 22 DRlt SR1 ampOP2 lt PC PCLSHFo 1 9 1 T 18 DRltSR1 XOR OPZquot set cc T018 15 ARlt7LSHIFZEX39IIR7 01 LDE LDW STW T018 20 R7 3 PClt BaseR Zl R7lt7PC PClt7PCLSHFof 11 T018 T018 T018 6 7 3 T018 MARltiB0ff6 T018 24 NorrEs B0ff6 Base SEXT0ffsew R R 1 DRlt7MDR 7 set CC MMARlt MDR R R T018 T018 T018 opz may be SR2 or SEXT1mm5 15 8 0m 0depend1ng on MAR0 DRltSEXTBYTE DATA set CC Figure C2 A state machine for the LC3b 6APPENDIX C THE MICROARCHITEC TURE OF THE LC 3B BASIC lVIACHlNE C3 The Data Path The data path consists of all components that actually process the information during a cycleithe functional units e g the ALU that operate on the information the registers that store information at the end of one cycle so it will be available for further use in subsequent cycles and the buses and wires that carry information from one point to another in the data path Figure C3 illustrates the data path of our microarchitecture for the LC3b Note the control signals that are associated with each component in the data path For example ALUK consisting of two control signals is associated with the ALU These control signals determine how the component will be used each cycle Table Cl lists the set of control signals that control the elements of the data path and the set of values that each control signal can have Actually for readability we list a symbolic name for each value rather than the binary value For example since ALUK consists of two bits it can have one of four values Which value it has during any particular clock cycle depends on whether the ALU is required to ADD AND XOR or simply pass one of its inputs to the output during that clock cycle PCM39UX also consists of two control signals and speci es which of the three inputs to the MUX PC2 the output of the adder or whatever has been gated to the bus is required during a given clock cycle LDPC is a singlebit control signal and is a 0 NO or a 1 YES depending on whether or not the PC is to be loaded during the given clock cycle During each clock cycle corresponding to the current state in the state machine the 26 bits of control direct the processing of all components in the data path that are required during that clock cycle The processing that takes place in the data path during that clock cycle as we have said is speci ed inside the node representing that state CA The Control Structure As described above the state machine determines which control signals are needed to process information in the data path during each clock cycle The state machine also determines which control signals are needed to direct the ow of control from each state to its successor state Figure C4 shows a block diagram of the control structure of our implementation of the LC3b Many implementations are possible and the design considerations that must be studied to determine which of many possible implementations should be used is the subject ofmuch of this course We have chosen here at the outset a very straightforward microprogrammed im plem entation The current state of the control structure is represented by the 26 bits that control the processing in the data path and the 9 bits that help determine which state comes next These 35 bits are collectively known as a microinstruction Each microin struction ie each state of the control structure is stored in one 35bit location in a special memory called the control store Since there are 31 states in the state machine and since each state corresponds to one microinstruction stored in the control store the control store for our microprogrammed implementation requires ve bits to specify the address of each microinstruction However as we have already said we elected to C 4 THE CONTROL STRUCTURE 7 ADDR CTL MEMORY L0Gquot Figure C3 The LC3b data path provide you with the additional exibility of more states so we have selected a control store consisting of 26 locations SAPPENDIX C THE MICROARCHITEC TURE OF THE LC 3B BASIC lVIACHlNE Signal Name Signal Values LD MAR1 NO LOAD LD MDRl NO LOAD D 1R1 NO LOAD LD BEN1 NO LOAD LD REG1 NO LOAD LD CCl NO LOAD LD PCl NO LOAD GatePCl NO YES GateMDRi NO YES GateALUi NO YES GateMARMUxi NO YES GateSHEi NO YES PCMUXZ Pc2 se1ect c2 BUS se1ect value from bus ADDER se1ect output of address adder DRMUxi 11 9 destinationIR119 R7 destination R7 SRiMUxi 11 9 source 1R119 a 5 source IR86 ADDRiMUxi PC EaseR ADDR2MUx2 ZERO se1ect the value zero offset se1ect SEXT1R50 PCoffset9 se1ect SEXTR80 PCoffsetll se1ectSEXT1R100 MARMUxi 7 0 se1ect LSHEZEXT1R701 ADDER se1ect output of address adder ALUKz ADD AND XOR PASSA MIO EN1 NO YES R Wl RD WR DATA SIZE1 BYTE WORD NO YES Table C 1 Data path control signals Table C2 lists the function of the 9 bits of control information that help determine which state comes next Figure C5 shows the logic of the microsequencer The purpose of the microsequencer is to determine the address in the control store that corresponds to the next state that is the location Where the 35 bits of control information for the next state are stored Note that state 32 of the state machine Figure C2 has 16 next states depending Signal Name Signal Values J6 CONDZ CONDO Unconditional COND1 Memory eady COND2 Br CONDg Addressing Mode IRDl NOYES Table C2 Mcrosequencer control signals C 4 THE CONTROL STRUCTURE 9 IR15 1 1 BEN Microsequencer 6 Control Store 26x 35 J COND 1RD Figure C4 The control structure of a microprogrammedimplementation overall block diagram on the LC3b instruction being executed during the current instruction cycle This state carries out the DECODE phase of the instruction cycle If the 1RD control signal in the microinstruction corresponding to state 32 is 1 the output MUX of the microsequencer Figure C5 will take its source from the six bits formed by 00 concatenated with the four opcode bits 1R1512 Since IR1512 speci es the opcode of the current LC 3b instruction being processed the next address of the control store Will be one of 16 addresses corresponding to the 14 opcodes plus the two unused opcodes IR1512 1010 and 1011 That is each of the 16 next states is the rst state to be carried out after the instruction has been decoded in state 32 For example if the instruction being processed is ADD the address of the next state is state 1 Whose microinstruction is stored at location 000001 Recall that 1R1512 for ADD is 0001 If somehow the instruction inadvertently contained IR1512 1010 or 1011 the l OAPPENDIX C THE MICROARCHITEC TURE OF THE LC 3B BASIC lVIACHINE CONDl CONDO l BEN R lRl 1 Branch Ready Addr Mode 15 H4 H3 H2 J1 H0 00IR1512 i lt17 1RD Address ofNeXt State Figure CS The microsequencer of the LC3b base machine unused opcodes the microarchitecture would execute a sequence of microinstructions starting at state 10 or state ll depending on which illegal opcode was being decoded In both cases the sequence of microinstructions would respond to the fact that an instruction with an illegal opcode had been fetched Several signals necessary to control the data path and the microsequencer are not among those listed in Tables Cl and C2 They are DR SRl BEN and R Figure C6 shows the additional logic needed to generate DR SRl and BEN The remaining signal R is a signal generated by the memory in order to allow the C 4 THE CONTROL STRUCTURE 11 IR119 IR119 DR SR1 111 IR86 DRMUX SRlMUX a b IR119 N Logic S Z p a c Figure C6 Additional logic required to provide control signals LC3b to operate correctly with a memory that takes multiple clock cycles to read or store a value Suppose it takes memory ve cycles to read a value That is once MAR contains the address to be read and the microinstruction asserts READ it will take ve cycles before the contents of the speci ed location in memory are available to be loaded into MDR Note that the microinstruction asserts READ by means of three control signals MIQENYES RWRD and DATA SIZEWORD see Figure C3 Recall our discussion in Section C2 of the function of state 33 which accesses an instruction from memory during the fetch phase of each instruction cycle For the LC3b to operate correctly state 33 must execute ve times before moving on to state 35 That is until MDR contains valid data from the memory location speci ed by the contents of MAR we want state 33 to continue to reexecute After ve clock cycles the memory has completed the read resulting in valid data in MDR so the processor can move on to state 35 What if the microarchitecture did not wait for the memory to complete the read operation before moving on to state 35 Since the contents of MDR would still be garbage the microarchitecture would put garbage into 1R in state 35 The ready signal R enables the memory read to execute correctly Since the mem ory knows it needs ve clock cycles to complete the read it asserts a ready signal R throughout the fth clock cycle Figure C2 shows that the next state is 33 ie 100001 if the memory read will not complete in the current clock cycle and state 35 ie 100011 if it will As we have seen it is the job of the microsequencer Figure C5 to produce the next state address 1 ZAPPENDIX C THE MICROARCHITEC TURE OF THE LC 3B BASIC lVIACHINE The 9 microsequencer control bits for state 33 are as follows IRDO NO CONDOl Memory Ready JlOOOOl With these control signals what next state address is generated by the microsequencer For each of the rst four executions of state 33 since R 0 the next state address is 100001 This causes state 33 to be executed again in the next clock cycle In the fth clock cycle since R 1 the next state address is 100011 and the LC3b moves on to state 35 Note that in order for the ready signal R from memory to be part of the next state address COND had to be set to 01 which allowed R to pass through its threeinput AND gate C5 Alignment correction for Byte Loads and Stores Everything in the discussion thus far has involved word accesses from memory Be cause the LC3b is byteaddressable and loads and stores can access either byte or word data additional support is required from both the data path and the microse quencer The only memory read that is accessing a byte of data is state 29 in the state machine The only memory store that is writing a byte of data is state 17 in the state machine Support is provided for both in the data path as follows C51 Byte loads in state 29 In state 29 16 bits are read from memory as usual and loaded into MDR 1n state 31 the data read is loaded into the destination register as speci ed by bits1 1 9 of the LDB instruction as follows A 1IUX selects whether MDR158 or MDR70 is the correct byte to be loaded based on the low bit of the address MAROD This byte is signextended to 16 bits A second MUX selects either this signextended byte of data or the word in MDR based on the control signal DATA SIZE Since the instruction being processed is LDB state 31 has the control signal DATA SIZEBYTE The output of this MUX the signextended byte of data is gated onto the bus and loaded into DR C52 Byte stores in state 17 In state 24 just prior to state 17 which does the actual byte store the data to be stored is loaded into MDR as follows If MAR01 SR70 must be loaded into the odd address speci ed by MAR A MUX selects either SR150 or SR70 SR70 based on MAR0 In that way if the instruction being processed is STW MARO must be 0 and the store proceeds ne If the instruction being processed is STB SR70 is in MDR70 if MAR00 and in MDR158 if MAR01 That is the data in MDR is properly aligned ready to be stored 1n state 17 the actual store takes place as follows Two write enable signals W131 and WEO control the stores to the odd and even addresses of a memory word WEl controls bits 158 and WEO controls bits 70 of the same word ofmemory Which C 6 MEMORYNIAPPED IO 1 3 write enable signals are asserted depends on RW DATA SIZE and MAR0 Write enable signals are only asserted if the machine is doing a store Ergo RW must be WR If DATA SIZE is BYTE MAR0 determines whether WEl or WEO is asserted Recall that if DATA SIZE is BYTE MDR was previously loaded with SR70 SR70 If MAR00 WEO is asserted and MDR70 ie SR70 is written to memory If MAR01 WEl is asserted and MDR1 5 8 i e SR70 is written to memory Thus in both cases the relevant byte is stored to the correct location in memory If DATA SIZE is WORD and MAR00 then WEl and WEO are both asserted and the word in MDR is written to memory If DATA SIZE is WORD and MAR01 an illegal operand address exception would have been taken earlier in the microsequence Once the write completes Memory Ready is asserted and control passes from state 17 to state 19 State 19 is an exact duplicate of state 18 State 18 and 19 then begin the processing of the next LC3b instruction C6 Memorymapped IO As you know from Chapter 8 the LC3b ISA performs input and output via mem ory mapped 10 that is with the same data movement instructions that it uses to read from and write to memory The LC3b does this by assigning an address to each device register Input is accomplished by a load instruction whose effective address is the address of an input device register Output is accomplished by a store instruction whose effective address is the address of an output device register For example in state 25 of Figure C2 if the address in MAR is xFE02 MDR is supplied by the KBDR and the data input will be the last keyboard character typed On the other hand if the address in MAR is a legitimate memory address MDR is supplied by the memory The state machine of Figure C2 does not have to be altered to accommodate mem orym apped IO However something has to determine when memory should be accessed and when IO device registers should be accessed This is the job of the address control logic shown in Figure C3 The control signals that are generated are based on 1 the contents of MAR 2 whether or not memory or 10 is accessed this cycle MIOENNO YES and 3 whether a load or store is requested RWRead Write One of your tasks in problem set 2 will be to generate the truth table for this block Incidentially the device registers are all 16 bit registers and have even addresses They are accessed by LDW and STW instructions This eliminates all alignment problems on 10 accesses C7 Control Store Figure C7 completes our microprogrammed implementation of the LC3b It shows the contents of each location of the control store corresponding to the 35 control sig nals required by each state of the state machine We have left the exact entries blank to allow you dear reader the joy of lling in the required signals yourself


Buy Material

Are you sure you want to buy this material for

25 Karma

Buy Material

BOOM! Enjoy Your Free Notes!

We've added these Notes to your profile, click here to view them now.


You're already Subscribed!

Looks like you've already subscribed to StudySoup, you won't need to purchase another subscription to get this material. To access this material simply click 'View Full Document'

Why people love StudySoup

Jim McGreen Ohio University

"Knowing I can count on the Elite Notetaker in my class allows me to focus on what the professor is saying instead of just scribbling notes the whole time and falling behind."

Amaris Trozzo George Washington University

"I made $350 in just two days after posting my first study guide."

Steve Martinelli UC Los Angeles

"There's no way I would have passed my Organic Chemistry class this semester without the notes and study guides I got from StudySoup."

Parker Thompson 500 Startups

"It's a great way for students to improve their educational experience and it seemed like a product that everybody wants, so all the people participating are winning."

Become an Elite Notetaker and start selling your notes online!

Refund Policy


All subscriptions to StudySoup are paid in full at the time of subscribing. To change your credit card information or to cancel your subscription, go to "Edit Settings". All credit card information will be available there. If you should decide to cancel your subscription, it will continue to be valid until the next payment period, as all payments for the current period were made in advance. For special circumstances, please email


StudySoup has more than 1 million course-specific study resources to help students study smarter. If you’re having trouble finding what you’re looking for, our customer support team can help you find what you need! Feel free to contact them here:

Recurring Subscriptions: If you have canceled your recurring subscription on the day of renewal and have not downloaded any documents, you may request a refund by submitting an email to

Satisfaction Guarantee: If you’re not satisfied with your subscription, you can contact us for further help. Contact must be made within 3 business days of your subscription purchase and your refund request will be subject for review.

Please Note: Refunds can never be provided more than 30 days after the initial purchase date regardless of your activity on the site.