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Computer Organization

by: Ashleigh148

Computer Organization IT1205

GPA 2.75

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About this Document

Chapter 3 of OS - Computer Organization
Class Notes
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This 6 page Class Notes was uploaded by Ashleigh148 on Sunday November 22, 2015. The Class Notes belongs to IT1205 at Nanyang Polytechnic taught by TEO WEI LING MICHELLE STF-SIT; YOW MEI LING STF-SIT; CHUNG JASON STF-SIT; in Fall 2015. Since its upload, it has received 40 views. For similar materials see OPERATING SYSTEMS in Information technology at Nanyang Polytechnic.

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Date Created: 11/22/15
Chapter 3 Computer Organization Program 0 File of instructions Source file 0 High level programming language C Java 0 Low level programming language assembly language processor specific 0 Machine language processor specific Machine Language The von Neumann Architecture 0 Forms the basis for almost all modern computer systems 0 Most other specialized systems evolved from this architecture 0 Has a fixed set of electronic parts which can be manipulated to perform various tasks determined by a variable program 0 Consists of the following parts 0 A central processing unit CPU 0 A primary memory unit 0 A collection of IO Devices 0 Buses to interconnect the components A von Neumann computer contains a CPU which contains an ArithmeticalLogical Unit ALU and control unit The control unit decodes stored instructions and the ALU executes them The primary executable memory is used to store the program and data that are operated on by the CPU The devices are used for input output communications and storage The bus interconnections the CPU primary memory and devices Central Processing Unit The CPU is the brain of the computer and it consists of the ArithmeticalLogical Unit ALU and the Control Unit ArithmeticalLogical Unit ALU Responsible for performing arithmetic and logical operations Contains Functional unit 0 Performs the operations Registers very fast memory 0 Data status registers o Loaded and saved tofrom primary memory 0 32 to 64 registers to hold 32bit data Computations are accomplished by 0 Loading binary values into registers Performing operations on the registers using the function unit Storing the result back into a general register Saving the register contents back to memory Control Unit Causes a sequence of instructions stored in the memory to be retrieved and executed Contains 0 Fetch Unit Fetches an instruction from memory 0 Decode Unit Decode an instruction 0 Execute Unit Signal ALU to execute instruction 0 Instruction Register IR Contains a copy of the current instruction 0 Program Counter register PC Contains the memory address of the next instruction the unit is to load Works based on fetchexecute algorithm Control Unit Operation When the computer is powered up the control unit begins to execute the fetchexecute algorithm until the computer shuts down Fetch phase 0 Instruction retrieved from memory at location specified by PC 0 Loaded into IR 0 PC is incremented Execute phase 0 ALU operation 0 Cause memory data reference IO operation Primary Memory Unit 0 Stores both programs and data while they are being operated on by the CPU 0 Interface between CPU and memory is made up of 3 registers 0 Memory address register MAR I Stores address of data to be read from or written to 0 Memory data register MDR I Stores data that is read or to be written 0 Command register CMD I Stores the command to be executed 0 Stores programs and data in binary format 0 Referred to as random access memory RAM InputOutput Devices 0 Each device operation is controlled by a device controller It connects the device to the computer s address and data bus 0 Provides an interface which the OS Device manager can use to manipulate device 0 Interfaces varies among controllers 0 OS provides abstraction to hide differences from programmer Device Controller Interface 0 Device may need constant attentionmonitoring during operation 0 Device controller does this with mainly hardware algorithms 0 Software interface provided by controller allows OS to operate and synchronize its behavior with the device operation 0 Device controller include the following as part of the interface 0 Data registers 0 Command registers 0 Status flags with includes done busy and error code Determining When lO is complete When the CPU initiates IO we need the device to notify the CPU when the IO is done Two ways of notification Polling Simplest way is for CPU to keep polling the device to see state of the IO Device implements the status of the device as a flag If the IO is not done the CPU executes a busywait command to wait for the IO to end but the CPU is effectively waiting and doing nothing Waste precious processor cycles Interrupt A more advanced but more complicated way is to have the CPU implement an interrupt request flag When device IQ is done the device sets the interrupt request flag to signal the end of ID The CPU on its fetch cycle would detect the flag and proceed to execute a set of routines to service the IO CPUDevice operation CPU Device operation Performing a Write Operation polling Devices much slower than CPU CPU waits while device operates Would like to multiplex CPU to a different process while IO is in process This is possible using the Interrupt method Traps When a program wishes to execute a privileged instruction it issues a trap to the OS kernel Kernel switches the CPU to supervisor mode Based on the arguments provided the kernel executes the instruction on behalf of the program A trap is a software generated interrupt as it closely resembles how an interrupt works The OS is interrupted by the running program to perform certain tasks which require privileged instructions Direct Memory Access In conventional design the CPU transfers data between the controller data registers and the primary memory This means that the CPU is involved in all operations on the memory Problem is that most operations require memory access In IO operations when the data to be copied to memory is large the CPU can get very busy just copying data It is more efficient to implement direct memory access DMA DMA memory controllers are able to readwrite data fromto memory without CPU intervention The DMA controller is able to perform the tasks that the CPU would otherwise have to perform CPU can start a DMA block transfer and then perform other work in parallel with the DMA operation This can significantly increase the machine s IO performance


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