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## eerf assignment 4

by: Prarthana ramani

24

1

11

# eerf assignment 4 EERF 6311.001

Prarthana ramani
UTD

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## About this Document

it describes the assignment 4
COURSE
RF and Microwave circuits
PROF.
Ricardo Saad
TYPE
Class Notes
PAGES
11
WORDS
CONCEPTS
rf
KARMA
25 ?

## Popular in Education and Teacher Studies

This 11 page Class Notes was uploaded by Prarthana ramani on Sunday April 3, 2016. The Class Notes belongs to EERF 6311.001 at University of Texas at Dallas taught by Ricardo Saad in Spring 2016. Since its upload, it has received 24 views. For similar materials see RF and Microwave circuits in Education and Teacher Studies at University of Texas at Dallas.

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Date Created: 04/03/16
The University of Texas at Dallas CE/EEDG:6301 Advance Digital Logic Spring 2016 Assignment #4 Submitted By : Prarthana Ramani (2021250223) Ques 1): Verilog code: module hw4q1(rst, sensor, close, red); input rst; input [2:0] sensor; output reg close,red; reg [1:0] state; reg D; always@(*) begin if(!rst) begin state=2'b00; close=1'b0; red=1'b0; D=1'b0; end else if(rst) begin if (sensor==3'b000) begin if(state==2'b00) begin close=1'b0; red=1'b0; end else begin close=1'b1; red=1'b1; end end else if(sensor==3'b100) begin if(D) begin D=1'b0; state=2'b00; close=1'b1; red=1'b1; end else begin close=1'b1; red=1'b1; state=2'b01; end end else if(sensor==3'b010) begin close=1'b1; red=1'b1; state=2'b10; end else if(sensor==3'b001) if(state==2'b00) begin close=1'b1; red=1'b1; state=2'b01; D=1'b1; end else begin close=1'b1; red=1'b1; state=2'b00; end else begin close=close; red=red; state=state; end end end endmodule Verilog Testbench: module hw4q1tb; reg rst; reg [2:0] sensor; wire close; wire red; hw4q1 u1 (.rst(rst), .sensor(sensor), .close(close), .red(red)); initial begin rst = 0; sensor = 0; #100; rst=1; sensor=3'b001; #20 sensor=3'b010; #20 sensor=3'b000; #20 sensor=3'b100; #20 sensor=3'b000; end endmodule Result: Ques 3): Verilog code: module assg3(P,R,Z); input P,R; output Z; wire Y1,Z,Y1_bar,R_bar,net1,net2,net3,net4,net5; not a8(R_bar,R); not a9(Y1_bar,Y1); and a1(net1,P,R); and a2(net2,P,Y1); and a3(net3,Z,R_bar); and a4(net4,Y1_bar,Z,P); and a5(net5,Y1_bar,P,R_bar); or a6(Y1,net1,net2); or a7(Z,net3,net4,net5); endmodule Verilog Testbench: module assg3_tb; reg P; reg R; wire Z; assg3 u1 (.P(P), .R(R), .Z(Z)); initial begin P=0; R=0; #100; P=1; #100; P=0; #100; R=1; #100; end endmodule Result:

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