A designer wishing to lower the overall upper 3-dB
Chapter 1, Problem 1.73(choose chapter or problem)
A designer wishing to lower the overall upper 3-dB frequency of a three-stage amplifier to 10 kHz considers shunting one of two nodes: Node A, between the output of the first stage and the input of the second stage, and Node B, between the output of the second stage and the input of the third stage, to ground with a small capacitor. While measuring the overall frequency response of the amplifier, she connects a capacitor of 1 nF, first to node A and then to node B, lowering the 3-dB frequency from 2 MHz to 150 kHz and 15 kHz, respectively. If she knows that each amplifier stage has an input resistance of 100 k, what output resistance must the driving stage have at node A? At node B? What capacitor value should she connect to which node to solve her design problem most economically?
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