A particular implementation of the CMOS amplifier of Figs. 12.1 and 12.2 provides Gm1 = 0.3 mA/V, Gm2 = 0.6 mA/V, ro2 = ro4 = 222 k, ro6 = ro7 = 111 k, and C2 = 1 pF. (a) Find the frequency of the second pole, fP2. (b) Find the value of the resistance R which when placed in series with CC causes the transmission zero to be located at s = . (c) With R in place, as in (b), find the value of CC that results in the highest possible value of ft while providing a phase margin of 80. What value of ft is realized? What is the corresponding frequency of the dominant pole? (d) To what value should CC be changed to double the value of ft? At the new value of ft, what is the phase shift introduced by the second pole? To reduce this excess phase shift to 10 and thus obtain an 80 phase margin, as before, what value should R be changed to?
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